CN104867924B - Tft显示器件及其制作方法 - Google Patents

Tft显示器件及其制作方法 Download PDF

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CN104867924B
CN104867924B CN201510227667.XA CN201510227667A CN104867924B CN 104867924 B CN104867924 B CN 104867924B CN 201510227667 A CN201510227667 A CN 201510227667A CN 104867924 B CN104867924 B CN 104867924B
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silicon nitride
nitride film
conductive films
ito conductive
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谢克成
洪日
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Abstract

本发明公开了一种TFT显示器件及其制作方法,TFT显示器件包括:第一金属层,在第一金属层上沉积第一氮化硅薄膜;第二金属层,沉积在第一氮化硅薄膜上,经过刻蚀形成图案,第二金属层上沉积有第二氮化硅薄膜;过孔,在第二金属层与第一金属层重叠区域,第一金属层和/或第二金属层断开,在断开位置使用过孔刻蚀掉第一氮化硅薄膜和第二氮化硅薄膜,并沉积ITO导电薄膜以使断开位置连接导通。通过上述方式,本发明能够降低ESD对TFT显示器件的击伤,提高产品良率,提升产品竞争力。

Description

TFT显示器件及其制作方法
技术领域
本发明涉及液晶显示领域,尤其是涉及一种TFT显示器件及其制作方法。
背景技术
薄膜场效应晶体管(Thin Film Transistor,TFT)显示器件的制作过程相对比较复杂,需要经过很多个工序才能制作完成,其中又有很多高温工序,比如金属成膜,非金属成膜,干刻等工序,这些工序必须在高温环境下作业,静电放电(Electro-Staticdischarge,ESD)产生的几率相对较高,如果产品的设计对ESD的防护不好,TFT显示器件将很容易被ESD击伤。目前对TFT显示器件ESD防护的措施非常多,也有相对有效的方法。一般ESD容易发生在上下层金属交叠区域,如图1a和图1b所示,当上下两层11和12金属跨线重叠的时候,如果所携带的静电流过大时,上下重叠区13将发生ESD击穿现象。一般做法是将交叠区域13的金属线宽减小,以减少ESD对金属线路的击伤。
发明内容
本发明主要解决的技术问题是提供一种TFT显示器件及其制作方法,能够降低ESD对TFT显示器件的击伤,提高产品良率,提升产品竞争力。
为解决上述技术问题,本发明采用的一个技术方案是:提供一种TFT显示器件,包括:第一金属层,在第一金属层上沉积第一氮化硅薄膜;第二金属层,沉积在第一氮化硅薄膜上,经过刻蚀形成图案,第二金属层上沉积有第二氮化硅薄膜;过孔,在第二金属层与第一金属层重叠区域,第一金属层和/或第二金属层断开,在断开位置使用过孔刻蚀掉第一氮化硅薄膜和第二氮化硅薄膜,并沉积ITO导电薄膜以使断开位置连接导通;其中,所述第二金属层与所述第一金属层重叠区域的所述过孔内的材料与所述第一金属层的材料和所述第二金属层的材料不同。
其中,过孔穿过第一氮化硅薄膜和第二氮化硅薄膜,与第一金属层和/或第二金属层接触。
其中,ITO导电薄膜涂覆在第二氮化硅薄膜上。
其中,第一金属层断开时,过孔位置的ITO导电薄膜与第一金属层接触,使第一金属层的断开位置通过ITO导电薄膜连接导通。
其中,第二金属层断开时,过孔位置的ITO导电薄膜与第二金属层接触,使第二金属层的断开位置通过ITO导电薄膜连接导通。
为解决上述技术问题,本发明采用的另一个技术方案是:提供一种TFT显示器件的制作方法,包括:在第一金属层上沉积第一氮化硅薄膜;在第一氮化硅薄膜上沉积第二金属层,并经过刻蚀形成图案,第二金属层上沉积有第二氮化硅薄膜;在第二金属层与第一金属层重叠区域,第一金属层和/或第二金属层断开,在断开位置使用过孔刻蚀掉第一氮化硅薄膜和第二氮化硅薄膜,并沉积ITO导电薄膜以使断开位置连接导通;其中,所述第二金属层与所述第一金属层重叠区域的所述过孔内的材料与所述第一金属层的材料和所述第二金属层的材料不同。
其中,过孔穿过第一氮化硅薄膜和第二氮化硅薄膜,与第一金属层和/或第二金属层接触。
其中,ITO导电薄膜涂覆在第二氮化硅薄膜上。
其中,第一金属层断开时,过孔位置的ITO导电薄膜与第一金属层接触,使第一金属层的断开位置通过ITO导电薄膜连接导通。
其中,第二金属层断开时,过孔位置的ITO导电薄膜与第二金属层接触,使第二金属层的断开位置通过ITO导电薄膜连接导通。
本发明的有益效果是:区别于现有技术的情况,本发明的TFT显示器件通过在第一金属层上沉积第一氮化硅薄膜;第二金属层沉积在第一氮化硅薄膜上,经过刻蚀形成图案,第二金属层上沉积有第二氮化硅薄膜;在第二金属层与第一金属层重叠区域,第一金属层和/或第二金属层断开,在断开位置使用过孔刻蚀掉第一氮化硅薄膜和第二氮化硅薄膜,并沉积ITO导电薄膜以使断开位置连接导通,能够降低ESD对TFT显示器件的击伤,提高产品良率,提升产品竞争力。
附图说明
图1是现有技术中的TFT显示器件的ESD击穿的示意图;
图2是本发明第一实施例的TFT显示器件的剖面结构示意图;
图3是图2中的TFT显示器件的平面结构示意图;
图4是本发明第二实施例的TFT显示器件的剖面结构示意图;
图5是图4中的TFT显示器件的平面结构示意图;
图6是本发明实施例的TFT显示器件的制作方法的流程示意图。
具体实施方式
请参阅图2,图2是本发明第一实施例的TFT显示器件的剖面结构示意图。如图2所示,TFT显示器件20包括:第一金属层21、第二金属层22、第一氮化硅薄膜23、过孔24、ITO导电薄膜25以及第二氮化硅薄膜26。在第一金属层21上沉积第一氮化硅薄膜23。第二金属层22沉积在第一氮化硅薄膜23上,经过刻蚀形成图案。第二金属层22上沉积有第二氮化硅薄膜26;在第二金属层22与第一金属层21重叠区域,第一金属层21和/或第二金属层22断开,在断开位置使用过孔24刻蚀掉第一氮化硅薄膜23和第二氮化硅薄膜26,并沉积ITO导电薄膜25以使断开位置连接导通。如此,通过将TFT显示器件上显示区外围线宽较大的金属走线更改成由ITO薄膜组成的走线,并通过过孔桥接方式连通金属走线的两端,减少线宽较大金属走线与线宽较小金属走线上下跨线产生ESD,分散与导走TFT显示器件上的ESD,从而降低ESD对TFT显示器件的击伤,提高产品良率,提升产品竞争力。
在本发明实施例中,ITO导电薄膜25涂覆在第二氮化硅薄膜26上。过孔24穿过第一氮化硅薄膜23和第二氮化硅薄膜26,与第一金属层21和/或第二金属层22接触。第一氮化硅薄膜23和第二氮化硅薄膜26可以采用相同的氮化硅薄膜,如SiNx薄膜。在本发明的其他实施例中,也可以采用不同的氮化硅薄膜。
图2表示在第二金属层22与第一金属层21重叠区域,第一金属层21断开的剖面结构图,图3为对应的平面结构图,27为解剖线。此时,过孔24位置处的ITO导电薄膜25与第一金属层21接触,使第一金属层21的断开位置通过ITO导电薄膜25连接导通。
图4表示在第二金属层32与第一金属层31重叠区域,第二金属层32断开的剖面结构图,图5为对应的平面结构图,37为解剖线。第一层金属31上沉积第一氮化硅薄膜33,第一氮化硅薄膜33上沉积第二层金属32,经过刻蚀制程形成图案,第二层金属32上沉积第二氮化硅薄膜36,第二层金属32的断开位置使用过孔34将第一氮化硅薄膜33和第二氮化硅薄膜36刻蚀掉,在第二氮化硅薄膜36上沉积ITO导电薄膜35。此时,过孔34位置处的ITO导电薄膜35与第二金属层32接触,使第二金属层32的断开位置通过ITO导电薄膜35连接导通。如此,通过在第二金属层22与第一金属层21重叠区域使用过孔材料导电性不一致,利用不同材料间电容差异分散与导走TFT显示器件上的ESD,从而降低ESD对TFT显示器件的击伤,提高产品良率,提升产品竞争力。
图6是本发明实施例的TFT显示器件的制作方法的流程示意图。如图6所示,TFT显示器件的制作方法包括:
步骤S10:在第一金属层上沉积第一氮化硅薄膜。
步骤S11:在第一氮化硅薄膜上沉积第二金属层,并经过刻蚀形成图案,第二金属层上沉积有第二氮化硅薄膜。
步骤S12:在第二金属层与第一金属层重叠区域,第一金属层和/或第二金属层断开,在断开位置使用过孔刻蚀掉第一氮化硅薄膜和第二氮化硅薄膜,并沉积ITO导电薄膜以使断开位置连接导通。
其中,ITO导电薄膜涂覆在第二氮化硅薄膜上。过孔穿过第一氮化硅薄膜和第二氮化硅薄膜,与第一金属层和/或第二金属层接触。具体地,在第二金属层与第一金属层重叠区域,第一金属层断开时,过孔位置的ITO导电薄膜与第一金属层接触,使第一金属层的断开位置通过ITO导电薄膜连接导通。在第二金属层与第一金属层重叠区域,第二金属层断开时,过孔位置的ITO导电薄膜与第二金属层接触,使第二金属层的断开位置通过ITO导电薄膜连接导通。当然在本发明的其他实施例中,也可以在第二金属层与第一金属层重叠区域,第一金属层和第二金属层皆断开,第一金属层和第二金属层的断开位置分别通过不同或相同的ITO导电薄膜连接导通。如此,通过将TFT显示器件上显示区外围线宽较大的金属走线更改成由ITO薄膜组成的走线,并通过过孔桥接方式连通金属走线的两端,减少线宽较大金属走线与线宽较小金属走线上下跨线产生ESD。另外,在第二金属层与第一金属层重叠区域使用导电性不一致的过孔材料,如分别为金属和ITO导电薄膜,可以利用不同材料间电容差异分散与导走TFT显示器件上的ESD,从而降低ESD对TFT显示器件的击伤,提高产品良率,提升产品竞争力。
在本发明实施例中,第一氮化硅薄膜23和第二氮化硅薄膜26可以采用相同的氮化硅薄膜,如SiNx薄膜。在本发明的其他实施例中,也可以采用不同的氮化硅薄膜。
综上所述,本发明的TFT显示器件通过在第一金属层上沉积第一氮化硅薄膜;第二金属层沉积在第一氮化硅薄膜上,经过刻蚀形成图案,第二金属上层沉积有第二氮化硅薄膜;在第二金属层与第一金属层重叠区域,第一金属层和/或第二金属层断开,在断开位置使用过孔刻蚀掉氮化硅薄膜,并沉积ITO导电薄膜以使断开位置连接导通,能够降低ESD对TFT显示器件的击伤,提高产品良率,提升产品竞争力。
以上所述仅为本发明的实施例,并非因此限制本发明的专利范围,凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本发明的专利保护范围内。

Claims (2)

1.一种TFT显示器件,其特征在于,所述TFT显示器件包括:
第一金属层,在所述第一金属层上沉积第一氮化硅薄膜;
第二金属层,沉积在所述第一氮化硅薄膜上,经过刻蚀形成图案,所述第二金属层上沉积有第二氮化硅薄膜;
过孔,在所述第二金属层与所述第一金属层重叠区域,所述第一金属层和/或所述第二金属层断开,在所述断开位置使用所述过孔刻蚀掉所述第一氮化硅薄膜和所述第二氮化硅薄膜,并沉积ITO导电薄膜以使所述断开位置连接导通;其中,所述第二金属层与所述第一金属层重叠区域的所述过孔内的材料与所述第一金属层的材料和所述第二金属层的材料不同;
所述过孔穿过所述第一氮化硅薄膜和所述第二氮化硅薄膜,与所述第一金属层和/或所述第二金属层接触;所述ITO导电薄膜涂覆在所述第二氮化硅薄膜上;
所述第一金属层断开时,所述过孔位置的所述ITO导电薄膜与所述第一金属层接触,使所述第一金属层的断开位置通过所述ITO导电薄膜连接导通;
所述第二金属层断开时,所述过孔位置的所述ITO导电薄膜与第二金属层接触,使所述第二金属层的断开位置通过所述ITO导电薄膜连接导通。
2.一种TFT显示器件的制作方法,其特征在于,所述制作方法包括:
在第一金属层上沉积第一氮化硅薄膜;
在所述第一氮化硅薄膜上沉积第二金属层,并经过刻蚀形成图案,所述第二金属层上沉积有第二氮化硅薄膜;
在所述第二金属层与所述第一金属层重叠区域,所述第一金属层和/或所述第二金属层断开,在所述断开位置使用过孔刻蚀掉所述第一氮化硅薄膜和所述第二氮化硅薄膜,并沉积ITO导电薄膜以使所述断开位置连接导通;其中,所述第二金属层与所述第一金属层重叠区域的所述过孔内的材料与所述第一金属层的材料和所述第二金属层的材料不同;
其中,所述过孔穿过所述第一氮化硅薄膜和所述第二氮化硅薄膜,与所述第一金属层和/或所述第二金属层接触;所述ITO导电薄膜涂覆在所述第二氮化硅薄膜上;
其中,所述第一金属层断开时,所述过孔位置的所述ITO导电薄膜与所述第一金属层接触,使所述第一金属层的断开位置通过所述ITO导电薄膜连接导通;
其中,所述第一金属层断开时,所述过孔位置的所述ITO导电薄膜与所述第一金属层接触,使所述第一金属层的断开位置通过所述ITO导电薄膜连接导通;
其中,所述第二金属层断开时,所述过孔位置的所述ITO导电薄膜与第二金属层接触,使所述第二金属层的断开位置通过所述ITO导电薄膜连接导通。
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011309A (en) * 1997-03-06 2000-01-04 Lg Electronics Inc. Wiring structure of thin film transistor array and method of manufacturing the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011309A (en) * 1997-03-06 2000-01-04 Lg Electronics Inc. Wiring structure of thin film transistor array and method of manufacturing the same

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