WO2016173011A1 - Tft基板的制作方法及其结构 - Google Patents

Tft基板的制作方法及其结构 Download PDF

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WO2016173011A1
WO2016173011A1 PCT/CN2015/079376 CN2015079376W WO2016173011A1 WO 2016173011 A1 WO2016173011 A1 WO 2016173011A1 CN 2015079376 W CN2015079376 W CN 2015079376W WO 2016173011 A1 WO2016173011 A1 WO 2016173011A1
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Prior art keywords
layer
gate
contact hole
drain
tft
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French (fr)
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李文辉
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/786,158 priority Critical patent/US9666653B2/en
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    • H10D86/01—Manufacture or treatment
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    • H10D30/67—Thin-film transistors [TFT]
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    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
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    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/871—Self-supporting sealing arrangements
    • H10K59/8723—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate and a structure thereof.
  • OLED Organic Light-Emitting Diode
  • PMOLEDs passive OLEDs
  • AMOLEDs active OLEDs
  • LTPS low temperature poly-silicon
  • FIG. 1 is a schematic cross-sectional view of a conventional TFT (Thin Film Transistor) substrate structure applied to an AMOLED, including a substrate 100, a first gate 210 disposed on the substrate 100, and a first a gate electrode 220, a gate insulating layer 300 disposed on the first gate 210, the second gate 220, and the substrate 100, and the gate insulating layer 300 disposed above the first gate 210 a first semiconductor layer 410, a second semiconductor layer 420 disposed on the gate insulating layer 300 above the second gate 220, and the first semiconductor layer 410 and the second semiconductor layer 420.
  • TFT Thin Film Transistor
  • Two first via holes 510 are disposed on the etch stop layer 500 corresponding to the first semiconductor layer 410, and two second via holes are disposed on the etch stop layer 500 corresponding to the second semiconductor layer 420.
  • 520, the etch stop layer 500, and a side of the gate insulating layer 300 corresponding to the second gate 220 adjacent to the first gate 210 is provided with a third via 530, the passivation layer 710,
  • a fourth via 810 is disposed on the flat layer 720 corresponding to the second source 630.
  • a fifth via 910 is disposed above the pixel defining layer 900 corresponding to the pixel electrode layer 800.
  • the first source 610 and the first drain 620 are respectively in contact with the first semiconductor layer 410 via the first via 510, and the second source 630 and the second drain 640 are respectively.
  • the second via 520 is in contact with the second semiconductor layer 420, and the first source 610 is in contact with the second gate 220 via the third via 530, and the pixel electrode layer 800 is via
  • the fourth via 810 is in contact with the second source 630, and the fifth via 910 exposes a portion of the pixel electrode layer 800.
  • the pole 620, the second source 630, and the second drain 640, the passivation layer 710, the flat layer 720, the pixel electrode layer 800, the pixel definition layer 900, and each of the photoresist spacers 920 need to pass through a light.
  • Inscribed process fabrication that is, the fabrication of the TFT substrate shown in FIG. 1 requires a total of ten lithography processes, which is cumbersome in process, affecting production efficiency and yield.
  • An object of the present invention is to provide a method for fabricating a TFT substrate, which has a simple process and can effectively improve production efficiency and yield.
  • Another object of the present invention is to provide a TFT substrate structure, which has a simple structure and is easy to manufacture, and can effectively improve production efficiency and yield.
  • the present invention provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 Providing a substrate on which a TFT region and a non-TFT region are disposed, depositing a first metal layer on the substrate, and patterning the first metal layer by a first photolithography process to obtain an interval setting a first gate and a second gate;
  • Step 2 sequentially depositing a gate insulating layer, a semiconductor layer, and an etch barrier layer on the first gate, the second gate, and the substrate;
  • Step 3 patterning the gate insulating layer, the semiconductor layer, and the etch barrier layer by a second lithography process, forming a first layer on the etch barrier layer corresponding to the first gate a contact hole and a second contact hole, corresponding to the second gate, forming a third contact hole and a fourth contact hole; corresponding to the etch stop layer, the semiconductor layer, and the gate insulating layer a fifth contact hole is formed on a side of the second gate adjacent to the first gate; the first contact hole, the second contact hole, the third contact hole, the fourth contact hole, and the fifth contact hole are both through holes;
  • Step 4 depositing a second metal layer on the etch barrier layer, and passing through a third lithography process map Forming the second metal layer to obtain spaced apart first source, first drain, second source, and second drain, the first source, the first drain, the second source, And the second drain is in contact with the semiconductor layer via the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole;
  • the first gate, the semiconductor layer, the first source, and the first drain constitute a first TFT;
  • the second gate, the semiconductor layer, the second source, and the second drain constitute a second TFT;
  • the first drain contacts the second gate via a fifth contact hole, and connects the first TFT and the second TFT in series;
  • Step 5 depositing a passivation layer on the first source, the first drain, the second source, the second drain, the etch barrier, and the substrate, and performing the blunt process by a fourth lithography process
  • the layer is patterned, and a sixth via hole is formed on the passivation layer corresponding to the second drain;
  • Step 6 depositing a flat layer on the passivation layer, and patterning the flat layer by a fifth photolithography process, forming a seventh via hole on the flat layer corresponding to the sixth via hole;
  • Step 7 depositing a pixel electrode layer on the planar layer, and patterning the pixel electrode layer through a sixth photolithography process, wherein the pixel electrode layer and the seventh via hole and the seventh via hole Two drain contacts;
  • Step 8 Deposit a pixel defining layer on the pixel electrode layer and the flat layer, and pattern it by a seventh lithography process, and form a pixel corresponding to the pixel electrode layer on the pixel defining layer.
  • Step 9 Deposit an organic photoresist layer on the pixel defining layer, and pattern it by an eighth photolithography process to form a plurality of photoresist spacers disposed at intervals.
  • the step 3 specifically includes:
  • Step 31 depositing a photoresist layer on the etch barrier layer, and exposing and developing the photoresist layer through a gray scale mask, so that portions of the non-TFT region on the corresponding substrate on the photoresist layer are completely etched away. And forming, on the photoresist layer, a first groove and a second groove disposed at intervals corresponding to the first gate, and correspondingly forming a third groove and a space disposed above the second gate a fourth recess, a first through hole corresponding to a side of the second gate adjacent to the first gate;
  • Step 32 The etch stop layer is etched by the first dry etch process by using the photoresist layer as an occlusion, so that a portion of the etch stop layer corresponding to the non-TFT region on the substrate is completely etched away. a portion of the etch stop layer corresponding to the first via hole on the photoresist layer is completely etched away;
  • Step 33 performing ashing treatment on the photoresist layer by a ashing process, so that the overall thickness of the photoresist layer is reduced, and the first groove, the second groove, and the third recess on the photoresist layer
  • the bottom of the groove and the fourth groove are penetrated to form a second through hole, a third through hole, a fourth through hole, and Fifth through hole;
  • Step 34 using the photoresist layer as an occlusion, etching the semiconductor layer by a wet etching process, so that a portion of the semiconductor layer on the non-TFT region on the corresponding substrate is completely etched away, and the semiconductor layer is a portion corresponding to the first via hole on the photoresist layer is completely etched away;
  • Step 35 occluding the photoresist layer, etching the etch barrier layer and the gate insulating layer by a second dry etching process, so that the etch barrier layer corresponds to the photoresist layer
  • Portions of the second via hole, the third via hole, the fourth via hole, and the fifth via hole are completely etched away, thereby forming a first contact hole corresponding to the first gate electrode and the first on the etch barrier layer
  • a portion of the gate insulating layer corresponding to the non-TFT region on the substrate is completely etched away, and a portion of the gate insulating layer corresponding to the first via hole on the photoresist layer is completely etched away.
  • Step 36 peeling off the photoresist layer.
  • the material of the gate insulating layer is silicon oxide or silicon nitride
  • the material of the semiconductor layer is metal oxide
  • the material of the etching barrier layer is silicon oxide or silicon nitride.
  • the specific process parameters of the first dry etching process in the step 32 are: when the material of the etching barrier layer is silicon oxide, dry etching is performed using a CF 4 + O 2 atmosphere, and the CF 4 flow rate is 0 to 5000 sccm, O. flow rate of 2 0 ⁇ 5000sccm, the etching time is 1 ⁇ 1000s; when the material layer (5) of the silicon nitride etch stop using SF 6 + Cl 2 atmosphere dry etching, SF 6 flow rate of 0 ⁇ 5000sccm, The Cl 2 flow rate is 0 to 5000 sccm, and the etching time is 1 to 1000 s;
  • the specific process parameter of the ashing process in the step 33 is: performing photoresist ashing using an O 2 atmosphere, the O 2 flow rate is 0 to 5000 sccm, and the ashing time is 1 to 1000 s;
  • the specific process parameters of the wet etching process in the step 34 are: wet etching using a H 2 C 2 O 4 solution, the concentration of the H 2 C 2 O 4 solution is 0.1% to 50% mol/L, and the etching time is 1 to 1000 s;
  • the specific process parameters of the second dry etching process in the step 35 are: when the materials of the etching barrier layer and the gate insulating layer are both silicon oxide, dry etching is performed using a CF 4 + O 2 atmosphere, and the CF 4 flow rate is performed. 0 to 5000 sccm, O 2 flow rate is 0 to 5000 sccm, etching time is 1 to 1000 s; when the etching barrier layer and the gate insulating layer are both silicon nitride, dry etching is performed using SF 6 +Cl 2 atmosphere The SF 6 flow rate is 0 to 5000 sccm, the Cl 2 flow rate is 0 to 5000 sccm, and the etching time is 1 to 1000 s.
  • the substrate is a glass substrate, and the material of the first gate and the second gate is copper, aluminum, or molybdenum, the first source, the first drain, the second source, and the second drain
  • the material is copper, aluminum, or molybdenum.
  • the present invention also provides a TFT substrate structure, including a substrate, a first gate disposed on the substrate and spaced apart from each other, and a second gate disposed on the first gate, the second gate, and the substrate a gate insulating layer, a semiconductor layer disposed on the gate insulating layer, an etch barrier layer disposed on the semiconductor layer, a first source disposed on the etch stop layer and spaced apart from each other a drain, a second source, and a second drain, and a passivation layer covering the substrate on the first source, the first drain, the second source, and the second drain a flat layer on the passivation layer, a pixel electrode layer disposed on the flat layer, a pixel defining layer disposed on the flat layer and the pixel electrode layer, and a pixel defining layer disposed on the pixel defining layer Photoresist spacer
  • the etch barrier layer is provided with a first contact hole and a second contact hole corresponding to the first gate, and a third contact hole and a fourth contact hole corresponding to the second gate; the etch barrier layer a fifth contact hole is disposed on a side of the semiconductor layer and the gate insulating layer corresponding to the second gate above the first gate; the first contact hole, the second contact hole, the third contact hole, The fourth contact hole and the fifth contact hole are both through holes;
  • the first source, the first drain, the second source, and the second drain are respectively connected to the semiconductor layer via the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole Contacting the first gate, the semiconductor layer, the first source, and the first drain to form a first TFT;
  • the second gate, the semiconductor layer, the second source, and the second drain constitute a first a second TFT;
  • the first drain is in contact with the second gate via a fifth contact hole, and the first TFT is connected in series with the second TFT;
  • a sixth through hole is disposed on the passivation layer corresponding to the second drain, and a seventh through hole is disposed on the flat layer corresponding to the sixth through hole, where the pixel electrode layer passes through
  • the sixth via hole and the seventh via hole are in contact with the second drain;
  • the pixel defining layer is provided with an eighth via hole corresponding to the pixel electrode layer, and the eighth via hole is exposed A portion of the pixel electrode layer is formed.
  • the gate insulating layer, the semiconductor layer, and the etch barrier layer are fabricated by a photolithography process.
  • the first TFT is a switching TFT
  • the second TFT is a driving TFT
  • the substrate is a glass substrate, the material of the first gate and the second gate is copper, aluminum, or molybdenum, and the material of the gate insulating layer is silicon oxide or silicon nitride, and the material of the semiconductor layer It is a metal oxide; the material of the semiconductor layer is a metal oxide.
  • the material of the etch barrier layer is silicon oxide or silicon nitride, and the material of the first source, the first drain, the second source, and the second drain is copper, aluminum, or molybdenum.
  • the present invention also provides a TFT substrate structure, including a substrate, a first gate disposed on the substrate and spaced apart from each other, and a second gate disposed on the first gate, the second gate, and the substrate a gate insulating layer, a semiconductor layer disposed on the gate insulating layer, and a semiconductor layer disposed on the semiconductor layer
  • the etch barrier layer is provided with a first contact hole and a second contact hole corresponding to the first gate, and a third contact hole and a fourth contact hole corresponding to the second gate; the etch barrier layer a fifth contact hole is disposed on a side of the semiconductor layer and the gate insulating layer corresponding to the second gate above the first gate; the first contact hole, the second contact hole, the third contact hole, The fourth contact hole and the fifth contact hole are both through holes;
  • the first source, the first drain, the second source, and the second drain are respectively connected to the semiconductor layer via the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole Contacting the first gate, the semiconductor layer, the first source, and the first drain to form a first TFT;
  • the second gate, the semiconductor layer, the second source, and the second drain constitute a first a second TFT;
  • the first drain is in contact with the second gate via a fifth contact hole, and the first TFT is connected in series with the second TFT;
  • a sixth through hole is disposed on the passivation layer corresponding to the second drain, and a seventh through hole is disposed on the flat layer corresponding to the sixth through hole, where the pixel electrode layer passes through
  • the sixth via hole and the seventh via hole are in contact with the second drain;
  • the pixel defining layer is provided with an eighth via hole corresponding to the pixel electrode layer, and the eighth via hole is exposed a portion of the pixel electrode layer;
  • the gate insulating layer, the semiconductor layer, and the etch barrier layer are fabricated by a photolithography process
  • the first TFT is a switching TFT
  • the second TFT is a driving TFT
  • a gate insulating layer, a semiconductor layer, and an etch barrier layer are formed together by a photolithography process, and the number of photolithography processes is determined by The reduction of ten lanes to eight lanes reduces the use of masks, simplifies the production process, and effectively improves production efficiency and yield.
  • the gate insulating layer, the semiconductor layer, and the etch barrier layer can be fabricated by a lithography process using a gray scale mask, the structure is simple, and the fabrication is easy, and the production efficiency and the yield can be effectively improved.
  • FIG. 1 is a schematic cross-sectional view showing a conventional TFT substrate structure applied to an AMOLED
  • step 1 is a schematic view of step 1 of a method of fabricating a TFT substrate of the present invention
  • FIG. 3 is a schematic view showing a step 2 of a method of fabricating a TFT substrate of the present invention
  • 4-5 is a schematic view showing the step 31 of the method for fabricating the TFT substrate of the present invention.
  • FIG. 6 is a schematic view showing a step 32 of a method of fabricating a TFT substrate of the present invention
  • FIG. 7 is a schematic view showing a step 33 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 8 is a schematic view showing a step 34 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 9 is a schematic view showing a step 35 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 10 is a schematic view showing a step 36 of a method of fabricating a TFT substrate of the present invention
  • FIG. 11 is a schematic view showing a step 4 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 12 is a schematic view showing a step 5 of a method of fabricating a TFT substrate of the present invention.
  • Figure 13 is a schematic view showing the step 6 of the method for fabricating the TFT substrate of the present invention.
  • Figure 14 is a schematic view showing the step 7 of the method for fabricating the TFT substrate of the present invention.
  • 15 is a schematic view showing a step 8 of a method of fabricating a TFT substrate of the present invention.
  • Figure 16 is a schematic view showing the step 9 of the method for fabricating the TFT substrate of the present invention and a schematic cross-sectional view showing the structure of the TFT substrate of the present invention.
  • the present invention provides a method for fabricating a TFT substrate, including the following steps:
  • Step 1 as shown in FIG. 2, a substrate 1 is provided.
  • the substrate 1 is provided with a TFT region and a non-TFT region, and a first metal layer is deposited on the substrate 1 and patterned by a first photolithography process.
  • the first metal layer is described, and the first gate electrode 21 and the second gate electrode 22 are provided at intervals.
  • the substrate 1 is a glass substrate.
  • the material of the first gate 21 and the second gate 22 is copper, aluminum, or molybdenum.
  • Step 2 As shown in FIG. 3, a gate insulating layer 3, a semiconductor layer 4, and an etch barrier layer 5 are sequentially deposited on the first gate 21, the second gate 22, and the substrate 1.
  • the material of the gate insulating layer 3 is silicon oxide (SiO x ) or silicon nitride (SiN x ).
  • the material of the semiconductor layer 4 is a metal oxide.
  • the metal oxide is IGZO (indium gallium zinc oxide) or IZO (indium zinc oxide).
  • the material of the etch barrier layer 5 is silicon oxide or silicon nitride.
  • Step 3 as shown in FIG. 4-10, patterning the gate insulating layer 3, the semiconductor layer 4, and the etch barrier layer 5 by a second photolithography process, corresponding to the etch barrier layer 5 a first contact hole 51 and a second contact hole 52 are formed above the first gate 21, and a third contact hole 53 and a fourth contact hole 54 are formed above the second gate 22; a fifth contact hole 55 is formed on the etch stop layer 5, the semiconductor layer 4, and the gate insulating layer 3 corresponding to a side of the second gate 22 adjacent to the first gate 21; the first contact hole 51, The second contact hole 52, the third contact hole 53, the fourth contact hole 54, and the fifth contact hole 55 are all through holes.
  • the step 3 includes the following steps:
  • Step 31 depositing a photoresist layer 6 on the etch barrier layer 5, and exposing and developing the photoresist layer 6 through a gray scale mask 10, so that the photoresist layer 6 is formed.
  • a portion of the upper non-TFT region on the corresponding substrate 1 is completely etched away, and a first groove 61 and a second groove 62 are formed on the photoresist layer 6 corresponding to the first gate electrode 21 at intervals.
  • a third recess 63 and a fourth recess 64 are formed on the second gate 22, and a first through hole 65 is formed on a side of the second gate 22 adjacent to the first gate 21 . ;
  • Step 32 as shown in FIG. 6, the photoresist layer 6 is used as a shielding layer, and the etching stopper layer 5 is etched by a first dry etching process, so that the etching barrier layer 5 is on the corresponding substrate 1 A portion of the TFT region is completely etched away, and a portion of the etch stop layer 5 corresponding to the first via hole 65 on the photoresist layer 6 is completely etched away;
  • the specific process parameters of the first dry etching process are:
  • dry etching may be performed using a CF 4 (carbon tetrafluoride) + O 2 (oxygen) atmosphere, and the CF 4 flow rate is 0 to 5000 sccm.
  • the O 2 flow rate is 0 to 5000 sccm, and the etching time is 1 to 1000 s;
  • dry etching may be performed using an SF 6 (sulfur hexafluoride) + Cl 2 (chlorine gas) atmosphere, and the flow rate of the SF 6 is 0 to 5000 sccm.
  • the Cl 2 flow rate is 0 to 5000 sccm, and the etching time is 1 to 1000 s.
  • Step 33 as shown in FIG. 7, the ashing process is performed on the photoresist layer 6 by a ashing process, so that the overall thickness of the photoresist layer 6 is reduced, and the first groove on the photoresist layer 6 is formed.
  • the bottoms of the second recess 62, the third recess 63, and the fourth recess 64 are penetrated to form a second through hole 66, a third through hole 67, a fourth through hole 68, and a fifth pass, respectively.
  • the specific process parameters of the ashing process are: photoresist ashing using an O 2 atmosphere, an O 2 flow rate of 0 to 5000 sccm, and an ashing time of 1 to 1000 s.
  • Step 34 as shown in FIG. 8, the photoresist layer 6 is used as a shielding layer, and the semiconductor layer 4 is etched by a wet etching process so that the semiconductor layer 4 is non-TFT on the corresponding substrate 1. A portion of the region is completely etched away, and a portion of the semiconductor layer 4 corresponding to the first via 65 on the photoresist layer 6 is completely etched away;
  • the specific process parameters of the wet etching process are: wet etching using a H 2 C 2 O 4 (oxalic acid) solution, the concentration of the H 2 C 2 O 4 solution is 0.1% to 50% mol/L, and the etching time is 1 to 1000s.
  • Step 35 as shown in FIG. 9, the photoresist layer 6 is used as a shielding layer, and the etching barrier layer 5 and the gate insulating layer 3 are etched by a second dry etching process to make the etching barrier layer Portions of the second through holes 66, the third through holes 67, the fourth through holes 68, and the fifth through holes 69 corresponding to the photoresist layer 6 are completely etched away, so that the etching barrier layer is 5, a first contact hole 51 and a second contact hole 52 corresponding to the upper portion of the first gate 21, and a third contact hole 53 and a fourth contact hole 54 corresponding to the second gate 22;
  • a portion of the gate insulating layer 3 corresponding to the non-TFT region on the substrate 1 is completely etched away, and a portion of the gate insulating layer 3 corresponding to the first via hole 65 on the photoresist layer 6 is simultaneously removed. Is completely etched away, so as to form a fifth contact hole 55 on the etching barrier layer 5, the semiconductor layer 4 and the gate insulating layer 3 corresponding to the side of the second gate 22 close to the first gate 21;
  • dry etching may be performed in a CF 4 + O 2 atmosphere, the CF 4 flow rate is 0 to 5000 sccm, the O 2 flow rate is 0 to 5000 sccm, and the etching time is 1 to 1000 s;
  • etching stopper layer 5 When the material of the etching stopper layer 5 is silicon nitride, dry etching may be performed in an SF 6 +Cl 2 atmosphere, the flow rate of SF 6 is 0 to 5000 sccm, the flow rate of Cl 2 is 0 to 5000 sccm, and the etching time is 1 to 1000 s. Step 36, as shown in FIG. 10, peeling off the photoresist layer 6.
  • the step 3 is formed by using a gray scale mask to pattern the gate insulating layer 3, the semiconductor layer 4, and the etch barrier layer 5 by a photolithography process, thereby reducing the mask of the TFT substrate during the fabrication process.
  • the use amount simplifies the production process and can effectively improve production efficiency and yield.
  • Step 4 depositing a second metal layer on the etch barrier layer 5, patterning the second metal layer by a third lithography process, and obtaining a first source 71 and a first interval a drain 72, a second source 73, and a second drain 74, wherein the first source 71, the first drain 72, the second source 73, and the second drain 74 are respectively via the first contact
  • the hole 51, the second contact hole 52, the third contact hole 53, and the fourth contact hole 54 are in contact with the semiconductor layer 4;
  • the first gate 21, the semiconductor layer 4, the first source 71, and the first drain 72 constitute a first TFT; the second gate 22, the semiconductor layer 4, the second source 73, and the second The drain electrode 74 constitutes a second TFT; the first drain electrode 72 is in contact with the second gate electrode 22 via a fifth contact hole 55, and the first TFT is connected in series with the second TFT.
  • the material of the first source 71, the first drain 72, the second source 73, and the second drain 74 is copper, aluminum, or molybdenum.
  • Step 5 depositing a passivation layer 75 on the first source 71, the first drain 72, the second source 73, the second drain 74, the etch barrier 5, and the substrate 1.
  • the passivation layer 75 is patterned by a fourth photolithography process, and a sixth via hole 751 is formed on the passivation layer 75 corresponding to the second drain electrode 74.
  • the material of the passivation layer 75 is silicon nitride or silicon oxide.
  • Step 6 as shown in FIG. 13, depositing a planarization layer 76 on the passivation layer 75, and patterning the planarization layer 76 by a fifth lithography process, corresponding to the planarization layer 76
  • a sixth through hole 761 is formed above the sixth through hole 751.
  • the material of the flat layer 76 is an organic photoresist.
  • Step 7 as shown in FIG. 14, depositing a pixel electrode layer 8 on the flat layer 76, and patterning it by a sixth photolithography process, the pixel electrode layer 8 passing through the sixth through hole 751 And the seventh via 761 is in contact with the second drain 64.
  • the material of the pixel electrode layer 8 is ITO (Indium Tin Oxide).
  • Step 8 As shown in FIG. 15, a pixel defining layer 9 is deposited on the pixel electrode layer 8 and the flat layer 76, and patterned by a seventh photolithography process on the pixel defining layer 9. An eighth via 91 corresponding to the upper side of the pixel electrode layer 8 is formed to expose a portion of the pixel electrode layer 8.
  • Step 9 an organic photoresist layer is deposited on the pixel defining layer 9, and patterned by an eighth photolithography process to form a plurality of photoresist spacers 92 disposed at intervals.
  • the gate insulating layer, the semiconductor layer, and the etch barrier layer are formed by a photolithography process by using a gray scale mask, and the number of photolithography processes is reduced from ten to eight, which simplifies The process effectively improves production efficiency and yield.
  • the present invention further provides a TFT substrate structure, including a substrate 1, a first gate electrode 21 disposed on the substrate 1 and spaced apart from each other, and a second gate electrode 22 disposed on the first gate. a gate 21, a second gate 22, and a gate insulating layer 3 on the substrate 1, a semiconductor layer 4 provided on the gate insulating layer 3, and an etch stop layer 5 provided on the semiconductor layer 4.
  • the etch barrier layer 5 is provided with a first contact hole 51 and a second contact hole 52 corresponding to the upper portion of the first gate electrode 21, and a third contact hole 53 and a fourth contact hole corresponding to the upper portion of the second gate electrode 22. 54; the etch stop layer 5, the semiconductor layer 4, and the gate insulating layer 3 corresponding to the second gate A fifth contact hole 55 is disposed on a side of the upper portion of the second gate 21; the first contact hole 51, the second contact hole 52, the third contact hole 53, the fourth contact hole 54, and the fifth contact The holes 55 are all through holes;
  • the first source 71, the first drain 72, the second source 73, and the second drain 74 respectively pass through the first contact hole 51, the second contact hole 52, the third contact hole 53, and the fourth
  • the contact hole 54 is in contact with the semiconductor layer 4;
  • the first gate 21, the semiconductor layer 4, the first source 71, and the first drain 72 constitute a first TFT;
  • the layer 4, the second source 73, and the second drain 74 constitute a second TFT;
  • the first drain 72 is in contact with the second gate 22 via the fifth contact hole 55, and the first TFT and the first TFT Two TFTs are connected in series;
  • a sixth through hole 751 is disposed on the passivation layer 75 corresponding to the second drain 74, and a seventh through hole 761 is disposed on the flat layer 76 corresponding to the sixth through hole 751.
  • the pixel electrode layer 8 is in contact with the second drain electrode 74 via the sixth via hole 751 and the seventh via hole 761; the pixel defining layer 9 is provided with a corresponding portion above the pixel electrode layer 8
  • An eight-via hole 91 exposing a portion of the pixel electrode layer 8.
  • the gate insulating layer 3, the semiconductor layer 4, and the etch barrier layer 5 are fabricated by a photolithography process.
  • the first TFT is a switching TFT
  • the second TFT is a driving TFT
  • the substrate 1 is a glass substrate
  • the material of the first gate 21 and the second gate 22 is copper, aluminum, or molybdenum
  • the material of the gate insulating layer 3 is silicon oxide or silicon nitride.
  • the material of the semiconductor layer 4 is a metal oxide.
  • the metal oxide is IGZO (indium gallium zinc oxide) or IZO (indium zinc oxide).
  • the material of the etch barrier layer 5 is silicon oxide or silicon nitride.
  • the material of the first source 71, the first drain 72, the second source 73, and the second drain 74 is copper, aluminum, or molybdenum.
  • the material of the passivation layer 75 is silicon nitride or silicon oxide.
  • the material of the flat layer 76 is an organic photoresist.
  • the material of the pixel electrode layer 8 is ITO.
  • the TFT substrate structure, the gate insulating layer, the semiconductor layer, and the etch barrier layer can be fabricated by a photolithography process using a gray scale mask, and the structure is simple and easy to manufacture, and the production efficiency and the yield can be effectively improved.
  • the method for fabricating the TFT substrate of the present invention uses a gray scale mask to fabricate the gate insulating layer, the semiconductor layer, and the etch barrier layer together by a photolithography process, and the number of photolithography processes is ten.
  • the number of roads is reduced to eight, which reduces the amount of reticle used, simplifies the production process, and effectively improves production efficiency and yield.
  • the TFT substrate structure of the present invention, wherein the gate insulating layer, The semiconductor layer and the etch barrier layer can be fabricated by a lithography process using a gray scale mask, which is simple in structure and easy to manufacture, and can effectively improve production efficiency and yield.

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Abstract

一种TFT基板的制作方法及其结构，该TFT基板的制作方法通过使用灰阶光罩，将栅极绝缘层、半导体层、及蚀刻阻挡层通过一道光刻制程一同制作，将光刻制程的次数由十道减少至八道，减少了光罩的使用量，简化了生产制程，有效提高了生产效率及良率。该TFT基板结构，其中的栅极绝缘层（3）、半导体层（4）、及蚀刻阻挡层（5）可使用灰阶光罩通过一道光刻制程一同制作，结构简单，易于制作，可有效提高生产效率及良率。

Description

TFT基板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法及其结构。
背景技术
OLED(Organic Light-Emitting Diode)即有机发光二极管，具备自发光、高亮度、宽视角、高对比度、可挠曲、低能耗等特性，因此受到广泛的关注，并作为新一代的显示方式，已开始逐渐取代传统液晶显示器，被广泛应用在手机屏幕、电脑显示器、全彩电视等。OLED按照驱动类型可分为无源OLED(PMOLED，Passive matrix OLED)和有源OLED(AMOLED，Active-matrix OLED)。AMOLED常使用氧化物半导体型背板，其结构与低温多晶硅(LTPS，Low Temperature Poly-silicon)型背板相比更为简单。
请参阅图1，为一种现有的应用于AMOLED的TFT(薄膜晶体管，Thin Film Transistor)基板结构的剖面示意图，包括基板100、设于所述基板100上的第一栅极210、及第二栅极220、设于所述第一栅极210、第二栅极220、及基板100上的栅极绝缘层300、位于所述第一栅极210上方设于所述栅极绝缘层300上的第一半导体层410、位于所述第二栅极220上方设于所述栅极绝缘层300上的第二半导体层420、设于所述第一半导体层410、第二半导体层420、及栅极绝缘层300上的蚀刻阻挡层500、位于所述第一栅极210上方设于所述蚀刻阻挡层500上的第一源极610、及第一漏极620、位于所述第二栅极220上方设于所述蚀刻阻挡层500上的第二源极630、及第二漏极640、设于所述第一源极610、第一漏极620、第二源极630、及第二漏极640、及蚀刻阻挡层500上的钝化层710、设于所述钝化层710上的平坦层720、设于所述平坦层720上的像素电极层800、设于所述像素电极层800与平坦层720上的像素定义层900、及设于所述像素定义层900上的光阻间隙物920。
所述蚀刻阻挡层500上对应所述第一半导体层410上方设有两个第一过孔510，所述蚀刻阻挡层500上对应所述第二半导体层420上方设有两个第二过孔520，所述蚀刻阻挡层500、及栅极绝缘层300上对应所述第二栅极220上方靠近第一栅极210的一侧设有第三过孔530，所述钝化层710、 及平坦层720上对应所述第二源极630上方设有第四过孔810，所述像素定义层900上方对应所述像素电极层800上方设有第五过孔910。
所述第一源极610、第一漏极620分别经由所述第一过孔510与所述第一半导体层410相接触，所述第二源极630、第二漏极640分别经由所述第二过孔520与所述第二半导体层420相接触，所述第一源极610经由所述第三过孔530与所述第二栅极220相接触，所述像素电极层800经由所述第四过孔810与所述第二源极630相接触，所述第五过孔910暴露出部分像素电极层800。
其中，所述第一栅极210、及第二栅极220，栅极绝缘层300，第一半导体层410、及第二半导体层420，蚀刻阻挡层500，第一源极610、第一漏极620、第二源极630、及第二漏极640，钝化层710，平坦层720，像素电极层800，像素定义层900，光阻间隙物920中的每一层均需要通过一道光刻制程制作，即制作图1所示的TFT基板总计需要十道光刻制程，制程较为繁琐，影响生产效率及良率。
发明内容
本发明的目的在于提供一种TFT基板的制作方法，制程简单，可有效提高生产效率及良率。
本发明的目的还在于提供一种TFT基板结构，结构简单，易于制作，可有效提高生产效率及良率。
为实现上述目的，本发明提供一种TFT基板的制作方法，包括如下步骤：
步骤1、提供基板，所述基板上设有TFT区域与非TFT区域，在所述基板上沉积第一金属层，并通过第一道光刻制程图案化所述第一金属层，得到间隔设置的第一栅极与第二栅极；
步骤2、在所述第一栅极、第二栅极、及基板上依次沉积栅极绝缘层、半导体层、及蚀刻阻挡层；
步骤3、通过第二道光刻制程对所述栅极绝缘层、半导体层、及蚀刻阻挡层进行图案化处理，在所述蚀刻阻挡层上对应于所述第一栅极的上方形成第一接触孔与第二接触孔，对应于所述第二栅极的上方形成第三接触孔与第四接触孔；在所述蚀刻阻挡层、半导体层、及栅极绝缘层上对应于所述第二栅极上方靠近第一栅极的一侧形成第五接触孔；所述第一接触孔、第二接触孔、第三接触孔、第四接触孔、及第五接触孔均为通孔；
步骤4、在所述蚀刻阻挡层上沉积第二金属层，通过第三道光刻制程图 案化该第二金属层，得到间隔设置的第一源极、第一漏极、第二源极、及第二漏极，所述第一源极、第一漏极、第二源极、及第二漏极分别经由所述第一接触孔、第二接触孔、第三接触孔、第四接触孔与所述半导体层相接触；
所述第一栅极、半导体层、第一源极、及第一漏极构成第一TFT；所述第二栅极、半导体层、第二源极、及第二漏极构成第二TFT；所述第一漏极经由第五接触孔与所述第二栅极相接触，将第一TFT与第二TFT串联起来；
步骤5、在所述第一源极、第一漏极、第二源极、第二漏极、蚀刻阻挡层、及基板上沉积钝化层，并通过第四道光刻制程对所述钝化层进行图案化，在所述钝化层上对应所述第二漏极的上方形成第六通孔；
步骤6、在所述钝化层上沉积平坦层，并通过第五道光刻制程对所述平坦层进行图案化，在所述平坦层上对应第六通孔的上方形成第七通孔；
步骤7、在所述平坦层上沉积像素电极层，并通过第六道光刻制程对其进行图案化，所述像素电极层经由所述第六通孔、及第七通孔与所述第二漏极相接触；
步骤8、在所述像素电极层、及平坦层上沉积像素定义层，并通过第七道光刻制程对其进行图案化，在所述像素定义层上形成对应于所述像素电极层上方的第八通孔，从而暴露出所述像素电极层的一部分；
步骤9、在所述像素定义层上沉积有机光阻层，并通过第八道光刻制程对其进行图案化，形成间隔设置的数个光阻间隙物。
所述步骤3具体包括：
步骤31、在所述蚀刻阻挡层上沉积光阻层，并通过一灰阶光罩对所述光阻层进行曝光、显影，使得光阻层上对应基板上非TFT区域的部分被完全蚀刻掉，且所述光阻层上对应所述第一栅极上方形成有间隔设置的第一凹槽与第二凹槽，对应所述第二栅极上方形成有间隔设置的第三凹槽与第四凹槽，对应所述第二栅极上方靠近第一栅极的一侧形成有第一通孔；
步骤32、以所述光阻层为遮挡，通过第一次干蚀刻制程对所述蚀刻阻挡层进行蚀刻，使得所述蚀刻阻挡层上对应基板上非TFT区域的部分被完全蚀刻掉，所述蚀刻阻挡层上对应于所述光阻层上的第一通孔的部分被完全蚀刻掉；
步骤33、通过一次灰化制程对所述光阻层进行灰化处理，使得所述光阻层的整体厚度降低，所述光阻层上的第一凹槽、第二凹槽、第三凹槽、及第四凹槽的底部被穿透，分别形成第二通孔、第三通孔、第四通孔、及 第五通孔；
步骤34、以所述光阻层为遮挡，通过一次湿蚀刻制程对所述半导体层进行蚀刻，使得所述半导体层上对应基板上非TFT区域的部分被完全蚀刻掉，且所述半导体层上对应于所述光阻层上的第一通孔的部分被完全蚀刻掉；
步骤35、以所述光阻层为遮挡，通过第二次干蚀刻制程对所述蚀刻阻挡层、及栅极绝缘层进行蚀刻，使得所述蚀刻阻挡层上对应于所述光阻层上的第二通孔、第三通孔、第四通孔、及第五通孔的部分被完全蚀刻掉，从而在所述蚀刻阻挡层上形成对应于第一栅极上方的第一接触孔与第二接触孔，及对应于第二栅极上方的第三接触孔与第四接触孔；
同时，所述栅极绝缘层上对应基板上非TFT区域的部分被完全蚀刻掉，且所述栅极绝缘层上对应于所述光阻层上的第一通孔的部分被完全蚀刻掉，从而在所述蚀刻阻挡层、半导体层及栅极绝缘层上对应于所述第二栅极上方靠近第一栅极的一侧形成第五接触孔；
步骤36、剥离所述光阻层。
所述栅极绝缘层的材料为氧化硅或氮化硅，所述半导体层的材料为金属氧化物，所述蚀刻阻挡层的材料为氧化硅或氮化硅。
所述步骤32中第一次干蚀刻制程的具体工艺参数为：当所述蚀刻阻挡层的材料为氧化硅时，采用CF4+O2气氛进行干蚀刻，CF4流量为0～5000sccm，O2流量为0～5000sccm，蚀刻时间为1～1000s；当所述蚀刻阻挡层(5)的材料为氮化硅时，采用SF6+Cl2气氛进行干蚀刻，SF6流量为0～5000sccm，Cl2流量为0～5000sccm，蚀刻时间为1～1000s；
所述步骤33中灰化制程的具体工艺参数为：采用O2气氛进行光阻灰化，O2流量为0～5000sccm，灰化时间为1～1000s；
所述步骤34中湿蚀刻制程的具体工艺参数为：采用H2C2O4溶液进行湿蚀刻，所述H2C2O4溶液的浓度为0.1％～50％mol/L，蚀刻时间为1～1000s；
所述步骤35中第二次干蚀刻制程的具体工艺参数为：当所述蚀刻阻挡层与栅极绝缘层的材料均为氧化硅时，采用CF4+O2气氛进行干蚀刻，CF4流量为0～5000sccm，O2流量为0～5000sccm，蚀刻时间为1～1000s；当所述蚀刻阻挡层与栅极绝缘层的材料均为氮化硅时，采用SF6+Cl2气氛进行干蚀刻，SF6流量为0～5000sccm，Cl2流量为0～5000sccm，蚀刻时间为1～1000s。
所述基板为玻璃基板，所述第一栅极与第二栅极的材料为铜、铝、或钼，所述第一源极、第一漏极、第二源极、及第二漏极的材料为铜、铝、或钼。
本发明还提供一种TFT基板结构，包括基板、设于所述基板上且间隔设置的第一栅极、及第二栅极、设于所述第一栅极、第二栅极、及基板上的栅极绝缘层、设于所述栅极绝缘层上的半导体层、设于所述半导体层上的蚀刻阻挡层、设于所述蚀刻阻挡层上且间隔设置的第一源极、第一漏极、第二源极、及第二漏极、设于所述第一源极、第一漏极、第二源极、及第二漏极上覆盖所述基板的钝化层、设于所述钝化层上的平坦层、设于所述平坦层上的像素电极层、设于所述平坦层、及像素电极层上的像素定义层、及设于所述像素定义层上的光阻间隙物；
所述蚀刻阻挡层上设有对应于第一栅极上方的第一接触孔与第二接触孔，及对应于第二栅极上方的第三接触孔与第四接触孔；所述蚀刻阻挡层、半导体层、及栅极绝缘层上对应所述第二栅极上方靠近第一栅极的一侧设有第五接触孔；所述第一接触孔、第二接触孔、第三接触孔、第四接触孔、及第五接触孔均为通孔；
所述第一源极、第一漏极、第二源极、及第二漏极分别经由所述第一接触孔、第二接触孔、第三接触孔、第四接触孔与所述半导体层相接触；所述第一栅极、半导体层、第一源极、及第一漏极构成第一TFT；所述第二栅极、半导体层、第二源极、及第二漏极构成第二TFT；所述第一漏极经由第五接触孔与所述第二栅极相接触，将第一TFT与第二TFT串联起来；
所述钝化层上对应所述第二漏极的上方设有第六通孔，所述平坦层上对应所述第六通孔的上方设有第七通孔，所述像素电极层经由所述第六通孔、及第七通孔与所述第二漏极相接触；所述像素定义层上设有对应于所述像素电极层上方的第八通孔，所述第八通孔暴露出所述像素电极层的一部分。
所述栅极绝缘层、半导体层、及蚀刻阻挡层通过一道光刻制程制作而成。
所述第一TFT为开关TFT，所述第二TFT为驱动TFT。
所述基板为玻璃基板，所述第一栅极与第二栅极的材料为铜、铝、或钼，所述栅极绝缘层的材料为氧化硅或氮化硅，所述半导体层的材料为金属氧化物；所述半导体层的材料为金属氧化物。
所述蚀刻阻挡层的材料为氧化硅或氮化硅，所述第一源极、第一漏极、第二源极、及第二漏极的材料为铜、铝、或钼。
本发明还提供一种TFT基板结构，包括基板、设于所述基板上且间隔设置的第一栅极、及第二栅极、设于所述第一栅极、第二栅极、及基板上的栅极绝缘层、设于所述栅极绝缘层上的半导体层、设于所述半导体层上 的蚀刻阻挡层、设于所述蚀刻阻挡层上且间隔设置的第一源极、第一漏极、第二源极、及第二漏极、设于所述第一源极、第一漏极、第二源极、及第二漏极上覆盖所述基板的钝化层、设于所述钝化层上的平坦层、设于所述平坦层上的像素电极层、设于所述平坦层、及像素电极层上的像素定义层、及设于所述像素定义层上的光阻间隙物；
所述蚀刻阻挡层上设有对应于第一栅极上方的第一接触孔与第二接触孔，及对应于第二栅极上方的第三接触孔与第四接触孔；所述蚀刻阻挡层、半导体层、及栅极绝缘层上对应所述第二栅极上方靠近第一栅极的一侧设有第五接触孔；所述第一接触孔、第二接触孔、第三接触孔、第四接触孔、及第五接触孔均为通孔；
所述第一源极、第一漏极、第二源极、及第二漏极分别经由所述第一接触孔、第二接触孔、第三接触孔、第四接触孔与所述半导体层相接触；所述第一栅极、半导体层、第一源极、及第一漏极构成第一TFT；所述第二栅极、半导体层、第二源极、及第二漏极构成第二TFT；所述第一漏极经由第五接触孔与所述第二栅极相接触，将第一TFT与第二TFT串联起来；
所述钝化层上对应所述第二漏极的上方设有第六通孔，所述平坦层上对应所述第六通孔的上方设有第七通孔，所述像素电极层经由所述第六通孔、及第七通孔与所述第二漏极相接触；所述像素定义层上设有对应于所述像素电极层上方的第八通孔，所述第八通孔暴露出所述像素电极层的一部分；
其中，所述栅极绝缘层、半导体层、及蚀刻阻挡层通过一道光刻制程制作而成；
其中，所述第一TFT为开关TFT，所述第二TFT为驱动TFT。
本发明的有益效果：本发明的TFT基板的制作方法，通过使用灰阶光罩，将栅极绝缘层、半导体层、及蚀刻阻挡层通过一道光刻制程一同制作，将光刻制程的次数由十道减少至八道，减少了光罩的使用量，简化了生产制程，有效提高了生产效率及良率。本发明的TFT基板结构，栅极绝缘层、半导体层、及蚀刻阻挡层可使用灰阶光罩通过一道光刻制程一同制作，结构简单，易于制作，可有效提高生产效率及良率。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种现有的应用于AMOLED的TFT基板结构的剖面示意图；
图2为本发明的TFT基板的制作方法的步骤1的示意图；
图3为本发明的TFT基板的制作方法的步骤2的示意图；
图4-5为本发明的TFT基板的制作方法的步骤31的示意图；
图6为本发明的TFT基板的制作方法的步骤32的示意图；
图7为本发明的TFT基板的制作方法的步骤33的示意图；
图8为本发明的TFT基板的制作方法的步骤34的示意图；
图9为本发明的TFT基板的制作方法的步骤35的示意图；
图10为本发明的TFT基板的制作方法的步骤36的示意图；
图11为本发明的TFT基板的制作方法的步骤4的示意图；
图12为本发明的TFT基板的制作方法的步骤5的示意图；
图13为本发明的TFT基板的制作方法的步骤6的示意图；
图14为本发明的TFT基板的制作方法的步骤7的示意图；
图15为本发明的TFT基板的制作方法的步骤8的示意图；
图16为本发明的TFT基板的制作方法的步骤9的示意图暨本发明TFT基板结构的剖面示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2-14，本发明提供一种TFT基板的制作方法，包括如下步骤：
步骤1、如图2所示，提供基板1，所述基板1上设有TFT区域与非TFT区域，在所述基板1上沉积第一金属层，并通过第一道光刻制程图案化所述第一金属层，得到间隔设置的第一栅极21与第二栅极22。
具体的，所述基板1为玻璃基板。
所述第一栅极21与第二栅极22的材料为铜、铝、或钼。
步骤2、如图3所示，在所述第一栅极21、第二栅极22、及基板1上依次沉积栅极绝缘层3、半导体层4、及蚀刻阻挡层5。
具体的，所述栅极绝缘层3的材料为氧化硅(SiOx)或氮化硅(SiNx)。
所述半导体层4的材料为金属氧化物，优选的，所述金属氧化物为IGZO(铟镓锌氧化物)或IZO(氧化铟锌)。
所述蚀刻阻挡层5的材料为氧化硅或氮化硅。
步骤3、如图4-10所示，通过第二道光刻制程对所述栅极绝缘层3、半导体层4、及蚀刻阻挡层5进行图案化处理，在所述蚀刻阻挡层5上对应于所述第一栅极21的上方形成第一接触孔51与第二接触孔52，对应于所述第二栅极22的上方形成第三接触孔53与第四接触孔54；在所述蚀刻阻挡层5、半导体层4、及栅极绝缘层3上对应于所述第二栅极22上方靠近第一栅极21的一侧形成第五接触孔55；所述第一接触孔51、第二接触孔52、第三接触孔53、第四接触孔54、及第五接触孔55均为通孔。
具体的，所述步骤3包括以下步骤：
步骤31、如图4-5所示，在所述蚀刻阻挡层5上沉积光阻层6，并通过一灰阶光罩10对所述光阻层6进行曝光、显影，使得光阻层6上对应基板1上非TFT区域的部分被完全蚀刻掉，且所述光阻层6上对应所述第一栅极21上方形成有间隔设置的第一凹槽61与第二凹槽62，对应所述第二栅极22上方形成有间隔设置的第三凹槽63与第四凹槽64，对应所述第二栅极22上方靠近第一栅极21的一侧形成有第一通孔65；
步骤32、如图6所示，以所述光阻层6为遮蔽层，通过第一次干蚀刻制程对所述蚀刻阻挡层5进行蚀刻，使得所述蚀刻阻挡层5上对应基板1上非TFT区域的部分被完全蚀刻掉，所述蚀刻阻挡层5上对应于所述光阻层6上的第一通孔65的部分被完全蚀刻掉；
所述第一次干蚀刻制程的具体工艺参数为：
当所述蚀刻阻挡层5与栅极绝缘层3的材料均为氧化硅时，可采用CF4(四氟化碳)+O2(氧气)气氛进行干蚀刻，CF4流量为0～5000sccm，O2流量为0～5000sccm，蚀刻时间为1～1000s；
当所述蚀刻阻挡层5与栅极绝缘层3的材料均为氮化硅时，可采用SF6(六氟化硫)+Cl2(氯气)气氛进行干蚀刻，SF6流量为0～5000sccm，Cl2流量为0～5000sccm，蚀刻时间为1～1000s。
步骤33、如图7所示，通过一次灰化制程对所述光阻层6进行灰化处理，使得所述光阻层6的整体厚度降低，所述光阻层6上的第一凹槽61、第二凹槽62、第三凹槽63、及第四凹槽64的底部被穿透，分别形成第二通孔66、第三通孔67、第四通孔68、及第五通孔69；
所述灰化制程的具体工艺参数为：采用O2气氛进行光阻灰化，O2流量为0～5000sccm，灰化时间为1～1000s。
步骤34、如图8所示，以所述光阻层6为遮蔽层，通过一次湿蚀刻制程对所述半导体层4进行蚀刻，使得所述半导体层4上对应基板1上非TFT 区域的部分被完全蚀刻掉，且所述半导体层4上对应于所述光阻层6上的第一通孔65的部分被完全蚀刻掉；
所述湿蚀刻制程的具体工艺参数为：采用H2C2O4(草酸)溶液进行湿蚀刻，所述H2C2O4溶液的浓度为0.1％～50％mol/L，蚀刻时间为1～1000s。
步骤35、如图9所示，以所述光阻层6为遮蔽层，通过第二次干蚀刻制程对所述蚀刻阻挡层5、及栅极绝缘层3进行蚀刻，使得所述蚀刻阻挡层5上对应于所述光阻层6上的第二通孔66、第三通孔67、第四通孔68、及第五通孔69的部分被完全蚀刻掉，从而在所述蚀刻阻挡层5上形成对应于第一栅极21上方的第一接触孔51与第二接触孔52，及对应于第二栅极22上方的第三接触孔53与第四接触孔54；
同时，所述栅极绝缘层3上对应基板1上非TFT区域的部分被完全蚀刻掉，且所述栅极绝缘层3上对应于所述光阻层6上的第一通孔65的部分被完全蚀刻掉，从而在所述蚀刻阻挡层5、半导体层4及栅极绝缘层3上对应于所述第二栅极22上方靠近第一栅极21的一侧形成第五接触孔55；
所述第二次干蚀刻制程的具体工艺参数为：
当所述蚀刻阻挡层5的材料为氧化硅时，可采用CF4+O2气氛进行干蚀刻，CF4流量为0～5000sccm，O2流量为0～5000sccm，蚀刻时间为1～1000s；
当所述蚀刻阻挡层5的材料为氮化硅时，可采用SF6+Cl2气氛进行干蚀刻，SF6流量为0～5000sccm，Cl2流量为0～5000sccm，蚀刻时间为1～1000s。步骤36、如图10所示，剥离所述光阻层6。
所述步骤3通过采用一灰阶光罩，将栅极绝缘层3、半导体层4、及蚀刻阻挡层5的图案通过一道光刻制程制作而成，减少了TFT基板的制作过程中光罩的使用量，简化了生产制程，可有效提高生产效率及良率。
步骤4、如图11所示，在所述蚀刻阻挡层5上沉积第二金属层，通过第三道光刻制程图案化该第二金属层，得到间隔设置的第一源极71、第一漏极72、第二源极73、及第二漏极74，所述第一源极71、第一漏极72、第二源极73、及第二漏极74分别经由所述第一接触孔51、第二接触孔52、第三接触孔53、第四接触孔54与所述半导体层4相接触；
所述第一栅极21、半导体层4、第一源极71、及第一漏极72构成第一TFT；所述第二栅极22、半导体层4、第二源极73、及第二漏极74构成第二TFT；所述第一漏极72经由第五接触孔55与所述第二栅极22相接触，将第一TFT与第二TFT串联起来。
具体的，所述第一源极71、第一漏极72、第二源极73、及第二漏极74的材料为铜、铝、或钼。
步骤5、如图12所示，在所述第一源极71、第一漏极72、第二源极73、第二漏极74、蚀刻阻挡层5、及基板1上沉积钝化层75，并通过第四道光刻制程对所述钝化层75进行图案化，在所述钝化层75上对应所述第二漏极74的上方形成第六通孔751。
具体的，所述钝化层75的材料为氮化硅或氧化硅。
步骤6、如图13所示，在所述钝化层75上沉积平坦层76，并通过第五道光刻制程对所述平坦层76进行图案化，在所述平坦层76上对应所述第六通孔751的上方形成第六通孔761。
具体的，所述平坦层76的材料为有机光阻。
步骤7、如图14所示，在所述平坦层76上沉积像素电极层8，并通过第六道光刻制程对其进行图案化，所述像素电极层8经由所述第六通孔751、及第七通孔761与所述第二漏极64相接触。
具体的，所述像素电极层8的材料为ITO(氧化铟锡)。
步骤8、如图15所示，在所述像素电极层8、及平坦层76上沉积像素定义层9，并通过第七道光刻制程对其进行图案化，在所述像素定义层9上形成对应于所述像素电极层8上方的第八通孔91，从而暴露出所述像素电极层8的一部分。
步骤9、如图16所示，在所述像素定义层9上沉积有机光阻层，并通过第八道光刻制程对其进行图案化，形成间隔设置的数个光阻间隙物92。
上述TFT基板的制作方法，通过使用灰阶光罩，将栅极绝缘层、半导体层、及蚀刻阻挡层通过一道光刻制程一同制作，将光刻制程的次数由十道减少至八道，简化了制程，有效提高了生产效率及良率。
请参阅图16，本发明还提供一种TFT基板结构，包括基板1、设于所述基板1上且间隔设置的第一栅极21、及第二栅极22、设于所述第一栅极21、第二栅极22、及基板1上的栅极绝缘层3、设于所述栅极绝缘层3上的半导体层4、设于所述半导体层4上的蚀刻阻挡层5、设于所述蚀刻阻挡层5上且间隔设置的第一源极71、第一漏极72、第二源极73、及第二漏极74、设于所述第一源极71、第一漏极72、第二源极73、及第二漏极74上覆盖所述基板1的钝化层75、设于所述钝化层75上的平坦层76、设于所述平坦层76上的像素电极层8、设于所述平坦层76、及像素电极层8上的像素定义层9、及设于所述像素定义层9上的光阻间隙物92。
所述蚀刻阻挡层5上设有对应于第一栅极21上方的第一接触孔51与第二接触孔52，及对应于第二栅极22上方的第三接触孔53与第四接触孔54；所述蚀刻阻挡层5、半导体层4、及栅极绝缘层3上对应所述第二栅极 22的上方靠近第一栅极21的一侧设有第五接触孔55；所述第一接触孔51、第二接触孔52、第三接触孔53、第四接触孔54、及第五接触孔55均为通孔；
所述第一源极71、第一漏极72、第二源极73、及第二漏极74分别经由所述第一接触孔51、第二接触孔52、第三接触孔53、第四接触孔54与所述半导体层4相接触；所述第一栅极21、半导体层4、第一源极71、及第一漏极72构成第一TFT；所述第二栅极22、半导体层4、第二源极73、及第二漏极74构成第二TFT；所述第一漏极72经由第五接触孔55与所述第二栅极22相接触，将第一TFT与第二TFT串联起来；
所述钝化层75上对应所述第二漏极74的上方设有第六通孔751，所述平坦层76上对应第六通孔751的的上方设有第七通孔761，所述像素电极层8经由所述第六通孔751、及第七通孔761与所述第二漏极74相接触；所述像素定义层9上设有对应于所述像素电极层8上方的第八通孔91，所述第八通孔91暴露出所述像素电极层8的一部分。
具体的，所述栅极绝缘层3、半导体层4、及蚀刻阻挡层5通过一道光刻制程制作而成。
具体的，所述第一TFT为开关TFT，所述第二TFT为驱动TFT。
优选的，所述基板1为玻璃基板，所述第一栅极21与第二栅极22的材料为铜、铝、或钼，所述栅极绝缘层3的材料为氧化硅或氮化硅。
具体的，所述半导体层4的材料为金属氧化物，优选的，所述金属氧化物为IGZO(铟镓锌氧化物)或IZO(氧化铟锌)。
所述蚀刻阻挡层5的材料为氧化硅或氮化硅。
具体的，所述第一源极71、第一漏极72、第二源极73、及第二漏极74的材料为铜、铝、或钼。
具体的，所述钝化层75的材料为氮化硅或氧化硅。
具体的，所述平坦层76的材料为有机光阻。
所述像素电极层8的材料为ITO。
上述TFT基板结构，栅极绝缘层、半导体层、及蚀刻阻挡层可使用灰阶光罩通过一道光刻制程一同制作，结构简单，易于制作，可有效提高生产效率及良率。
综上所述，本发明的TFT基板的制作方法，通过使用灰阶光罩，将栅极绝缘层、半导体层、及蚀刻阻挡层通过一道光刻制程一同制作，将光刻制程的次数由十道减少至八道，减少了光罩的使用量，简化了生产制程，有效提高了生产效率及良率。本发明的TFT基板结构，其中的栅极绝缘层、 半导体层、及蚀刻阻挡层可使用灰阶光罩通过一道光刻制程一同制作，结构简单，易于制作，可有效提高生产效率及良率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (13)

  1. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供基板，所述基板上设有TFT区域与非TFT区域，在所述基板上沉积第一金属层，并通过第一道光刻制程图案化所述第一金属层，得到间隔设置的第一栅极与第二栅极；
    步骤2、在所述第一栅极、第二栅极、及基板上依次沉积栅极绝缘层、半导体层、及蚀刻阻挡层；
    步骤3、通过第二道光刻制程对所述栅极绝缘层、半导体层、及蚀刻阻挡层进行图案化处理，在所述蚀刻阻挡层上对应于所述第一栅极的上方形成第一接触孔与第二接触孔，对应于所述第二栅极的上方形成第三接触孔与第四接触孔；在所述蚀刻阻挡层、半导体层、及栅极绝缘层上对应于所述第二栅极上方靠近第一栅极的一侧形成第五接触孔；所述第一接触孔、第二接触孔、第三接触孔、第四接触孔、及第五接触孔均为通孔；
    步骤4、在所述蚀刻阻挡层上沉积第二金属层，通过第三道光刻制程图案化该第二金属层，得到间隔设置的第一源极、第一漏极、第二源极、及第二漏极，所述第一源极、第一漏极、第二源极、及第二漏极分别经由所述第一接触孔、第二接触孔、第三接触孔、第四接触孔与所述半导体层相接触；
    所述第一栅极、半导体层、第一源极、及第一漏极构成第一TFT；所述第二栅极、半导体层、第二源极、及第二漏极构成第二TFT；所述第一漏极经由第五接触孔与所述第二栅极相接触，将第一TFT与第二TFT串联起来；
    步骤5、在所述第一源极、第一漏极、第二源极、第二漏极、蚀刻阻挡层、及基板上沉积钝化层，并通过第四道光刻制程对所述钝化层进行图案化，在所述钝化层上对应所述第二漏极的上方形成第六通孔；
    步骤6、在所述钝化层上沉积平坦层，并通过第五道光刻制程对所述平坦层进行图案化，在所述平坦层对应所述第六通孔的上方形成第七通孔；
    步骤7、在所述平坦层上沉积像素电极层，并通过第六道光刻制程对其进行图案化，所述像素电极层经由所述第六通孔、及第七通孔与所述第二漏极相接触；
    步骤8、在所述像素电极层、及平坦层上沉积像素定义层，并通过第七道光刻制程对其进行图案化，在所述像素定义层上形成对应于所述像素电 极层上方的第八通孔，从而暴露出所述像素电极层的一部分；
    步骤9、在所述像素定义层上沉积有机光阻层，并通过第八道光刻制程对其进行图案化，形成间隔设置的数个光阻间隙物。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤3具体包括：
    步骤31、在所述蚀刻阻挡层上沉积光阻层，并通过一灰阶光罩对所述光阻层进行曝光、显影，使得光阻层上对应基板上非TFT区域的部分被完全蚀刻掉，且所述光阻层上对应所述第一栅极上方形成有间隔设置的第一凹槽与第二凹槽，对应所述第二栅极上方形成有间隔设置的第三凹槽与第四凹槽，对应所述第二栅极上方靠近第一栅极的一侧形成有第一通孔；
    步骤32、以所述光阻层为遮蔽层，通过第一次干蚀刻制程对所述蚀刻阻挡层进行蚀刻，使得所述蚀刻阻挡层上对应基板上非TFT区域的部分被完全蚀刻掉，所述蚀刻阻挡层上对应于所述光阻层上的第一通孔的部分被完全蚀刻掉；
    步骤33、通过一次灰化制程对所述光阻层进行灰化处理，使得所述光阻层的整体厚度降低，所述光阻层上的第一凹槽、第二凹槽、第三凹槽及第四凹槽的底部被穿透，分别形成第二通孔、第三通孔、第四通孔、及第五通孔；
    步骤34、以所述光阻层为遮蔽层，通过一次湿蚀刻制程对所述半导体层进行蚀刻，使得所述半导体层上对应基板上非TFT区域的部分被完全蚀刻掉，且所述半导体层上对应于所述光阻层上的第一通孔的部分被完全蚀刻掉；
    步骤35、以所述光阻层为遮蔽层，通过第二次干蚀刻制程对所述蚀刻阻挡层、及栅极绝缘层进行蚀刻，使得所述蚀刻阻挡层上对应于所述光阻层上的第二通孔、第三通孔、第四通孔、及第五通孔的部分被完全蚀刻掉，从而在所述蚀刻阻挡层上形成对应于第一栅极上方的第一接触孔与第二接触孔，及对应于第二栅极上方的第三接触孔与第四接触孔；
    同时，所述栅极绝缘层上对应基板上非TFT区域的部分被完全蚀刻掉，且所述栅极绝缘层对应于所述光阻层上的第一通孔的部分被完全蚀刻掉，从而在所述蚀刻阻挡层、半导体层及栅极绝缘层对应于所述第二栅极上方靠近第一栅极的一侧形成第五接触孔；
    步骤36、剥离所述光阻层。
  3. 如权利要求2所述的TFT基板的制作方法，其中，所述栅极绝缘层的材料为氧化硅或氮化硅，所述半导体层的材料为金属氧化物，所述蚀刻 阻挡层的材料为氧化硅或氮化硅。
  4. 如权利要求3所述的TFT基板的制作方法，其中，所述步骤32中第一次干蚀刻制程的具体工艺参数为：当所述蚀刻阻挡层的材料为氧化硅时，采用CF4+O2气氛进行干蚀刻，CF4流量为0～5000sccm，O2流量为0～5000sccm，蚀刻时间为1～1000s；当所述蚀刻阻挡层的材料为氮化硅时，采用SF6+Cl2气氛进行干蚀刻，SF6流量为0～5000sccm，Cl2流量为0～5000sccm，蚀刻时间为1～1000s；
    所述步骤33中灰化制程的具体工艺参数为：采用O2气氛进行光阻灰化，O2流量为0～5000sccm，灰化时间为1～1000s；
    所述步骤34中湿蚀刻制程的具体工艺参数为：采用H2C2O4溶液进行湿蚀刻，所述H2C2O4溶液的浓度为0.1％～50％mol/L，蚀刻时间为1～1000s；
    所述步骤35中第二次干蚀刻制程的具体工艺参数为：当所述蚀刻阻挡层与栅极绝缘层的材料均为氧化硅时，采用CF4+O2气氛进行干蚀刻，CF4流量为0～5000sccm，O2流量为0～5000sccm，蚀刻时间为1～1000s；当所述蚀刻阻挡层与栅极绝缘层的材料均为氮化硅时，采用SF6+Cl2气氛进行干蚀刻，SF6流量为0～5000sccm，Cl2流量为0～5000sccm，蚀刻时间为1～1000s。
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述基板为玻璃基板，所述第一栅极与第二栅极的材料为铜、铝、或钼，所述第一源极、第一漏极、第二源极、及第二漏极的材料为铜、铝、或钼。
  6. 一种TFT基板结构，包括基板、设于所述基板上且间隔设置的第一栅极、及第二栅极、设于所述第一栅极、第二栅极、及基板上的栅极绝缘层、设于所述栅极绝缘层上的半导体层、设于所述半导体层上的蚀刻阻挡层、设于所述蚀刻阻挡层上且间隔设置的第一源极、第一漏极、第二源极、及第二漏极、设于所述第一源极、第一漏极、第二源极、及第二漏极上覆盖所述基板的钝化层、设于所述钝化层上的平坦层、设于所述平坦层上的像素电极层、设于所述平坦层、及像素电极层上的像素定义层、及设于所述像素定义层上的光阻间隙物；
    所述蚀刻阻挡层上设有对应于第一栅极上方的第一接触孔与第二接触孔，及对应于第二栅极上方的第三接触孔与第四接触孔；所述蚀刻阻挡层、半导体层、及栅极绝缘层上对应所述第二栅极上方靠近第一栅极的一侧设有第五接触孔；所述第一接触孔、第二接触孔、第三接触孔、第四接触孔、及第五接触孔均为通孔；
    所述第一源极、第一漏极、第二源极、及第二漏极分别经由所述第一接触孔、第二接触孔、第三接触孔、第四接触孔与所述半导体层相接触； 所述第一栅极、半导体层、第一源极、及第一漏极构成第一TFT；所述第二栅极、半导体层、第二源极、及第二漏极构成第二TFT；所述第一漏极经由第五接触孔与所述第二栅极相接触，将第一TFT与第二TFT串联起来；
    所述钝化层上对应所述第二漏极的上方设有第六通孔，所述平坦层上对应所述第六通孔的上方设有第七通孔，所述像素电极层经由所述第六通孔、及第七通孔与所述第二漏极相接触；所述像素定义层上设有对应于所述像素电极层上方的第八通孔，所述第八通孔暴露出所述像素电极层的一部分。
  7. 如权利要求6所述的TFT基板结构，其中，所述栅极绝缘层、半导体层、及蚀刻阻挡层通过一道光刻制程制作而成。
  8. 如权利要求6所述的TFT基板结构，其中，所述第一TFT为开关TFT，所述第二TFT为驱动TFT。
  9. 如权利要求6所述的TFT基板结构，其中，所述基板为玻璃基板，所述第一栅极与第二栅极的材料为铜、铝、或钼，所述栅极绝缘层的材料为氧化硅或氮化硅，所述半导体层的材料为金属氧化物；所述半导体层的材料为金属氧化物。
  10. 如权利要求6所述的TFT基板结构，其中，所述蚀刻阻挡层的材料为氧化硅或氮化硅，所述第一源极、第一漏极、第二源极、及第二漏极的材料为铜、铝、或钼。
  11. 一种TFT基板结构，包括基板、设于所述基板上且间隔设置的第一栅极、及第二栅极、设于所述第一栅极、第二栅极、及基板上的栅极绝缘层、设于所述栅极绝缘层上的半导体层、设于所述半导体层上的蚀刻阻挡层、设于所述蚀刻阻挡层上且间隔设置的第一源极、第一漏极、第二源极、及第二漏极、设于所述第一源极、第一漏极、第二源极、及第二漏极上覆盖所述基板的钝化层、设于所述钝化层上的平坦层、设于所述平坦层上的像素电极层、设于所述平坦层、及像素电极层上的像素定义层、及设于所述像素定义层上的光阻间隙物；
    所述蚀刻阻挡层上设有对应于第一栅极上方的第一接触孔与第二接触孔，及对应于第二栅极上方的第三接触孔与第四接触孔；所述蚀刻阻挡层、半导体层、及栅极绝缘层上对应所述第二栅极上方靠近第一栅极的一侧设有第五接触孔；所述第一接触孔、第二接触孔、第三接触孔、第四接触孔、及第五接触孔均为通孔；
    所述第一源极、第一漏极、第二源极、及第二漏极分别经由所述第一接触孔、第二接触孔、第三接触孔、第四接触孔与所述半导体层相接触； 所述第一栅极、半导体层、第一源极、及第一漏极构成第一TFT；所述第二栅极、半导体层、第二源极、及第二漏极构成第二TFT；所述第一漏极经由第五接触孔与所述第二栅极相接触，将第一TFT与第二TFT串联起来；
    所述钝化层上对应所述第二漏极的上方设有第六通孔，所述平坦层上对应所述第六通孔的上方设有第七通孔，所述像素电极层经由所述第六通孔、及第七通孔与所述第二漏极相接触；所述像素定义层上设有对应于所述像素电极层上方的第八通孔，所述第八通孔暴露出所述像素电极层的一部分；
    其中，所述栅极绝缘层、半导体层、及蚀刻阻挡层通过一道光刻制程制作而成；
    其中，所述第一TFT为开关TFT，所述第二TFT为驱动TFT。
  12. 如权利要求11所述的TFT基板结构，其中，所述基板为玻璃基板，所述第一栅极与第二栅极的材料为铜、铝、或钼，所述栅极绝缘层的材料为氧化硅或氮化硅，所述半导体层的材料为金属氧化物；所述半导体层的材料为金属氧化物。
  13. 如权利要求11所述的TFT基板结构，其中，所述蚀刻阻挡层的材料为氧化硅或氮化硅，所述第一源极、第一漏极、第二源极、及第二漏极的材料为铜、铝、或钼。
PCT/CN2015/079376 2015-04-29 2015-05-20 Tft基板的制作方法及其结构 Ceased WO2016173011A1 (zh)

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