WO2016170678A1 - 半導体装置およびマルチチップモジュール - Google Patents
半導体装置およびマルチチップモジュール Download PDFInfo
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- WO2016170678A1 WO2016170678A1 PCT/JP2015/062514 JP2015062514W WO2016170678A1 WO 2016170678 A1 WO2016170678 A1 WO 2016170678A1 JP 2015062514 W JP2015062514 W JP 2015062514W WO 2016170678 A1 WO2016170678 A1 WO 2016170678A1
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- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
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- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
- G01R31/67—Testing the correctness of wire connections in electric apparatus or circuits
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- G01R31/52—Testing for short-circuits, leakage current or ground faults
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- G01R31/54—Testing for continuity
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Definitions
- This disclosure relates to a technology for monitoring a connection state of a wiring path and identifying an abnormal portion in a semiconductor LSI, a semiconductor LSI package, and a printed wiring board used in information devices, control devices for infrastructure, automobiles, and the like.
- wiring for connecting the chips in the package is provided. If there is a defect in this wiring, even if there is no defect in each chip, it becomes a defective product as a multichip module.
- Patent Document 1 JP-A-2008-122338
- This publication describes a method for inspecting wiring between circuit blocks and a circuit for facilitating inspection.
- a test pin is provided so that a signal can be applied from the outside of the IC to the cathode of the diode connected to the V DD side in the input protection circuit of IC # i + 1 to be inspected, and changed to an easy-to-inspect input protection circuit is doing.
- the inspection pin of the inspection target IC # i + 1 is connected to the GND via the resistor Rm, and the failure excitation input “H level” is output from the boundary scan flip-flop to the output pin d of the connection target IC # i. .
- Current flows along the current path from the power supply voltage supply pin of IC # i to the resistor Rm to the inspection target wiring (wiring between the pin e of IC # i + 1 and the pin d of IC # i). .
- This current is measured, and if there is an abnormality in the current, it is determined that there is a failure. It has the feature that it can also identify the location of failure.
- SiP System Package
- HBM High Bandwidth Memory
- JEDEC JEDEC
- LSIs mounted on the interposer are connected with about 20 ⁇ m diameter solder called micro bumps, and breakage and poor connection are problems in mounting.
- Patent Document 1 The inspection technique disclosed in Patent Document 1 can be used to monitor the state of breakage of the microbump. Specifically, as the breakage of the microbump portion proceeds, the electrical resistance of the microbump portion increases, so that the voltage generated in the external resistor portion is lowered when a static current is passed, and the breakage state can be visualized. .
- the state of the wiring is visualized by connecting the wiring part (micro bump part) to be inspected and an external voltage observation resistor in series. Therefore, it is effective for the target connected 1: 1 like the signal wiring, but the test of the wiring part connected to many target pins through many paths from one pin like power supply / ground is possible. There was a problem that it was difficult in principle.
- the signal pins 51-1 to 51-4 for data signals, the power supply pin 52-1 and the ground pins 53-1 and 53-2 have the bump arrangement as shown in FIG.
- the ratio of the numbers is 4: 1: 2. Therefore, since the number of power supplies and grounds is small relative to the number of signals, if even one breaks, the power supply impedance around the broken part increases and the power supply noise of the input / output circuit deteriorates. State grasping is also an important factor for ensuring operational reliability.
- the bump connection part causes the breakage of the connection part due to the mounting state of the LSI and the current distribution during operation mounted on the product, it is indispensable to monitor the state of the apparatus during operation.
- a semiconductor LSI package that constitutes a System Package (SiP) is mounted on a product by a multichip module, and an additional circuit to the semiconductor LSI is added to ensure the operational reliability of the semiconductor LSI during product operation.
- SiP System Package
- an inspection circuit that grasps the electrical / physical connection status of signals, power supplies, and ground pins while the equipment is operating, while minimizing it.
- a semiconductor device includes a first circuit block having first and second output circuits, and a second circuit block having first and second input circuits.
- the output pin from the first output circuit and the input pin to the first input circuit are connected by wiring, and the output pin from the second output circuit and the input pin to the second input circuit are wired
- a step of switching from a low to a high logic input to the first output circuit and a low to high input to the second output circuit A wave logic input is given, and the power supply fluctuation waveform branched by the path switching circuit in the previous stage of the first input circuit is observed by the voltage observation circuit to check the connection state of the power supply pins.
- the first output circuit has a logic input for transitioning from Low ⁇ High ⁇ Low, and the DC resistance is measured during the High period.
- a logic input that is fixed for a sufficient time (in the order of ⁇ s) is given, and a power supply fluctuation waveform branched by a path switching circuit in the previous stage of the first input circuit is observed by the voltage observation circuit, and the first The connection state of the wiring path that connects the output pin from the output circuit and the input pin to the first input circuit is inspected.
- a multichip module includes a first semiconductor LSI having first and second output circuits, and a second semiconductor circuit having first and second input circuits.
- a semiconductor LSI, an output pin from the first output circuit and an input pin to the first input circuit are connected by wiring, and an output pin from the second output circuit and an input to the second input circuit And a power supply pin and a ground pin of the first and second semiconductor LSIs that supply power to the output circuits and the input circuits.
- the second semiconductor LSI includes a path switching circuit in front of each input circuit, a resistance switch at the end of the path branched by the path switching circuit, and Resistance cut off And configured to have a voltage monitoring circuit for monitoring the voltage across the resistor in place unit.
- a means for monitoring the connection state of the power supply, the ground, and the signal pin while the apparatus is operating is provided.
- Such means can be applied to a wide variety of semiconductor products such as information equipment, infrastructure control equipment, and in-vehicle equipment.
- FIG. 10 is a circuit diagram of an example of a conventional technique described in Patent Document 1.
- FIG. It is an example of bump arrangement of a semiconductor LSI to be inspected.
- FIG. 2 shows an example of a power supply fluctuation waveform when monitoring the connection state of the power supply / ground pin in the first embodiment.
- FIG. 5 is a configuration diagram of a third embodiment when the present invention is applied to a 3D stacked LSI. It is a fourth embodiment and is a configuration diagram when the present invention is applied to a normal semiconductor package. It is one of the implementation examples of the voltage observation circuit which is one of the basic configurations of the present invention, and is a circuit for digitizing voltage waveform information. It is one of the implementation examples of the voltage observation circuit which is one of the basic configurations of the present invention, and is a circuit for detecting a voltage drop amount.
- notations such as “first”, “second”, and “third” are attached to identify the constituent elements, and do not necessarily limit the number or order.
- a number for identifying a component is used for each context, and a number used in one context does not necessarily indicate the same configuration in another context. Further, it does not preclude that a component identified by a certain number also functions as a component identified by another number.
- FIG. 8 a basic circuit configuration in a first example is shown in FIG.
- SiP System-in Package
- a Si interposer A circuit is proposed for monitoring all signal connections via the power supply 11 and the connection state between the power supply VDDQ supplied from the Si interposer 11 and the ground potential VSSQ.
- FIG. 1 shows a configuration in which a first circuit block 1 and a second circuit block 2 are electrically connected via a wiring block 11 as a broader expression. Power is supplied to the first circuit block 1 and the second circuit block 2 through the wiring block 11.
- the first circuit block 1 includes output circuits 9-1 and 9-2
- the second circuit block 2 includes input circuits 10-1 and 10-2.
- the same configuration can be realized in the case of bidirectional communication having both input and output circuits.
- two signal systems are described as representatives (corresponding to an arrangement of four bumps indicated by 54 in the example of the bump arrangement shown in FIG. 3). However, even if there are more signal systems than this, it can be realized with the same configuration.
- the path switching circuit 7-1, 7-2 are arranged in front of the input circuits 10-1 and 10-2.
- the path switching circuits 7-1 and 7-2 are connected to the output path to the receiver circuits 10-1 and 10-2 and to the resistance switch 6 with respect to the input from the left side (first circuit block 1) in the figure.
- the output path is switched by input from the control circuit 8.
- the resistance switch 6 also has a voltage observation circuit 5 for monitoring the voltage across the resistor.
- all circuits other than the output circuits 9-1 and 9-2 are collectively described as internal circuits.
- internal circuits connected after the input circuits 10-1 and 10-2 are not shown.
- Figure 4 shows an example of the configuration of the path switching circuits 7-1 and 7-2.
- This circuit has a 1-input 2-output configuration as shown in FIG. 4A, and the path and switching timing are controlled by an external control signal or clock.
- pass transistors 30-1 to 30-3 are used to control the path and input / output availability by a 2-bit control signal.
- the operation procedure consists of the following four steps. (1) Switch the resistance of the resistance switch 6 to a resistance value (High-Z) of 1 k ⁇ or higher. (2) The route is switched as follows using the route selection circuits 7-2 and 7-2. In 7-1, the output destination is the resistance switch 6, and 7-2 is connected to the receiver circuit 10-2. (3) Determine the input logic to the output circuit 9-1 and the output circuit 9-2. Here, the input logic (signal 1) to the output circuit 9-1 is fixed high, and the input logic (signal 2) to the output circuit 9-2 is a step wave that continues for 1 for a while after the logic switches from 0 to 1. The input is as follows. The signal fixing time of the step wave here is on the order of ⁇ seconds. (4) The voltage observation circuit 5 measures the power supply fluctuation waveform based on the power supply current fluctuation 20 that flows to the resistance switch 6 via the path switching circuit 7-1 via the output circuit 9-1 and monitors the state.
- the phenomenon observed as the power supply current fluctuation 20 is that when the input logic (signal 1) to the output circuit 9-1 is fixed high, the power supply line 14 and the path are short-circuited, and the power supply line state is the signal pin 41- Come out through 1. In this state, if a signal that switches the input logic (signal 2) to the output circuit 9-2 from 0 to 1 is given, when this is switched, it tries to draw the power supply current from the outside, and the surrounding impedance As a result, the power supply current fluctuates.
- one of the signal pins 41-1 near the power supply / ground pins 42 and 43 is used as a path for transmitting the power supply or the ground current, and the other signal pin 41-2 in the vicinity thereof is used as the power supply.
- the connection state of a specific power supply or ground pin is measured by a physical quantity such as power supply or ground fluctuation.
- the output of the output circuit 9-1 is fixed to High and the input to the output circuit 9-2 is set to a step wave for switching from Low to High.
- the output of the output circuit 9-1 is fixed to Low, and the input to the output circuit 9-2 is a step wave switching from High to Low.
- the reason why the resistance setting value of the resistance switch 6 is set to High-Z of k ⁇ or more is to observe the generated power supply fluctuation with as large an amplitude as possible.
- FIG. 6 shows the state of power supply fluctuation after the step wave is input at the logic switching time.
- a vibration waveform corresponding to the maximum value of the power source impedance viewed from the target circuit unit and the frequency at which the maximum value exists is generated.
- two types of voltage waveform 22-1 generated in a normal bump connection state and a voltage waveform 22-2 generated in an abnormal bump connection state such as breakage are described.
- the inductance of the power feeding system increases, so that the frequency of the anti-resonance impedance of the power feeding system decreases and the impedance maximum value increases. For this reason, there is a change in which the period of power supply fluctuation becomes longer and the amplitude of power supply fluctuation becomes larger.
- the amount of measurement to estimate these changes includes the maximum voltage drop difference (23-1, 23-2), maximum voltage drop time difference (24-1, 24-2), as shown in Figure 6, and This is realized by combining any one or more of the difference in vibration period (25-1, 25-2). Therefore, the voltage observation circuit 5 only needs to have a function capable of measuring either of these.
- the output of the output circuit 9-1 is fixed to High and the input to the output circuit 9-2 is changed from Low to observe the state of the power supply pin 42 in FIG. It is an example of a power fluctuation waveform observed as a step wave for switching to High.
- the waveform shows the same tendency as in FIG.
- the first example is a circuit for measuring voltage fluctuation as a waveform, which is shown in FIG. FIG. 11 includes a multi-stage level shift circuit, comparators 82-1 to 82-4 connected thereto, FF circuits 83-1 to 83-4, and shift registers 84-1 to 84-4.
- a current to flow through the level shift circuit shown in FIG. 81 the voltage is reduced by the resistance, compared with a predetermined threshold voltage Vref by a comparator circuit, and 0 or 1 is written to FF according to the magnitude relationship.
- This circuit repeats this at specific time intervals, stores the digital information in the shift register circuit, and can quantify which range the voltage is at which time.
- the resolution of the power fluctuation waveform observed in the multi-stage shift register is used as the boundary line of the 0, 1 pattern area to increase the resolution. Can be supplemented.
- this circuit can be used to obtain a power fluctuation waveform, the above-mentioned maximum voltage drop difference, maximum voltage drop time difference, and vibration period difference should be observed using the data measured by this circuit. Can do. Although it is a circuit that is suitable for knowing voltage waveform information in detail, it is necessary to increase the number of level shift stages and the number of bits of the shift register if sufficient voltage resolution and time resolution are to be obtained. A trade-off occurs.
- the configuration example of the second voltage observation circuit 5 is a circuit for detecting that the voltage drop amount exceeds a certain value as shown in FIG.
- This circuit includes a level shift circuit 91, a comparator 93, and a hold circuit 94.
- the comparator 93 has only one stage.
- a signal of Logic 1 can be transmitted to the hold circuit 94 only when the amount of voltage drop exceeds a certain value. Since the threshold value Vref of the voltage drop amount for detection can be changed by the switch circuit 92, the desired voltage drop amount can be known by changing this threshold value according to the measurement object. This is a method of observing only the difference in the amount of voltage drop described above, but has a feature that the circuit scale and power can be suppressed.
- the operation procedure at this time consists of the following four steps.
- the resistance of the resistance switch 6 is set to a resistance value (within a range of 0.1 ⁇ to 10 ⁇ ) comparable to the resistance value at the time of wiring failure (the resistance value when the bump 41-1 is about to break). (Resistance of value, usually around several ohms.)
- the route selection circuits 7-1 and 7-2 the route is switched as follows.
- the path selection circuit 7-1 has an output destination as the resistance switch 6, and the path selection circuit 6-2 is connected to the receiver circuit 10-2.
- the input to the output circuit 9-1 is changed from Low ⁇ High ⁇ Low.
- the voltage observation circuit 5 measures the power supply fluctuation waveform based on the power supply current fluctuation flowing through the resistance switching device 6 via the path switching circuit 7-1 via the output circuit 9-1 and monitors the state. In this case, when the bump breaks or the like occurs, it appears as a potential difference between both ends of the resistance of the resistance switch 6, so that the situation can be monitored.
- the rupture state of the bump appears as an analog change in the electrical characteristics in any case of the power source, the ground, and the signal, so that it is possible to monitor the state of the rupture other than the simple disconnection.
- the operation to monitor sequentially is executed.
- the input logic to be input to the output circuits 9-1 and 9-2 is, for example, provided with a boundary scan flip-flop circuit in the internal circuit, The corresponding input logic may be output sequentially to the output circuit.
- the voltage observing circuit 5 for observing the connection state of each power source / ground / signal with a power source fluctuation waveform is constituted by, for example, a circuit shown in FIG.
- This voltage observation circuit 5 is measured by the current flowing through one connection path (the wiring from the bump on the first circuit block 1 side to the bump on the second circuit block 2 side, including all electrical conductors).
- One power fluctuation waveform thus recorded is recorded in the shift register.
- the power fluctuation waveform data is read from the shift register of the voltage observation circuit 5, and is executed by a logic circuit or CPU that calculates each feature quantity of the maximum voltage drop, the maximum voltage drop time, and the vibration cycle.
- the above-described logic circuit is included in the control circuit (8 in the figure) in FIGS. Although not specifically illustrated, the above-described inspection program executed by the CPU operates, for example, on the internal circuit 1 in FIG.
- the semiconductor LSI package that constitutes the System Package (SiP) is mounted on the product, and the connection state of each power supply, ground, and signal is observed in advance by the voltage observation circuit 5 at the time of product shipment, and the connection state is normal.
- the maximum voltage drop of the power supply fluctuation waveform, the maximum voltage drop time, and the feature quantities of the vibration period are calculated and recorded in the memory.
- the logic circuit evaluates the difference in maximum voltage drop, the difference in maximum voltage drop time, and the difference in vibration period in comparison with each feature amount of the same connection path recorded in the memory. It is determined whether the state of each connection path is normal or abnormal. The logic circuit executes the determination of one connection path, resets the shift register of the voltage observation circuit 5, and repeatedly executes the process of reading the power fluctuation waveform data of the next connection path.
- FIG. 8 shows a cross-sectional view when utilized in System® Package (SiP).
- SiP System® Package
- the semiconductor circuit block can be considered as a plurality of LSIs mounted on the interposer.
- the connection paths 12, 13, 14, and 15 between the first circuit block 1 and the second circuit block 2 in FIG. 1 include micro bumps that connect each LSI and the interposer, and wiring in the interposer. included.
- the inspection circuit of this embodiment is suitable mainly for monitoring the connection state of the micro bump portion connecting the LSI and the interposer.
- FIG. 8 shows an example of unidirectional transmission with two LSIs
- the number of LSIs and the signal transmission direction may be arbitrary such as bidirectional.
- FIG. 9 shows an example in which a plurality of DRAMs DIE 1-1 and 1-2 (about 8 at maximum) are three-dimensionally stacked on ASIC DIE 2. Show. In this embodiment, it is possible to monitor the connection state of the through silicon via TSV16 for connecting the upper and lower LSIs.
- FIG. 10 shows an example in which a normal LSI package is used to inspect the connection state between LSIs when mounted on a board (printed circuit board) 70.
- a board printed circuit board
- the communication device since the communication device has a diagnostic control unit (for example, a diagnostic processor), the power fluctuation waveform data from the shift register of the voltage observation circuit 5 executed by the logic circuit or the inspection program. Is a diagnostic controller that evaluates the difference in maximum voltage drop, difference in maximum voltage drop time, and difference in vibration period to determine whether the state of each connection path to be evaluated is normal or abnormal. May be executed.
- a diagnostic control unit for example, a diagnostic processor
- each connection path is determined, for example, in the bump arrangement as shown in FIG. 3, which channel signal pin corresponds to the channels 55 and 56 that are a group of signal pins corresponding to the group of data read units. It can also be used to keep track of whether an abnormality is occurring at an early stage, to disconnect a broken or likely broken channel at an early stage, and to switch to an alternative channel.
- a control device used in a plant or the like provides a diagnosis cycle in addition to a normal control cycle.
- a connection test can be performed using this diagnostic cycle.
- an example when applied to an in-vehicle semiconductor component will be described.
- Cars are difficult to test while driving, but can be tested within minutes after stopping or after the engine has stopped.
- an inspection can be performed immediately after the engine is turned on, and if there is an abnormality, an alarm can be raised to notify the user.
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Abstract
Description
が入力回路10-1,10-2の前段に配置されている。経路切り替え回路7-1,7-2は、図中左側(第1の回路ブロック1)からの入力に対して、レシーバ回路10-1,10-2への出力経路と抵抗切り替え器6への出力経路を制御回路8からの入力にて切り替えられる機能を有する。また、抵抗切り替え器6には、その抵抗の両端の電圧をモニタするための電圧観測回路5を有する。
第1の回路ブロック1には、出力回路9-1,9-2以外の全ての回路を内部回路として纏めて記載している。また、第2の回路ブロック2には、入力回路10-1,10-2の後に接続される内部回路は省略して記載していない。
(1)抵抗切り替え器6の抵抗を1kΩ以上の抵抗値(High-Z)のものに切り替える。
(2)経路選択回路7-2,7-2を用いて以下のように経路を切り替える。7-1は出力先を抵抗切り替え器6にして、7-2はレシーバ回路10-2へと繋ぐ。
(3)出力回路9-1と出力回路9-2への入力論理を決める。ここでは出力回路9-1への入力論理(信号1)はHigh固定とし、出力回路9-2への入力論理(信号2)は0から1に論理が切り替わった後、しばらく1が続くステップ波のような入力とする。ここでのステップ波の信号固定時間はμ秒のオーダーである。
(4)出力回路9-1経由で経路切り替え回路7-1を介して抵抗切り替え器6に流れる電源電流変動20に基づく電源変動波形を電圧観測回路5で測定し、状態をモニタリングする。
電圧波形の情報を詳しく知るために適した回路であるが、電圧分解能や時間分解能を十分にとろうとすると、レベルシフトの段数、シフトレジスタのビット数を増やす必要があるため、回路規模や電力とトレードオフが発生する。
(1)抵抗切り替え器6の抵抗を、配線故障時の抵抗値(バンプ41-1が破断しそうになった時の抵抗値)と同程度の抵抗値(0.1Ω乃至10Ωの範囲内で適当な値の抵抗。通常、数Ω程度。)に切り替える。
(2)経路選択回路7-1,7-2を用いて以下のように経路を切り替える。経路選択回路7-1は出力先を抵抗切り替え器6にして、経路選択回路7-2はレシーバ回路10-2へと繋ぐ。
(3)出力回路9-1への入力論理を決める。ここでは出力回路9-1への入力はLow→High→Lowと遷移させる。このときHighの期間はDC抵抗を測定するのに十分な時間(μ秒のオーダー)で固定する。
(4)出力回路9-1経由で経路切り替え回路7-1を介して抵抗切り替え器6に流れる電源電流変動に基づく電源変動波形を電圧観測回路5で測定し、状態をモニタリングする。
この場合、バンプの破断等が起こるとそれが抵抗切り替え器6の抵抗の両端の電位差として表れるので、これで状況をモニタできる。
従って、本実施例では、入力論理の生成手段を特定はしない。
1-1~1-2:DRAM DIE
2:第2の回路ブロック、ASIC DIE
5:電圧観測回路
6:抵抗切り替え器
7-1~7-2:経路切り替え回路
8:制御回路
9-1~9-2:出力回路(ドライバ回路)
10-1~10-2:入力回路(レシーバ回路)
11:配線ブロック、インターポーザ
12:第1の信号配線
13:第2の信号配線
14:電源配線
15:グランド配線
20,21:電流経路
22-1~22-2:電圧波形
23-1~23-2:電圧ドロップ量
24-1~24-2:最大電圧降下時刻
25-1~25-2:電圧変動周期
30-1~30-3:パストランジスタ
41-1~41-2:信号用端子
42:電源用端子
43:グランド用端子
51-1~51-4:信号用マイクロバンプ
52-1~52-2:電源用マイクロバンプ
53-1~53-2:グランド用マイクロバンプ
60:LSIパッケージ基板
61-1~61-2:信号用C4バンプ
62-1~62-2:電源用C4バンプ
63-1~63-2:グランド用C4バンプ
70:プリント基板
71-1~71-2:信号用BGAボール
72-1~72-2:電源用BGAボール
73-1~73-2:グランド用BGAボール
81:レベルシフト回路
82-1~4:コンパレータ
83-1~4:FF回路
84-1~4:シフトレジスタ回路
91:レベルシフト回路
92:スイッチ回路
93:コンパレータ
94:ホールド回路
Claims (19)
- 第1、および第2の出力回路を有する第1の回路ブロックと、
第1、および第2の入力回路を有する第2の回路ブロックと、
前記第1の出力回路からの出力ピンと前記第1の入力回路への入力ピンを配線で接続し、および前記第2の出力回路からの出力ピンと前記第2の入力回路への入力ピンを配線で接続する配線ブロックとを備え、
前記各出力回路、および前記各入力回路への給電を担う前記第1、および第2の回路ブロックの電源ピン、およびグランドピンが前記配線ブロックの給電用配線、およびグランド用配線と接続され、
前記第2の回路ブロックには、各入力回路の前段に経路切り替え回路と、前記経路切り替え回路にて分岐された経路の先に抵抗切り替え器と、及び前記抵抗切り替え器の抵抗の両端の電圧を観測する電圧観測回路とを有することを特徴とする半導体装置。 - 前記第1の出力回路にはHigh固定の論理入力を、及び前記第2の出力回路にはLowからHighへの切り替えのステップ波の論理入力を与えて、前記第1の入力回路の前段の経路切り替え回路により分岐された電源変動波形を前記電圧観測回路で観測して前記電源ピンの接続状態を検査することを特徴とする請求項1に記載の半導体装置。
- 前記第1の出力回路にはLow固定の論理入力を、及び前記第2の出力回路にはHighからLowへの切り替えのステップ波の論理入力を与えて、前記第1の入力回路の前段の経路切り替え回路により分岐された電源変動波形を前記電圧観測回路で観測して前記グランドピンの接続状態を検査することを特徴とする請求項1に記載の半導体装置。
- 前記第1の出力回路に、Low→High→Lowと遷移させる論理入力で、およびHighの期間はDC抵抗を測定するのに十分な時間(μ秒のオーダー)で固定する論理入力を与えて、前記第1の入力回路の前段の経路切り替え回路により分岐された電源変動波形を前記電圧観測回路で観測して、前記第1の出力回路からの出力ピンと前記第1の入力回路への入力ピンとを接続する配線経路の接続状態を検査することを特徴とする請求項1に記載の半導体装置。
- 前記経路切り替え回路は、3個のパストランジスタを使用して、2bitの制御信号で1入力2出力の構成であることを特徴とする請求項1に記載の半導体装置。
- 前記電圧観測回路は、多段のレベルシフト回路と、それに繋がる多段のコンパレータと、多段のFF回路と、および多段のシフトレジスタから構成されていることを特徴とする請求項1に記載の半導体装置。
- 前記電圧観測回路は、レベルシフト回路と、コンパレータと、およびホールド回路により構成されていることを特徴とする請求項1に記載の半導体装置。
- 前記抵抗切り替え器には0.1Ω乃至10Ωの範囲の抵抗と1kΩ以上の抵抗を備え、
前記抵抗切り替え器の抵抗を1kΩ以上の抵抗に切り替えることを特徴とする請求項2に記載の半導体装置。 - 前記抵抗切り替え器には0.1Ω乃至10Ωの範囲の抵抗と1kΩ以上の抵抗を備え、
前記抵抗切り替え器の抵抗を0.1Ω乃至10Ωの範囲内で適切な値の抵抗に切り替えることを特徴とする請求項4に記載の半導体装置。 - 第1、および第2の出力回路を有する第1の半導体LSIと、
第1、および第2の入力回路を有する第2の半導体LSIと、
前記第1の出力回路からの出力ピンと前記第1の入力回路への入力ピンを配線で接続し、および前記第2の出力回路からの出力ピンと前記第2の入力回路への入力ピンを配線で接続する配線基板とを備え、
前記各出力回路、および前記各入力回路への給電を担う前記第1、および第2の半導体LSIの電源ピン、およびグランドピンが前記配線基板の給電用配線、およびグランド用配線と接続され、
前記第2の半導体LSIには、各入力回路の前段に経路切り替え回路と、前記経路切り替え回路にて分岐された経路の先に抵抗切り替え器と、及び前記抵抗切り替え器の抵抗の両端の電圧を観測する電圧観測回路とを有することを特徴とするマルチチップモジュール。 - 前記第1の出力回路にはHigh固定の論理入力を、及び前記第2の出力回路にはLowからHighへの切り替えのステップ波の論理入力を与えて、前記第1の入力回路の前段の経路切り替え回路により分岐された電源変動波形を前記電圧観測回路で観測して前記電源ピンの接続状態を検査することを特徴とする請求項10に記載のマルチチップモジュール。
- 前記第1の出力回路にはLow固定の論理入力を、及び前記第2の出力回路にはHighからLowへの切り替えのステップ波の論理入力を与えて、前記第1の入力回路の前段の経路切り替え回路により分岐された電源変動波形を前記電圧観測回路で観測して前記グランドピンの接続状態を検査することを特徴とする請求項10に記載のマルチチップモジュール。
- 前記第1の出力回路に、Low→High→Lowと遷移させる論理入力で、およびHighの期間はDC抵抗を測定するのに十分な時間(μ秒のオーダー)で固定する論理入力を与えて、前記第1の入力回路の前段の経路切り替え回路により分岐された電源変動波形を前記電圧観測回路で観測して、前記第1の出力回路からの出力ピンと前記第1の入力回路への入力ピンとを接続する配線経路の接続状態を検査することを特徴とする請求項10に記載のマルチチップモジュール。
- 前記第2の半導体LSIは、前記配線基板の上に搭載され、
前記第1の半導体LSIは、前記第2の半導体LSIの上に搭載され、
前記第1の出力回路からの出力ピンと前記第1の入力回路への入力ピンとの接続、および前記第2の出力回路からの出力ピンと前記第2の入力回路への入力ピンとの接続を、前記配線基板の配線に替えて、前記第2の半導体LSIの内部に形成されたシリコン管ビアTSVにより行い、
前記第1の半導体LSIの電源ピン、およびグランドピンと、前記配線基板の配線との接続にも、前記第2の半導体LSIの内部に形成されたシリコン貫通ビアTSVを使用することを特徴とする請求項10に記載のマルチチップモジュール。 - 請求項1乃至9のいずれか1項に記載の半導体装置を有し、
装置出荷時の正常なピン接続状態の電圧量をメモリ等に保存しておくことで、
そのときの値との比較により異常時の状態を判断可能とすることを特徴とする半導体システム。 - 請求項1乃至9のいずれか1項に記載の半導体装置を有し、
検査回路により異常を検出したときに、異常個所や状態をシステムに対してアラームを出す機構を有することを特徴とする半導体システム。 - 請求項1乃至9のいずれか1項に記載の半導体装置を有し、
検査回路により異常を検出した際に、
故障箇所を切り離すか冗長系に切り替えることを特徴とする半導体システム。 - 請求項10に記載のマルチチップモジュールを有し、
検査プログラムの実行を前記第1の半導体LSIおよび前記第2の半導体LSIの動作アイドル時間を利用して行うことを特徴とする半導体システム。 - 請求項1乃至9のいずれか1項に記載の半導体装置を有し、
検査プログラムの実行を行うための診断制御モードを一定の周期ごとに繰り返す
ことを特徴とする半導体システム。
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JP7122740B2 (ja) | 2018-03-29 | 2022-08-22 | 株式会社新川 | 接続状態判定装置及び接続状態判定方法 |
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TWI628448B (zh) * | 2017-03-07 | 2018-07-01 | 慧榮科技股份有限公司 | 電路測試方法 |
US10057976B1 (en) * | 2017-08-31 | 2018-08-21 | Xilinx, Inc. | Power-ground co-reference transceiver structure to deliver ultra-low crosstalk |
US10431563B1 (en) | 2018-04-09 | 2019-10-01 | International Business Machines Corporation | Carrier and integrated memory |
US10515929B2 (en) | 2018-04-09 | 2019-12-24 | International Business Machines Corporation | Carrier and integrated memory |
JP6897628B2 (ja) | 2018-04-26 | 2021-07-07 | 株式会社デンソー | 半導体装置 |
EP3790043A4 (en) * | 2018-07-10 | 2021-07-14 | Aisin Aw Co., Ltd. | CIRCUIT MODULE AND POWER SUPPLY CHIP MODULE |
KR102628847B1 (ko) * | 2019-06-12 | 2024-01-25 | 삼성디스플레이 주식회사 | 디스플레이 장치 |
US11309246B2 (en) | 2020-02-05 | 2022-04-19 | Apple Inc. | High density 3D interconnect configuration |
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JP2007017229A (ja) * | 2005-07-06 | 2007-01-25 | Denso Corp | マルチチップモジュール |
JP2009210369A (ja) * | 2008-03-04 | 2009-09-17 | Yokogawa Electric Corp | 半導体試験装置および半導体試験方法 |
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JP6339232B2 (ja) | 2018-06-06 |
US9933475B2 (en) | 2018-04-03 |
JPWO2016170678A1 (ja) | 2017-04-27 |
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