JP4365433B2 - 半導体集積回路 - Google Patents
半導体集積回路 Download PDFInfo
- Publication number
- JP4365433B2 JP4365433B2 JP2007235165A JP2007235165A JP4365433B2 JP 4365433 B2 JP4365433 B2 JP 4365433B2 JP 2007235165 A JP2007235165 A JP 2007235165A JP 2007235165 A JP2007235165 A JP 2007235165A JP 4365433 B2 JP4365433 B2 JP 4365433B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- logic
- pad
- integrated circuit
- exclusive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31717—Interconnect testing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Description
T1〜T5 外部端子
S1〜S5 固定論理パッド
11 TRIINV回路
12 排他的否定論理和回路
13 NAND回路
Claims (3)
- 各々が対応する外部端子との間のボンディングワイヤ接続によって前記外部端子に印加される信号に対応した論理レベルとされる複数のパッドと、前記複数のパッド各々と前記対応する外部端子との間の接続状態を検査するテスト回路と、を備えた半導体集積回路であって、
前記テスト回路は、前記複数のパッド各々について、
前記対応する外部端子の印加信号の論理レベルに等しい論理レベルの制御信号を受け入れる制御端子と、
前記制御端子の論理レベルを反転し、その反転出力端が前記パッドの接続ラインに接続されたインバータと、
前記接続ラインと前記制御端子とに個別に接続され、前記接続ラインの論理レベルと前記制御端子の論理レベルとの排他的否定論理和出力を生成する排他的否定論理和ゲートと、を備え、
前記排他的否定論理和出力が前記パッドと前記対応する外部端子との間の接続状態の良否を示すことを特徴とする半導体集積回路。 - 前記テスト回路は、前記複数のパッド各々の前記排他的否定論理和ゲートの論理出力の論理積の反転信号を生成するNAND回路を更に備えたことを特徴とする請求項1記載の半導体集積回路。
- 前記インバータは、前記制御端子の論理レベルと前記パッドの論理レベルとが等しいとき前記接続ラインの論理レベルが前記パッドの論理レベルに等しくなるように動作することを特徴とする請求項1記載の半導体集積回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007235165A JP4365433B2 (ja) | 2007-09-11 | 2007-09-11 | 半導体集積回路 |
US12/175,478 US7639036B2 (en) | 2007-09-11 | 2008-07-18 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007235165A JP4365433B2 (ja) | 2007-09-11 | 2007-09-11 | 半導体集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009068885A JP2009068885A (ja) | 2009-04-02 |
JP4365433B2 true JP4365433B2 (ja) | 2009-11-18 |
Family
ID=40431191
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007235165A Expired - Fee Related JP4365433B2 (ja) | 2007-09-11 | 2007-09-11 | 半導体集積回路 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7639036B2 (ja) |
JP (1) | JP4365433B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8614584B2 (en) * | 2011-03-02 | 2013-12-24 | Sandisk Technologies Inc. | System and method for bonded configuration pad continuity check |
US9933475B2 (en) * | 2015-04-24 | 2018-04-03 | Hitachi, Ltd. | Semiconductor device and multi-chip module |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05275621A (ja) | 1992-03-30 | 1993-10-22 | Nec Ic Microcomput Syst Ltd | 半導体集積回路 |
JPH11237441A (ja) | 1998-02-20 | 1999-08-31 | Nec Corp | 半導体集積回路装置、半導体集積回路装置の製造方法、及び半導体集積回路装置の検査方法 |
JP2000193709A (ja) | 1998-12-25 | 2000-07-14 | Nec Corp | 半導体デバイス及びそのオ―プン検出方法 |
ATE406582T1 (de) * | 2002-07-08 | 2008-09-15 | Nxp Bv | Elektronische schaltung mit prüfeinheit zur prüfung von verbindungsleitungen |
JP2005189834A (ja) * | 2003-12-03 | 2005-07-14 | Renesas Technology Corp | 半導体装置およびその試験方法 |
-
2007
- 2007-09-11 JP JP2007235165A patent/JP4365433B2/ja not_active Expired - Fee Related
-
2008
- 2008-07-18 US US12/175,478 patent/US7639036B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2009068885A (ja) | 2009-04-02 |
US7639036B2 (en) | 2009-12-29 |
US20090066362A1 (en) | 2009-03-12 |
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