WO2016165185A1 - 双栅极氧化物半导体tft基板的制作方法及其结构 - Google Patents

双栅极氧化物半导体tft基板的制作方法及其结构 Download PDF

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WO2016165185A1
WO2016165185A1 PCT/CN2015/079471 CN2015079471W WO2016165185A1 WO 2016165185 A1 WO2016165185 A1 WO 2016165185A1 CN 2015079471 W CN2015079471 W CN 2015079471W WO 2016165185 A1 WO2016165185 A1 WO 2016165185A1
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layer
oxide semiconductor
gate insulating
insulating layer
oxide
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French (fr)
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葛世民
张合静
曾志远
苏智昱
李文辉
石龙强
吕晓文
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/763,824 priority Critical patent/US9570620B2/en
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method and a structure for fabricating a dual gate oxide semiconductor TFT substrate suitable for an LCD.
  • the flat display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • TFTs Thin film transistors
  • the TFT may be formed on a glass substrate or a plastic substrate, and is generally used as a switching member and a driving member on a flat display device such as an LCD or an OLED.
  • Oxide semiconductor TFT technology is currently a popular technology.
  • Oxide semiconductors have higher electron mobility, and compared with low temperature polysilicon (LTPS), oxide semiconductors are simple in process and highly compatible with amorphous silicon processes, and can be applied to LCD and OLED planar display devices, and the like. Compatible with high-generation production lines, it can be applied to large, medium and small size displays, and has good application prospects.
  • LTPS low temperature polysilicon
  • a TFT substrate is usually a single-gate oxide semiconductor thin film transistor (Single-Gate TFT).
  • Dual-gate oxide semiconductor thin film transistor has superior performance compared to single-gate oxide semiconductor thin film transistor, such as higher electron mobility, larger on-state current, smaller subthreshold swing, and threshold Better voltage stability and uniformity, better gate bias and illumination stability.
  • a conventional dual gate oxide semiconductor TFT substrate structure suitable for LCD using COA technology includes a substrate 100 , a bottom gate 200 on the substrate 100 , and is disposed on the substrate 100 and the bottom gate 200 .
  • the source/drain 600 disposed on the etch stop layer 500 is disposed on the source/drain 600 and the passivation layer 700 on the etch stop layer 500, and is disposed on the passivation layer 700 over the source/drain 600.
  • the top gate 800 is disposed on the top gate 800 and the red/green/blue resist layer 900 on the passivation layer 700, and is disposed on the red/green/blue resist layer 900 and the passivation layer 700.
  • a flat layer 910, and an ITO pixel electrode disposed on the first planar layer 910 1100.
  • a first via 510 and a second via 520 are formed on the etch barrier layer 500 corresponding to the oxide semiconductor layer 400.
  • the source/drain 600 are respectively passed through the first via 510 and the second via 520.
  • Contacting the oxide semiconductor layer 400; the passivation layer 700 and the first planar layer 910 are formed with a third via 530 corresponding to the source/drain 600, and the ITO pixel electrode 1100 is connected to the source via the third via 530/ The drain 600 is in contact.
  • the double-gate oxide semiconductor TFT substrate is fabricated, except for the substrate 100 and the gate insulating layer 300, each of the other structural layers is patterned by a mask process, and the required number of mask processes is high. .
  • the existing double-gate oxide semiconductor TFT substrate suitable for LCD using COA technology has a complicated structure, and the manufacturing method has a long process flow, low production efficiency, and high process cost.
  • An object of the present invention is to provide a method for fabricating a dual gate oxide semiconductor TFT substrate suitable for an LCD, which can reduce the number of photomask processes, shorten the manufacturing process flow, improve production efficiency, and reduce production cost.
  • Another object of the present invention is to provide a dual-gate oxide semiconductor TFT substrate structure suitable for an LCD, which can reduce the number of photomask processes, shorten the manufacturing process flow, improve production efficiency, and reduce production costs.
  • the present invention first provides a method for fabricating a dual gate oxide semiconductor TFT substrate, comprising the following steps:
  • Step 1 Providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer by a first mask process to form a bottom gate;
  • Step 2 depositing a bottom gate insulating layer on the bottom gate and the substrate;
  • Step 3 depositing a color resist layer on the bottom gate insulating layer, and sequentially patterning the color resist layer through the second, third, and fourth mask processes to form a red/green/blue resist layer And then depositing a flat layer on the red/green/blue resist layer, and patterning the flat layer by a fifth mask process to form a flat layer covering the red/green/blue resist layer respectively ;
  • Step 4 depositing an oxide semiconductor layer on the bottom gate insulating layer and the flat layer, coating a photoresist layer on the oxide semiconductor layer, and performing a sixth mask process using a halftone mask: Exposing and developing the photoresist layer to obtain a first photoresist layer and a second photoresist layer respectively covering the oxide semiconductor layer above the bottom gate and the planar layer; the first photoresist layer The thickness of the two side regions and the second photoresist layer is smaller than the thickness of the intermediate portion of the first photoresist layer;
  • Step 5 first removing both side regions of the first photoresist layer and the second photoresist layer; and using a middle portion of the remaining first photoresist layer as a shielding layer, two of the first oxide semiconductor layers The side and the second oxide semiconductor layer are ion-doped to convert both side regions of the first oxide semiconductor layer into a conductor, and the second oxide semiconductor layer is converted into an oxide conductor layer; and then the remaining portion is removed The middle region of the first photoresist layer;
  • Step 6 depositing a top gate insulating layer on the first oxide semiconductor layer, the oxide conductor layer, and the bottom gate insulating layer, and patterning the top gate insulating layer by a seventh mask process to form respectively a first via located above the two side regions of the first oxide semiconductor layer, and a second via located above the oxide conductor layer;
  • Step 7 Depositing a second and a third metal layer on the top gate insulating layer, and patterning the second and third metal layers through an eighth mask process to obtain the first oxide semiconductor a top gate above the layer, a source and a drain on both sides of the top gate;
  • the source and the drain are respectively in contact with both side regions of the first oxide semiconductor layer via the first via, and the source is in phase with the oxide conductor layer via the second via contact;
  • Step 8 depositing a passivation layer on the top gate, the source, the drain, and the top gate insulating layer; simultaneously patterning the passivation layer and the top gate insulating layer by a ninth mask process, Obtaining a third via hole above the oxide conductor layer to expose a portion of the oxide conductor layer;
  • the bottom gate, the first oxide semiconductor layer, the source, the drain, and the top gate constitute a double gate TFT; and the oxide conductor layer constitutes a pixel electrode of the LCD.
  • the step 3 further includes performing plasma treatment on the bottom gate insulating layer.
  • the step 4 deposits the oxide semiconductor layer by physical vapor deposition.
  • the step 6 performs patterning treatment on the top gate insulating layer by dry etching.
  • the material of the oxide semiconductor layer is IGZO.
  • the material of the bottom gate, the source, the drain, and the top gate is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the bottom gate insulating layer and the top gate insulating layer is silicon nitride, silicon oxide, or a combination of the two.
  • the present invention also provides a dual gate oxide semiconductor TFT substrate structure, comprising a substrate, a bottom gate disposed on the substrate, a bottom gate insulating layer disposed on the substrate and the bottom gate, and being disposed on the bottom gate insulating layer a red/green/blue resist layer, a flat layer corresponding to the red/green/blue resist layer, a first oxide semiconductor layer disposed on the bottom gate insulating layer above the bottom gate, and located in red/green/ An oxide conductor layer disposed on the planar layer above the blue resist layer, located in the first oxide semiconductor layer, the oxide conductor a top gate insulating layer on the layer and the bottom gate insulating layer, a top gate electrode disposed on the top gate insulating layer above the oxide semiconductor layer, and a source electrode disposed on the top gate insulating layer on both sides of the top gate electrode And a drain, and a passivation layer disposed on the top gate, the source, the drain, and the top gate insulating layer;
  • the two sides of the first oxide semiconductor layer are ion-doped conductor layers;
  • the top gate insulating layer is respectively provided with a first via hole above the two side regions of the first oxide semiconductor layer, the top gate a second via hole is disposed on the insulating layer corresponding to the oxide conductor layer, and the top via insulating layer and the passivation layer are respectively provided with a third via hole above the oxide conductor layer;
  • the source and the drain are respectively in contact with both side regions of the first oxide semiconductor layer via the first via hole; the source is in phase with the oxide conductor layer via the second via hole Contacting; the third via exposes a portion of the oxide conductor layer;
  • the bottom gate, the first oxide semiconductor layer, the source, the drain, and the top gate constitute a double gate TFT; and the oxide conductor layer constitutes a pixel electrode of the LCD.
  • the material of the first oxide semiconductor layer is IGZO, and the oxide conductor layer is obtained by ion doping the IGZO semiconductor layer.
  • the material of the bottom gate insulating layer and the top gate insulating layer is silicon nitride, silicon oxide, or a combination of the two; the bottom gate, top gate, source, and drain materials are molybdenum, titanium, A stack combination of one or more of aluminum and copper.
  • the present invention also provides a dual gate oxide semiconductor TFT substrate structure, comprising a substrate, a bottom gate disposed on the substrate, a bottom gate insulating layer disposed on the substrate and the bottom gate, and being disposed on the bottom gate insulating layer a red/green/blue resist layer, a flat layer corresponding to the red/green/blue resist layer, a first oxide semiconductor layer disposed on the bottom gate insulating layer above the bottom gate, and located in red/green/ An oxide conductor layer disposed on the planar layer above the blue resist layer, a top gate insulating layer on the first oxide semiconductor layer, the oxide conductor layer, and the bottom gate insulating layer, and located in the oxide semiconductor layer a top gate disposed on the top gate insulating layer, a source and a drain disposed on the top gate insulating layer on both sides of the top gate, and the top gate, the source, the drain, and the top a passivation layer on the gate insulating layer;
  • the two sides of the first oxide semiconductor layer are ion-doped conductor layers;
  • the top gate insulating layer is respectively provided with a first via hole above the two side regions of the first oxide semiconductor layer, the top gate a second via hole is disposed on the insulating layer corresponding to the oxide conductor layer, and the top via insulating layer and the passivation layer are respectively provided with a third via hole above the oxide conductor layer;
  • the source and the drain are respectively in contact with both side regions of the first oxide semiconductor layer via the first via hole; the source is in phase with the oxide conductor layer via the second via hole Contacting; the third via exposes a portion of the oxide conductor layer;
  • the bottom gate, the first oxide semiconductor layer, the source, the drain, and the top gate constitute a double gate TFT;
  • the oxide conductor layer constitutes a pixel electrode of the LCD;
  • the material of the first oxide semiconductor layer is IGZO, and the oxide conductor layer is obtained by ion doping the IGZO semiconductor layer;
  • the material of the bottom gate insulating layer and the top gate insulating layer is silicon nitride, silicon oxide, or a combination of the two; the bottom gate, the top gate, the source, and the drain are made of molybdenum, A stack combination of one or more of titanium, aluminum, and copper.
  • the present invention provides a method for fabricating a dual-gate oxide semiconductor TFT substrate, which uses a halftone mask to perform a mask process, which can complete the patterning of the oxide semiconductor layer and pass through Ion doping to form an oxide conductor layer, which serves as a pixel electrode of the LCD instead of the ITO pixel electrode in the prior art; the source, the drain, and the top gate are simultaneously fabricated through a mask process; A mask process simultaneously patterns the passivation layer and the top gate insulating layer, reducing the mask to nine channels, shortening the manufacturing process flow, improving production efficiency, and reducing production costs.
  • the invention provides a dual gate oxide semiconductor TFT substrate structure, which is provided as a pixel electrode of an LCD by providing an oxide conductor layer, and the source, the drain and the top gate are both disposed on the top gate insulating layer.
  • the number of times of the mask process can be reduced, the manufacturing process flow can be shortened, the production efficiency can be improved, and the production cost can be reduced.
  • FIG. 1 is a schematic cross-sectional view showing a structure of a dual gate oxide semiconductor TFT substrate suitable for an LCD using a COA technology
  • FIG. 2 is a flow chart showing a method of fabricating a dual gate oxide semiconductor TFT substrate of the present invention
  • FIG. 3 is a schematic view showing a step 1 of a method for fabricating a dual gate oxide semiconductor TFT substrate according to the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a dual gate oxide semiconductor TFT substrate according to the present invention
  • step 3 is a schematic diagram of step 3 of a method for fabricating a dual gate oxide semiconductor TFT substrate according to the present invention
  • step 4 is a schematic diagram of step 4 of a method for fabricating a dual gate oxide semiconductor TFT substrate according to the present invention
  • FIG. 7 is a view showing the step 5 of the method for fabricating the dual gate oxide semiconductor TFT substrate of the present invention. intention;
  • step 6 is a schematic diagram of step 6 of a method for fabricating a dual gate oxide semiconductor TFT substrate according to the present invention.
  • FIG. 9 is a schematic view showing a step 7 of a method for fabricating a dual gate oxide semiconductor TFT substrate according to the present invention.
  • FIG. 10 is a schematic view showing the step 8 of the method for fabricating the double gate oxide semiconductor TFT substrate of the present invention and a cross-sectional view showing the structure of the double gate oxide semiconductor TFT substrate of the present invention.
  • the present invention first provides a method for fabricating a dual gate oxide semiconductor TFT substrate suitable for an LCD, comprising the following steps:
  • Step 1 as shown in FIG. 3, a substrate 1 is provided, a first metal layer is deposited on the substrate 1, and the first metal layer is patterned by a first mask process to form a bottom gate 2.
  • the substrate 1 is a transparent substrate, and preferably, the substrate 1 is a glass substrate.
  • the material of the first metal layer is a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu), that is, the material of the bottom gate 2 is molybdenum A stack combination of one or more of titanium, aluminum, and copper.
  • Step 2 As shown in FIG. 4, a bottom gate insulating layer 31 is deposited on the bottom gate 2 and the substrate 1.
  • the material of the bottom gate insulating layer 31 is silicon nitride (SiNx), silicon oxide (SiOx), or a combination of the two.
  • Step 3 as shown in FIG. 5, depositing a color resist layer on the bottom gate insulating layer 31, and sequentially patterning the color resist layer through the second, third, and fourth mask processes to form a red color.
  • a green/blue resist layer 3 depositing a flat layer on the red/green/blue resist layer 3, and patterning the flat layer by a fifth mask process to form the red layer respectively
  • the material of the flat layer 4 is an organic photoresist, which can protect the red/green/blue resist layer 3 from covering.
  • the step 3 further includes performing a plasma treatment on the bottom gate insulating layer 31 to improve the film quality of the bottom gate insulating layer 31.
  • Step 4 depositing an oxide semiconductor layer on the bottom gate insulating layer 31 and the flat layer 4, coating a photoresist layer on the oxide semiconductor layer, and using a halftone mask (Half- Tone) performs a sixth mask process: first exposing and developing the photoresist layer a first photoresist layer 41 covering the oxide semiconductor layer and a second photoresist layer 42 over the bottom gate 2 and the flat layer 4; the two sides of the first photoresist layer 41 And the thickness of the second photoresist layer 42 is smaller than the thickness of the intermediate portion of the first photoresist layer 41.
  • a halftone mask Half- Tone
  • the step 4 deposits a transparent oxide semiconductor layer by Physical Vapor Deposition (PVD).
  • PVD Physical Vapor Deposition
  • the material of the oxide semiconductor layer is Indium Gallium Zinc Oxide (IGZO).
  • Step 5 as shown in FIG. 7, first remove the two side regions of the first photoresist layer 41 and the second photoresist layer 42; and use the remaining intermediate portion of the first photoresist layer 41 as a shielding layer.
  • the two sides of the first oxide semiconductor layer 51 and the second oxide semiconductor layer 52 are ion-doped to convert both side regions of the first oxide semiconductor layer 51 into conductors, so that the second oxide The semiconductor layer 52 is converted into an oxide conductor layer 52'; then the intermediate portion of the remaining first photoresist layer 41 is removed.
  • Step 6 as shown in FIG. 8, a top gate insulating layer 32 is deposited on the first oxide semiconductor layer 51, the oxide conductor layer 52', and the bottom gate insulating layer 31, and is processed by a seventh mask process.
  • the top gate insulating layer 32 is patterned to form a first via 91 located above both side regions of the first oxide semiconductor layer 51 and a second via 92 above the oxide conductor layer 52'. .
  • step 6 the top gate insulating layer 32 is patterned by dry etching.
  • the material of the top gate insulating layer 32 is silicon nitride, silicon oxide, or a combination of the two.
  • Step 7 depositing the second and third metal layers on the top gate insulating layer 32, and patterning the second and third metal layers through the eighth mask process to obtain the respective A top gate 71 above the first oxide semiconductor layer 51 and a source 81 and a drain 82 on both sides of the top gate 71.
  • the source 81 and the drain 82 are respectively in contact with both side regions of the first oxide semiconductor layer 51 via the first via 91, and the source 81 is connected to the second via 92 via the second via 92
  • the oxide conductor layer 52' is in contact.
  • the material of the second and third metal layers is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper, that is, the source 81, the drain 82, and the top gate 71.
  • the material is a stack combination of one or more of molybdenum, titanium, aluminum, copper.
  • Step 8 as shown in FIG. 10, a passivation layer 8 is deposited on the top gate 71, the source 81, the drain 82, and the top gate insulating layer 32; the passivation layer 8 is processed through a ninth mask process. And top grid The edge layer 32 is simultaneously patterned to obtain a third via 93 above the oxide conductor layer 52' to expose a portion of the oxide conductor layer 52'.
  • the bottom gate 2, the first oxide semiconductor layer 51, the source 81, the drain 82, and the top gate 71 constitute a double gate TFT T; the oxide conductor layer 52' constitutes a pixel electrode of the LCD.
  • a mask process is performed using a halftone mask to perform patterning of the oxide semiconductor layer and to form an oxide conductor layer 52' by ion doping.
  • the source 81, the drain 82, and the top gate 71 are simultaneously formed by a mask process; the passivation layer 8 and the top gate insulating layer 32 are simultaneously patterned by a mask process, and the mask process is reduced.
  • the present invention further provides a dual gate oxide semiconductor TFT substrate structure suitable for an LCD, comprising a substrate 1 and a bottom gate 2 disposed on the substrate 1 and disposed on the substrate 1 and the bottom gate 2 a bottom gate insulating layer 31, a red/green/blue resist layer 3 disposed on the bottom gate insulating layer 31, a flat layer 4 corresponding to the red/green/blue resist layer 3, and a bottom gate 2 a first oxide semiconductor layer 51 disposed on the bottom gate insulating layer 31, an oxide conductor layer 52' disposed on the planar layer 4 over the red/green/blue resist layer 3, and the first oxide semiconductor a layer 51, an oxide conductor layer 52', and a top gate insulating layer 32 on the bottom gate insulating layer 31, a top gate 71 disposed on the top gate insulating layer 32 above the oxide semiconductor layer 51, and a top gate
  • the source of the pole 71 is disposed on the top gate insulating layer 32
  • a passivation layer 8 provided on the top gate 71, the source 81, the drain 82, and the top gate insulating layer 32.
  • the two sides of the first oxide semiconductor layer 51 are ion-doped conductor layers; the top gate insulating layer 32 is respectively disposed above the two sides of the first oxide semiconductor layer 51 a hole 91, the top gate insulating layer 32 is provided with a second via hole 92 corresponding to the oxide conductor layer 52', and the top gate insulating layer 32 and the passivation layer 8 are disposed above the oxide conductor layer 52'.
  • Three vias 93 Three vias 93.
  • the source 81 and the drain 82 are respectively in contact with both side regions of the first oxide semiconductor layer 51 via the first via 91; the source 81 is connected to the second via 92 via the second via 92 The oxide conductor layer 52' is in contact; the third via 93 exposes a portion of the oxide conductor layer 52'.
  • the bottom gate 21, the first oxide semiconductor layer 51, the source 81, the drain 82, and the top gate 71 constitute a double gate TFT T; the oxide conductor layer 52' constitutes a pixel electrode of the LCD.
  • the material of the first oxide semiconductor layer 51 is IGZO, and the oxide conductor layer 52' is obtained by ion doping the IGZO semiconductor layer.
  • the material of the bottom gate insulating layer 31 and the top gate insulating layer 32 is silicon nitride, silicon oxide, or a combination of the two; the bottom gate 2
  • the material of the top gate 71, the source 81, and the drain 82 is a stacked combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the double gate oxide semiconductor TFT substrate structure is provided with an oxide conductor layer 52' as a pixel electrode of the LCD, and the oxide conductor layer 52' and the first oxide semiconductor layer 51 are formed by a mask process;
  • the source 81, the drain 82, and the top gate 71 are all disposed on the top gate insulating layer 32.
  • the TFT substrate structure can be simplified, on the one hand, the number of photomask processes can be reduced, the manufacturing process flow is shortened, and the production efficiency is improved. Production costs are reduced.
  • the method for fabricating the dual-gate oxide semiconductor TFT substrate of the present invention uses a halftone mask to perform a mask process, which can complete the patterning of the oxide semiconductor layer and can be doped by ion doping.
  • An oxide conductor layer is used as a pixel electrode of the LCD to replace the ITO pixel electrode in the prior art; the source, the drain, and the top gate are simultaneously fabricated through a mask process; and a mask process is performed through a mask process.
  • the passivation layer and the top gate insulating layer are patterned, and the mask process is reduced to nine channels, which shortens the manufacturing process flow, improves production efficiency, and reduces production cost.
  • the dual gate oxide semiconductor TFT substrate structure of the present invention is provided as a pixel electrode of an LCD by providing an oxide conductor layer, and the source, the drain and the top gate are both disposed on the top gate insulating layer.
  • the structure of the TFT substrate can be simplified, on the one hand, the number of times of the mask process can be reduced, the manufacturing process flow can be shortened, the production efficiency can be improved, and the production cost can be reduced.

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Abstract

提供一种双栅极氧化物半导体TFT基板的制作方法及其结构。该双栅极氧化物半导体TFT基板的制作方法使用半色调掩膜板进行一道光罩制程，既能够完成氧化物半导体层的图案化、又能够通过离子掺杂制得氧化物导体层（52'），该氧化物导体层（52'）作为LCD的像素电极替代现有技术中的ITO像素电极；通过一道光罩制程同时制得源极（81）、漏极（82）与顶栅极（71）；通过一道光罩制成对钝化层（8）及顶栅绝缘层（32）进行图案化处理，光罩制程减少至九道，缩短了制作工序流程，提高了生产效率，降低了生产成本。

Description

双栅极氧化物半导体TFT基板的制作方法及其结构 技术领域
本发明涉及显示技术领域，尤其涉及一种适用于LCD的双栅极氧化物半导体TFT基板的制作方法及其结构。
背景技术
平面显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平面显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机发光二极管显示装置(Organic Light Emitting Display，OLED)。
薄膜晶体管(TFT)是平面显示装置的重要组成部分。TFT可形成在玻璃基板或塑料基板上，通常作为开关部件和驱动部件用在诸如LCD、OLED等平面显示装置上。
氧化物半导体TFT技术是当前的热门技术。由于氧化物半导体具有较高的电子迁移率，而且相比低温多晶硅(LTPS)，氧化物半导体制程简单，与非晶硅制程相容性较高，可以应用于LCD、OLED平面显示装置等，且与高世代生产线兼容，可应用于大中小尺寸显示，具有良好的应用发展前景。
目前，在有源阵列平面显示装置中，TFT基板通常采用单栅极氧化物半导体薄膜晶体管(Single-Gate TFT)。双栅极氧化物半导体薄膜晶体管(Dual-Gate)相比单栅极氧化物半导体薄膜晶体管具有更优的性能，如电子迁移率更高，开态电流较大、亚阈值摆幅更小、阈值电压的稳定性及均匀性更好、栅极偏压及照光稳定性更好等。
在LCD的制程中，可将彩色滤光片在TFT基板的阵列制程中完成，即采用COA(Color Filter On Array)技术。如图1所示，现有的采用COA技术的适用于LCD的双栅极氧化物半导体TFT基板结构包括基板100，位于基板100上的底栅极200，位于基板100、与底栅极200上的栅极绝缘层300，位于底栅极200上方设于栅极绝缘层300上的氧化物半导体层400，设于氧化物半导体层400、与栅极绝缘层300上的刻蚀阻挡层500，设于刻蚀阻挡层500上的源/漏极600，设于源/漏极600、与刻蚀阻挡层500上的钝化层700，位于源/漏极600上方设于钝化层700上的顶栅极800，设于顶栅极800、与钝化层700上的红/绿/蓝色阻层900，设于红/绿/蓝色阻层900及钝化层700上的第一平坦层910，及设于第一平坦层910上的ITO像素电极 1100。
所述刻蚀阻挡层500对应氧化物半导体层400上方形成有第一过孔510、及第二过孔520，所述源/漏极600分别经由第一过孔510、及第二过孔520与氧化物半导体层400相接触；所述钝化层700、及第一平坦层910对应源/漏极600上方形成有第三过孔530，ITO像素电极1100经由第三过孔530与源/漏极600相接触。
制作上述双栅极氧化物半导体TFT基板时，除基板100与栅极绝缘层300外，其它的每一结构层均通过一道光罩制程来进行图案化处理，所需的光罩制程次数较多。显然，现有的采用COA技术的适用于LCD的双栅极氧化物半导体TFT基板的结构较复杂，其制作方法的工序流程较长，生产效率较低，制程成本较高。
发明内容
本发明的目的在于提供一种适用于LCD的双栅极氧化物半导体TFT基板的制作方法，能够减少光罩制程次数，缩短制作工序流程，提高生产效率，降低生产成本。
本发明的另一目的在于提供一种适用于LCD的双栅极氧化物半导体TFT基板结构，能够使得光罩制程次数减少，制作工序流程缩短，生产效率提高，生产成本降低。
为实现上述目的，本发明首先提供一种双栅极氧化物半导体TFT基板的制作方法，包括如下步骤：
步骤1、提供一基板，在该基板上沉积第一金属层，通过第一道光罩制程对所述第一金属层进行图案化处理，形成底栅极；
步骤2、在所述底栅极、及基板上沉积底栅绝缘层；
步骤3、在所述底栅绝缘层上沉积色阻层，分别通过第二、第三、第四道光罩制程依次对所述色阻层进行图案化处理，形成红/绿/蓝色阻层；接着在所述红/绿/蓝色阻层上沉积平坦层，通过第五道光罩制程对所述平坦层进行图案化处理，形成分别覆盖所述红/绿/蓝色阻层的平坦层；
步骤4、在所述底栅绝缘层、及平坦层上沉积氧化物半导体层，在氧化物半导体层上涂覆光阻层，使用半色调掩膜板进行第六道光罩制程：先对所述光阻层进行曝光、显影，得到分别位于所述底栅极、及平坦层上方覆盖所述氧化物半导体层的第一光阻层、及第二光阻层；所述第一光阻层的两侧区域、及第二光阻层的厚度小于所述第一光阻层的中间区域的厚度；
再利用所述第一光阻层、及第二光阻层对所述氧化物半导体层进行刻 蚀，使所述氧化物半导体层图案化，得到分别位于所述底栅极、及平坦层上方的第一氧化物半导体层、及第二氧化物半导体层；
步骤5、先去除所述第一光阻层的两侧区域、及第二光阻层；以余下的第一光阻层的中间区域为遮蔽层，对所述第一氧化物半导体层的两侧、及第二氧化物半导体层进行离子掺杂，使所述第一氧化物半导体层的两侧区域转变为导体，使所述第二氧化物半导体层转变为氧化物导体层；然后去除余下的第一光阻层的中间区域；
步骤6、在所述第一氧化物半导体层、氧化物导体层、及底栅绝缘层上沉积顶栅绝缘层，通过第七道光罩制程对所述顶栅绝缘层进行图案化处理，形成分别位于所述第一氧化物半导体层两侧区域上方的第一过孔、及位于所述氧化物导体层上方的第二过孔；
步骤7、在所述顶栅绝缘层上沉积第二、第三金属层，通过第八道光罩制程对第二、第三金属层进行图案化处理，分别得到位于所述第一氧化物半导体层上方的顶栅极、位于所述顶栅极两侧的源极与漏极；
所述源极与漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触，所述源极经由所述第二过孔与所述氧化物导体层相接触；
步骤8、在所述顶栅极、源极、漏极及顶栅绝缘层上沉积钝化层；通过第九道光罩制程对所述钝化层、及顶栅绝缘层同时进行图案化处理，得到位于所述氧化物导体层上方的第三过孔，以暴露出部分氧化物导体层；
所述底栅极、第一氧化物半导体层、源极、漏极、及顶栅极构成双栅极TFT；所述氧化物导体层构成LCD的像素电极。
所述步骤3还包括对所述底栅绝缘层进行等离子处理。
所述步骤4采用物理气相沉积法沉积所述氧化物半导体层。
所述步骤6采用干法刻蚀对所述顶栅绝缘层进行图案化处理。
所述氧化物半导体层的材料为IGZO。
所述底栅极、源极、漏极、及顶栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
所述底栅绝缘层及顶栅绝缘层的材料为氮化硅、氧化硅、或二者的组合。
本发明还提供一种双栅极氧化物半导体TFT基板结构，包括基板、设于基板上的底栅极、设于基板与底栅极上的底栅绝缘层、设于底栅绝缘层上的红/绿/蓝色阻层、对应覆盖所述红/绿/蓝色阻层的平坦层、位于底栅极上方设于底栅绝缘层上的第一氧化物半导体层、位于红/绿/蓝色阻层上方设于平坦层上的氧化物导体层、位于所述第一氧化物半导体层、氧化物导体 层、及底栅绝缘层上的顶栅绝缘层、位于所述氧化物半导体层上方设于顶栅绝缘层上的顶栅极、位于顶栅极两侧设于顶栅绝缘层上的源极与漏极、及设于所述顶栅极、源极、漏极、与顶栅绝缘层上的钝化层；
所述第一氧化物半导体层的两侧区域为离子掺杂的导体层；所述顶栅绝缘层对应第一氧化物半导体层两侧区域的上方分别设有第一过孔，所述顶栅绝缘层对应氧化物导体层上方设有第二过孔，所述顶栅绝缘层、及钝化层对应氧化物导体层上方设有第三过孔；
所述源极、漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触；所述源极经由所述第二过孔与所述氧化物导体层相接触；所述第三过孔暴露出部分氧化物导体层；
所述底栅极、第一氧化物半导体层、源极、漏极、及顶栅极构成双栅极TFT；所述氧化物导体层构成LCD的像素电极。
所述第一氧化物半导体层的材料为IGZO，所述氧化物导体层通过对IGZO半导体层进行离子掺杂制得。
所述底栅绝缘层及顶栅绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述底栅极、顶栅极、源极、及漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明还提供一种双栅极氧化物半导体TFT基板结构，包括基板、设于基板上的底栅极、设于基板与底栅极上的底栅绝缘层、设于底栅绝缘层上的红/绿/蓝色阻层、对应覆盖所述红/绿/蓝色阻层的平坦层、位于底栅极上方设于底栅绝缘层上的第一氧化物半导体层、位于红/绿/蓝色阻层上方设于平坦层上的氧化物导体层、位于所述第一氧化物半导体层、氧化物导体层、及底栅绝缘层上的顶栅绝缘层、位于所述氧化物半导体层上方设于顶栅绝缘层上的顶栅极、位于顶栅极两侧设于顶栅绝缘层上的源极与漏极、及设于所述顶栅极、源极、漏极、与顶栅绝缘层上的钝化层；
所述第一氧化物半导体层的两侧区域为离子掺杂的导体层；所述顶栅绝缘层对应第一氧化物半导体层两侧区域的上方分别设有第一过孔，所述顶栅绝缘层对应氧化物导体层上方设有第二过孔，所述顶栅绝缘层、及钝化层对应氧化物导体层上方设有第三过孔；
所述源极、漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触；所述源极经由所述第二过孔与所述氧化物导体层相接触；所述第三过孔暴露出部分氧化物导体层；
所述底栅极、第一氧化物半导体层、源极、漏极、及顶栅极构成双栅极TFT；所述氧化物导体层构成LCD的像素电极；
其中，所述第一氧化物半导体层的材料为IGZO，所述氧化物导体层通过对IGZO半导体层进行离子掺杂制得；
其中，所述底栅绝缘层及顶栅绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述底栅极、顶栅极、源极、及漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
本发明的有益效果：本发明提供的一种双栅极氧化物半导体TFT基板的制作方法，使用半色调掩膜板进行一道光罩制程，既能够完成氧化物半导体层的图案化、又能够通过离子掺杂制得氧化物导体层，该氧化物导体层作为LCD的像素电极替代现有技术中的ITO像素电极；通过一道光罩制程同时制得源极、漏极、与顶栅极；通过一道光罩制程同时对钝化层、及顶栅绝缘层进行图案化处理，光罩减少至九道，缩短了制作工序流程，提高了生产效率，降低了生产成本。本发明提供的一种双栅极氧化物半导体TFT基板结构，通过设置氧化物导体层来作为LCD的像素电极，并将源极、漏极与顶栅极均设置于顶栅绝缘层上，一方面能够简化TFT基板结构，一方面能够使得光罩制程次数减少，制作工序流程缩短，生产效率提高，生产成本降低。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的采用COA技术的适用于LCD的双栅极氧化物半导体TFT基板结构的剖面示意图；
图2为本发明双栅极氧化物半导体TFT基板的制作方法的流程图；
图3为本发明双栅极氧化物半导体TFT基板的制作方法的步骤1的示意图；
图4为本发明双栅极氧化物半导体TFT基板的制作方法的步骤2的示意图；
图5为本发明双栅极氧化物半导体TFT基板的制作方法的步骤3的示意图；
图6为本发明双栅极氧化物半导体TFT基板的制作方法的步骤4的示意图；
图7为本发明双栅极氧化物半导体TFT基板的制作方法的步骤5的示 意图；
图8为本发明双栅极氧化物半导体TFT基板的制作方法的步骤6的示意图；
图9为本发明双栅极氧化物半导体TFT基板的制作方法的步骤7的示意图；
图10为本发明双栅极氧化物半导体TFT基板的制作方法的步骤8的示意图暨本发明双栅极氧化物半导体TFT基板结构的剖面示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2，本发明首先提供一种适用于LCD的双栅极氧化物半导体TFT基板的制作方法，包括如下步骤：
步骤1、如图3所示，提供一基板1，在该基板1上沉积第一金属层，通过第一道光罩制程对所述第一金属层进行图案化处理，形成底栅极2。
具体地，所述基板1为透明基板，优选地，所述基板1为玻璃基板。
所述第一金属层的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合，即所述底栅极2的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
步骤2、如图4所示，在所述底栅极2、及基板1上沉积底栅绝缘层31。
具体地，所述底栅绝缘层31的材料为氮化硅(SiNx)、氧化硅(SiOx)、或二者的组合。
步骤3、如图5所示，在所述底栅绝缘层31上沉积色阻层，分别通过第二、第三、第四道光罩制程依次对所述色阻层进行图案化处理，形成红/绿/蓝色阻层3；接着在所述红/绿/蓝色阻层3上沉积平坦层，通过第五道光罩制程对所述平坦层进行图案化处理，形成分别覆盖所述红/绿/蓝色阻层3的平坦层4。
所述平坦层4的材料为有机光阻，能够对红/绿/蓝色阻层3起到覆盖保护作用。
进一步地，该步骤3还包括对所述底栅绝缘层31进行等离子处理(Plasma Treatment)，以改善所述底栅绝缘层31的膜质。
步骤4、如图6所示，在所述底栅绝缘层31、及平坦层4上沉积氧化物半导体层，在氧化物半导体层上涂覆光阻层，使用半色调掩膜板(Half-Tone)进行第六道光罩制程：先对所述光阻层进行曝光、显影，得 到分别位于所述底栅极2、及平坦层4上方覆盖所述氧化物半导体层的第一光阻层41、及第二光阻层42；所述第一光阻层41的两侧区域、及第二光阻层42的厚度小于所述第一光阻层41的中间区域的厚度。
再利用所述第一光阻层41、及第二光阻层42对所述氧化物半导体层进行刻蚀，使所述氧化物半导体层图案化，得到分别位于所述底栅极2、及平坦层4上方的第一氧化物半导体层51、及第二氧化物半导体层52。
具体地，该步骤4采用物理气相沉积法(Physical Vapor Deposition，PVD)沉积透明的氧化物半导体层。
所述氧化物半导体层的材料为铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)。
步骤5、如图7所示，先去除所述第一光阻层41的两侧区域、及第二光阻层42；以余下的第一光阻层41的中间区域为遮蔽层，对所述第一氧化物半导体层51的两侧、及第二氧化物半导体层52进行离子掺杂，使所述第一氧化物半导体层51的两侧区域转变为导体，使所述第二氧化物半导体层52转变为氧化物导体层52’；然后去除余下的第一光阻层41的中间区域。
步骤6、如图8所示，在所述第一氧化物半导体层51、氧化物导体层52’、及底栅绝缘层31上沉积顶栅绝缘层32，通过第七道光罩制程对所述顶栅绝缘层32进行图案化处理，形成分别位于所述第一氧化物半导体层51两侧区域上方的第一过孔91、及位于所述氧化物导体层52’上方的第二过孔92。
具体地，该步骤6采用干法刻蚀对所述顶栅绝缘层32进行图案化处理。
所述顶栅绝缘层32的材料为氮化硅、氧化硅、或二者的组合。
步骤7、如图9所示，在所述顶栅绝缘层32上沉积第二、第三金属层，通过第八道光罩制程对第二、第三金属层进行图案化处理，分别得到位于所述第一氧化物半导体层51上方的顶栅极71、位于所述顶栅极71两侧的源极81与漏极82。
所述源极81与漏极82分别经由所述第一过孔91与所述第一氧化物半导体层51的两侧区域相接触，所述源极81经由所述第二过孔92与所述氧化物导体层52’相接触。
具体地，所述第二、及第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合，即所述源极81、漏极82、及顶栅极71的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
步骤8、如图10所示，在所述顶栅极71、源极81、漏极82及顶栅绝缘层32上沉积钝化层8；通过第九道光罩制程对所述钝化层8、及顶栅绝 缘层32同时进行图案化处理，得到位于所述氧化物导体层52’上方的第三过孔93，以暴露出部分氧化物导体层52’。
所述底栅极2、第一氧化物半导体层51、源极81、漏极82、及顶栅极71构成双栅极TFT T；所述氧化物导体层52’构成LCD的像素电极。
上述双栅极氧化物半导体TFT基板的制作方法，使用半色调掩膜板进行一道光罩制程，既能够完成氧化物半导体层的图案化、又能够通过离子掺杂制得氧化物导体层52’；通过一道光罩制程同时制得源极81、漏极82、与顶栅极71；通过一道光罩制程同时对钝化层8、及顶栅绝缘层32进行图案化处理，光罩制程减少至九道，缩短了制作工序流程，提高了生产效率，降低了生产成本。
请参阅图10，本发明还提供一种适用于LCD的双栅极氧化物半导体TFT基板结构，包括基板1、设于基板1上的底栅极2、设于基板1与底栅极2上的底栅绝缘层31、设于底栅绝缘层31上的红/绿/蓝色阻层3、对应覆盖所述红/绿/蓝色阻层3的平坦层4、位于底栅极2上方设于底栅绝缘层31上的第一氧化物半导体层51、位于红/绿/蓝色阻层3上方设于平坦层4上的氧化物导体层52’、位于所述第一氧化物半导体层51、氧化物导体层52’、及底栅绝缘层31上的顶栅绝缘层32、位于所述氧化物半导体层51上方设于顶栅绝缘层32上的顶栅极71、位于顶栅极71两侧设于顶栅绝缘层32上的源极
81与漏极82、及设于所述顶栅极71、源极81、漏极82、与顶栅绝缘层32上的钝化层8。
具体地，所述第一氧化物半导体层51的两侧区域为离子掺杂的导体层；所述顶栅绝缘层32对应第一氧化物半导体层51两侧区域的上方分别设有第一过孔91，所述顶栅绝缘层32对应氧化物导体层52’上方设有第二过孔92，所述顶栅绝缘层32、及钝化层8对应氧化物导体层52’上方设有第三过孔93。
所述源极81、漏极82分别经由所述第一过孔91与所述第一氧化物半导体层51的两侧区域相接触；所述源极81经由所述第二过孔92与所述氧化物导体层52’相接触；所述第三过孔93暴露出部分氧化物导体层52’。
所述底栅极21、第一氧化物半导体层51、源极81、漏极82、及顶栅极71构成双栅极TFT T；所述氧化物导体层52’构成LCD的像素电极。
具体地，所述第一氧化物半导体层51的材料为IGZO，所述氧化物导体层52’通过对IGZO半导体层进行离子掺杂制得。所述底栅绝缘层31及顶栅绝缘层32的材料为氮化硅、氧化硅、或二者的组合；所述底栅极2、 顶栅极71、源极81、及漏极82的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
上述双栅极氧化物半导体TFT基板结构，设置氧化物导体层52’来作为LCD的像素电极，且该氧化物导体层52’与所述第一氧化物半导体层51经一道光罩制程制作；将源极81、漏极82、及顶栅极71均设置于顶栅绝缘层32上，一方面能够简化TFT基板结构，一方面能够使得光罩制程次数减少，制作工序流程缩短，生产效率提高，生产成本降低。
综上所述，本发明的双栅极氧化物半导体TFT基板的制作方法，使用半色调掩膜板进行一道光罩制程，既能够完成氧化物半导体层的图案化、又能够通过离子掺杂制得氧化物导体层，该氧化物导体层作为LCD的像素电极替代现有技术中的ITO像素电极；通过一道光罩制程同时制得源极、漏极、与顶栅极；通过一道光罩制程同时对钝化层、及顶栅绝缘层进行图案化处理，光罩制程减少至九道，缩短了制作工序流程，提高了生产效率，降低了生产成本。本发明的双栅极氧化物半导体TFT基板结构，通过设置氧化物导体层来作为LCD的像素电极，并将源极、漏极与顶栅极均设置于顶栅绝缘层上，
一方面能够简化TFT基板结构，一方面能够使得光罩制程次数减少，制作工序流程缩短，生产效率提高，生产成本降低。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (11)

  1. 一种双栅极氧化物半导体TFT基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在该基板上沉积第一金属层，通过第一道光罩制程对所述第一金属层进行图案化处理，形成底栅极；
    步骤2、在所述底栅极、及基板上沉积底栅绝缘层；
    步骤3、在所述底栅绝缘层上沉积色阻层，分别通过第二、第三、第四道光罩制程依次对所述色阻层进行图案化处理，形成红/绿/蓝色阻层；接着在所述红/绿/蓝色阻层上沉积平坦层，通过第五道光罩制程对所述平坦层进行图案化处理，形成分别覆盖所述红/绿/蓝色阻层的平坦层；
    步骤4、在所述底栅绝缘层、及平坦层上沉积氧化物半导体层，在氧化物半导体层上涂覆光阻层，使用半色调掩膜板进行第六道光罩制程：先对所述光阻层进行曝光、显影，得到分别位于所述底栅极、及平坦层上方覆盖所述氧化物半导体层的第一光阻层、及第二光阻层；所述第一光阻层的两侧区域、及第二光阻层的厚度小于所述第一光阻层的中间区域的厚度；
    再利用所述第一光阻层、及第二光阻层对所述氧化物半导体层进行刻蚀，使所述氧化物半导体层图案化，得到分别位于所述底栅极、及平坦层上方的第一氧化物半导体层、及第二氧化物半导体层；
    步骤5、先去除所述第一光阻层的两侧区域、及第二光阻层；以余下的第一光阻层的中间区域为遮蔽层，对所述第一氧化物半导体层的两侧、及第二氧化物半导体层进行离子掺杂，使所述第一氧化物半导体层的两侧区域转变为导体，使所述第二氧化物半导体层转变为氧化物导体层；然后去除余下的第一光阻层的中间区域；
    步骤6、在所述第一氧化物半导体层、氧化物导体层、及底栅绝缘层上沉积顶栅绝缘层，通过第七道光罩制程对所述顶栅绝缘层进行图案化处理，形成分别位于所述第一氧化物半导体层两侧区域上方的第一过孔、及位于所述氧化物导体层上方的第二过孔；
    步骤7、在所述顶栅绝缘层上沉积第二、第三金属层，通过第八道光罩制程对第二、第三金属层进行图案化处理，分别得到位于所述第一氧化物半导体层上方的顶栅极、位于所述顶栅极两侧的源极与漏极；
    所述源极与漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触，所述源极经由所述第二过孔与所述氧化物导体层相接触；
    步骤8、在所述顶栅极、源极、漏极及顶栅绝缘层上沉积钝化层；通过 第九道光罩制程对所述钝化层、及顶栅绝缘层同时进行图案化处理，得到位于所述氧化物导体层上方的第三过孔，以暴露出部分氧化物导体层；
    所述底栅极、第一氧化物半导体层、源极、漏极、及顶栅极构成双栅极TFT；所述氧化物导体层构成LCD的像素电极。
  2. 如权利要求1所述的双栅极氧化物半导体TFT基板的制作方法，其中，所述步骤3还包括对所述底栅绝缘层进行等离子处理。
  3. 如权利要求1所述的双栅极氧化物半导体TFT基板的制作方法，其中，所述步骤4采用物理气相沉积法沉积所述氧化物半导体层。
  4. 如权利要求1所述的双栅极氧化物半导体TFT基板的制作方法，其中，所述步骤6采用干法刻蚀对所述顶栅绝缘层进行图案化处理。
  5. 如权利要求1所述的双栅极氧化物半导体TFT基板的制作方法，其中，所述氧化物半导体层的材料为IGZO。
  6. 如权利要求1所述的双栅极氧化物半导体TFT基板的制作方法，其中，所述底栅极、源极、漏极、及顶栅极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  7. 如权利要求1所述的双栅极氧化物半导体TFT基板的制作方法，其中，所述底栅绝缘层及顶栅绝缘层的材料为氮化硅、氧化硅、或二者的组合。
  8. 一种双栅极氧化物半导体TFT基板结构，包括基板、设于基板上的底栅极、设于基板与底栅极上的底栅绝缘层、设于底栅绝缘层上的红/绿/蓝色阻层、对应覆盖所述红/绿/蓝色阻层的平坦层、位于底栅极上方设于底栅绝缘层上的第一氧化物半导体层、位于红/绿/蓝色阻层上方设于平坦层上的氧化物导体层、位于所述第一氧化物半导体层、氧化物导体层、及底栅绝缘层上的顶栅绝缘层、位于所述氧化物半导体层上方设于顶栅绝缘层上的顶栅极、位于顶栅极两侧设于顶栅绝缘层上的源极与漏极、及设于所述顶栅极、源极、漏极、与顶栅绝缘层上的钝化层；
    所述第一氧化物半导体层的两侧区域为离子掺杂的导体层；所述顶栅绝缘层对应第一氧化物半导体层两侧区域的上方分别设有第一过孔，所述顶栅绝缘层对应氧化物导体层上方设有第二过孔，所述顶栅绝缘层、及钝化层对应氧化物导体层上方设有第三过孔；
    所述源极、漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触；所述源极经由所述第二过孔与所述氧化物导体层相接触；所述第三过孔暴露出部分氧化物导体层；
    所述底栅极、第一氧化物半导体层、源极、漏极、及顶栅极构成双栅 极TFT；所述氧化物导体层构成LCD的像素电极。
  9. 如权利要求8所述的双栅极氧化物半导体TFT基板结构，其中，所述第一氧化物半导体层的材料为IGZO，所述氧化物导体层通过对IGZO半导体层进行离子掺杂制得。
  10. 如权利要求8所述的双栅极氧化物半导体TFT基板结构，其中，所述底栅绝缘层及顶栅绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述底栅极、顶栅极、源极、及漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
  11. 一种双栅极氧化物半导体TFT基板结构，包括基板、设于基板上的底栅极、设于基板与底栅极上的底栅绝缘层、设于底栅绝缘层上的红/绿/蓝色阻层、对应覆盖所述红/绿/蓝色阻层的平坦层、位于底栅极上方设于底栅绝缘层上的第一氧化物半导体层、位于红/绿/蓝色阻层上方设于平坦层上的氧化物导体层、位于所述第一氧化物半导体层、氧化物导体层、及底栅绝缘层上的顶栅绝缘层、位于所述氧化物半导体层上方设于顶栅绝缘层上的顶栅极、位于顶栅极两侧设于顶栅绝缘层上的源极与漏极、及设于所述顶栅极、源极、漏极、与顶栅绝缘层上的钝化层；
    所述第一氧化物半导体层的两侧区域为离子掺杂的导体层；所述顶栅绝缘层对应第一氧化物半导体层两侧区域的上方分别设有第一过孔，所述顶栅绝缘层对应氧化物导体层上方设有第二过孔，所述顶栅绝缘层、及钝化层对应氧化物导体层上方设有第三过孔；
    所述源极、漏极分别经由所述第一过孔与所述第一氧化物半导体层的两侧区域相接触；所述源极经由所述第二过孔与所述氧化物导体层相接触；所述第三过孔暴露出部分氧化物导体层；
    所述底栅极、第一氧化物半导体层、源极、漏极、及顶栅极构成双栅极TFT；所述氧化物导体层构成LCD的像素电极；
    其中，所述第一氧化物半导体层的材料为IGZO，所述氧化物导体层通过对IGZO半导体层进行离子掺杂制得；
    其中，所述底栅绝缘层及顶栅绝缘层的材料为氮化硅、氧化硅、或二者的组合；所述底栅极、顶栅极、源极、及漏极的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104952880A (zh) * 2015-05-06 2015-09-30 深圳市华星光电技术有限公司 双栅极tft基板的制作方法及其结构
CN105304643A (zh) * 2015-09-28 2016-02-03 深圳市华星光电技术有限公司 一种tft阵列基板及其制作方法
CN105226015B (zh) * 2015-09-28 2018-03-13 深圳市华星光电技术有限公司 一种tft阵列基板及其制作方法
CN108780221B (zh) * 2016-03-25 2020-11-03 夏普株式会社 显示面板、显示装置和显示面板的制造方法
CN107204309B (zh) * 2017-05-22 2019-09-24 深圳市华星光电技术有限公司 双栅极金属氧化物半导体tft基板的制作方法及其结构
CN107293554A (zh) * 2017-06-19 2017-10-24 深圳市华星光电技术有限公司 顶发射型oled面板的制作方法及其结构
US11011642B2 (en) * 2018-06-19 2021-05-18 Ohio University Ambipolar field-effect device using engineered work-functions
CN209000913U (zh) * 2018-11-06 2019-06-18 惠科股份有限公司 一种显示面板和显示装置
CN110211925B (zh) * 2019-04-04 2021-07-06 Tcl华星光电技术有限公司 顶发光型氧化铟镓锌薄膜晶体管器件制造方法
CN111477687A (zh) * 2020-04-26 2020-07-31 昆山龙腾光电股份有限公司 氧化物薄膜晶体管及其制作方法
US12068333B2 (en) * 2020-09-30 2024-08-20 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate, display panel, and display device
WO2022257081A1 (zh) 2021-06-10 2022-12-15 京东方科技集团股份有限公司 显示面板及其制作方法、显示装置
CN115472506B (zh) * 2021-07-08 2025-02-07 北京邮电大学 双栅极器件的制备方法及双栅极器件
CN114594639A (zh) * 2022-03-09 2022-06-07 昆山龙腾光电股份有限公司 阵列基板及制作方法
CN115084277A (zh) * 2022-06-29 2022-09-20 昆山龙腾光电股份有限公司 金属氧化物薄膜晶体管及其制作方法、阵列基板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102956649A (zh) * 2012-11-26 2013-03-06 京东方科技集团股份有限公司 阵列基板、阵列基板制作方法及显示装置
CN103309081A (zh) * 2013-05-30 2013-09-18 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN103681514A (zh) * 2013-12-23 2014-03-26 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104867959A (zh) * 2015-04-14 2015-08-26 深圳市华星光电技术有限公司 双栅极氧化物半导体tft基板的制作方法及其结构

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100425858B1 (ko) * 1998-07-30 2004-08-09 엘지.필립스 엘시디 주식회사 박막트랜지스터및그제조방법
JP3498020B2 (ja) * 1999-09-29 2004-02-16 Ｎｅｃ液晶テクノロジー株式会社 アクティブマトリックス基板及びその製造方法
JP4869516B2 (ja) * 2001-08-10 2012-02-08 株式会社半導体エネルギー研究所 半導体装置
TW546853B (en) * 2002-05-01 2003-08-11 Au Optronics Corp Active type OLED and the fabrication method thereof
US7297977B2 (en) * 2004-03-12 2007-11-20 Hewlett-Packard Development Company, L.P. Semiconductor device
US20150357480A1 (en) * 2008-09-08 2015-12-10 Gang Yu Stable metal-oxide thin film transistor and method of making
WO2010110179A1 (ja) * 2009-03-23 2010-09-30 株式会社フューチャービジョン アクティブ素子基板とその製造方法、及びこの製造方法で製造したアクティブ素子基板を用いた表示装置
JP5796760B2 (ja) * 2009-07-29 2015-10-21 Ｎｌｔテクノロジー株式会社 トランジスタ回路
JP5323604B2 (ja) * 2009-07-30 2013-10-23 株式会社ジャパンディスプレイ 表示装置及びその製造方法
US20120146043A1 (en) * 2009-09-01 2012-06-14 Sharp Kabushiki Kaisha Semiconductor device, active matrix substrate, and display device
US20120153289A1 (en) * 2009-09-01 2012-06-21 Sharp Kabushiki Kaisha Semiconductor device, active matrix substrate, and display device
US20120200546A1 (en) * 2009-10-16 2012-08-09 Sharp Kabushiki Kaisha Semiconductor device, display device provided with same, and method for manufacturing semiconductor device
KR101274591B1 (ko) * 2009-12-18 2013-06-13 엘지디스플레이 주식회사 표면 플라즈몬을 이용한 컬러필터와 액정표시장치 및 그 제조방법
KR101272052B1 (ko) * 2009-12-18 2013-06-05 엘지디스플레이 주식회사 표면 플라즈몬을 이용한 컬러필터 및 액정표시장치의 제조방법
JP2011181596A (ja) * 2010-02-26 2011-09-15 Mitsubishi Electric Corp 半導体装置及びその製造方法
KR101741732B1 (ko) * 2010-05-07 2017-05-31 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
KR101108176B1 (ko) * 2010-07-07 2012-01-31 삼성모바일디스플레이주식회사 더블 게이트형 박막 트랜지스터 및 이를 구비한 유기 발광 표시 장치
CN102130009B (zh) * 2010-12-01 2012-12-05 北京大学深圳研究生院 一种晶体管的制造方法
JP2012146956A (ja) * 2010-12-20 2012-08-02 Canon Inc チャネルエッチ型薄膜トランジスタとその製造方法
KR101483026B1 (ko) * 2012-08-31 2015-01-15 엘지디스플레이 주식회사 산화물 박막트랜지스터를 포함하는 기판 및 이의 제조방법, 이를 이용한 액정표시장치용 구동회로
CN105026962B (zh) * 2013-01-25 2018-05-04 凸版印刷株式会社 滤色器基板、液晶显示装置及滤色器基板的制造方法
US9012261B2 (en) * 2013-03-13 2015-04-21 Intermolecular, Inc. High productivity combinatorial screening for stable metal oxide TFTs
CN103309108B (zh) * 2013-05-30 2016-02-10 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
KR102063983B1 (ko) * 2013-06-26 2020-02-11 엘지디스플레이 주식회사 금속 산화물 반도체를 포함하는 박막 트랜지스터 기판 및 그 제조 방법
KR102045036B1 (ko) * 2013-08-27 2019-11-14 엘지디스플레이 주식회사 고 개구율 유기발광 다이오드 표시장치 및 그 제조 방법
KR102227474B1 (ko) * 2013-11-05 2021-03-15 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판, 유기발광표시장치 및 박막트랜지스터 어레이 기판의 제조 방법
US9105527B2 (en) * 2013-12-19 2015-08-11 Intermolecular, Inc. High Productivity Combinatorial material screening for stable, high-mobility non-silicon thin film transistors
CN103715267A (zh) * 2013-12-30 2014-04-09 京东方科技集团股份有限公司 薄膜晶体管、tft阵列基板及其制造方法和显示装置
TWI560882B (en) * 2014-01-17 2016-12-01 E Ink Holdings Inc Semiconductor structure
US20160013243A1 (en) * 2014-03-10 2016-01-14 Dpix, Llc Photosensor arrays for detection of radiation and process for the preparation thereof
US9337030B2 (en) * 2014-03-26 2016-05-10 Intermolecular, Inc. Method to grow in-situ crystalline IGZO using co-sputtering targets
US20150279674A1 (en) * 2014-04-01 2015-10-01 Intermolecular, Inc. CAAC IGZO Deposited at Room Temperature
KR101600306B1 (ko) * 2014-04-17 2016-03-08 엘지디스플레이 주식회사 표시장치용 어레이 기판 및 그 제조방법
US20160079385A1 (en) * 2014-09-16 2016-03-17 Carolyn Rae Ellinger Vertical tft with multilayer passivation
US9391210B2 (en) * 2014-09-16 2016-07-12 Eastman Kodak Company Top gate TFT with polymer interface control layer
US9577104B2 (en) * 2014-11-11 2017-02-21 Shenzhen China Star Optoelectronics Technology Co., Ltd COA substrate and liquid crystal display panel
US9761732B2 (en) * 2015-02-25 2017-09-12 Snaptrack Inc. Tunnel thin film transistor with hetero-junction structure
CN104966501B (zh) * 2015-07-21 2017-07-28 深圳市华星光电技术有限公司 用于窄边框lcd的goa电路结构

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102956649A (zh) * 2012-11-26 2013-03-06 京东方科技集团股份有限公司 阵列基板、阵列基板制作方法及显示装置
CN103309081A (zh) * 2013-05-30 2013-09-18 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN103681514A (zh) * 2013-12-23 2014-03-26 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104867959A (zh) * 2015-04-14 2015-08-26 深圳市华星光电技术有限公司 双栅极氧化物半导体tft基板的制作方法及其结构

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BAEK GWANGHYEON ET AL.: "Electrical Properties and Stability of Dual-Gate Coplanar Homojunction DC Supttered A-IGZO TFT and Its Application to AM -OLEDs", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 58, no. 12, 31 December 2011 (2011-12-31), pages 4345, XP011369484 *

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