WO2022257081A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2022257081A1
WO2022257081A1 PCT/CN2021/099477 CN2021099477W WO2022257081A1 WO 2022257081 A1 WO2022257081 A1 WO 2022257081A1 CN 2021099477 W CN2021099477 W CN 2021099477W WO 2022257081 A1 WO2022257081 A1 WO 2022257081A1
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sub
active
base substrate
conductive
orthographic projection
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PCT/CN2021/099477
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English (en)
French (fr)
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WO2022257081A9 (zh
Inventor
杨维
刘凤娟
刘威
宁策
袁广才
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180001515.1A priority Critical patent/CN115812232A/zh
Priority to EP21944590.5A priority patent/EP4207152A4/en
Priority to PCT/CN2021/099477 priority patent/WO2022257081A1/zh
Publication of WO2022257081A1 publication Critical patent/WO2022257081A1/zh
Publication of WO2022257081A9 publication Critical patent/WO2022257081A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a manufacturing method thereof, and a display device.
  • Display panels generally include multiple circuits such as pixel drive circuits and gate drive circuits integrated on the array substrate, and various circuits integrated on the array substrate generally include transistors.
  • circuits such as pixel drive circuits and gate drive circuits integrated on the array substrate
  • various circuits integrated on the array substrate generally include transistors.
  • the size of transistors cannot Meet preset requirements.
  • a display panel wherein the display panel includes a first transistor, and the display panel includes: a base substrate, a second conductive layer, a second active layer, a third gate insulation layer, the third conductive layer.
  • the second conductive layer is located on one side of the base substrate, the second conductive layer includes a first conductive part, and the first conductive part is used to form the first gate of the first transistor;
  • the second active layer is located on the side of the second conductive layer away from the base substrate, the second active layer includes a first active portion, and the first active portion includes a first sub-active portion, a second sub-active portion an active part, a third sub-active part connected between the first sub-active part and the second sub-active part; the first sub-active part is used to form the first transistor
  • the first pole, the second sub-active part is used to form the second pole of the first transistor, the partial structure of the third sub-active part is used to form the channel region of the first transistor, and the first sub-active part is used to form the channel region of the first transistor.
  • a conductive part covers the orthographic projection of the third sub-active part on the base substrate in the orthographic projection of the base substrate; the third gate insulating layer is located on the side of the second active layer away from the base substrate On one side, the orthographic projection of the third gate insulating layer on the base substrate covers the orthographic projection of the first active part on the base substrate; the third conductive layer is located on the third gate insulating layer. layer away from the side of the base substrate, the third conductive layer includes a second conductive part, the second conductive part is used to form the second gate of the first transistor, and the second conductive part
  • the orthographic projection on the base substrate covers the orthographic projection of the channel region of the first transistor on the base substrate.
  • the third sub-active portion includes a first sub-active portion, a second sub-active portion, and a third sub-active portion, and the first sub-active portion is connected to the Between the first sub-active part and the third sub-active part, the second sub-active part is connected between the third sub-active part and the second sub-active part, the first sub-active part
  • the three sub-active parts are used to form the channel region of the first transistor; the orthographic projection of the second conductive part on the base substrate covers the orthographic projection of the third sub-active part on the base substrate, and
  • the second conductive portion is located between the first sub-active portion on the base substrate and the second sub-active portion on the base substrate in the orthographic projection of the base substrate .
  • the difference between the square resistance of the first sub-active part and the square resistance of the second sub-active part is less than a preset value, and the preset value is 0-100 ⁇ /sq , the sheet resistance of the first sub-active portion is smaller than the sheet resistance of the first sub-active portion, and the sheet resistance of the first sub-active portion is smaller than the sheet resistance of the second sub-active portion.
  • the difference between the square resistance of the first sub-active part and the square resistance of the second sub-active part is less than a preset value, and the preset value is 0-100 ⁇ /sq , the sheet resistance of the first sub-active part is 2000 ⁇ 20000 ⁇ /sq.
  • the sheet resistance of the first sub-active part is 500-2000 ⁇ /sq
  • the sheet resistance of the second sub-active part is 500-2000 ⁇ /sq.
  • the display panel further includes: a fourth conductive layer located on a side of the third conductive layer away from the base substrate, and the fourth conductive layer includes a third conductive portion and a fourth conductive part; the third conductive part is connected to the first sub-active part through a first via hole, and the fourth conductive part is connected to the second sub-active part through a second via hole.
  • the first via hole is located on the orthographic projection of the first sub-active portion on the base substrate in the orthographic projection of the base substrate, and the second via hole is located in the
  • the orthographic projection of the substrate is located on the orthographic projection of the second sub-active part on the orthographic projection of the substrate; the area of the orthographic projection of the first via hole on the substrate is smaller than or equal to that of the first sub-active portion
  • the area of the orthographic projection of the source portion on the base substrate; the area of the orthographic projection of the second via hole on the base substrate is smaller than or equal to the area of the orthographic projection of the second sub-active portion on the base substrate.
  • the orthographic projection of the edge of the first sub-active portion on the base substrate at least partially coincides with the orthographic projection of the first conductive portion on the base substrate;
  • the orthographic projection of the edge of the two sub-active parts on the base substrate is at least partially coincident with the orthographic projection of the first conductive part on the base substrate.
  • the first active part further includes a sixth sub-active part, and the sixth sub-active part is located between the first sub-active part and the third sub-active part.
  • the sixth sub-active part is located on the substrate orthographic projection of the first sub-active part and the first conductive part is on the substrate orthographic projection.
  • the sheet resistance of the sixth sub-active part is 2000-20000 ⁇ /sq.
  • the first transistor is an oxide transistor.
  • the display panel further includes a pixel driving circuit, the pixel driving circuit includes the first transistor; the pixel driving circuit further includes a driving transistor, and the first transistor of the first transistor The pole is connected to the gate of the drive transistor, and the second pole is connected to the first initial signal terminal; the pixel drive circuit also includes a second transistor, the first pole of the second transistor is connected to the gate of the drive transistor, and the second pole is connected to the gate of the drive transistor. The two poles are connected to the second pole of the driving transistor, and the second transistor is an oxide transistor.
  • the first active part further includes: a fourth sub-active part, a fifth sub-active part, and the fourth sub-active part is used to form the first sub-active part of the second transistor.
  • Diode; the fifth sub-active part is connected between the fourth sub-active part and the first sub-active part, and a part of the structure of the fifth sub-active part is used to form the second transistor channel region; the first sub-active portion is shared as the first pole of the second transistor;
  • the second conductive layer further includes a fifth conductive portion, and the fifth conductive portion is used to form the first The first gate of the second transistor, the fifth conductive part covers the fifth sub-active part on the base substrate orthographic projection; the third conductive layer also includes a sixth A conductive part, the sixth conductive part is used to form the second gate of the second transistor, and the orthographic projection of the sixth conductive part on the base substrate covers the channel region of the second transistor in the An orthographic projection of the substrate substrate described above.
  • the fifth sub-active part includes a fourth sub-active part, a fifth sub-active part, and a sixth sub-active part, and the fourth sub-active part is connected to Between the first sub-active part and the sixth sub-active part, the fifth sub-active part is connected between the sixth sub-active part and the fourth sub-active part,
  • the sixth sub-active portion is used to form the channel region of the second transistor; the sixth conductive portion covers the sixth sub-active portion on the base substrate in an orthographic projection on the base substrate In an orthographic projection, the sixth conductive part is located on the orthographic projection of the base substrate on the fifth sub-active part and on the orthographic projection of the base substrate and the fourth sub-active part is on the orthographic projection of the base substrate between projections.
  • the difference between the square resistance of the fourth sub-active part and the square resistance of the fifth sub-active part is less than a preset value, and the preset value is 0-100 ⁇ /sq , the square resistance of the fourth sub-active part is smaller than the square resistance of the fourth sub-active part, and the square resistance of the fourth sub-active part is smaller than the square resistance of the first sub-active part.
  • the difference between the square resistance of the fourth sub-active part and the square resistance of the fifth sub-active part is less than a preset value, and the preset value is 0-100 ⁇ /sq , the sheet resistance of the fourth sub-active part is 2000 ⁇ 20000 ⁇ /sq.
  • a method for manufacturing a display panel wherein the display panel includes a first transistor, and the method for manufacturing a display panel includes:
  • a second conductive layer is formed on one side of the base substrate, the second conductive layer includes a first conductive part, and the first conductive part is used to form a first gate of the first transistor;
  • a second active material layer is formed on the side of the second conductive layer away from the base substrate, the second active material layer includes a first active material portion, and the first active material portion includes a first active material portion.
  • the partial structure of the third sub-active material part is used to form the channel region of the first transistor, and the first conductive part covers the third sub-active material part in the orthographic projection of the base substrate an orthographic projection on the substrate substrate;
  • a third gate insulating layer is formed on the side of the second active material layer away from the base substrate, and the third gate insulating layer covers the first active material layer in the orthographic projection of the base substrate. an orthographic projection of the material part on the base substrate;
  • a third conductive layer is formed on a side of the third gate insulating layer away from the base substrate, the third conductive layer includes a second conductive part, and the second conductive part is used to form the first transistor
  • the second grid, and the orthographic projection of the second conductive part on the base substrate partly overlaps with the orthographic projection of the third sub-active material part on the base substrate;
  • the first transistor is an oxidation transistor
  • the second active material layer is an oxide semiconductor
  • conducting the second active material layer by using the third conductive layer as a mask includes:
  • conducting ions are generated during the formation of the second dielectric layer, and the conducting ions can conduct the second active material layer.
  • the material of the second dielectric layer is silicon nitride, and the conductive ions are hydrogen ions.
  • the display panel manufacturing method further includes:
  • a first via hole and a second via hole penetrating through the third gate insulating layer and the second dielectric layer are formed by dry etching gas, and the first via hole is located at the The first sub-active material portion is on the orthographic projection of the base substrate, and the second via hole is located on the orthographic projection of the base substrate of the second sub-active material portion on the orthographic projection of the base substrate , wherein the dry etching gas can generate conductive ions during the dry etching process, and the conductive ions can conduct the second active material layer;
  • the fourth conductive layer including a third conductive portion and a fourth conductive portion
  • the third conductive part is connected to the first sub-active material part through the first via hole, and the fourth conductive part is connected to the second sub-active material part through the second via hole.
  • the area of the orthographic projection of the first via hole on the base substrate is smaller than or equal to the area of the orthographic projection of the first sub-active material portion on the base substrate;
  • the area of the orthographic projection of the second via hole on the base substrate is smaller than or equal to the area of the orthographic projection of the second sub-active material portion on the base substrate.
  • the orthographic projection of the edge of the first sub-active material portion on the base substrate at least partially coincides with the orthographic projection of the first conductive portion on the base substrate;
  • the orthographic projection of the edge of the second sub-active material portion on the base substrate is at least partially coincident with the orthographic projection of the first conductive portion on the base substrate.
  • conducting the second active material layer by using the third conductive layer as a mask includes:
  • Conducting ions are implanted into the second active material layer through an ion implantation process.
  • the third sub-active material portion includes a first sub-active material portion, a second sub-active material portion, and a third sub-active material portion, and the first sub-active material portion
  • the material part is connected between the first sub-active material part and the third sub-active material part
  • the second sub-active material part is connected between the third sub-active material part and the second sub-active material part.
  • the orthographic projection of the second conductive part on the base substrate covers the orthographic projection of the third sub-active material part on the base substrate.
  • a display device wherein the display device includes the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of a circuit structure of a pixel driving circuit in the related art
  • FIG. 2 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 1;
  • FIG. 3 is a structural layout of a display panel in the related art
  • FIG. 4 is a structural layout of the first active layer in FIG. 3;
  • FIG. 5 is a structural layout of the first conductive layer in FIG. 3;
  • FIG. 6 is a structural layout of the second conductive layer in FIG. 3;
  • FIG. 7 is a structural layout of the second active layer in FIG. 3;
  • FIG. 8 is a structural layout of the third conductive layer in FIG. 3;
  • FIG. 9 is a structural layout of the fourth conductive layer in FIG. 3;
  • FIG. 10 is a structural layout of the fifth conductive layer in FIG. 3;
  • FIG. 11 is a structural layout of the first active layer and the first conductive layer in FIG. 3;
  • FIG. 12 is a structural layout of the first active layer, the first conductive layer, and the second conductive layer in FIG. 3;
  • FIG. 13 is a structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG. 3;
  • FIG. 14 is a structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG. 3;
  • FIG. 15 is a structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG. 3;
  • Fig. 16 is a partial cross-sectional view at the dotted line A in Fig. 15;
  • FIG. 17 is a process flow diagram of an exemplary embodiment of the method for manufacturing a display panel of the present disclosure.
  • FIG. 18 is a process flow diagram of an exemplary embodiment of a method for manufacturing a display panel of the present disclosure
  • FIG. 19 is a process flow diagram of an exemplary embodiment of a method for manufacturing a display panel of the present disclosure.
  • FIG. 20 is a structural layout of an exemplary embodiment of a display panel of the present disclosure.
  • FIG. 21 is a structural layout of the first active layer in FIG. 20;
  • FIG. 22 is a structural layout of the first conductive layer in FIG. 20;
  • FIG. 23 is a structural layout of the second conductive layer in FIG. 20;
  • FIG. 24 is a structural layout of the second active layer in FIG. 20;
  • FIG. 25 is a structural layout of the third conductive layer in FIG. 20;
  • FIG. 26 is a structural layout of the fourth conductive layer in FIG. 20;
  • FIG. 27 is a structural layout of the fifth conductive layer in FIG. 20;
  • FIG. 28 is a structural layout of the first active layer and the first conductive layer in FIG. 20;
  • FIG. 29 is a structural layout of the first active layer, the first conductive layer, and the second conductive layer in FIG. 20;
  • FIG. 30 is a structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG. 20;
  • FIG. 31 is a structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG. 20;
  • FIG. 32 is a structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG. 20;
  • 33 is a partial structural layout of the second conductive layer and the second active layer in 20;
  • 34 is a partial structural layout of the second conductive layer, the second active layer, and the third conductive layer in 20;
  • Figure 35 is a partial cross-sectional view along the dotted line B in Figure 32;
  • FIG. 36 is a schematic structural diagram of a first transistor in another exemplary embodiment of a display panel of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • the pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C.
  • the first pole of the fourth transistor T4 is connected to the data signal terminal Da
  • the second pole is connected to the first pole of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2
  • the first pole of the fifth transistor T5 is connected to the A power supply terminal VDD
  • the second pole is connected to the first pole of the driving transistor T3, and the gate is connected to the enable signal terminal EM
  • the gate of the driving transistor T3 is connected to the node N
  • the first pole of the second transistor T2 is connected to the node N
  • the second pole is connected to the node N.
  • the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor T3, and the second pole is connected to the first pole of the seventh transistor T7.
  • the pixel driving circuit may be connected to a light emitting unit OLED for driving the light emitting unit OLED to emit light, and the light emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power supply terminal VSS.
  • the first transistor T1 and the second transistor T2 can be N-type metal oxide transistors, and the N-type metal oxide transistors have a small leakage current, so that the light-emitting phase can be avoided, and the node N passes through the first transistor T1 and the second transistor T2 leakage.
  • the driving transistor T3, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polysilicon transistors, and low-temperature polysilicon transistors have higher carrier Mobility, which is conducive to the realization of display panels with high resolution, high response speed, high pixel density, and high aperture ratio.
  • the first initial signal terminal and the second initial signal terminal may output the same or different voltage signals according to actual conditions.
  • FIG. 2 it is a timing diagram of each node in a driving method of the pixel driving circuit in FIG. 1 .
  • G1 represents the timing of the first gate driving signal terminal G1
  • G2 represents the timing of the second gate driving signal terminal G2
  • Re1 represents the timing of the first reset signal terminal Re1
  • Re2 represents the timing of the second reset signal terminal Re2
  • EM represents the timing of the enable signal terminal EM
  • Da represents the timing of the data signal terminal Da.
  • the driving method of the pixel driving circuit may include a first reset phase t1, a compensation phase t2, a second reset phase T3, and a light emitting phase t4.
  • the first reset phase t1 the first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs an initial signal to the node N.
  • the compensation stage t2 the first gate drive signal terminal G1 outputs a high-level signal, the second gate drive signal terminal G2 outputs a low-level signal, the fourth transistor T4, the second transistor T2, and the data signal terminal Da outputs a drive The signal is to write the voltage Vdata+Vth to the node N, wherein Vdata is the voltage of the driving signal, and Vth is the threshold voltage of the driving transistor T3.
  • the second reset signal terminal Re2 outputs a low level signal
  • the seventh The transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second pole of the sixth transistor T6.
  • the driving transistor output current formula I ( ⁇ WCox/2L)(Vgs-Vth) 2 , where ⁇ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, and L drives The length of the transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor.
  • the pixel driving circuit can avoid the influence of the threshold value of the driving transistor on its output current. It should be understood that the pixel driving circuit shown in FIG. 1 can also have other driving methods, for example, both the first transistor T1 and the seventh transistor T7 can be reset in the first reset stage, so the driving method does not need to set the second reset stage .
  • the display panel may include the pixel driving circuit shown in FIG. Source layer, third conductive layer, fourth conductive layer, fifth conductive layer.
  • An insulating layer may be provided between the above-mentioned levels.
  • Figure 3 is the structural layout of the display panel in the related art
  • Figure 4 is the structural layout of the first active layer in Figure 3
  • Figure 5 is the structural layout of the first conductive layer in Figure 3
  • 6 is the structural layout of the second conductive layer in FIG. 3
  • FIG. 7 is the structural layout of the second active layer in FIG.
  • FIG. 8 is the structural layout of the third conductive layer in FIG. 3
  • FIG. 9 is the fourth active layer in FIG.
  • FIG. 10 The structural layout of the conductive layer
  • Figure 10 is the structural layout of the fifth conductive layer in Figure 3
  • Figure 11 is the structural layout of the first active layer and the first conductive layer in Figure 3
  • Figure 12 is the first active layer in Figure 3 Layer
  • the first conductive layer the structural layout of the second conductive layer
  • Fig. 13 is the structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer in Fig. 3
  • Fig. 13 is the structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer in Fig. 3
  • Figure 14 is a diagram The structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in Figure 3
  • Figure 15 is the first active layer, the first conductive layer, the second conductive layer in Figure 3
  • the first active layer may include an active portion 064, an active portion 065, an active portion 066, and an active portion 067, wherein the active portion 064 is used to form the fourth transistor In the channel region, the active part 065 is used to form the channel region of the fifth transistor, the active part 066 is used to form the channel region of the sixth transistor, and the active part 067 is used to form the channel region of the seventh transistor.
  • the source portion 063 is used to form a channel region of the driving transistor T3.
  • the first active layer may be formed of polysilicon semiconductor.
  • the first conductive layer may include a second gate drive signal line G2, an enable signal line EM, a second reset signal line Re2, and a conductive part 011, wherein the second gate drive signal line
  • the line G2 is used to provide the second gate drive signal terminal G2 in FIG. 1
  • the enable signal line EM is used to provide the enable signal terminal EM in FIG. 1
  • the second reset signal line Re2 is used to provide the second Reset signal terminal Re2.
  • the conductive portion 011 is used to form the gate of the driving transistor T3 and an electrode of the capacitor C.
  • the first active layer can be formed as a conductor by using the first conductive layer as a mask, that is, the part covered by the first conductive layer forms the channel region of the transistor, and the part not covered by the first conductive layer forms a conductive structure.
  • the second conductive layer may include: a first sub-reset signal line 1Re1, a first sub-gate drive signal line 1G1, and a conductive part 021, wherein the first sub-reset signal line 1Re1 is used for The first reset signal terminal in FIG. 1 is provided, the first sub-gate driving signal line 1G1 is used to provide the first gate driving signal terminal in FIG. 1 , and the conductive part 021 can form another electrode of the capacitor C.
  • the second active layer may include an active portion 07, and the active portion 07 may include an active portion 071 and an active portion 072, and the active portion 071 is used to form the trench of the first transistor.
  • the channel region, the active part 072 is used to form the channel region of the second transistor.
  • the second active layer may be formed of an oxide semiconductor such as indium gallium zinc oxide.
  • the third conductive layer may include: a second sub-reset signal line 2Re1, a second sub-gate drive signal line 2G1, and the second sub-reset signal line 2Re1 is used to provide the second sub-reset signal line in FIG. A reset signal terminal, the second sub-gate driving signal line 2G1 is used to provide the first gate driving signal terminal in FIG. 1 .
  • the second sub-reset signal line 2Re1 and the first sub-reset signal line 1R1 may be connected through a via hole, and the second sub-gate driving signal line 2G1 may be connected with the first sub-gate driving signal line 1G1 through a via hole.
  • the second active layer can be formed as a conductor by using the third conductive layer as a mask, that is, the part covered by the third conductive layer forms the channel region of the transistor, and the part not covered by the third conductive layer forms a conductive structure.
  • the fourth conductive layer may include: a first power supply line VDD1, a first initial signal line Vinit1, a second initial signal line Vinit2, a connection part 041, a connection part 042, a connection part 043, a connection Section 044.
  • the first power line VDD1 is used to provide the first power terminal in Figure 1
  • the first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 1
  • the second initial signal line Vinit2 is used to provide the first power terminal in Figure 1.
  • the connection part 041 may be connected to the first active layer on one side of the active part 064 through a via hole (black square), so as to be connected to the first electrode of the fourth transistor.
  • the connecting part 042 can be respectively connected to the second active layer between the conductive part 011, the active part 071 and the active part 072 through via holes, so as to connect the gate of the driving transistor and the first pole of the first transistor, and the driving transistor gate and the first pole of the second transistor.
  • the connecting part 043 can respectively connect the first active layer on the side of the active part 066 and the second active layer on the side of the active part 072 through via holes, so as to connect the first pole of the sixth transistor and the first electrode of the second transistor. Diode.
  • the connection part 044 may be connected to the first active layer on one side of the active part 066 through a via hole, so as to be connected to the second electrode of the sixth transistor.
  • the first power line VDD1 can be connected to the first active layer on the side of the active part 065 through a via hole to connect the first pole of the fifth transistor and the first power supply terminal, and the first power line VDD1 can also be connected to the conductive layer through a via hole. Section 021 to connect the capacitor C and the first power supply terminal.
  • the first initial signal line Vinit1 can be connected to the second active layer on one side of the active portion 071 through a via hole, so as to connect the second pole of the first transistor to the first initial signal terminal.
  • the second initial signal line can be connected to the first active layer on one side of the active part 067 through a via hole, so as to connect the second initial signal terminal and the second pole of the seventh transistor.
  • the fifth conductive layer may include: a second power line VDD2, a data line Da, and a connection part 051, wherein the second power line VDD2 is used to provide the first power terminal in Figure 1, and the data line Da is used to provide the data signal terminal in Figure 1.
  • the second power line VDD2 may be connected to the first power line VDD1 through a via hole.
  • the data line Da can be connected to the connection portion 041 through a via hole, so as to connect the first pole of the fourth transistor and the data signal terminal.
  • the connection part 051 can be connected to the connection part 044 through a via hole, and the connection part 051 can be used to connect the anode of the light emitting unit in FIG. 1 . As shown in FIG.
  • the first power line VDD1 on the substrate orthographic projection can be located between the data line Da on the substrate orthographic projection and the conductive part 011 on the substrate orthographic projection, and the first power supply line VDD1 can shield the data line Da interferes with the conductive part 011.
  • the display panel further includes a first buffer layer 082, a first gate insulating layer 083, a second gate insulating layer 084, a first dielectric layer 085, a second buffer layer 086, a third gate insulating layer 087, The second dielectric layer 088.
  • the base substrate 081, the first buffer layer 082, the first active layer, the first gate insulating layer 083, the first conductive layer, the second gate insulating layer 084, the second conductive layer, the first dielectric layer 085, a second buffer layer 086, a second active layer, a third gate insulating layer 087, a third conductive layer, a second dielectric layer 088, and a fourth conductive layer are stacked in sequence. As shown in FIG.
  • the method for conducting the second active layer is: after forming the third conductive layer on the side of the third gate insulating layer 087 away from the base substrate 081, removing The third gate insulating layer covered by the three conductive layers, and then a second dielectric layer 088 is formed on the side of the third conductive layer away from the base substrate through a vapor chemical deposition process.
  • a second dielectric layer 088 is formed on the side of the third conductive layer away from the base substrate through a vapor chemical deposition process.
  • the second dielectric layer can be silicon nitride, and the second dielectric layer can be made of silane Synthesized with nitrogen, hydrogen ions will be formed during the synthesis of the second dielectric layer, and the hydrogen ions can conduct the active part 07.
  • the lateral diffusion of hydrogen ions will make the actual length L1 of the channel region of the second transistor smaller than its designed length L1+2L2, wherein the designed length L1+2L2 of the channel region is The lateral length of the transistor gate.
  • the second transistor is prone to short-channel effects.
  • the threshold voltage Vth of the second transistor is highly related to its channel length, which is not conducive to the realization of the stability and uniformity of the threshold voltage Vth.
  • this exemplary embodiment provides a display panel device method, as shown in FIG. 17 , which is a process flow chart in an exemplary embodiment of the display panel manufacturing method of the present disclosure.
  • the display panel may include a first transistor T1
  • the manufacturing method of the display panel may include:
  • Step S1 providing a base substrate 81 .
  • Step S2 forming a second conductive layer on the side of the base substrate 81, the second conductive layer may include a first conductive portion 1Re11, and the first conductive portion 1Re11 is used to form the first conductive portion 1Re11 of the first transistor T1. a gate.
  • Step S3 forming a second active material layer on the side of the second conductive layer away from the base substrate 81, the second active material layer includes a first active material portion 71, and the first active material portion
  • the source material part 71 includes a first sub-active material part 711, a second sub-active material part 712, a second sub-active material part connected between the first sub-active material part 711 and the second sub-active material part 712. Three sub-active material parts 713.
  • the partial structure of the third sub-active material part 713 is used to form the channel region of the first transistor T1, and the first conductive part 1Re11 covers the third sub-active material part in the orthographic projection of the base substrate.
  • the material portion 713 is orthographically projected on the base substrate.
  • Step S4 forming a third gate insulating layer 87 on the side of the second active material layer away from the base substrate 81, the third gate insulating layer 87 covering the orthographic projection of the base substrate Orthographic projection of the first active material portion 71 on the base substrate.
  • Step S5 forming a third conductive layer on the side of the third gate insulating layer 87 away from the base substrate 81, the third conductive layer includes a second conductive part 2Re12, and the second conductive part 2Re12 is used for The second gate of the first transistor T1 is formed, and the orthographic projection of the second conductive portion 2Re12 on the base substrate and the orthographic projection of the third sub-active material portion 713 on the base substrate Partially overlapping, the orthographic projection of the partial structure of the third sub-active material portion 713 on the base substrate does not intersect the orthographic projection of the second conductive portion 2Re12 on the base substrate.
  • the third conductive layer can be formed by a photolithography process, wherein the third conductive layer can be etched by a dry etching process.
  • the dry etching process has a small CD Bias (Critical Dimension Bias, the deviation between the photoresist and the edge of the etched body), so that the third conductive layer with high dimensional accuracy can be realized.
  • CD Bias of the dry etching process can reach 0.5 microns.
  • Step S6 Conducting conductorization treatment on the second active material layer by using the third conductive layer as a mask.
  • the first transistor may be an oxide transistor
  • the second active material layer may be an oxide semiconductor, for example, the material of the second active material layer may be indium gallium zinc oxide.
  • the display panel in this exemplary embodiment may include a pixel driving circuit, and the display driving circuit may be as shown in FIG. 1 , wherein the first transistor in this exemplary embodiment may be the first transistor in FIG. 1 .
  • the pixel driving circuit in the display panel may also have other structures, such as an 8T1C structure; the first transistor in FIG. 17 may also be a low-temperature polysilicon transistor, and the first transistor in FIG.
  • a transistor can also be located in other circuit structures in the display panel, for example, the first transistor can be located in the gate driving circuit in the display panel.
  • conducting the second active material layer by using the third conductive layer as a mask may include: using a meteorological chemical deposition process, in the The side of the third conductive layer away from the base substrate forms a second dielectric layer 88 .
  • conducting ions can be generated during the formation of the second dielectric layer 88 , and the conducting ions can conduct the second active material layer not covered by the third conductive layer.
  • the second dielectric layer 88 can be silicon nitride, and the second dielectric layer 88 can be synthesized by silane and nitrogen.
  • hydrogen ions can be formed, and the hydrogen ions can realize the second active Conductorization of material layers.
  • the third gate insulating layer 87 is The diffusion of conductive ions has a blocking effect, so that the diffusion amount of conductive ions in the lateral direction is very small or even zero, and then the channel region formed by the second conductive part 2Re12 as a mask is in the same horizontal direction as the second conductive part 2Re12.
  • the lateral length of the portion 2Re12 is the same, or the lateral length of the channel region is slightly smaller than the lateral length of the second conductive portion 2Re12. That is, the display panel manufacturing method can greatly reduce the value of L2 in FIG.
  • the display panel manufacturing method can form a larger-sized channel region under the action of the limited-sized second conductive portion 2Re12.
  • the third gate insulating layer 87 has a blocking effect on the diffusion of conductive ions, the ion doping concentration of the part of the third sub-active material part 713 not covered by the second conductive part 2Re12 is relatively low, and the sheet resistance is relatively high. , so the conduction current of the first transistor is small.
  • the orthographic projection of the first conductive portion 1Re11 on the base substrate covers the orthographic projection of the third sub-active material portion 713 on the base substrate, and the orthographic projection of the first conductive portion 1Re11 Under the action of the conduction voltage, the sheet resistance of the third sub-active material portion 713 located between the first electrode and the second electrode of the first transistor and not covered by the second conductive portion 2Re12 decreases, so that the first transistor can be compared large on-current.
  • the off current of the first transistor is small, thereby further reducing the power of the node N during the light-emitting phase through the first Transistor leakage current.
  • the lateral direction in FIG. 17 may be the distribution direction of the first sub-active material portion 711, the third sub-active material portion 713, and the second sub-active material portion 712, that is, the length direction of the channel region.
  • the third sub-active material portion 713 may include a first sub-active material portion 7131 , a second sub-active material portion 7132 , and a third sub-active material portion 7133 , the first sub-active material portion 7131 may be connected between the first sub-active material portion 711 and the third sub-active material portion 7133, and the second sub-active material portion 7132 may be connected to between the third sub-active material portion 7133 and the second sub-active material portion 712 .
  • the orthographic projection of the second conductive portion 2Re12 on the base substrate may cover the orthographic projection of the third sub-active material portion 7133 on the base substrate.
  • the third sub-active material portion 7133 can form the channel region of the first transistor.
  • conducting the second active material layer by using the third conductive layer as a mask may also include other methods.
  • the ion implantation process can be used to implant conductive ions into the second active layer, and the ion implantation process will provide a certain initial energy to the conductive ions, so that the conductive ions will Pass through the third gate insulating layer 87 and reach the second active layer.
  • the conduction ions may be B, Al, F, In, Zn plasma.
  • the conductorization of the second active material layer can be realized through the ion implantation process alone, or the second active material layer can be further improved through the ion implantation process on the basis of the vapor phase chemical deposition process of the second dielectric layer. degree of conductivity.
  • FIG. 18 it is a process flow diagram of an exemplary embodiment of the method for manufacturing a display panel of the present disclosure.
  • the display panel manufacturing method may further include: forming a first via hole H1 and a second via hole H2 penetrating through the third gate insulating layer 87 and the second dielectric layer 88 by dry etching gas, the first via hole H1
  • the orthographic projection of a via hole H1 on the base substrate may be located on the orthographic projection of the first sub-active material portion 711 on the base substrate, and the second via hole H2 may be located on the orthographic projection of the base substrate. It is located on the orthographic projection of the second sub-active material portion 712 on the base substrate.
  • the dry etching gas can generate conductive ions during the dry etching process, and the conductive ions can conduct the second active material layer, so that the first sub-active material portion 711, the second sub-active material portion 711, and the second active material layer can be improved.
  • the dry etching gas can contain fluorine element, hydrogen element, etc., and the conducting ions can be fluorine ion and hydrogen ion. .
  • the indium gallium zinc oxide layer can be further treated with argon gas Ar, and Ar can also occupy the gaps in the indium gallium zinc oxide lattice to make the indium gallium zinc oxide conductive, and the inert gas Ar does not affect the characteristics of the oxide transistor.
  • the conductorization degree of the first sub-active material part 711 and the second sub-active material part 712 may be higher than that of the first sub-active material part 7131 and the second sub-active material part 7132 .
  • the sheet resistance of the conductive first sub-active material portion 7131 is smaller than the sheet resistance of the conductive first sub-active material portion 711, that is, the sheet resistance of the conductive first sub-active material portion 7131 is smaller than that of the conductive first sub-active material portion 711.
  • the sheet resistance of the conductive second sub-active material part 712 may be equal to the sheet resistance of the conductive second sub-active material portion 7132 .
  • the sheet resistance of the conductorized first sub-active material portion 711 may be equal to the sheet resistance of the second sub-active material portion 712 .
  • the conductorized first sub-active material portion 711 can be used to form the first pole of the first transistor, and the conductorized second sub-active material portion 712 can be used to form the second pole of the first transistor.
  • the sheet resistance of the conductorized first sub-active material portion may be 2000 ⁇ 20000 ⁇ /sq, for example, 2000 ⁇ /sq, 5000 ⁇ /sq, 10000 ⁇ /sq, 20000 ⁇ /sq.
  • the sheet resistance of the conductorized first sub-active material portion may be 500 ⁇ 2000 ⁇ /sq, for example, 500 ⁇ /sq, 1000 ⁇ /sq, 2000 ⁇ /sq.
  • the sheet resistance of the conductorized second sub-active material portion may be 500 ⁇ 2000 ⁇ /sq, for example, 500 ⁇ /sq, 1000 ⁇ /sq, 2000 ⁇ /sq.
  • the orthographic projection of the first via hole H1 on the substrate may be slightly smaller than the orthographic projection of the first sub-active material portion 711 on the substrate, and the orthographic projection of the second via hole H2 on the substrate may be slightly smaller than that of the second sub-active material portion 711.
  • Section 712 is orthographically projected on the base substrate.
  • the orthographic projection of the edge 7111 of the first sub-active portion 711 on the substrate and the orthographic projection of the first conductive portion 1Re11 on the substrate may at least partially overlap.
  • the orthographic projection of the edge 7121 of the source portion 712 on the base substrate and the orthographic projection of the first conductive portion 1Re11 on the base substrate may at least partially overlap.
  • the orthographic projection of the first conductive part 1Re11 on the substrate may at least partially overlap with the orthographic projection of the first via hole H1 on the substrate, and the orthographic projection of the first conductive part 1Re11 on the substrate may also be At least partially coincide with the orthographic projection of the second via hole H2 on the base substrate.
  • the first transistor may also have other structures, for example, the first transistor may also include a plurality of channel regions connected in parallel or in series.
  • the above structure can also be used to increase the channel length of the first transistor.
  • FIG. 19 it is a process flow diagram of an exemplary embodiment of the method for manufacturing a display panel of the present disclosure.
  • the display panel manufacturing method may further include: forming a fourth conductive layer on the side of the second dielectric layer 88 away from the base substrate 81, and the fourth conductive layer may include a third conductive part 43 and a fourth conductive part 43. Department Vinit14.
  • the third conductive part 43 can be connected to the first sub-active material part 711 through the first via hole H1, and the fourth conductive part Vinit14 can be connected to the second sub-active material part 711 through the second via hole H2.
  • Active material section 712 is a process flow diagram of an exemplary embodiment of the method for manufacturing a display panel of the present disclosure.
  • the display panel manufacturing method may further include: forming a fourth conductive layer on the side of the second dielectric layer 88 away from the base substrate 81, and the fourth conductive layer may include a third conductive part 43 and a fourth conductive part 43. Department Vinit14.
  • the second transistor in FIG. 1 may also have the same structure as the first transistor in FIGS. 17-19.
  • This exemplary embodiment also provides a display panel, which can be manufactured by the above method for manufacturing a display panel.
  • the display panel may include the pixel driving circuit shown in FIG.
  • the source layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be sequentially stacked.
  • FIGS. 20-32 FIG. 20 is a structural layout of an exemplary embodiment of a display panel of the present disclosure
  • FIG. 21 is a structural layout of the first active layer in FIG. 20
  • 22 is a structural layout of the first conductive layer in FIG. 20 Structural layout
  • Fig. 23 is the structural layout of the second conductive layer in Fig. 20
  • Fig. 24 is the structural layout of the second active layer in Fig. 20, Fig.
  • FIG. 25 is the structural layout of the third conductive layer in Fig. 20, and Fig. 26 is a diagram The structural layout of the fourth conductive layer in Figure 20, Figure 27 is the structural layout of the fifth conductive layer in Figure 20, Figure 28 is the structural layout of the first active layer and the first conductive layer in Figure 20, Figure 29 is the structural layout of the fifth conductive layer in Figure 20 The structural layout of the first active layer, the first conductive layer, and the second conductive layer.
  • FIG. 30 is the structural layout of the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG. 20, Fig. 31 is the structural layout of the first active layer, the first conductive layer, the second conductive layer, the second active layer and the third conductive layer in Fig. 20, and Fig.
  • FIG. 32 is the first active layer, the first conductive layer in Fig. 20 The structural layout of the conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer.
  • FIG. 33 is a partial structural layout of the second conductive layer and the second active layer in 20.
  • FIG. 34 is Partial structural layout of the second conductive layer, the second active layer, and the third conductive layer in 20.
  • the first active layer may include an active portion 63, an active portion 64, an active portion 65, an active portion 66, and an active portion 67, wherein the active portion 64 is used for Form the channel region of the fourth transistor, the active portion 65 is used to form the channel region of the fifth transistor, the active portion 66 is used to form the channel region of the sixth transistor, and the active portion 67 is used to form the channel region of the seventh transistor The channel region, the active portion 63 is used to form the channel region of the driving transistor T3.
  • the first active layer may be formed of polysilicon semiconductor.
  • the first conductive layer may include a second gate drive signal line G2, an enable signal line EM, a second reset signal line Re2, and a conductive portion 11, wherein the second gate drive signal line Line G2 is used to provide the second gate drive signal terminal in Figure 1, the enable signal line EM is used to provide the enable signal terminal in Figure 1, and the second reset signal line Re2 is used to provide the second reset signal in Figure 1 end.
  • the orthographic projection of the second gate driving signal line G2 on the substrate, the orthographic projection of the enable signal line EM on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate may extend along the first direction X.
  • the conductive portion 11 is used to form the gate of the driving transistor T3 and an electrode of the capacitor C.
  • the first active layer can be formed as a conductor by using the first conductive layer as a mask, that is, the part covered by the first conductive layer forms the channel region of the transistor, and the part not covered by the first conductive layer forms a conductive structure.
  • the second conductive layer may include: a first sub-reset signal line 1Re1, a first sub-gate drive signal line 1G1, and a conductive portion 21, wherein the first sub-reset signal line 1Re1 is used for The first reset signal terminal in FIG. 1 is provided, the first sub-gate drive signal line 1G1 is used to provide the first gate drive signal terminal in FIG. 1 , and the conductive part 21 can form another electrode of the capacitor C.
  • the first sub-reset signal line 1Re1 may include a first conductive portion 1Re11, and the first conductive portion 1Re11 may be used to form a first gate of the first transistor; the first sub-gate drive signal line 1G1 may include a fifth conductive portion 1G15, The fifth conductive part may be used to form the first gate of the second transistor T2.
  • the orthographic projection of the first sub-reset signal line 1Re1 on the substrate and the orthographic projection of the first sub-gate driving signal line 1G1 on the substrate may extend along the first direction X.
  • the second active layer may include a first active portion 71, and the orthographic projection of the first active portion 71 on the base substrate may extend along the second direction Y, wherein the second The direction Y and the first direction X may intersect, for example, the second direction Y and the first direction X may be perpendicular.
  • the first active part 71 may include a first sub-active part 711, a second sub-active part 712, and a connection between the first sub-active part 711 and the second sub-active part 712
  • the third sub-active part 713; the first sub-active part 711 can be used to form the first pole of the first transistor T1, and the second sub-active part 712 can be used to form the first pole of the first transistor T1
  • the second pole, part of the structure of the third sub-active portion 713 may be used to form the channel region of the first transistor T1.
  • the third sub-active part 713 may include a first sub-active part 7131, a second sub-active part 7132, and a third sub-active part 7133, and the first sub-active part 7131 is connected to the first sub-active part. Between the active part 711 and the third sub-active part 7133, the second sub-active part 7132 is connected between the third sub-active part 7133 and the second sub-active part 712, the The third sub-active portion 7133 may be used to form a channel region of the first transistor T1.
  • the first active part 71 may further include: a fourth sub-active part 714 and a fifth sub-active part 715, and the fourth sub-active part 714 may be used to form the second pole of the second transistor T2;
  • the fifth sub-active part 715 may be connected between the fourth sub-active part 714 and the first sub-active part 711, and part of the structure of the fifth sub-active part 715 may be used to form the The channel region of the second transistor T2.
  • the fifth sub-active part 715 may include a fourth sub-active part 7154, a fifth sub-active part 7155, and a sixth sub-active part 7156, and the fourth sub-active part 7154 may be connected to the first sub-active part 7154.
  • the fifth sub-active part 7155 can be connected to the sixth sub-active part 7156 and the fourth sub-active part 714 Between them, the sixth sub-active portion 7156 can be used to form the channel region of the second transistor T2.
  • the second sub-active portion 712 is orthographically projected on the base substrate
  • the second sub-active portion 7132 is orthographically projected on the base substrate
  • the third sub-active portion 7133 is orthographically projected on the base substrate
  • the first sub-active portion 7131 is The orthographic projection of the first sub-active portion 711 on the base substrate
  • the orthographic projection of the fifth sub-active portion 7155 on the base substrate and the orthographic projection of the fourth sub-active portion 714 on the base substrate may be sequentially connected in the second direction Y.
  • the second active layer may be formed of an oxide semiconductor such as indium gallium zinc oxide.
  • the third conductive layer may include: a second sub-reset signal line 2Re1, a second sub-gate drive signal line 2G1, and the second sub-reset signal line 2Re1 is used to provide The first reset signal terminal of the second sub-gate drive signal line 2G1 is used to provide the first gate drive signal terminal in FIG. 1 .
  • the second sub-gate drive signal line 2G1 may include a sixth conductive portion 2G16, and the sixth conductive portion 2G16 may be used to form the second gate of the second transistor T2;
  • the second sub-reset signal line 2Re1 may include a second conductive portion 2Re2 , the second conductive portion 2Re2 may be used to form the second pole of the first transistor.
  • the second sub-reset signal line 2Re1 and the first sub-reset signal line 1R1 may be connected through a via hole, and the second sub-gate driving signal line 2G1 may be connected with the first sub-gate driving signal line 1G1 through a via hole.
  • different voltages may be applied to the first gate and the second gate of the first transistor, and the first gate and the second gate of the second transistor may also be respectively Apply different voltages.
  • the orthographic projection of the second sub-reset signal line 2Re1 on the substrate, and the orthographic projection of the second sub-gate driving signal line 2G1 on the substrate may extend along the first direction.
  • the second active layer can be formed as a conductor by using the third conductive layer as a mask, that is, the part covered by the third conductive layer forms the channel region of the transistor, and the part not covered by the third conductive layer forms a conductive structure.
  • the conductive ions will inevitably diffuse in a direction perpendicular to the stacking direction, so that the second conductive portion 2Re2 is orthographically projected on the base substrate
  • the size in the second direction Y may be slightly larger than the size of the third sub-active portion 7133 in the second direction Y in the orthographic projection of the base substrate; the size of the sixth conductive portion 2G16 in the second direction Y in the orthographic projection of the base substrate may be Slightly larger than the dimension of the sixth sub-active portion 7156 in the orthographic projection of the base substrate in the second direction Y.
  • the fourth conductive layer may include: a first power line VDD1, a first initial signal line Vinit1, a second initial signal line Vinit2, a conductive part 41, a third conductive part 43, and a conductive part 42 , the conductive portion 44 .
  • the first power line VDD1 is used to provide the first power terminal in Figure 1
  • the first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 1
  • the second initial signal line Vinit2 is used to provide the first power terminal in Figure 1.
  • the conductive part 41 may be connected to the first active layer on one side of the active part 64 through the via hole H4, so as to be connected to the first electrode of the fourth transistor.
  • the third conductive part 43 can be connected to the conductive part 11 through the via hole H5, and connected to the first sub-active part 711 through the via hole H1, so as to connect the gate of the driving transistor and the first pole of the first transistor, and the gate of the driving transistor and the first pole of the second transistor.
  • the conductive part 42 can be connected to the first active layer on one side of the active part 66 through the via hole H6, and connected to the fourth sub-active part 714 through the via hole H3, so as to connect the first electrode of the sixth transistor and the first electrode of the second transistor. Diode.
  • the conductive part 44 can be connected to the first active layer on one side of the active part 66 through the via hole H9, so as to be connected to the second electrode of the sixth transistor.
  • the first power line VDD1 can be connected to the first active layer on one side of the active part 65 through the via hole H7 to connect the first pole of the fifth transistor and the first power supply terminal, and the first power line VDD1 can also be connected through the via hole H8
  • the conductive part 21 is connected to connect the capacitor C and the first power supply terminal.
  • the first initial signal line Vinit1 may include a fourth conductive portion Vinit14, and the fourth conductive portion Vinit14 may be connected to the second sub-active portion 712 through the via hole H2 to connect the second pole of the first transistor and the first initial signal terminal.
  • the second initial signal line Vinit2 can be connected to the first active layer on one side of the active portion 67 through the via hole H10 to connect the second initial signal terminal and the second electrode of the seventh transistor.
  • the orthographic projection of the first via hole H1 on the substrate may be slightly smaller than the orthographic projection of the first sub-active portion 711 on the substrate, and the orthographic projection of the second via hole H2 on the substrate may be slightly smaller than that of the second sub-active portion 711.
  • the active portion 712 is orthographically projected on the base substrate.
  • the first sub-active part 711 may include an edge 7111 and an edge 7112 opposite in the second direction Y
  • the second sub-active part 712 may include an edge near the first sub-active part 711. 7121.
  • the fourth sub-active part 714 may include an edge 7141 facing one side of the first sub-active part 711.
  • the orthographic projection of the edge 7111 on the substrate may at least partially overlap with the orthographic projection of the first conductive portion 1Re11 on the substrate; the orthographic projection of the edge 7112 on the substrate may at least partially overlap with the orthographic projection of the fifth conductive portion 1G15 on the substrate Coincident; the orthographic projection of the edge 7121 on the substrate may at least partially overlap with the orthographic projection of the first conductive part 1Re11 on the substrate; the orthographic projection of the edge 7141 on the substrate may be at least partially coincident with the orthographic projection of the fifth conductive part 1G15 on the substrate coincide.
  • the orthographic projection of the first conductive part 1Re11 on the base substrate may at least partially overlap with the orthographic projection of the first via hole H1 on the base substrate, and the orthographic projection of the first conductive part 1Re11 on the base substrate may also overlap with the second via hole H2
  • the base substrate orthographic projections are at least partially coincident.
  • the orthographic projection of the fifth conductive portion 1G15 on the substrate may at least partially overlap with the orthographic projection of the first via hole H1 on the substrate, and the orthographic projection of the fifth conductive portion 1G15 on the substrate may also be At least partially coincide with the orthographic projection of the second via hole H3 on the base substrate.
  • the fifth conductive layer may include: a second power line VDD2, a data line Da, and a connecting portion 51, wherein the second power line VDD2 is used to provide the first power terminal in Figure 1, and the data line Da is used to provide the data signal terminal in Figure 1.
  • the second power line VDD2 may be connected to the first power line VDD1 through the via hole H11.
  • the data line Da can be connected to the connection part 41 through the via hole H12, so as to connect the first pole of the fourth transistor and the data signal terminal.
  • the connection part 51 can be connected to the conductive part 44 through a via hole, and the connection part 51 can be used to connect the anode of the light emitting unit in FIG. 1 . As shown in FIG.
  • the positive projection of the first power line VDD1 on the base substrate can be located between the positive projection of the data line Da on the base substrate and the positive projection of the conductive part 11 on the base substrate, and the first power line VDD1 can shield the data line. Da interferes with the conductive part 11 .
  • the display panel may further include a first buffer layer 82, a first gate insulating layer 83, a second gate insulating layer 84, a first dielectric layer 85, a second buffer layer 86, and a third gate insulating layer 87. , The second dielectric layer 88 .
  • the base substrate 81, the first buffer layer 82, the first active layer, the first gate insulating layer 83, the first conductive layer, the second gate insulating layer 84, the second conductive layer, the first dielectric layer 85 , the second buffer layer 86 , the second active layer, the third gate insulating layer 87 , the third conductive layer, the second dielectric layer 88 , and the fourth conductive layer are stacked in sequence.
  • the first buffer layer and the second buffer layer may include at least one of a silicon oxide layer and a silicon nitride layer.
  • the first gate insulating layer, the second gate insulating layer, and the third gate insulating layer may be silicon oxide layers.
  • the first dielectric layer and the second dielectric layer may be silicon nitride layers.
  • the material of the fourth conductive layer and the fifth conductive layer may include metal materials, such as molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum/titanium alloy or laminate, etc., or may be titanium/titanium Aluminum/titanium stack.
  • the material of the first conductive layer, the second conductive layer, and the third conductive layer may be molybdenum, aluminum, copper, titanium, niobium, one of them or an alloy, or a molybdenum/titanium alloy or laminated layers.
  • the base substrate 81 may include a glass substrate, a barrier layer, and a polyimide layer that are sequentially stacked, and the barrier layer may be an inorganic material.
  • the orthographic projection of the first conductive portion 1Re11 on the base substrate may cover the orthographic projection of the third sub-active portion 713 on the base substrate.
  • the orthographic projection of the third gate insulating layer 87 on the base substrate may cover the orthographic projection of the first active portion 71 on the base substrate.
  • the orthographic projection of the second conductive portion 2Re12 on the base substrate may cover the orthographic projection of the first transistor channel region (third sub-active portion 7133 ) on the base substrate.
  • the second conductive portion is located between the first sub-active portion on the base substrate and the second sub-active portion on the base substrate in the orthographic projection of the base substrate That is, the orthographic projection of the second conductive portion 2Re12 on the substrate may not intersect with the orthographic projection of the first sub-active portion 7131 on the substrate, and the second conductive portion 2Re12 on the substrate The orthographic projection of the base substrate may not intersect with the orthographic projection of the second sub-active portion 7132 on the base substrate.
  • the display panel can form the first transistor T1 with a larger channel size under the action of the second conductive portion 2Re12 with a limited size.
  • the third gate insulating layer 87 has a blocking effect on the diffusion of conductive ions, the ion doping concentration of the first sub-active portion 7131 and the second sub-active portion 7132 not covered by the second conductive portion 2Re12 is relatively low. low, so that the conduction current of the first transistor T1 is small.
  • the orthographic projection of the first conductive part 1Re11 on the base substrate covers the orthographic projection of the third sub-active part 713 on the base substrate, and the conductive part 1Re11 Under the action of the on-voltage, the sheet resistance of the first sub-active portion 7131 and the second sub-active portion 7132 not covered by the second conductive portion 2Re12 is reduced, thereby ensuring a larger on-current of the first transistor T1.
  • the first sub-active portion 7131 and the second sub-active portion 7132 not covered by the second conductive portion 2Re12 have a larger sheet resistance, the first transistor has a smaller turn-off current.
  • the square resistance of the first sub-active portion 7131 may be equal to the square resistance of the second sub-active portion 7132, and the square resistance of the first sub-active portion 7131 may be smaller than the first sub-active portion 7131.
  • the sheet resistance of the sub-active portion 711 , the sheet resistance of the first sub-active portion 7131 may be smaller than the sheet resistance of the second sub-active portion 712 .
  • the sheet resistance of the first sub-active part may be 2000 ⁇ 20000 ⁇ /sq, for example, 2000 ⁇ /sq, 5000 ⁇ /sq, 10000 ⁇ /sq, 20000 ⁇ /sq.
  • the sheet resistance of the first sub-active part may be 500 ⁇ 2000 ⁇ /sq, for example, 500 ⁇ /sq, 1000 ⁇ /sq, 2000 ⁇ /sq.
  • the sheet resistance of the second sub-active part may be 500 ⁇ 2000 ⁇ /sq, for example, 500 ⁇ /sq, 1000 ⁇ /sq, 2000 ⁇ /sq.
  • the sheet resistance of the first sub-active portion 7131 may be slightly greater than or slightly smaller than the sheet resistance of the second sub-active portion 7132, and the sheet resistance of the first sub-active portion is the same as that of the second sub-active portion.
  • the difference of the sheet resistance of the sub-active part is smaller than a preset value, and the preset value may be 0-100 ⁇ /sq, for example, the preset value may be 0, 50, 100.
  • the first sub-active portion 711 may be shared as the first pole of the second transistor T2.
  • the orthographic projection of the fifth conductive portion 1G15 on the base substrate may cover the orthographic projection of the fifth sub-active portion 715 on the base substrate.
  • the orthographic projection of the sixth conductive portion 2G16 on the base substrate may cover the orthographic projection of the second transistor T2 channel region (sixth sub-active portion 7156 ) on the base substrate.
  • the sixth conductive portion is located between the fifth sub-active portion on the base substrate and the fourth sub-active portion on the base substrate in the orthographic projection of the base substrate , that is, the orthographic projection of the sixth conductive portion 2G16 on the substrate does not intersect the orthographic projection of the fifth sub-active portion 7155 on the substrate, and the sixth conductive portion 2G16 on the substrate The orthographic projection of the substrate does not intersect with the orthographic projection of the fourth sub-active portion 7154 on the substrate.
  • the display panel can form the second transistor T2 with a larger channel size under the action of the sixth conductive portion 2G16 with a limited size.
  • the third gate insulating layer 87 has a blocking effect on the diffusion of conductive ions, the ion doping concentration of the fourth sub-active portion 7154 and the fifth sub-active portion 7155 not covered by the sixth conductive portion 2G16 is relatively low. low, so that the conduction current of the second transistor T2 is small.
  • the orthographic projection of the fifth conductive portion 1G15 on the base substrate covers the orthographic projection of the fifth sub-active portion 715 on the base substrate, and the conductive portion 1G15 leads Under the action of the on-voltage, the sheet resistance of the fourth sub-active portion 7154 and the fifth sub-active portion 7155 not covered by the sixth conductive portion 2G16 is reduced, thereby ensuring a larger on-current of the second transistor T2.
  • the fourth sub-active portion 7154 and the fifth sub-active portion 7155 not covered by the sixth conductive portion 2G16 have a larger sheet resistance, the second transistor T2 has a smaller off current.
  • the square resistance of the fourth sub-active portion 7154 may be equal to the square resistance of the fifth sub-active portion 7155, and the square resistance of the fourth sub-active portion 7154 may be smaller than the fourth sub-active portion 7154.
  • the sheet resistance of the sub-active portion 714 , the sheet resistance of the fourth sub-active portion 7154 may be smaller than the sheet resistance of the first sub-active portion 711 .
  • the sheet resistance of the fourth sub-active portion 7154 is 2000 ⁇ 20000 ⁇ /sq, for example, 2000 ⁇ /sq, 5000 ⁇ /sq, 10000 ⁇ /sq, 20000 ⁇ /sq.
  • the sheet resistance of the fourth sub-active part 714 may be 500 ⁇ 2000 ⁇ /sq, for example, 500 ⁇ /sq, 1000 ⁇ /sq, 2000 ⁇ /sq. It should be understood that due to process errors, the square resistance of the fourth sub-active portion 7154 may be slightly greater than or slightly smaller than the square resistance of the fifth sub-active portion 7155, and the square resistance of the fourth sub-active portion 7154 is the same as that of the fifth sub-active portion 7155.
  • the difference of the sheet resistance of the five sub-active parts 7155 is smaller than a preset value, and the preset value can be 0-100 ⁇ /sq, for example, the preset value can be 0, 50, 100.
  • the first active part may further include a sixth sub-active part 716, and the sixth sub-active part 716 may be located in the first sub-active part 711. Between the third sub-active portion 713, the sixth sub-active portion 716 may be located between the first sub-active portion 711 and the base substrate in the orthographic projection of the substrate. Between the orthographic projection of the first conductive part 1Re11 on the substrate, that is, the orthographic projection of the sixth sub-active part 716 on the substrate and the orthographic projection of the first conductive part 1Re11 on the substrate not intersect.
  • the sheet resistance of the sixth sub-active part may be 2000-20000 ⁇ /sq.
  • the first active part may further include a seventh sub-active part 717, and the seventh sub-active part 717 may be located in the second sub-active part 712 and the third sub-active part 713.
  • the orthographic projection of the seventh sub-active portion 717 on the base substrate may be located between the orthographic projection of the second sub-active portion 712 on the substrate and the orthographic projection of the first conductive portion 1Re11 on the substrate between the orthographic projections of the substrate, that is, the orthographic projection of the seventh sub-active portion 717 on the substrate does not intersect the orthographic projection of the first conductive portion 1Re11 on the substrate.
  • the sheet resistance of the seventh sub-active portion 717 may be 2000 ⁇ 20000 ⁇ /sq.
  • the size of the sixth sub-active portion 716 and the seventh sub-active portion 717 in the length direction of the channel region of the first transistor cannot be too large.
  • the total length of the sixth sub-active portion 716 and the seventh sub-active portion 717 in the length direction of the channel region of the first transistor may be S1, the sixth sub-active portion 716, the seventh sub-active portion
  • the total length of the active part 717, the first sub-active part, and the second sub-active part in the length direction of the channel region of the first transistor may be S2, and S2/(S1+S2) may be greater than or equal to 80%, wherein,
  • the length direction of the channel region of the first transistor is the conduction direction of the channel region of the first transistor.
  • the second transistor in the display panel may have the same structure as the first transistor.
  • a display device wherein the display device includes the above-mentioned display panel.
  • the display device may be a display device of a mobile phone, a tablet computer, or a television.

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Abstract

一种显示面板及其制作方法、显示装置，其中，显示面板包括第一晶体管(T1)，显示面板还包括：衬底基板(81)、第二导电层、第二有源层、第三栅极绝缘层(87)、第三导电层，第二导电层位于衬底基板(81)的一侧，第二导电层包括第一导电部(1G11)，第一导电部(1G11)用于形成第一晶体管(T1)的第一栅极；第二有源层位于第二导电层背离衬底基板(81)的一侧，第二有源层包括第一有源部(71)，第一有源部包括第一子有源部(711)、第二子有源部(712)、连接于第一子有源部(711)和第二子有源部(712)之间的第三子有源部(713)；第一子有源部(711)用于形成第一晶体管(T1)的第一极，第二子有源部(712)用于形成第一晶体管(T1)的第二极，第三子有源部(713)的部分结构用于形成第一晶体管(T1)的沟道区，第一导电部(1G11)在衬底基板(81)正投影覆盖第三子有源部(713)在衬底基板(81)正投影；第三栅极绝缘层(87)位于第二有源层背离衬底基板(81)的一侧，第三栅极绝缘层(87)在衬底基板(81)的正投影覆盖第一有源部(71)在衬底基板(81)的正投影；第三导电层位于第三栅极绝缘层背离衬底基板(81)的一侧，第三导电层包括第二导电部(2Re12)，第二导电部(2Re12)用于形成第一晶体管(T1)的第二栅极，且第二导电部(2Re12)在衬底基板(81)的正投影覆盖第一晶体管(T1)沟道区在衬底基板(81)的正投影。显示面板具有较好的驱动效果。

Description

显示面板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制作方法、显示装置。
背景技术
显示面板一般包括有集成于阵列基板上像素驱动电路、栅极驱动电路等多种电路，集成于阵列基板上多种电路一般包括有晶体管，相关技术中，由于制作工艺等原因，晶体管的尺寸不能达到预设要求。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括第一晶体管，所述显示面板包括：衬底基板、第二导电层、第二有源层、第三栅极绝缘层、第三导电层。第二导电层位于所述衬底基板的一侧，所述第二导电层包括第一导电部，所述第一导电部用于形成所述第一晶体管的第一栅极；第二有源层位于所述第二导电层背离所述衬底基板的一侧，所述第二有源层包括第一有源部，所述第一有源部包括第一子有源部、第二子有源部、连接于所述第一子有源部和所述第二子有源部之间的第三子有源部；所述第一子有源部用于形成所述第一晶体管的第一极，第二子有源部用于形成所述第一晶体管的第二极，所述第三子有源部的部分结构用于形成所述第一晶体管的沟道区，所述第一导电部在所述衬底基板正投影覆盖所述第三子有源部在所述衬底基板正投影；第三栅极绝缘层位于所述第二有源层背离所述衬底基板的一侧，所述第三栅极绝缘层在所述衬底基板的正投影覆盖所述第一有源部在所述衬底基板的正投影；第三导电层位于所述第三栅极绝缘层背离所述衬底基板的一侧，所述第三导电层包括第二导电部，所述第二导电部用于形成所述第一晶体管的第二栅极，且所述第二导电部在所述衬底基板的正投影覆盖所述第一晶体管沟道区在所述衬底基板的正投影。
本公开一种示例性实施例中，所述第三子有源部包括第一亚有源部、第二亚有源部、第三亚有源部，所述第一亚有源部连接于所述第一子有源部和所述第三亚有源部之间，所述第二亚有源部连接于所述第三亚有源部和所述第二子有源部之间，所述第三亚有源部用于形成所述第一晶体管的沟道区；所述第二导电部在所述衬底基板正投 影覆盖所述第三亚有源部在所述衬底基板的正投影，且所述第二导电部在所述衬底基板正投影位于所述第一亚有源部在所述衬底基板正投影和所述第二亚有源部在所述衬底基板正投影之间。
本公开一种示例性实施例中，所述第一亚有源部的方块电阻与第二亚有源部的方块电阻的差值小于预设值，所述预设值为0-100Ω/sq，所述第一亚有源部的方块电阻小于所述第一子有源部的方块电阻，所述第一亚有源部的方块电阻小于所述第二子有源部的方块电阻。
本公开一种示例性实施例中，所述第一亚有源部的方块电阻与第二亚有源部的方块电阻的差值小于预设值，所述预设值为0-100Ω/sq，所述第一亚有源部的方块电阻为2000～20000Ω/sq。
本公开一种示例性实施例中，所述第一子有源部的方块电阻为500～2000Ω/sq，所述第二子有源部的方块电阻为500～2000Ω/sq。
本公开一种示例性实施例中，所述显示面板还包括：第四导电层，位于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括第三导电部和第四导电部；所述第三导电部通过第一过孔连接所述第一子有源部，所述第四导电部通过第二过孔连接所述第二子有源部。
本公开一种示例性实施例中，所述第一过孔在所述衬底基板正投影位于所述第一子有源部在所述衬底基板正投影上，所述第二过孔在所述衬底基板正投影位于所述第二子有源部在所述衬底基板正投影上；所述第一过孔在所述衬底基板正投影的面积小于等于所述第一子有源部在所述衬底基板正投影的面积；所述第二过孔在所述衬底基板正投影的面积小于等于所述第二子有源部在所述衬底基板正投影的面积。
本公开一种示例性实施例中，所述第一子有源部的边沿在所述衬底基板正投影与所述第一导电部在所述衬底基板正投影至少部分重合；所述第二子有源部的边沿在所述衬底基板正投影与所述第一导电部在所述衬底基板正投影至少部分重合。
本公开一种示例性实施例中，所述第一有源部还包括第六子有源部，所述第六子有源部位于所述第一子有源部和所述第三子有源部之间，所述第六子有源部在所述衬底基板正投影位于所述第一子有源部在所述衬底基板正投影和所述第一导电部在所述衬底基板正投影之间；所述第六子有源部的方块电阻为2000～20000Ω/sq。
本公开一种示例性实施例中，所述第一晶体管为氧化物晶体管。
本公开一种示例性实施例中，所述显示面板还包括像素驱动电路，所述像素驱动 电路包括所述第一晶体管；所述像素驱动电路还包括驱动晶体管，所述第一晶体管的第一极连接所述驱动晶体管的栅极，第二极连接第一初始信号端；所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极，所述第二晶体管为氧化物晶体管。
本公开一种示例性实施例中，所述第一有源部还包括：第四子有源部、第五子有源部，第四子有源部用于形成所述第二晶体管的第二极；第五子有源部连接于所述第四子有源部和所述第一子有源部之间，所述第五子有源部的部分结构用于形成所述第二晶体管的沟道区；所述第一子有源部共用为所述第二晶体管的第一极；所述第二导电层还包括第五导电部，所述第五导电部用于形成所述第二晶体管的第一栅极，所述第五导电部在所述衬底基板正投影覆盖所述第五子有源部在所述衬底基板正投影；所述第三导电层还包括第六导电部，所述第六导电部用于形成所述第二晶体管的第二栅极，且所述第六导电部在所述衬底基板的正投影覆盖所述第二晶体管沟道区在所述衬底基板的正投影。
本公开一种示例性实施例中，所述第五子有源部包括第四亚有源部、第五亚有源部、第六亚有源部，所述第四亚有源部连接于所述第一子有源部和所述第六亚有源部之间，所述第五亚有源部连接于所述第六亚有源部和所述第四子有源部之间，所述第六亚有源部用于形成所述第二晶体管的沟道区；所述第六导电部在所述衬底基板正投影覆盖所述第六亚有源部在所述衬底基板正投影，所述第六导电部在所述衬底基板正投影位于所述第五亚有源部在所述衬底基板正投影和所述第四亚有源部在所述衬底基板正投影之间。
本公开一种示例性实施例中，所述第四亚有源部的方块电阻与第五亚有源部的方块电阻的差值小于预设值，所述预设值为0-100Ω/sq，所述第四亚有源部的方块电阻小于所述第四子有源部的方块电阻，所述第四亚有源部的方块电阻小于所述第一子有源部的方块电阻。
本公开一种示例性实施例中，所述第四亚有源部的方块电阻与第五亚有源部的方块电阻的差值小于预设值，所述预设值为0-100Ω/sq，所述第四亚有源部的方块电阻为2000～20000Ω/sq。
根据本公开的一个方面，提供一种显示面板制作方法，其中，所述显示面板包括第一晶体管，所述显示面板制作方法包括：
提供一衬底基板；
在所述衬底基板一侧形成第二导电层，所述第二导电层包括第一导电部，所述第一导电部用于形成所述第一晶体管的第一栅极；
在所述第二导电层背离所述衬底基板的一侧形成第二有源材料层，所述第二有源材料层包括第一有源材料部，所述第一有源材料部包括第一子有源材料部、第二子有源材料部、连接于所述第一子有源材料部和所述第二子有源材料部之间的第三子有源材料部；
所述第三子有源材料部的部分结构用于形成所述第一晶体管的沟道区，且所述第一导电部在所述衬底基板正投影覆盖所述第三子有源材料部在所述衬底基板正投影；
在所述第二有源材料层背离所述衬底基板的一侧形成第三栅极绝缘层，所述第三栅极绝缘层在所述衬底基板的正投影覆盖所述第一有源材料部在所述衬底基板的正投影；
在所述第三栅极绝缘层背离所述衬底基板的一侧形成第三导电层，所述第三导电层包括第二导电部，所述第二导电部用于形成所述第一晶体管的第二栅极，且所述第二导电部在所述衬底基板的正投影与所述第三子有源材料部在所述衬底基板正投影部分交叠；
以所述第三导电层为掩膜对所述第二有源材料层进行导体化处理。
本公开一种示例性实施例中，所述第一晶体管为氧化晶体管，所述第二有源材料层为氧化物半导体。
本公开一种示例性实施例中，以所述第三导电层为掩膜对所述第二有源材料层进行导体化处理，包括：
利用气象化学沉积工艺，在所述第三导电层背离所述衬底基板的一侧形成第二介电层；
其中，形成所述第二介电层过程中生成有导体化离子，所述导体化离子能够对所述第二有源材料层实现导体化。
本公开一种示例性实施例中，所述第二介电层的材料为氮化硅，所述导体化离子为氢离子。
本公开一种示例性实施例中，所述显示面板制作方法还包括：
通过干刻气体形成贯穿所述第三栅极绝缘层、所述第二介电层的第一过孔和第二过孔，所述第一过孔在所述衬底基板正投影位于所述第一子有源材料部在所述衬底基板正投影上，所述第二过孔在所述衬底基板正投影位于所述第二子有源材料部在所述 衬底基板正投影上，其中，所述干刻气体在干刻过程中能够产生导体化离子，所述导体化离子能够对所述第二有源材料层实现导体化；
在所述第二介电层背离所述衬底基板一侧形成第四导电层，所述第四导电层包括第三导电部和第四导电部；
所述第三导电部通过所述第一过孔连接所述第一子有源材料部，所述第四导电部通过所述第二过孔连接所述第二子有源材料部。
本公开一种示例性实施例中，所述第一过孔在所述衬底基板正投影的面积小于等于所述第一子有源材料部在所述衬底基板正投影的面积；所述第二过孔在所述衬底基板正投影的面积小于等于所述第二子有源材料部在所述衬底基板正投影的面积。
本公开一种示例性实施例中，所述第一子有源材料部的边沿在所述衬底基板正投影与所述第一导电部在所述衬底基板正投影至少部分重合；所述第二子有源材料部的边沿在所述衬底基板正投影与所述第一导电部在所述衬底基板正投影至少部分重合。
本公开一种示例性实施例中，以所述第三导电层为掩膜对所述第二有源材料层进行导体化处理，包括：
通过离子注入工艺，向所述第二有源材料层注入导体化离子。
本公开一种示例性实施例中，所述第三子有源材料部包括第一亚有源材料部、第二亚有源材料部、第三亚有源材料部，所述第一亚有源材料部连接于所述第一子有源材料部和所述第三亚有源材料部之间，所述第二亚有源材料部连接于所述第三亚有源材料部和所述第二子有源材料部之间；所述第二导电部在所述衬底基板的正投影覆盖所述第三亚有源材料部在所述衬底基板正投影。
根据本公开的一个方面，提供一种显示装置，其中，该显示装置包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中像素驱动电路的电路结构示意图；
图2为图1像素驱动电路一种驱动方法中各节点的时序图；
图3为相关技术中显示面板的结构版图；
图4为图3中第一有源层的结构版图；
图5为图3中第一导电层的结构版图；
图6为图3中第二导电层的结构版图；
图7为图3中第二有源层的结构版图；
图8为图3中第三导电层的结构版图；
图9为图3中第四导电层的结构版图；
图10为图3中第五导电层的结构版图；
图11为图3中第一有源层和第一导电层的结构版图；
图12为图3中第一有源层、第一导电层、第二导电层的结构版图；
图13为图3中第一有源层、第一导电层、第二导电层、第二有源层的结构版图；
图14为图3中第一有源层、第一导电层、第二导电层、第二有源层、第三导电层的结构版图；
图15为图3中第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图；
图16为图15中虚线A处的部分剖视图；
图17为本公开显示面板制作方法一种示例性实施例中的工艺流程图；
图18为本公开显示面板制作方法一种示例性实施例的工艺流程图；
图19为本公开显示面板制作方法一种示例性实施例的工艺流程图；
图20为本公开显示面板一种示例性实施例的结构版图；
图21为图20中第一有源层的结构版图；
图22为图20中第一导电层的结构版图；
图23为图20中第二导电层的结构版图；
图24为图20中第二有源层的结构版图；
图25为图20中第三导电层的结构版图；
图26为图20中第四导电层的结构版图；
图27为图20中第五导电层的结构版图；
图28为图20中第一有源层和第一导电层的结构版图；
图29为图20中第一有源层、第一导电层、第二导电层的结构版图；
图30为图20中第一有源层、第一导电层、第二导电层、第二有源层的结构版图；
图31为图20中第一有源层、第一导电层、第二导电层、第二有源层、第三导电层的结构版图；
图32为图20中第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图；
图33为20中第二导电层、第二有源层的部分结构版图；
图34为20中第二导电层、第二有源层、第三导电层的部分结构版图；
图35为图32中沿虚线B的部分剖视图；
图36为本公开显示面板另一种示例性实施例中第一晶体管的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为相关技术中像素驱动电路的电路结构示意图。该像素驱动电路可以包括：驱动晶体管T3、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、电容C。其中，第四晶体管T4的第一极连接数据信号端Da、第二极连接驱动晶体管T3的第一极，栅极连接第二栅极驱动信号端G2；第五晶体管T5的第一极连接第一电源端VDD，第二极连接驱动晶体管T3的第一极，栅极连接使能信号端EM；驱动晶体管T3的栅极连接节点N；第二晶体管T2的第一极连接节点N，第二极连接驱动晶体管T3的第二极，栅极连接第一栅极驱动信号端G1；第六晶体管T6的第一极连接驱动晶体管T3的第二极，第二极连接第七晶体管T7的第一极，栅极连接使能信号端EM，第七晶体管T7的第二极连接第二初始信号端Vinit2，栅极连接第二复位信号端Re2；第一晶体管T1的第一极连接节点N，第二极连接第一初始信号端Vinit1，栅极连接第一复位信号端Re1，电容C连接于第一电源端VDD和节点N之间。该像素驱动电路可以连接一发光单元OLED，用于驱动该发光单元OLED发光，发光单元OLED可以连接于第六晶体管T6的第二极和第二电源端VSS之间。其中，第一晶体管T1和第二晶体管T2可以为N型金属氧化物晶体管，N型金属氧化物晶体管具有较小的漏电流，从而可以避免发光阶段，节点N通过第一晶体管T1和第二晶体管T2漏电。同时，驱动晶体管T3、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型低温多晶体硅晶体管，低温多晶硅晶体管具有较高的载流子迁移率，从而有利于实现高分辨率、高反应速度、高像素密度、高开口率的显示面板。第一初始信号端和第二初始信号端可以根据实际情况输出相同或不同电压信号。
如图2所示，为图1像素驱动电路一种驱动方法中各节点的时序图。其中，G1表示第一栅极驱动信号端G1的时序，G2表示第二栅极驱动信号端G2的时序，Re1表示第一复位信号端Re1的时序，Re2表示第二复位信号端Re2的时序，EM表示使能信号端EM的时序，Da表示数据信号端Da的时序。该像素驱动电路的驱动方法可以包括第一复位阶段t1、补偿阶段t2，第二复位阶段T3、发光阶段t4。在第一复位阶段t1：第一复位信号端Re1输出高电平信号，第一晶体管T1导通，第一初始信号端Vinit1向节点N输入初始信号。在补偿阶段t2：第一栅极驱动信号端G1输出高电平信号，第二栅极驱动信号端G2输出低电平信号，第四晶体管T4、第二晶体管T2，同时数据信号端Da输出驱动信号以向节点N写入电压Vdata+Vth，其中Vdata为驱动信号的电压，Vth为驱动晶体管T3的阈值电压，在第二复位阶段t3，第二复位信号端Re2输出低电平信号，第七晶体管T7导通，第二初始信号端Vinit2向第六晶体管T6的第二极输入初始信号。发光阶段t4：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，驱动晶体管T3在电容C存储的电压Vdata+Vth作用下发光。根据驱动晶体管输出电流公式I＝(μWCox/2L)(Vgs-Vth) 2，其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。本公开像素驱动电路中驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth) 2。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。应该理解的是，图1所示像素驱动电路还可以有其他驱动方式，例如，第一晶体管T1和第七晶体管T7均可在第一复位阶段复位，从而该驱动方法可以不设置第二复位阶段。
相关技术中，显示面板可以包括图1所示的像素驱动电路，该显示面板还可以包括依次层叠设置的衬底基板、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层。上述各层级之间可以设置有绝缘层。如图3-15所示，图3为相关技术中显示面板的结构版图，图4为图3中第一有源层的结构版图，图5为图3中第一导电层的结构版图，图6为图3中第二导电层的结构版图，图7为图3中第二有源层的结构版图，图8为图3中第三导电层的结构版图，图9为图3中第四导电层的结构版图，图10为图3中第五导电层的结构版图，图11为图3中第一有源层和第一导电层的结构版图，图12为图3中第一有源层、第一导电层、第二导电层的结构版图，图13为图3中第一有源层、第一导电层、第二导电层、第二有源层的结构版图，图14为图3中第一有源层、第一导电层、第二导电层、第二有源层、第三 导电层的结构版图，图15为图3中第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图。
如图3、4、11所示，第一有源层可以包括有源部064、有源部065、有源部066、有源部067，其中，有源部064用于形成第四晶体管的沟道区，有源部065用于形成第五晶体管的沟道区，有源部066用于形成第六晶体管的沟道区，有源部067用于形成第七晶体管的沟道区，有源部063用于形成驱动晶体管T3的沟道区。第一有源层可以由多晶硅半导体形成。
如图3、5、11所示，第一导电层可以包括第二栅极驱动信号线G2、使能信号线EM、第二复位信号线Re2、导电部011，其中，第二栅极驱动信号线G2用于提供图1中的第二栅极驱动信号端G2，使能信号线EM用于提供图1中使能信号端EM，第二复位信号线Re2用于提供图1中的第二复位信号端Re2。导电部011用于形成驱动晶体管T3的栅极和电容C的一电极。其中，第一有源层可以以第一导电层为掩膜版进行导体化形成，即被第一导电层遮挡部分形成晶体管的沟道区，未被第一导电层遮挡部分形成导体结构。
如图3、6、12所示，第二导电层可以包括：第一子复位信号线1Re1、第一子栅极驱动信号线1G1、导电部021，其中，第一子复位信号线1Re1用于提供图1中的第一复位信号端，第一子栅极驱动信号线1G1用于提供图1中的第一栅极驱动信号端，导电部021可以形成电容C的另一电极。
如图3、7、13所示，第二有源层可以包括有源部07，有源部07可以包括有源部071和有源部072，有源部071用于形成第一晶体管的沟道区，有源部072用于形成第二晶体管的沟道区。第二有源层可以由氧化物半导体形成，例如氧化铟镓锌。
如图3、8、14所示，第三导电层可以包括：第二子复位信号线2Re1、第二子栅极驱动信号线2G1，第二子复位信号线2Re1用于提供图1中的第一复位信号端，第二子栅极驱动信号线2G1用于提供图1中的第一栅极驱动信号端。第二子复位信号线2Re1和第一子复位信号线1R1可以通过过孔连接，第二子栅极驱动信号线2G1和第一子栅极驱动信号线1G1可以通过过孔连接。其中，第二有源层可以以第三导电层为掩膜版进行导体化形成，即被第三导电层遮挡部分形成晶体管的沟道区，未被第三导电层遮挡部分形成导体结构。
如图3、9、15所示，第四导电层可以包括：第一电源线VDD1、第一初始信号线Vinit1、第二初始信号线Vinit2、连接部041、连接部042、连接部043、连接部044。 其中，第一电源线VDD1用于提供图1中的第一电源端，第一初始信号线Vinit1用于提供图1中第一初始信号端，第二初始信号线Vinit2用于提供图1中的第二初始信号端。连接部041可以通过过孔(黑色方块)与有源部064一侧的第一有源层连接，以连接第四晶体管的第一极。连接部042可以分别通过过孔与导电部011、有源部071和有源部072之间的第二有源层连接，以连接驱动晶体管栅极和第一晶体管的第一极，以及驱动晶体管栅极和第二晶体管的第一极。连接部043可以通过过孔分别连接有源部066一侧的第一有源层、有源部072一侧的第二有源层，以连接第六晶体管的第一极和第二晶体管的第二极。连接部044可以通过过孔连接有源部066一侧的第一有源层，以连接第六晶体管的第二极。第一电源线VDD1可以通过过孔连接有源部065一侧的第一有源层，以连接第五晶体管的第一极和第一电源端，第一电源线VDD1还可以通过过孔连接导电部021，以连接电容C和第一电源端。第一初始信号线Vinit1可以通过过孔连接有源部071一侧的第二有源层，以连接第一晶体管的第二极和第一初始信号端。第二初始信号线可以通过过孔连接有源部067一侧的第一有源层，以连接第二初始信号端和第七晶体管的第二极。
如图3、10所示，第五导电层可以包括：第二电源线VDD2、数据线Da、连接部051，其中，第二电源线VDD2用于提供图1中的第一电源端，数据线Da用于提供图1中的数据信号端。第二电源线VDD2可以通过过孔与第一电源线VDD1连接。数据线Da可以通过过孔连接连接部041，以连接第四晶体管的第一极和数据信号端。连接部051可以通过过孔连接连接部044，连接部051可以用于连接图1中发光单元的阳极。如图3所述，第一电源线VDD1在衬底基板正投影可以位于数据线Da在衬底基板正投影和导电部011在衬底基板正投影之间，第一电源线VDD1可以屏蔽数据线Da对导电部011的干扰。
如图16所示，为图15中虚线A处的部分剖视图。其中，该显示面板还包括第一缓冲层082、第一栅极绝缘层083、第二栅极绝缘层084、第一介电层085、第二缓冲层086、第三栅极绝缘层087、第二介电层088。其中，衬底基板081、第一缓冲层082、第一有源层、第一栅极绝缘层083、第一导电层、第二栅极绝缘层084、第二导电层、第一介电层085、第二缓冲层086、第二有源层、第三栅极绝缘层087、第三导电层、第二介电层088、第四导电层依次层叠设置。如图16所示，在相关技术中，对第二有源层进行导体化的方法是：在第三栅极绝缘层087背离衬底基板081一侧形成第三导电层后，去除未被第三导电层覆盖的第三栅极绝缘层，然后通过气象化学沉积工艺在第三导电层背离衬底基板一侧 形成第二介电层088。其中，在形成第二介电层088过程中，会产生能够使第二有源层导体化的导体化离子，例如，第二介电层可以为氮化硅，第二介电层可以通过硅烷和氮气合成，第二介电层合成过程中会形成氢离子，氢离子可以实现对有源部07的导体化。然而，在对有源部07导体化过程中，氢离子的横向扩散会使得第二晶体管沟道区的实际长度L1小于其设计长度L1+2L2，其中，沟道区的设计长度L1+2L2为该晶体管栅极在横向的长度。从而第二晶体管容易发生短沟道效应。这种情况下，第二晶体管的阈值电压Vth就会与其沟道长度相关到非常严重的程度，从而不利于阈值电压Vth的稳定性和均一性的实现。
基于此，本示例性实施例提供一种显示面板装置方法，如图17所示，为本公开显示面板制作方法一种示例性实施例中的工艺流程图。其中，所述显示面板可以包括第一晶体管T1，所述显示面板制作方法可以包括：
步骤S1：提供一衬底基板81。
步骤S2：在所述衬底基板81一侧形成第二导电层，所述第二导电层可以包括第一导电部1Re11，所述第一导电部1Re11用于形成所述第一晶体管T1的第一栅极。
步骤S3：在所述第二导电层背离所述衬底基板81的一侧形成第二有源材料层，所述第二有源材料层包括第一有源材料部71，所述第一有源材料部71包括第一子有源材料部711、第二子有源材料部712、连接于所述第一子有源材料部711和所述第二子有源材料部712之间的第三子有源材料部713。
所述第三子有源材料部713的部分结构用于形成所述第一晶体管T1的沟道区，所述第一导电部1Re11在所述衬底基板正投影覆盖所述第三子有源材料部713在所述衬底基板正投影。
步骤S4：在所述第二有源材料层背离所述衬底基板81的一侧形成第三栅极绝缘层87，所述第三栅极绝缘层87在所述衬底基板的正投影覆盖所述第一有源材料部71在所述衬底基板的正投影。
步骤S5：在所述第三栅极绝缘层87背离所述衬底基板81的一侧形成第三导电层，所述第三导电层包括第二导电部2Re12，所述第二导电部2Re12用于形成所述第一晶体管T1的第二栅极，且所述第二导电部2Re12在所述衬底基板的正投影与所述第三子有源材料部713在所述衬底基板正投影部分交叠，第三子有源材料部713的部分结构在所述衬底基板正投影与第二导电部2Re12在所述衬底基板正投影不相交。第三导电层可以通过光刻工艺形成，其中，第三导电层可以通过干刻工艺实现刻蚀。干刻工艺具有较小的CD Bias(Critical Dimension Bias，光刻胶与被刻蚀体边沿偏差)，从而可 以实现尺寸精度较高的第三导电层。其中，干刻工艺的CD Bias可以做到0.5微米。
步骤S6：以所述第三导电层为掩膜对所述第二有源材料层进行导体化处理。
本示例性实施例中，所述第一晶体管可以为氧化晶体管，所述第二有源材料层为氧化物半导体，例如，第二有源材料层的材料可以为氧化铟镓锌。本示例性实施例中的显示面板可以包括像素驱动电路，该显示驱动电路可以如图1所示，其中，本示例性实施例中的第一晶体管可以为图1中的第一晶体管。应该理解的是，在其他示例性实施例中，该显示面板中的像素驱动电路还可以为其他结构，例如8T1C结构；图17中的第一晶体管还可以为低温多晶硅晶体管，图17中的第一晶体管还可以位于显示面板中的其他电路结构，例如，第一晶体管可以位于显示面板的中的栅极驱动电路。
在本示例性实施例中，如图17所示，以所述第三导电层为掩膜对所述第二有源材料层进行导体化处理，可以包括：利用气象化学沉积工艺，在所述第三导电层背离所述衬底基板的一侧形成第二介电层88。其中，形成所述第二介电层88过程中能够生成有导体化离子，导体化离子能够对未被第三导电层覆盖的第二有源材料层实现导体化。例如，第二介电层88可以为氮化硅，第二介电层88可以通过硅烷和氮气合成，第二介电层88合成过程中会形成氢离子，氢离子可以实现对第二有源材料层的导体化。
如图17所示，本示例性实施例对第二有源材料层进行导体化工艺时，由于第二有源材料层上覆盖有第三栅极绝缘层87，第三栅极绝缘层87对导体化离子的扩散有阻挡作用，从而导体化离子在横向上的扩散量极少甚至为零，进而通过第二导电部2Re12为掩膜版形成的沟道区在在横向的长度与第二导电部2Re12在横向的长度相同，或沟道区在横向的长度略小于第二导电部2Re12在横向的长度。即该显示面板制作方法能够极大减小图16中L2的值，从而该显示面板制作方法能够在有限尺寸的第二导电部2Re12作用下，形成较大尺寸的沟道区。同时，由于第三栅极绝缘层87对导体化离子的扩散有阻挡作用，第三子有源材料部713中未被第二导电部2Re12覆盖部分的离子掺杂浓度较低，方块电阻较大，因而第一晶体管的导通电流较小。此外，本示例性实施例还将所述第一导电部1Re11在所述衬底基板正投影覆盖所述第三子有源材料部713在所述衬底基板正投影，在第一导电部1Re11导通电压作用下，位于第一晶体管第一极和第二极之间且未被第二导电部2Re12覆盖的第三子有源材料部713的方块电阻减小，从而可以实现第一晶体管较大的导通电流。此外，由于未被第二导电部2Re12覆盖的第三子有源材料部713具有较大的方块电阻，第一晶体管的关断电流较小，从而可以进一步降低节点N在在发光阶段通过第一晶体管的漏电流。需要说明的是，图 17中的横向可以为第一子有源材料部711、第三子有源材料部713、第二子有源材料部712的分布方向，即沟道区的长度方向。
本示例性实施例中，如图17所示，所述第三子有源材料部713可以包括第一亚有源材料部7131、第二亚有源材料部7132、第三亚有源材料部7133，所述第一亚有源材料部7131可以连接于所述第一子有源材料部711和所述第三亚有源材料部7133之间，所述第二亚有源材料部7132可以连接于所述第三亚有源材料部7133和所述第二子有源材料部712之间。所述第二导电部2Re12在所述衬底基板的正投影可以覆盖所述第三亚有源材料部7133在所述衬底基板正投影。其中，第二有源层被导体化后，第三亚有源材料部7133可以形成第一晶体管的沟道区。
本示例性实施例中，以所述第三导电层为掩膜对所述第二有源材料层进行导体化处理，还可以包括其他方法。例如，可以在形成第二介电层88前：通过离子注入工艺，向所述第二有源层注入导体化离子，离子注入工艺会向导体化离子提供一定的初始能量，从而导体化离子会通过第三栅极绝缘层87且到达第二有源层。其中，导通化离子可以为B、Al、F、In、Zn等离子。本示例性实施例可以单独通过离子注入工艺实现第二有源材料层的导体化，也可以在上述第二介电层气相化学沉积工艺基础上，通过离子注入工艺进一步提高第二有源材料层的导体化程度。
本示例性实施例中，如图18所示，为本公开显示面板制作方法一种示例性实施例的工艺流程图。所述显示面板制作方法还可以包括：通过干刻气体形成贯穿所述第三栅极绝缘层87、所述第二介电层88的第一过孔H1和第二过孔H2，所述第一过孔H1在所述衬底基板正投影可以位于所述第一子有源材料部711在所述衬底基板正投影上，所述第二过孔H2在所述衬底基板正投影可以位于所述第二子有源材料部712在所述衬底基板正投影上。其中，所述干刻气体在干刻过程中能够产生导体化离子，所述导体化离子能够对所述第二有源材料层实现导体化，从而能够提高第一子有源材料部711、第二子有源材料部712的导体化程度。例如，干刻气体中可以含有氟元素、氢元素等，导体化离子可以为氟离子、氢离子，氟离子等导体化离子能够占据氧化铟镓锌晶格空隙处，使氧化铟镓锌导体化。另外，在干刻完成后，还可以通过氩气Ar对氧化铟镓锌层进行进一步导体化处理，Ar也能够占据氧化铟镓锌晶格空隙处，使氧化铟镓锌导体化，并且惰性气体Ar不会对氧化物晶体管的特性造成影响。从而，第一子有源材料部711和第二子有源材料部712的导体化程度可以高于第一亚有源材料部7131和第二亚有源材料部7132的导体化程度。即导体化后的第一亚有源材料部7131的方 块电阻小于导体化的的第一子有源材料部711的方块电阻，即导体化后的第一亚有源材料部7131的方块电阻小于导体化的的第二子有源材料部712的方块电阻。此外，导体化后的第一亚有源材料部7131的方块电阻可以等于导体化后的第二亚有源材料部7132的方块电阻。导体化后的第一子有源材料部711的方块电阻可以等于第二子有源材料部712的方块电阻。导体化后的第一子有源材料部711可以用于形成第一晶体管的第一极，导体化后的第二子有源材料部712可以用于形成第一晶体管的第二极。本示例性实施例中，导体化后的第一亚有源材料部的方块电阻可以为2000～20000Ω/sq，例如，2000Ω/sq、5000Ω/sq、10000Ω/sq、20000Ω/sq。导体化后的第一子有源材料部的方块电阻可以为500～2000Ω/sq，例如，500Ω/sq、1000Ω/sq、2000Ω/sq。导体化后的第二子有源材料部的方块电阻可以为500～2000Ω/sq，例如，500Ω/sq、1000Ω/sq、2000Ω/sq。
需要说明的是，干刻气体干刻过程中产生的导体化离子对第一子有源材料部711、第二子有源材料部712进行导体化过程中，导体化离子会发生横向扩散，从而，第一过孔H1在衬底基板正投影可以略小于第一子有源材料部711在衬底基板正投影，第二过孔H2在衬底基板正投影可以略小于第二子有源材料部712在衬底基板正投影。
本示例性实施例中，如图17所示，第一子有源部711的边沿7111在衬底基板正投影与第一导电部1Re11在衬底基板正投影可以至少部分重合，第二子有源部712的边沿7121在衬底基板正投影与第一导电部1Re11在衬底基板正投影可以至少部分重合。在其他示例性实施例中，第一导电部1Re11在衬底基板正投影还可以与第一过孔H1在衬底基板正投影至少部分重合，第一导电部1Re11在衬底基板正投影还可以与第二过孔H2在衬底基板正投影至少部分重合。
应该理解的是，在其示例性实施例中，第一晶体管还可以为其他结构，例如，第一晶体管还可以包括多个并联或串联的沟道区。相应的，其他实施例同样可以利用上述结构增加第一晶体管的沟道长度。
本示例性实施例中，如图19所示，为本公开显示面板制作方法一种示例性实施例的工艺流程图。该显示面板制作方法还可以包括：在所述第二介电层88背离所述衬底基板81一侧形成第四导电层，所述第四导电层可以包括第三导电部43和第四导电部Vinit14。所述第三导电部43可以通过所述第一过孔H1连接所述第一子有源材料部711，所述第四导电部Vinit14可以通过所述第二过孔H2连接所述第二子有源材料部712。
本示例性实施例中，图1中的第二晶体管也可以与图17-19中的第一晶体管具有 相同结构。
本示例性实施例还提供一种显示面板，该显示面板可以通过上述显示面板制作方法制成。
除此之外，该显示面板可以包括图1所示的像素驱动电路，该显示面板还可以包括第一有源层、第一导电层、第五导电层，其中，衬底基板、第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层、第五导电层可以依次层叠设置。如图20-32所示，图20为本公开显示面板一种示例性实施例的结构版图，图21为图20中第一有源层的结构版图，22为图20中第一导电层的结构版图，图23为图20中第二导电层的结构版图，图24为图20中第二有源层的结构版图，图25为图20中第三导电层的结构版图，图26为图20中第四导电层的结构版图，图27为图20中第五导电层的结构版图，图28为图20中第一有源层和第一导电层的结构版图，图29为图20中第一有源层、第一导电层、第二导电层的结构版图，图30为图20中第一有源层、第一导电层、第二导电层、第二有源层的结构版图，图31为图20中第一有源层、第一导电层、第二导电层、第二有源层、第三导电层的结构版图，图32为图20中第一有源层、第一导电层、第二导电层、第二有源层、第三导电层、第四导电层的结构版图，图33为20中第二导电层、第二有源层的部分结构版图，图34为20中第二导电层、第二有源层、第三导电层的部分结构版图。
如图20、21、28所示，第一有源层可以包括有源部63、有源部64、有源部65、有源部66、有源部67，其中，有源部64用于形成第四晶体管的沟道区，有源部65用于形成第五晶体管的沟道区，有源部66用于形成第六晶体管的沟道区，有源部67用于形成第七晶体管的沟道区，有源部63用于形成驱动晶体管T3的沟道区。第一有源层可以由多晶硅半导体形成。
如图20、22、28所示，第一导电层可以包括第二栅极驱动信号线G2、使能信号线EM、第二复位信号线Re2、导电部11，其中，第二栅极驱动信号线G2用于提供图1中的第二栅极驱动信号端，使能信号线EM用于提供图1中使能信号端，第二复位信号线Re2用于提供图1中的第二复位信号端。第二栅极驱动信号线G2在衬底基板正投影、使能信号线EM在衬底基板正投影、第二复位信号线Re2在衬底基板正投影可以沿第一方向X延伸。导电部11用于形成驱动晶体管T3的栅极和电容C的一电极。其中，第一有源层可以以第一导电层为掩膜版进行导体化形成，即被第一导电层遮挡部分形成晶体管的沟道区，未被第一导电层遮挡部分形成导体结构。
如图20、23、29所示，第二导电层可以包括：第一子复位信号线1Re1、第一子栅极驱动信号线1G1、导电部21，其中，第一子复位信号线1Re1用于提供图1中的第一复位信号端，第一子栅极驱动信号线1G1用于提供图1中的第一栅极驱动信号端，导电部21可以形成电容C的另一电极。第一子复位信号线1Re1可以包括第一导电部1Re11，第一导电部1Re11可以用于形成第一晶体管的第一栅极；第一子栅极驱动信号线1G1可以包括第五导电部1G15，所述第五导电部可以用于形成所述第二晶体管T2的第一栅极。第一子复位信号线1Re1在衬底基板正投影、第一子栅极驱动信号线1G1在衬底基板正投影可以沿第一方向X延伸。
如图20、24、30、33所示，第二有源层可以包括第一有源部71，第一有源部71在衬底基板正投影可以沿第二方向Y延伸，其中，第二方向Y和第一方向X可以相交，例如，第二方向Y和第一方向X可以垂直。所述第一有源部71可以包括第一子有源部711、第二子有源部712、连接于所述第一子有源部711和所述第二子有源部712之间的第三子有源部713；所述第一子有源部711可以用于形成所述第一晶体管T1的第一极，第二子有源部712可以用于形成所述第一晶体管T1的第二极，所述第三子有源部713的部分结构可以用于形成所述第一晶体管T1的沟道区。所述第三子有源部713可以包括第一亚有源部7131、第二亚有源部7132、第三亚有源部7133，所述第一亚有源部7131连接于所述第一子有源部711和所述第三亚有源部7133之间，所述第二亚有源部7132连接于所述第三亚有源部7133和所述第二子有源部712之间，所述第三亚有源部7133可以用于形成所述第一晶体管T1的沟道区。所述第一有源部71还可以包括：第四子有源部714、第五子有源部715，第四子有源部714可以用于形成所述第二晶体管T2的第二极；第五子有源部715可以连接于所述第四子有源部714和所述第一子有源部711之间，所述第五子有源部715的部分结构可以用于形成所述第二晶体管T2的沟道区。所述第五子有源部715可以包括第四亚有源部7154、第五亚有源部7155、第六亚有源部7156，所述第四亚有源部7154可以连接于所述第一子有源部711和所述第六亚有源部7156之间，所述第五亚有源部7155可以连接于所述第六亚有源部7156和所述第四子有源部714之间，所述第六亚有源部7156可以用于形成所述第二晶体管T2的沟道区。其中，第二子有源部712在衬底基板正投影、第二亚有源部7132在衬底基板正投影、第三亚有源部7133在衬底基板正投影、第一亚有源部7131在衬底基板正投影、第一子有源部711在衬底基板正投影、第四亚有源部7154在衬底基板正投影、第六亚有源部7156在衬底基板正投影、第五亚有源部7155 在衬底基板正投影、第四子有源部714在衬底基板正投影可以在第二方向Y上依次连接。第二有源层可以由氧化物半导体形成，例如氧化铟镓锌。
需要说明的是，考虑工艺因素，本示例性实施例图中的边界可以有误差范围。
如图20、25、31、34所示，第三导电层可以包括：第二子复位信号线2Re1、第二子栅极驱动信号线2G1，第二子复位信号线2Re1用于提供图1中的第一复位信号端，第二子栅极驱动信号线2G1用于提供图1中的第一栅极驱动信号端。第二子栅极驱动信号线2G1可以包括第六导电部2G16，第六导电部2G16可以用于形成第二晶体管T2的第二栅极；第二子复位信号线2Re1可以包括第二导电部2Re2，第二导电部2Re2可以用于形成第一晶体管的第二极。第二子复位信号线2Re1和第一子复位信号线1R1可以通过过孔连接，第二子栅极驱动信号线2G1和第一子栅极驱动信号线1G1可以通过过孔连接。应该理解的是，在其他示例性实施例中，第一晶体管的第一栅极和第二栅极还可以分别施加不同的电压，第二晶体管的第一栅极和第二栅极也可以分别施加不同的电压。第二子复位信号线2Re1在衬底基板正投影、第二子栅极驱动信号线2G1在衬底基板正投影可以沿第一方向延伸。其中，第二有源层可以以第三导电层为掩膜版进行导体化形成，即被第三导电层遮挡部分形成晶体管的沟道区，未被第三导电层遮挡部分形成导体结构。此外，由于以第三导电部为掩膜版对第二有源层进行导体化处理时，导体化离子难免会在垂直于层叠方向的方向扩散，从而第二导电部2Re2在衬底基板正投影在第二方向Y的尺寸可以略大于第三亚有源部7133在衬底基板正投影在第二方向Y上的尺寸；第六导电部2G16在衬底基板正投影在第二方向Y的尺寸可以略大于第六亚有源部7156在衬底基板正投影在第二方向Y上的尺寸。
如图20、26、32所示，第四导电层可以包括：第一电源线VDD1、第一初始信号线Vinit1、第二初始信号线Vinit2、导电部41、第三导电部43、导电部42、导电部44。其中，第一电源线VDD1用于提供图1中的第一电源端，第一初始信号线Vinit1用于提供图1中第一初始信号端，第二初始信号线Vinit2用于提供图1中的第二初始信号端。导电部41可以通过过孔H4与有源部64一侧的第一有源层连接，以连接第四晶体管的第一极。第三导电部43可以通过过孔H5与导电部11连接，通过过孔H1与第一子有源部711连接，以连接驱动晶体管栅极和第一晶体管的第一极，以及驱动晶体管栅极和第二晶体管的第一极。导电部42可以通过过孔H6连接有源部66一侧的第一有源层，通过过孔H3连接第四子有源部714，以连接第六晶体管的第一极和第二晶体管的第二极。导电部44可以通过过孔H9连接有源部66一侧的第一有源层， 以连接第六晶体管的第二极。第一电源线VDD1可以通过过孔H7连接有源部65一侧的第一有源层，以连接第五晶体管的第一极和第一电源端，第一电源线VDD1还可以通过过孔H8连接导电部21，以连接电容C和第一电源端。第一初始信号线Vinit1可以包括第四导电部Vinit14，第四导电部Vinit14可以通过过孔H2连接第二子有源部712，以连接第一晶体管的第二极和第一初始信号端。第二初始信号线Vinit2可以通过过孔H10连接有源部67一侧的第一有源层，以连接第二初始信号端和第七晶体管的第二极。
需要说明的是，第一过孔H1在衬底基板正投影可以略小于第一子有源部711在衬底基板正投影，第二过孔H2在衬底基板正投影可以略小于第二子有源部712在衬底基板正投影。如图24所示，第一子有源部711可以包括在第二方向Y上相对的边沿7111和边沿7112，第二子有源部712可以包括靠近第一子有源部711一侧的边沿7121，第四子有源部714可以包括面向第一子有源部711一侧的边沿7141。其中，边沿7111在衬底基板正投影可以与第一导电部1Re11在衬底基板正投影至少部分重合；边沿7112在衬底基板正投影可以与第五导电部1G15在衬底基板正投影至少部分重合；边沿7121在衬底基板正投影可以与第一导电部1Re11在衬底基板正投影至少部分重合；边沿7141在衬底基板正投影可以与第五导电部1G15在衬底基板正投影至少部分重合。第一导电部1Re11在衬底基板正投影还可以与第一过孔H1在衬底基板正投影至少部分重合，第一导电部1Re11在衬底基板正投影还可以与第二过孔H2在衬底基板正投影至少部分重合。在其他示例性实施例中，第五导电部1G15在衬底基板正投影还可以与第一过孔H1在衬底基板正投影至少部分重合，第五导电部1G15在衬底基板正投影还可以与第二过孔H3在衬底基板正投影至少部分重合。
如图20、27所示，第五导电层可以包括：第二电源线VDD2、数据线Da、连接部51，其中，第二电源线VDD2用于提供图1中的第一电源端，数据线Da用于提供图1中的数据信号端。第二电源线VDD2可以通过过孔H11与第一电源线VDD1连接。数据线Da可以通过过孔H12连接连接部41，以连接第四晶体管的第一极和数据信号端。连接部51可以通过过孔连接导电部44，连接部51可以用于连接图1中发光单元的阳极。如图20所示，第一电源线VDD1在衬底基板正投影可以位于数据线Da在衬底基板正投影和导电部11在衬底基板正投影之间，第一电源线VDD1可以屏蔽数据线Da对导电部11的干扰。
如图35所示，为图32中沿虚线B的部分剖视图。其中，该显示面板还可以包括 第一缓冲层82、第一栅极绝缘层83、第二栅极绝缘层84、第一介电层85、第二缓冲层86、第三栅极绝缘层87、第二介电层88。其中，衬底基板81、第一缓冲层82、第一有源层、第一栅极绝缘层83、第一导电层、第二栅极绝缘层84、第二导电层、第一介电层85、第二缓冲层86、第二有源层、第三栅极绝缘层87、第三导电层、第二介电层88、第四导电层依次层叠设置。第一缓冲层、第二缓冲层可以包括氧化硅层、氮化硅层中的至少一层。第一栅极绝缘层、第二栅极绝缘层、第三栅极绝缘层可以为氧化硅层。第一介电层、第二介电层可以为氮化硅层。第四导电层、第五导电层的材料可以包括金属材料，例如可以是钼，铝，铜，钛，铌，其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。第一导电层、第二导电层、第三导电层的材料可以是钼，铝，铜，钛，铌，其中之一或者合金，或者钼/钛合金或者叠层等。衬底基板81可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。
本示例性实施例中，如图35所示，所述第一导电部1Re11在所述衬底基板正投影可以覆盖所述第三子有源部713在所述衬底基板正投影。所述第三栅极绝缘层87在所述衬底基板的正投影可以覆盖所述第一有源部71在所述衬底基板的正投影。所述第二导电部2Re12在所述衬底基板的正投影可以覆盖所述第一晶体管沟道区(第三亚有源部7133)在所述衬底基板的正投影。所述第二导电部在所述衬底基板正投影位于所述第一亚有源部在所述衬底基板正投影和所述第二亚有源部在所述衬底基板正投影之间，即所述第二导电部2Re12在所述衬底基板正投影与所述第一亚有源部7131在所述衬底基板正投影可以不相交，所述第二导电部2Re12在所述衬底基板正投影与所述第二亚有源部7132在所述衬底基板正投影可以不相交。
本示例性实施例对第二有源层进行导体化工艺时，由于第二有源层上覆盖有第三栅极绝缘层87，且第三栅极绝缘层87对导体化离子的扩散有阻挡作用，从而导体化离子在横向上的扩散量极少甚至为零，进而通过第二导电部2Re12为掩膜版形成的沟道区在其长度方向上(即第二方向Y)的尺寸与第二导电部2Re12在相同方向上的尺寸相同或极为接近。从而该显示面板能够在有限尺寸的第二导电部2Re12作用下，形成较大沟道尺寸的第一晶体管T1。同时，由于第三栅极绝缘层87对导体化离子的扩散有阻挡作用，未被第二导电部2Re12覆盖的第一亚有源部7131和第二亚有源部7132的离子掺杂浓度较低，从而第一晶体管T1的导通电流较小。此外，本示例性实施例还将所述第一导电部1Re11在所述衬底基板正投影覆盖所述第三子有源部713在所述衬底基板正投影，在第一导电部1Re11导 通电压作用下，未被第二导电部2Re12覆盖的第一亚有源部7131和第二亚有源部7132的方块电阻减小，从而可以保证第一晶体管T1较大的导通电流。此外，由于未被第二导电部2Re12覆盖的第一亚有源部7131和第二亚有源部7132具有较大的方块电阻，从而该第一晶体管具有较小的关断电流。
本示例性实施例中，所述第一亚有源部7131的方块电阻可以等于第二亚有源部7132的方块电阻，所述第一亚有源部7131的方块电阻可以小于所述第一子有源部711的方块电阻，所述第一亚有源部7131的方块电阻可以小于所述第二子有源部712的方块电阻。第一亚有源部的方块电阻可以为2000～20000Ω/sq，例如，2000Ω/sq、5000Ω/sq、10000Ω/sq、20000Ω/sq。第一子有源部的方块电阻可以为500～2000Ω/sq，例如，500Ω/sq、1000Ω/sq、2000Ω/sq。第二子有源部的方块电阻可以为500～2000Ω/sq，例如，500Ω/sq、1000Ω/sq、2000Ω/sq。应该理解的是，由于工艺误差，第一亚有源部7131的方块电阻可以略大于或略小于第二亚有源部7132的方块电阻，所述第一亚有源部的方块电阻与第二亚有源部的方块电阻的差值小于预设值，所述预设值可以为0-100Ω/sq，例如，预设值可以为0、50、100。
本示例性实施例中，如图35所示，所述第一子有源部711可以共用为所述第二晶体管T2的第一极。所述第五导电部1G15在所述衬底基板正投影可以覆盖所述第五子有源部715在所述衬底基板正投影。所述第六导电部2G16在所述衬底基板的正投影可以覆盖所述第二晶体管T2沟道区(第六亚有源部7156)在所述衬底基板的正投影。所述第六导电部在所述衬底基板正投影位于所述第五亚有源部在所述衬底基板正投影和所述第四亚有源部在所述衬底基板正投影之间，即所述第六导电部2G16在所述衬底基板正投影与所述第五亚有源部7155在所述衬底基板正投影不相交，所述第六导电部2G16在所述衬底基板正投影与所述第四亚有源部7154在所述衬底基板正投影不相交。
本示例性实施例对第二有源层进行导体化工艺时，由于第二有源层上覆盖有第三栅极绝缘层87，且第三栅极绝缘层87对导体化离子的扩散有阻挡作用，从而导体化离子在横向上的扩散量极少甚至为零，进而通过第六导电部2G16为掩膜版形成的沟道区在其长度方向(即第二方向Y)上的尺寸与第六导电部2G16在相同方向上的尺寸相同或极为接近。从而该显示面板能够在有限尺寸的第六导电部2G16作用下，形成较大沟道尺寸的第二晶体管T2。同时，由于第三栅极绝缘层87对导体化离子的扩散有阻挡作用，未被第六导电部2G16覆盖的第四亚有源部7154和第五亚有源部7155 的离子掺杂浓度较低，从而第二晶体管T2的导通电流较小。此外，本示例性实施例还将所述第五导电部1G15在所述衬底基板正投影覆盖所述第五子有源部715在所述衬底基板正投影，在第五导电部1G15导通电压作用下，未被第六导电部2G16覆盖第四亚有源部7154和第五亚有源部7155的方块电阻减小，从而可以保证第二晶体管T2较大的导通电流。此外，由于未被第六导电部2G16覆盖的第四亚有源部7154和第五亚有源部7155具有较大的方块电阻，从而该第二晶体管T2具有较小的关断电流。
本示例性实施例中，所述第四亚有源部7154的方块电阻可以等于第五亚有源部7155的方块电阻，所述第四亚有源部7154的方块电阻可以小于所述第四子有源部714的方块电阻，所述第四亚有源部7154的方块电阻可以小于所述第一子有源部711的方块电阻。所述第四亚有源部7154的方块电阻为2000～20000Ω/sq，例如，2000Ω/sq、5000Ω/sq、10000Ω/sq、20000Ω/sq。第四子有源部714的方块电阻可以为500～2000Ω/sq，例如，500Ω/sq、1000Ω/sq、2000Ω/sq。应该理解的是，由于工艺误差，第四亚有源部7154的方块电阻可以略大于或略小于第五亚有源部7155的方块电阻，所述第四亚有源部7154的方块电阻与第五亚有源部7155的方块电阻的差值小于预设值，所述预设值可以为0-100Ω/sq，例如，预设值可以为0、50、100。
如图36所示，为本公开显示面板另一种示例性实施例中第一晶体管的结构示意图。与图35中第一晶体管结构不同的是，所述第一有源部还可以包括第六子有源部716，所述第六子有源部716可以位于所述第一子有源部711和所述第三子有源部713之间，所述第六子有源部716在所述衬底基板正投影可以位于所述第一子有源部711在所述衬底基板正投影和所述第一导电部1Re11在所述衬底基板正投影之间，即所述第六子有源部716在所述衬底基板正投影与第一导电部1Re11在所述衬底基板正投影不相交。其中，所述第六子有源部的方块电阻可以为2000～20000Ω/sq。此外，所述第一有源部还可以包括第七子有源部717，所述第七子有源部717可以位于所述第二子有源部712和所述第三子有源部713之间，第七子有源部717在所述衬底基板正投影可以位于所述第二子有源部712在所述衬底基板正投影和所述第一导电部1Re11在所述衬底基板正投影之间，即第七子有源部717在所述衬底基板正投影与第一导电部1Re11在所述衬底基板正投影不相交。其中，第七子有源部717的方块电阻可以为2000～20000Ω/sq。此外，为了保证第一晶体管具有较大的导通电流，第六子有源部716和第七子有源部717在第一晶体管沟道区长度方向上的尺寸不能太大。本示例性实施例中，第六子有源部716和第七子有源部717在第一晶体管沟道区长度方向上的总长度可以为S1，第 六子有源部716、第七子有源部717、第一子有源部、第二子有源部在第一晶体管沟道区长度方向上的总长度可以为S2，S2/(S1+S2)可以大于等于80％，其中，第一晶体管沟道区的长度方向即为第一晶体管沟道区的导电方向。该显示面板中第二晶体管可以与第一晶体管具有相同的结构。
根据本公开的一个方面，提供一种显示装置，其中，该显示装置包括上述的显示面板。该显示装置可以为手机、平板电脑、电视的显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (25)

  1. 一种显示面板，其中，所述显示面板包括第一晶体管，所述显示面板包括：
    衬底基板；
    第二导电层，位于所述衬底基板的一侧，所述第二导电层包括第一导电部，所述第一导电部用于形成所述第一晶体管的第一栅极；
    第二有源层，位于所述第二导电层背离所述衬底基板的一侧，所述第二有源层包括第一有源部，所述第一有源部包括第一子有源部、第二子有源部、连接于所述第一子有源部和所述第二子有源部之间的第三子有源部；
    所述第一子有源部用于形成所述第一晶体管的第一极，第二子有源部用于形成所述第一晶体管的第二极，所述第三子有源部的部分结构用于形成所述第一晶体管的沟道区，所述第一导电部在所述衬底基板正投影覆盖所述第三子有源部在所述衬底基板正投影；
    第三栅极绝缘层，位于所述第二有源层背离所述衬底基板的一侧，所述第三栅极绝缘层在所述衬底基板的正投影覆盖所述第一有源部在所述衬底基板的正投影；
    第三导电层，位于所述第三栅极绝缘层背离所述衬底基板的一侧，所述第三导电层包括第二导电部，所述第二导电部用于形成所述第一晶体管的第二栅极，且所述第二导电部在所述衬底基板的正投影覆盖所述第一晶体管沟道区在所述衬底基板的正投影。
  2. 根据权利要求1所述的显示面板，其中，所述第三子有源部包括第一亚有源部、第二亚有源部、第三亚有源部，所述第一亚有源部连接于所述第一子有源部和所述第三亚有源部之间，所述第二亚有源部连接于所述第三亚有源部和所述第二子有源部之间，所述第三亚有源部用于形成所述第一晶体管的沟道区；
    所述第二导电部在所述衬底基板正投影覆盖所述第三亚有源部在所述衬底基板的正投影，且所述第二导电部在所述衬底基板正投影位于所述第一亚有源部在所述衬底基板正投影和所述第二亚有源部在所述衬底基板正投影之间。
  3. 根据权利要求2所述的显示面板，其中，所述第一亚有源部的方块电阻与第二亚有源部的方块电阻的差值小于预设值，所述预设值为0-100Ω/sq，所述第一亚有源部的方块电阻小于所述第一子有源部的方块电阻，所述第一亚有源部的方块电阻小于所述第二子有源部的方块电阻。
  4. 根据权利要求2所述的显示面板，其中，所述第一亚有源部的方块电阻与第 二亚有源部的方块电阻的差值小于预设值，所述预设值为0-100Ω/sq，所述第一亚有源部的方块电阻为2000～20000Ω/sq。
  5. 根据权利要求2所述的显示面板，其中，所述第一子有源部的方块电阻为500～2000Ω/sq，所述第二子有源部的方块电阻为500～2000Ω/sq。
  6. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    第四导电层，位于所述第三导电层背离所述衬底基板的一侧，所述第四导电层包括第三导电部和第四导电部；
    所述第三导电部通过第一过孔连接所述第一子有源部，所述第四导电部通过第二过孔连接所述第二子有源部。
  7. 根据权利要求6所述的显示面板，其中，所述第一过孔在所述衬底基板正投影位于所述第一子有源部在所述衬底基板正投影上，所述第二过孔在所述衬底基板正投影位于所述第二子有源部在所述衬底基板正投影上；
    所述第一过孔在所述衬底基板正投影的面积小于等于所述第一子有源部在所述衬底基板正投影的面积；
    所述第二过孔在所述衬底基板正投影的面积小于等于所述第二子有源部在所述衬底基板正投影的面积。
  8. 根据权利要求1所述的显示面板，其中，所述第一子有源部的边沿在所述衬底基板正投影与所述第一导电部在所述衬底基板正投影至少部分重合；
    所述第二子有源部的边沿在所述衬底基板正投影与所述第一导电部在所述衬底基板正投影至少部分重合。
  9. 根据权利要求1所述的显示面板，其中，所述第一有源部还包括：
    第六子有源部，所述第六子有源部位于所述第一子有源部和所述第三子有源部之间，所述第六子有源部在所述衬底基板正投影位于所述第一子有源部在所述衬底基板正投影和所述第一导电部在所述衬底基板正投影之间；
    所述第六子有源部的方块电阻为2000～20000Ω/sq。
  10. 根据权利要求1所述的显示面板，其中，所述第一晶体管为氧化物晶体管。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板还包括像素驱动电路，所述像素驱动电路包括所述第一晶体管；
    所述像素驱动电路还包括驱动晶体管，所述第一晶体管的第一极连接所述驱动晶体管的栅极，第二极连接第一初始信号端；
    所述像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极，所述第二晶体管为氧化物晶体管。
  12. 根据权利要求11所述的显示面板，其中，所述第一有源部还包括：
    第四子有源部，用于形成所述第二晶体管的第二极；
    第五子有源部，连接于所述第四子有源部和所述第一子有源部之间，所述第五子有源部的部分结构用于形成所述第二晶体管的沟道区；
    所述第一子有源部共用为所述第二晶体管的第一极；
    所述第二导电层还包括第五导电部，所述第五导电部用于形成所述第二晶体管的第一栅极，所述第五导电部在所述衬底基板正投影覆盖所述第五子有源部在所述衬底基板正投影；
    所述第三导电层还包括第六导电部，所述第六导电部用于形成所述第二晶体管的第二栅极，且所述第六导电部在所述衬底基板的正投影覆盖所述第二晶体管沟道区在所述衬底基板的正投影。
  13. 根据权利要求12所述的显示面板，其中，
    所述第五子有源部包括第四亚有源部、第五亚有源部、第六亚有源部，所述第四亚有源部连接于所述第一子有源部和所述第六亚有源部之间，所述第五亚有源部连接于所述第六亚有源部和所述第四子有源部之间，所述第六亚有源部用于形成所述第二晶体管的沟道区；
    所述第六导电部在所述衬底基板正投影覆盖所述第六亚有源部在所述衬底基板正投影，所述第六导电部在所述衬底基板正投影位于所述第五亚有源部在所述衬底基板正投影和所述第四亚有源部在所述衬底基板正投影之间。
  14. 根据权利要求13所述的显示面板，其中，所述第四亚有源部的方块电阻与第五亚有源部的方块电阻的差值小于预设值，所述预设值为0-100Ω/sq，所述第四亚有源部的方块电阻小于所述第四子有源部的方块电阻，所述第四亚有源部的方块电阻小于所述第一子有源部的方块电阻。
  15. 根据权利要求13所述的显示面板，其中，所述第四亚有源部的方块电阻与第五亚有源部的方块电阻的差值小于预设值，所述预设值为0-100Ω/sq，，所述第四亚有源部的方块电阻为2000～20000Ω/sq。
  16. 一种显示面板制作方法，其中，所述显示面板包括第一晶体管，所述显示面板制作方法包括：
    提供一衬底基板；
    在所述衬底基板一侧形成第二导电层，所述第二导电层包括第一导电部，所述第一导电部用于形成所述第一晶体管的第一栅极；
    在所述第二导电层背离所述衬底基板的一侧形成第二有源材料层，所述第二有源材料层包括第一有源材料部，所述第一有源材料部包括第一子有源材料部、第二子有源材料部、连接于所述第一子有源材料部和所述第二子有源材料部之间的第三子有源材料部；
    所述第三子有源材料部的部分结构用于形成所述第一晶体管的沟道区，且所述第一导电部在所述衬底基板正投影覆盖所述第三子有源材料部在所述衬底基板正投影；
    在所述第二有源材料层背离所述衬底基板的一侧形成第三栅极绝缘层，所述第三栅极绝缘层在所述衬底基板的正投影覆盖所述第一有源材料部在所述衬底基板的正投影；
    在所述第三栅极绝缘层背离所述衬底基板的一侧形成第三导电层，所述第三导电层包括第二导电部，所述第二导电部用于形成所述第一晶体管的第二栅极，且所述第二导电部在所述衬底基板的正投影与所述第三子有源材料部在所述衬底基板正投影部分交叠；
    以所述第三导电层为掩膜对所述第二有源材料层进行导体化处理。
  17. 根据权利要求16所述的显示面板制作方法，其中，所述第一晶体管为氧化晶体管，所述第二有源材料层为氧化物半导体。
  18. 根据权利要求16所述的显示面板制作方法，其中，以所述第三导电层为掩膜对所述第二有源材料层进行导体化处理，包括：
    利用气象化学沉积工艺，在所述第三导电层背离所述衬底基板的一侧形成第二介电层；
    其中，形成所述第二介电层过程中生成有导体化离子，所述导体化离子能够对所述第二有源材料层实现导体化。
  19. 根据权利要求18所述的显示面板制作方法，其中，所述第二介电层的材料为氮化硅，所述导体化离子为氢离子。
  20. 根据权利要求18所述的显示面板制作方法，其中，所述显示面板制作方法还包括：
    通过干刻气体形成贯穿所述第三栅极绝缘层、所述第二介电层的第一过孔和第二 过孔，所述第一过孔在所述衬底基板正投影位于所述第一子有源材料部在所述衬底基板正投影上，所述第二过孔在所述衬底基板正投影位于所述第二子有源材料部在所述衬底基板正投影上，其中，所述干刻气体在干刻过程中能够产生导体化离子，所述导体化离子能够对所述第二有源材料层实现导体化；
    在所述第二介电层背离所述衬底基板一侧形成第四导电层，所述第四导电层包括第三导电部和第四导电部；
    所述第三导电部通过所述第一过孔连接所述第一子有源材料部，所述第四导电部通过所述第二过孔连接所述第二子有源材料部。
  21. 根据权利要求20所述的显示面板制作方法，其中，所述第一过孔在所述衬底基板正投影的面积小于等于所述第一子有源材料部在所述衬底基板正投影的面积；
    所述第二过孔在所述衬底基板正投影的面积小于等于所述第二子有源材料部在所述衬底基板正投影的面积。
  22. 根据权利要求16所述的显示面板制作方法，其中，所述第一子有源材料部的边沿在所述衬底基板正投影与所述第一导电部在所述衬底基板正投影至少部分重合；
    所述第二子有源材料部的边沿在所述衬底基板正投影与所述第一导电部在所述衬底基板正投影至少部分重合。
  23. 根据权利要求16所述的显示面板制作方法，其中，以所述第三导电层为掩膜对所述第二有源材料层进行导体化处理，包括：
    通过离子注入工艺，向所述第二有源材料层注入导体化离子。
  24. 根据权利要求16所述的显示面板制作方法，其中，所述第三子有源材料部包括第一亚有源材料部、第二亚有源材料部、第三亚有源材料部，所述第一亚有源材料部连接于所述第一子有源材料部和所述第三亚有源材料部之间，所述第二亚有源材料部连接于所述第三亚有源材料部和所述第二子有源材料部之间；
    所述第二导电部在所述衬底基板的正投影覆盖所述第三亚有源材料部在所述衬底基板正投影。
  25. 一种显示装置，其中，包括权利要求1-15任一项所述的显示面板。
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