WO2016161841A1 - 横向扩散金属氧化物半导体场效应管 - Google Patents

横向扩散金属氧化物半导体场效应管 Download PDF

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Publication number
WO2016161841A1
WO2016161841A1 PCT/CN2016/072846 CN2016072846W WO2016161841A1 WO 2016161841 A1 WO2016161841 A1 WO 2016161841A1 CN 2016072846 W CN2016072846 W CN 2016072846W WO 2016161841 A1 WO2016161841 A1 WO 2016161841A1
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Prior art keywords
well
drain
region
plug
effect transistor
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PCT/CN2016/072846
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English (en)
French (fr)
Inventor
祁树坤
张广胜
孙贵鹏
张森
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab1 Co Ltd
CSMC Technologies Fab2 Co Ltd
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Priority to US15/564,172 priority Critical patent/US10014392B2/en
Priority to JP2018503703A priority patent/JP6484754B2/ja
Publication of WO2016161841A1 publication Critical patent/WO2016161841A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/655—Lateral DMOS [LDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

Definitions

  • the present invention relates to semiconductor processes, and more particularly to a laterally diffused metal oxide semiconductor field effect transistor having a RESURF structure.
  • the basic structure using the RESURF (Reduced Surface Electric Field) principle consists of a low doped P-type substrate and a low doped N-type epitaxial layer.
  • a P well is formed on the epitaxial layer and N+, P+ are implanted to form a lateral P-well/N-epi (P-well-N-type epitaxial layer) junction and a longitudinal P-sub/N-epi (P-type substrate).
  • -N type epitaxial layer) junction Due to the higher doping concentration at both ends of the lateral junction, the breakdown voltage is lower than the longitudinal junction.
  • RESURF The basic principle of RESURF is to make the epitaxial layer completely depleted before the lateral junction reaches the critical avalanche breakdown electric field by using the interaction of the lateral junction and the longitudinal junction. By reasonably optimizing the device parameters, the breakdown of the device occurs in the longitudinal junction, thereby Reduce the effect of the surface electric field.
  • a modified RESURF structure is formed by forming a very thin N-type deep well on a substrate or epitaxy, forming a first RESURF between the P-type substrate, and then implanting a P-type under the N-type deep well and under the field oxygen.
  • Floating field limit ring (Floating P-layer, FP), forms the second RESURF between the deep well and the deep well.
  • the RESURF of this structure satisfies certain high voltage and low on-resistance requirements, but the inventors have found that in an AC switch application of several tens of KHz to several hundred KHz, the device of the structure may have a spike current, thereby affecting the device and The reliability of the product, while the on-resistance can not continue to decrease.
  • a laterally diffused metal oxide semiconductor field effect transistor comprising a substrate, a source, a drain, a body region and a well region on the substrate, the well region comprising: a plug-in well, doping type P a type disposed below the drain and connected to the drain and the substrate, the width of the plug-in well being smaller than a width of the drain; and an N-well disposed in the plug-in well a N-well connected to both sides of the drain; and a P-well disposed at a periphery of the N-well and connected to the N-well; the laterally diffused metal-oxide-semiconductor field effect transistor Including a closed P-type field limiting ring disposed in the N-well and located below a lower periphery of the drain; the plug-in well extending in a length direction thereof and the P The type field limiting ring is in contact, and the source and body regions are disposed in the P well.
  • the laterally diffused metal oxide semiconductor field effect transistor, the P-type plug-in well passes outside the drain and the N-well outside the drain, and is connected to the P-type field limiting ring in the drift region to make the P-type field limit ring To the substrate potential, so that the P-type field limiting ring is released from the floating state, ensuring a stable junction capacitance between the P-type field limiting ring and the N-well under the AC high-frequency switching state, which helps to improve the dynamic characteristics of the device. To avoid spike currents. And because the plug-in trap is set, a triple is formed.
  • the RESURF structure helps to increase the doping concentration of the N-well and lower the on-resistance of the device, and helps to improve the breakdown characteristics of the device.
  • FIG. 1 is a schematic structural view of a laterally diffused metal oxide semiconductor field effect transistor in an embodiment
  • Figure 2 is a plan view of the active area shown in Figure 1;
  • Figure 3 is a cross-sectional view taken along line A-A' of Figure 2;
  • Figure 4 is a cross-sectional view taken along line B-B' of Figure 2;
  • Fig. 5 is a schematic view showing the structure of a laterally diffused metal oxide semiconductor field effect transistor in another embodiment.
  • the inventors have conducted experiments and studies that the reason for the peak current of the laterally diffused metal oxide semiconductor field effect transistor of the RESURF structure in which the P-type floating field ring (FP) is set in the background art is that the FP is suspended and cannot be guaranteed.
  • a stable junction capacitance is formed between the P-type floating field limiting ring and the N-type deep well in each switching cycle, so that the minority current of the reverse recovery is superimposed on the on-state current of the next cycle to cause a spike current.
  • a laterally diffused metal oxide semiconductor field effect transistor having a RESURF structure includes a substrate, a source, a drain, a body region, a P-type field limiting ring, and a well region on the substrate.
  • the well region specifically includes an N well, a P well, and a plug-in well inserted into the N well.
  • the plug-in well has a doping type of P-type, is disposed under the drain and is in contact with the drain and the substrate.
  • the N-well is disposed on the periphery of the plug-in well. In order to connect the two sides of the drain to the underlying N-well, the width of the plug-in well should be smaller than the width of the drain.
  • the plug-in well is elongated, its width is short. The length of the side is long and the length is long.
  • the P well is disposed on the periphery of the N well and is connected to the N well, and the source and the body region are disposed in the P well.
  • the P-type field limiting ring is disposed in the N-well and is a closed annular structure.
  • a closed annular structure refers to a closed strip structure connected end to end, including an elliptical ring, a ring, a racetrack ring (ie, a racetrack shape of a track and field field, a shape of a semicircle at each end of the rectangle and a shape obtained by taking the outer ring), Square ring and so on.
  • the P-type field limiting ring is located at the lower periphery of the drain, and surrounds the drain, that is, after the P-type field limiting ring and the N-well are projected on the plane of the drain, the drain, the N-well, and the P-type field limiting ring are three.
  • the relationship in the plane is that the periphery of the drain is covered by the N-well, and the ring formed by the P-type field limiting ring surrounds the drain and intercepts the N-well at the surface of the active region. Since the device structure determines that the plug-in well cannot contact the P-type field limiting ring in the width direction, the plug-in well extends in the length direction to a position in contact with the P-type field limiting ring.
  • LDMOS laterally diffused metal oxide semiconductor field effect transistor
  • RESURF structure in an embodiment, which is a left-right symmetric structure including a substrate 110, a well region on the substrate, a drain 140, and a source.
  • the substrate is P-doped
  • the drain 140 is N-doped
  • the source 150 is N-doped
  • the body region 160 is P-doped.
  • the well region includes a P-type doped plug well 122, an N well 124 as a drift region, and a P well 126 as a channel region.
  • the field oxide region 170 is disposed on the surface of the N-well 124.
  • the two field oxygen regions 170 are sandwiched between the drain electrodes 140.
  • the polysilicon structure 180 is composed of a polysilicon gate and a field portion, and is overlapped from the surface of the field oxide region 170 to the source 150. surface.
  • FIG. 2 is a plan view of the active region in the embodiment shown in FIG. 1, FIG. 3 is a cross-sectional view taken along line A-A' of FIG. 2, and FIG. 4 is along FIG. A cross-sectional view of the middle B-B' line.
  • the P-type field limiting ring 135 is a racetrack-shaped ring structure in which the plug-in well 122 extends in the X-axis direction to the middle of the arc of the runway.
  • the P-type field limiting ring 135 divides the N well 124 into a fingertip structure inside the ring and a square ring structure outside the ring at the surface of the active region.
  • the drain 140 shown in FIG. 2 is a drain-extracted pad (Bonding) The Pad portion is partially obscured by the structure of the active region in FIG.
  • the P-type plug-in well 122 extends from below the drain 140 outward (ie, in the X-axis direction) beyond the drain 140 and the N-well 124, and in the drift region.
  • the P-type field limiting ring 135 is connected such that the P-type field limiting ring 135 has the same potential as the substrate (Psub) (because the plug-in well 122 itself is connected to the substrate 110, so it has the same potential as the substrate 110), thereby The P-type field limiting ring 135 is released from the floating state, ensuring a stable junction capacitance between the P-type field limiting ring 135 and the N-well 124 in the AC high-frequency switching state, which helps to improve the dynamic characteristics of the device and avoid occurrence. Peak current.
  • the N well 124 is split to a certain width, and the plug-in well 122 is inserted to form a triple.
  • the RESURF structure allows the interposer well 122, the N well 124, the P well 126, and the substrate 110 to be depleted from each other, and the breakdown point is transferred into the device body, and the device is longitudinally broken down.
  • the width of the plug-in well 122 is not too wide, and it is necessary to ensure that the two N-wells 124 under the drain 140 are still connected to the drain 140, so that the concentration of the N-well 124 in the drift region is improved compared with the prior art, which helps to guide The reduction in the on resistance. This is because when an extra charge is added to the depletion region, the opposite type of charge density is correspondingly increased to achieve the charge balance requirement.
  • the plug-in well 122 should also not be too narrow. A certain width of the plug-in well 122 can effectively control the occurrence of breakdown in the device body. If the width is too narrow, the plug-in well 122 has less influence on the depletion region of the N-wells 124 on both sides, and the breakdown position is still in the prior art. When the breakdown position of the drift region N well 124 is not set when the plug-in well 122 is not provided, the insertion of the plug-in well 122 does not function to adjust the breakdown.
  • the intervening well 122 and the N well 124 of the drift region on both sides are depleted until the depletion layer formed by the N wells 124 on both sides gradually expands to overlap.
  • the potential lines on both sides are connected, and then depleted from the top to the bottom in the substrate 110, and the electric field peak is weakened, thereby effectively improving the breakdown voltage.
  • drain 140 is N+ drain
  • source 150 is N+ source
  • body region 160 is P+ body region.
  • FIG. 5 is a schematic structural view of a laterally diffused metal oxide semiconductor field effect transistor having a RESURF structure in another embodiment.
  • the laterally diffused metal oxide semiconductor field effect transistor of this embodiment is substantially the same as the structure of the embodiment shown in FIG. 1, except that the well region is composed of a high voltage well for mating with a high voltage device, and a layer for The low voltage device is composed of a low voltage device. That is, the LDMOS includes a substrate 210, a first well region on the substrate and a second well region on the first well region, a drain 240, a source 250, a body region 260, a field oxygen region 270, a polysilicon structure 280, and a P-type. Field limit ring 235.
  • the first well region includes a P-type doped first plug-in well 222, a first N-well 224, and a first P-well 226;
  • the second well region includes a P-type second plug-in well 232, a second N-well 234, and The third P-well 236, the second plug-in well 232, the second N-well 234, and the third P-well 236 are respectively connected to the first plug-in well 222, the first N-well 224, and the first P-well 226;
  • the well 224 and the second N-well 234 collectively function as a drift region.
  • the source 250 and the body region 260 are disposed in the second P well 236.
  • the N-well including the first N-well 224 and the second N-well 234.
  • the N+ between the plug-in wells still has a certain effective width, at least 30% of the active area of the drain 240. Therefore, the width of the first plug-in well 222 and the second plug-in well 232 should not exceed 40% of the width of the active region of the drain 240. In embodiments where the active region is 10 microns wide, the aforementioned effective width is at least 3 microns, i.e., the width of the first plug-in well 222 and the second plug-in well 232 does not exceed 2 microns.
  • drain 240 is N+ drain
  • source 250 is N+ source
  • body region 260 is P+ body region.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种横向扩散金属氧化物半导体场效应管，包括衬底(110)、源极(150)、漏极(140)、体区(160)、P型场限环(135)及衬底(110)上的阱区，阱区包括：插入式阱(122)，掺杂类型为P型，设于漏极的下方并与漏极相接；N阱(124)，设于插入式阱(122)的两侧；P阱(126)，设于N阱(124)的旁边并与N阱(124)连接；P型场限环(135)设于N阱(124)内，为封闭的环状结构，且位于漏极(140)的下方外围；插入式阱(122)在其长度方向上延伸至与所述P型场限环(135)相接触的位置，源极(150)和体区(160)设于所述P阱(126)内。

Description

横向扩散金属氧化物半导体场效应管
【技术领域】
本发明涉及半导体工艺，特别是涉及一种具RESURF结构的横向扩散金属氧化物半导体场效应管。
【背景技术】
采用RESURF（降低表面电场）原理的基本结构由低掺杂的P型衬底和低掺杂的N型外延层组成。在外延层上形成P阱并注入N+、P+，形成一个横向的P-well/N-epi（P阱-N型外延层）结和一个纵向的P-sub/N-epi（P型衬底-N型外延层）结。由于横向结两端有着更高的掺杂浓度，因此击穿电压比纵向结更低。RESURF的基本原理是利用横向结和纵向结的相互作用，使外延层在横向结达到临界雪崩击穿电场前完全耗尽，通过合理优化器件参数使得器件的击穿发生在纵向结，从而起到降低表面电场的作用。
一种改进型RESURF结构是在衬底或外延上形成很淡的N型深阱，形成与P型衬底间的第一次RESURF，之后在N型深阱内部、场氧下方注入形成P型浮空场限环（Floating P-layer, FP），形成与深阱间的第二次RESURF。
这种结构的RESURF满足一定的高压、低导通电阻的要求，但发明人发现，在几十KHz~几百KHz的交流开关应用中，该结构的器件会出现尖峰电流，从而影响了器件及产品的可靠性，同时导通电阻也不能继续降低。
【发明内容】
基于此，有必要提供一种在很高的频率下仍能保证稳定性的横向扩散金属氧化物半导体场效应管。
一种横向扩散金属氧化物半导体场效应管，包括衬底、源极、漏极、体区及位于所述衬底上的阱区，所述阱区包括：插入式阱，掺杂类型为P型，设于所述漏极的下方并与所述漏极和所述衬底相接，所述插入式阱的宽度小于所述漏极的宽度；N阱，设于所述插入式阱的外围，所述N阱与所述漏极的两侧相接；及P阱，设于所述N阱的外围并与所述N阱相接；所述横向扩散金属氧化物半导体场效应管还包括封闭的P型场限环，所述P型场限环设于所述N阱内，且位于所述漏极的下方外围；所述插入式阱在其长度方向上延伸并与所述P型场限环相接触，所述源极和体区设于所述P阱内。上述横向扩散金属氧化物半导体场效应管，P型的插入式阱在漏极下方向外渡过漏极和N阱，与漂移区中的P型场限环相连，使P型场限环接到衬底电位，从而使得P型场限环解除了悬空的状态，确保交流高频开关状态下P型场限环与N阱之间能保持稳定的结电容，有助于改善器件的动态特性，避免出现尖峰电流。且由于设置了插入式阱，形成了triple RESURF结构，有助于提高N阱的掺杂浓度，并降低器件的导通电阻，并且有助于改善器件的击穿特性。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一实施例中横向扩散金属氧化物半导体场效应管的结构示意图；
图2是图1所示有源区的俯视图；
图3是沿图2 中A-A’线的剖视图；
图4是沿图2 中B-B’线的剖视图；
图5是另一实施例中横向扩散金属氧化物半导体场效应管的结构示意图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
发明人经试验和研究认为，背景技术中所述设置了P型浮空场限环（FP）的RESURF结构横向扩散金属氧化物半导体场效应管出现尖峰电流的原因是，由于FP悬空，无法保证每一个开关周期内P型浮空场限环和N型深阱之间形成稳定的结电容，以至于反向恢复的少子电流叠加到下一个周期的开态电流中而出现尖峰电流。
一实施例的具RESURF结构的横向扩散金属氧化物半导体场效应管，包括衬底、源极、漏极、体区、P型场限环及衬底上的阱区。阱区具体包括N阱、P阱及插入N阱中的插入式阱。其中插入式阱的掺杂类型为P型，设于漏极的下方并与漏极和衬底相接。N阱设于插入式阱的外围，为了使漏极的两侧与下方的N阱相接，插入式阱的宽度应小于漏极的宽度，由于插入式阱为长条形，其宽度指短边边长，长度指长边边长。P阱设于N阱的外围并与N阱相接，源极和体区设于所述P阱内。P型场限环设于N阱内，为封闭的环状结构。封闭的环状结构指首尾相连的封闭条状结构，包括椭圆环、圆环、跑道形环（即田径场的跑道形状，矩形的两端各连接一个半圆然后取其外圈得到的形状）、方形环等。且P型场限环位于漏极的下方外围，将漏极包围，也就是将P型场限环和N阱投影于漏极所在平面后，漏极、N阱、P型场限环三者在平面上的关系为：漏极的外围被N阱包覆，P型场限环形成的环将漏极包围并在有源区表面将N阱截断。由于器件结构决定了插入式阱在宽度方向上无法与P型场限环相接触，因此将插入式阱在长度方向上延伸至与P型场限环相接触的位置。
图1是一实施例中具RESURF结构的横向扩散金属氧化物半导体场效应管（LDMOS）的结构示意图，其为左右对称结构，包括衬底110，衬底上的阱区，漏极140，源极150，体区160，场氧区170、多晶硅结构180以及P型场限环135。其中，衬底为P型掺杂，漏极140为N型掺杂，源极150为N型掺杂，体区160为P型掺杂。阱区包括P型掺杂的插入式阱122、作为漂移区的N阱124以及作为沟道区的P阱126。场氧区170设于N阱124表面，两块场氧区170结构将漏极140夹于中间，多晶硅结构180由多晶硅栅和搭场部分组成，从场氧区170表面搭接至源极150表面。
请参照图2~图4，图2是图1所示实施例中有源区的俯视图，图3是沿图2 中A-A’线的剖视图，图4是沿图2 中B-B’线的剖视图。如图2所示，在该实施例中，P型场限环135为跑道形环装结构，插入式阱122在X轴方向延伸至跑道的圆弧中部与其相接。P型场限环135在有源区表面将N阱124分隔成环内侧的指尖结构和环外侧的方形环结构。图2所示的漏极140为漏极引出的焊盘（Bonding Pad）部分，在图2中其中间被有源区的结构所遮挡。
上述具RESURF结构的横向扩散金属氧化物半导体场效应管，P型的插入式阱122从漏极140下方向外（即X轴方向）延伸至超出漏极140和N阱124，与漂移区中的P型场限环135相连，使P型场限环135与衬底（Psub）的电位相同（因为插入式阱122本身就接至衬底110，所以其与衬底110电位相同），从而使得P型场限环135解除了悬空的状态，确保交流高频开关状态下P型场限环135与N阱124之间能保持稳定的结电容，有助于改善器件的动态特性，避免出现尖峰电流。
如图1所示，在漏端N+结下方，通过将N阱124裂开一定宽度，插入插入式阱122，形成triple RESURF结构，使得插入式阱122、N阱124、P阱126及衬底110之间相互耗尽，击穿点向器件体内转移，器件得以纵向击穿。
插入式阱122的宽度不能太宽，需要保证漏极140下方的两侧N阱124仍然与漏极140相接，这样漂移区的N阱124浓度相较现有技术得以提高，有助于导通电阻的降低。这是因为当耗尽区中加入额外的电荷后，相反类型的电荷密度也会相应提高，以达到电荷平衡的要求。
插入式阱122同样不能太窄。一定宽度的插入式阱122可以有效控制器件体内击穿发生的先后，如宽度过窄，插入式阱122对两侧N阱124的耗尽区影响较小，击穿位置仍与现有技术中漂移区N阱124不设置插入式阱122时的击穿位置接近，那么插入式阱122的插入就起不到对于击穿的调整作用了。
当漏极140外接较高电位，耗尽至漏极140时，插入式阱122与两侧漂移区的N阱124相互耗尽，直至两侧N阱124形成的耗尽层逐渐扩大至交叠于P阱126中，两侧电势线相接，之后由上而下向衬底110中耗尽，电场峰值被削弱，进而有效改善击穿电压。
在图1所示实施例中，漏极140为N+漏极，源极150为N+源极，体区160为P+体区。
图5是另一实施例中具RESURF结构的横向扩散金属氧化物半导体场效应管的结构示意图。本实施例的横向扩散金属氧化物半导体场效应管与图1所示实施例的结构大致相同，其区别在于，阱区由一层用于与高压器件配合的高压阱、和一层用于与低压器件配合的低压阱组成。即LDMOS包括衬底210，衬底上的第一阱区和第一阱区上的第二阱区，漏极240，源极250，体区260，场氧区270、多晶硅结构280以及P型场限环235。第一阱区包括P型掺杂的第一插入式阱222、第一N阱224以及第一P阱226；第二阱区包括P型的第二插入式阱232、第二N阱234以及第三P阱236，第二插入式阱232、第二N阱234以及第三P阱236分别与第一插入式阱222、第一N阱224以及第一P阱226相接；第一N阱224和第二N阱234共同作为漂移区。其中源极250和体区260设于第二P阱236内。
为了确保漂移区耗尽至漏极240的有源区（DTO）时，仍有较高浓度的N型杂质，必须保证此时N阱（包括第一N阱224和第二N阱234）与插入式阱（包括第一插入式阱222和第二插入式阱232）间的N+的仍有一定的有效宽度，至少为漏极240的有源区的30%。因此，第一插入式阱222和第二插入式阱232的宽度不应超过漏极240的有源区宽度的40%。在有源区宽10微米的实施例中，前述有效宽度至少为3微米，即第一插入式阱222和第二插入式阱232的宽度不超过2微米。
在图2所示实施例中，漏极240为N+漏极，源极250为N+源极，体区260为P+体区。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (7)

  1. 一种横向扩散金属氧化物半导体场效应管，包括衬底、源极、漏极、体区及位于所述衬底上的阱区，其特征在于，所述阱区包括：
    插入式阱，掺杂类型为P型，设于所述漏极的下方并与所述漏极和所述衬底相接，所述插入式阱的宽度小于所述漏极的宽度；
    N阱，设于所述插入式阱的外围，所述N阱与所述漏极的两侧相接；及
    P阱，设于所述N阱的外围并与所述N阱相接；
    所述横向扩散金属氧化物半导体场效应管还包括封闭的P型场限环，所述P型场限环设于所述N阱内，且位于所述漏极的下方外围；所述插入式阱在其长度方向上延伸，并与所述P型场限环相接触，所述源极和所述体区设于所述P阱内。
  2. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述阱区包括位于所述衬底上的第一阱区和位于所述第一阱区上的第二阱区，所述插入式阱包括位于所述第一阱区内的第一插入式阱和位于所述第二阱区内的第二插入式阱，所述N阱包括位于所述第一阱区内的第一N阱和位于所述第二阱区内的第二N阱，所述P阱包括位于所述第一阱区内的第一P阱和位于所述第二阱区内的第二P阱。
  3. 根据权利要求2所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述第一N阱的掺杂浓度低于所述第二N阱的掺杂浓度，所述第一P阱的掺杂浓度低于所述第二P阱的掺杂浓度，所述第一插入式阱的掺杂浓度低于所述第二插入式阱的掺杂浓度。
  4. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，其还包括两个场氧区和多晶硅结构，所述两个场氧区设于所述N阱表面并将所述漏极夹于中间，所述多晶硅结构从所述两个场氧区表面搭接至所述源极表面。
  5. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述插入式阱的宽度不超过所述漏极的有源区宽度的40%。
  6. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述阱区的掺杂浓度低于所述漏极的掺杂浓度。
  7. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述衬底为P掺杂衬底，所述漏极为N掺杂漏极，所述源极为N掺杂源极，所述体区为P掺杂体区。
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