WO2017092419A1 - 横向扩散金属氧化物半导体场效应管 - Google Patents

横向扩散金属氧化物半导体场效应管 Download PDF

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Publication number
WO2017092419A1
WO2017092419A1 PCT/CN2016/096730 CN2016096730W WO2017092419A1 WO 2017092419 A1 WO2017092419 A1 WO 2017092419A1 CN 2016096730 W CN2016096730 W CN 2016096730W WO 2017092419 A1 WO2017092419 A1 WO 2017092419A1
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gate
oxide semiconductor
effect transistor
metal oxide
field effect
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PCT/CN2016/096730
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English (en)
French (fr)
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祁树坤
孙贵鹏
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无锡华润上华半导体有限公司
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Application filed by 无锡华润上华半导体有限公司 filed Critical 无锡华润上华半导体有限公司
Priority to KR1020187017322A priority Critical patent/KR102144625B1/ko
Priority to US15/779,666 priority patent/US10505036B2/en
Priority to EP16869730.8A priority patent/EP3385993B1/en
Priority to JP2018527941A priority patent/JP6615348B2/ja
Publication of WO2017092419A1 publication Critical patent/WO2017092419A1/zh

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Definitions

  • This invention relates to semiconductor processes, and more particularly to a laterally diffused metal oxide semiconductor field effect transistor having a RESURF structure.
  • the basic structure using the RESURF (Reduced Surface Electric Field) principle consists of a low doped P-type substrate and a low doped N-type epitaxial layer. A P well is formed on the epitaxial layer and N+, P+ are implanted to form a lateral P-well/N-epi junction and a longitudinal P-sub/N-epi junction. Due to the higher doping concentration at both ends of the lateral junction, the breakdown voltage is lower than the longitudinal junction.
  • the basic principle of RESURF is to make the epitaxial layer completely depleted before the lateral junction reaches the critical avalanche breakdown electric field by using the interaction of the lateral junction and the longitudinal junction. By reasonably optimizing the device parameters, the breakdown of the device occurs in the longitudinal junction, thereby Reduce the effect of the surface electric field.
  • the laterally diffused metal oxide semiconductor field effect transistor (LDMOSFET) of the conventional RESURF structure needs to improve the on-resistance Rsp mainly by adjusting the impurity concentration of the drift region while satisfying the RESURF requirement.
  • the doping concentration and the off-state breakdown are inversely related, improving the on-resistance only by improving the drift region resistance Rdr has its limitations.
  • a laterally diffused metal oxide semiconductor field effect transistor comprising a substrate, a gate, a source, a drain, a body region, a field oxygen region between the source and the drain, and first and second regions on the substrate a well region, wherein the first well region is of a first conductivity type, the second well region is of a second conductivity type, the first conductivity type and the second conductivity type are opposite conductivity types, and the source and body regions are disposed on the In the second well region, the drain is disposed in the first well region; and the second well region under the gate is provided with a plurality of gate doping regions of a first conductivity type, the gate
  • the polysilicon gate is a multi-segment structure, and the segments are separated from each other.
  • Each gate doped region is disposed under the gap between the polysilicon gates of each segment, and each gate doped region is separated from two segments on both sides thereof.
  • a polysilicon gate in the polysilicon gate close to the source direction is electrically connected (either directly or through a metal wiring layer) such that the potential of each gate doping region is equal to the gate.
  • the number of channel electrons increases, and electrons are accelerated multiple times during the process from the source to the drain, which is equivalent to increasing the channel electric field and the channel current, and thus the channel
  • the resistance is reduced, which reduces the on-resistance.
  • the concentration of the drift region can be further reduced, thereby improving the withstand voltage (breakdown voltage) of the device, or under the premise of maintaining the withstand voltage.
  • the length of the drift zone is further shortened, thereby reducing costs.
  • FIG. 1 is a schematic structural view of a laterally diffused metal oxide semiconductor field effect transistor in an embodiment
  • FIG. 2 is a top plan view showing a laterally diffused metal oxide semiconductor field effect transistor of FIG. 1.
  • the vocabulary of the semiconductor field used herein is a technical vocabulary commonly used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish the doping concentration, the simple P+ type represents a heavily doped concentration of the P-type, and the P-type represents P type with doping concentration, P-type represents P type with light doping concentration, N+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents light doping concentration N type.
  • FIG. 1 is a schematic view showing the structure of a laterally diffused metal oxide semiconductor field effect transistor including a P-type substrate 110, an N well 122, a P well 124, an N+ source 150 and a P+ body region 160 in the P well 124.
  • the polysilicon gate 182 has a multi-segment structure.
  • a polysilicon gate 182 closest to the drain 140 extends to the field oxide region 170 as a polycrystalline field plate; a portion of the polysilicon gate 182 closest to the source 150 extends to the source 150 at one end.
  • the first conductivity type is N-type
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type.
  • the LDMOSFET further includes a metal wiring layer.
  • metal electrodes are disposed in the gaps between the polysilicon gates 182 above the respective gate doping regions 184 to form metal wiring layers, and each gate doping region 184 is through a metal.
  • a wiring layer (not shown in FIG. 1) is connected to a section of polysilicon gate 182 on the left side thereof to ensure that the sub-channels formed by each of the polysilicon gates 182 operate in a saturation region to provide high carrier mobility under high electric fields.
  • the LDMOSFET is provided with 3 to 5 sets of gate doping regions 184 in the source and drain wiring directions. In the embodiment shown in FIG. 1, four sets of gate doped regions 184 are provided.
  • each set of gate doped regions 184 includes a plurality, and each of the gate doped regions 184 is arranged in a direction perpendicular to the direction of the channel current between the source 150 and the drain 140.
  • FIG 2. 2 is a top view, in which the direction of the channel current between the source 150 and the drain 140 (ie, the direction in which the source 150 and the drain 140 are connected) is the X-axis, and the height direction of the device is the Z-axis to establish a spatial rectangular coordinate system.
  • the gate doping region 184 is provided not only in the X-axis direction but also in the Y-axis direction (or in the XY plane at a certain angle from the Y-axis).
  • This design is more in a piecewise (ie, single) gate doped region structure, which helps to achieve charge balance between the P well 124 and the gate doped region 184, while increasing the redundancy of the implantation process, resulting in a small range.
  • the injection dose deviation does not cause a large pressure fluctuation.
  • the structure also ensures a maximum current path and reduces the on-resistance of the P-well 124, while these gate doped regions 184 can assist in depleting the P-well 124, increasing the device withstand voltage.
  • the gate doping regions 184 adjacent in the wiring direction of the source 150 and the drain 140 have a pitch of not more than 0.8 ⁇ m. In this way, the gate doping regions 184 are not connected together during manufacture, and a better on-resistance effect can be obtained. Accordingly, the width of each of the gate doped regions 184 (i.e., the dimension in the direction in which the source 150 and the drain 140 are connected) is from 1 micrometer to 2.5 micrometers.
  • the gate doping region 184 has an implantation dose of 0.8E13/cm2 to 1.5E13/cm2, a junction depth of about 0.8 micrometers, and a peak concentration of 1.0E13/cm2 to 2.0E17/cm3. Under the above conditions, the minimum breakdown voltage that the device can achieve is approximately 600V.
  • the number of channel electrons of the above LDMOSFET is increased, and electrons are accelerated multiple times during the process from the source to the drain, which is equivalent to an increase in the channel electric field and the channel current, so that the channel resistance is lowered. , thereby reducing the on-resistance.
  • the reduction of the channel resistance helps to improve the optimization space of the drift region, and the concentration of the drift region can be further reduced, thereby improving the withstand voltage (breakdown voltage) of the device, or further maintaining the withstand voltage. Reduce the length of the drift zone to reduce device cost.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种横向扩散金属氧化物半导体场效应管，包括衬底（110），栅极，源极（150），漏极（140），体区（160），源极（150）和漏极（140）之间的场氧区（170），以及衬底（110）上的第一阱区（122）、第二阱区（124），所述栅极下方的第二阱区（124）内设有多个栅极掺杂区（184），所述栅极的多晶硅栅（182）为多段式结构，各段之间相互分离，各个所述栅极掺杂区（184）设于各段多晶硅栅（182）之间的空隙下方，每个所述栅极掺杂区（184）均与其两侧的两段多晶硅栅（182）中靠源极（150）方向的一段电性连接。

Description

横向扩散金属氧化物半导体场效应管
【技术领域】
本发明涉及半导体工艺，特别是涉及一种具有RESURF结构的横向扩散金属氧化物半导体场效应管。
【背景技术】
采用RESURF（降低表面电场）原理的基本结构由低掺杂的P型衬底和低掺杂的N型外延层组成。在外延层上形成P阱并注入N+、P+，形成一个横向的P-well/N-epi结和一个纵向的P-sub/N-epi结。由于横向结两端有着更高的掺杂浓度，因此击穿电压比纵向结更低。RESURF的基本原理是利用横向结和纵向结的相互作用，使外延层在横向结达到临界雪崩击穿电场前完全耗尽，通过合理优化器件参数使得器件的击穿发生在纵向结，从而起到降低表面电场的作用。
传统RESURF结构的横向扩散金属氧化物半导体场效应管（LDMOSFET）要改善导通电阻Rsp，主要通过调整漂移区的杂质浓度，同时满足RESURF要求。但由于掺杂浓度与关态击穿是呈现反比关系，仅通过改善漂移区电阻Rdr来改善导通电阻有其局限性。
【发明内容】
基于此，有必要提供一种导通电阻较低的横向扩散金属氧化物半导体场效应管。
一种横向扩散金属氧化物半导体场效应管，包括衬底，栅极，源极，漏极，体区，源极和漏极之间的场氧区，以及衬底上的第一、第二阱区，其中第一阱区为第一导电类型，第二阱区为第二导电类型，第一导电类型和第二导电类型为相反的导电类型，所述源极和体区设于所述第二阱区内，所述漏极设于所述第一阱区内；所述栅极下方的第二阱区内设有多个第一导电类型的栅极掺杂区，所述栅极的多晶硅栅为多段式结构，各段之间相互分离，每一栅极掺杂区设于各段多晶硅栅之间的空隙下方，每一栅极掺杂区均与位于其两侧的两段多晶硅栅中靠近源极方向的一段多晶硅栅电性连接（可以是直接接触，也可以通过金属连线层连接），使得各栅极掺杂区的电位均与栅极相等。
上述横向扩散金属氧化物半导体场效应管，沟道电子的数量增加，且电子在从源极流向漏极的过程中被多次加速，相当于提高了沟道电场和沟道电流，因此沟道电阻得到降低，从而降低了导通电阻。同时，由于沟道电阻的降低有助于提高漂移区的优化空间，漂移区的浓度可以进一步降低，从而改善了器件的耐压（击穿电压），或者可以在保持耐压不变的前提下进一步缩短漂移区长度，从而降低成本。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1是一实施例中横向扩散金属氧化物半导体场效应管的结构示意图；
图2是图1所示横向扩散金属氧化物半导体场效应管的俯视角度局部示意图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
图1是一实施例中横向扩散金属氧化物半导体场效应管的结构示意图，包括P型的衬底110，N阱122，P阱124，P阱124内的N+源极150和P+体区160，N阱122内的N+漏极140，P阱124内的栅极掺杂区184，源极150和漏极140之间的场氧区170。多晶硅栅182为多段式结构，最靠近漏极140的一段多晶硅栅182延伸至场氧区170上，作为多晶场板；最靠近源极150的一段多晶硅栅182一端延伸至源极150上。在本实施例中第一导电类型为N型，第二导电类型为P型；在其他实施例中也可以是第一导电类型为P型，第二导电类型为N型。
上述横向扩散金属氧化物半导体场效应管，在开态时，电子由源极150注入进栅极下方的沟道中（图1中最左边的一段多晶硅栅182下方的子沟道），由于栅极和源极150之间的电位差，形成高电场加速沟道电子，使之进入图1中最左边的一个栅极掺杂区184。之后电子继续向漏极140运动，进入第二个子沟道（图1中左起第二段多晶硅栅182下方的沟道），同样被该沟道右侧的栅极掺杂区184加速。以此类推，电子在从源极150向漏极130运动的过程中，在相邻的两个栅极掺杂区184间被连续加速。
在其中一个实施例中，LDMOSFET还包括金属连线层。在图1所示实施例中，各个栅极掺杂区184上方、各段多晶硅栅182之间的空隙中设有金属电极以形成金属连线层，每个栅极掺杂区184是通过金属连线层（图1中未示）连接其左边的一段多晶硅栅182，确保每段多晶硅栅182形成的子沟道均工作在饱和区，以提供高电场下的高载流子迁移率。
设置较多的栅极掺杂区184有助于进一步降低导通电阻。但可以理解的，在器件宽度一定的条件下，在宽度方向上设置越多的栅极掺杂区184，意味着各栅极掺杂区184的宽度和间距就越小，那么在制造精度不够高的情况下，就可能导致在设计上相互分离的掺杂区184在制造时成片地连通在一起，这样会失去RESURF的作用，对器件的击穿电压BV有不利影响。因此，在其中一个实施例中，LDMOSFET在源极和漏极连线方向上设置有3~5组栅极掺杂区184。在图1所示实施例中，设置有4组栅极掺杂区184。
在其中一个实施例中，每组栅极掺杂区184包括多个，每组中各栅极掺杂区184的排列方向为垂直于源极150和漏极140之间的沟道电流方向，参见图2。图2为俯视图，以源极150和漏极140之间的沟道电流方向（即源极150和漏极140的连线方向）为X轴，器件的高度方向为Z轴建立空间直角坐标系，则栅极掺杂区184不仅在X轴方向上设置多个，在Y轴方向上（或者XY平面上与Y轴呈一定角度的方向上）也设置多个。这种设计较成片的（即单个）栅极掺杂区结构，更有助于实现P阱124和栅极掺杂区184的电荷平衡，同时可以提高注入工艺的冗余，使得小范围的注入剂量偏差不会引起较大的耐压波动。该结构还可以保证最大限度的电流路径，降低P阱124的导通电阻，同时这些栅极掺杂区184可以辅助耗尽P阱124，提高器件耐压。
在其中一个实施例中，在源极150和漏极140连线方向上相邻的栅极掺杂区184的间距不大于0.8微米。这样既使得栅极掺杂区184在制造时不会连通在一起，也能获得较好的降低导通电阻效果。相应地，每个栅极掺杂区184的宽度（即源极150和漏极140的连线方向上的尺寸）为1微米~2.5微米。
在其中一个实施例中，栅极掺杂区184的注入剂量为0.8E13/cm²~1.5E13/cm²，结深为0.8微米左右，峰值浓度为1.0E13/cm²~2.0E17/cm³。在上述条件下，器件能达到的最小击穿电压大约为600V。
相比于传统结构，上述LDMOSFET沟道电子的数量增加，且电子在从源极流向漏极的过程中被多次加速，相当于提高了沟道电场和沟道电流，因此沟道电阻得到降低，从而降低了导通电阻。同时，沟道电阻的降低有助于提高漂移区的优化空间，漂移区的浓度可以进一步降低，从而改善了器件的耐压（击穿电压），或者可以在保持耐压不变的前提下进一步缩短漂移区长度，从而降低器件成本。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种横向扩散金属氧化物半导体场效应管，包括衬底，栅极，源极，漏极，体区，源极和漏极之间的场氧区，以及衬底上的第一、第二阱区，其中第一阱区为第一导电类型，第二阱区为第二导电类型，第一导电类型和第二导电类型为相反的导电类型，所述源极和体区设于所述第二阱区内，所述漏极设于所述第一阱区内；所述栅极下方的第二阱区内设有多个第一导电类型的栅极掺杂区，所述栅极的多晶硅栅为多段式结构，各段之间相互分离，每一栅极掺杂区设于各段多晶硅栅之间的空隙下方，每一栅极掺杂区均与位于其两侧的两段多晶硅栅中靠近源极方向的一段多晶硅栅电性连接。
  2. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述栅极中的一段多晶硅栅延伸至所述场氧区上。
  3. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，还包括金属连线层，每一栅极掺杂区是通过所述金属连线层与多晶硅栅电性连接。
  4. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，各相邻的两段多晶硅栅在垂直于源极和漏极之间的沟道电流的方向上也设置有多个栅极掺杂区。
  5. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，在源极和漏极之间的沟道电流的方向上相邻的栅极掺杂区的间距不大于0.8微米。
  6. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，在源极和漏极之间的沟道电流的方向上设置有3~5组所述栅极掺杂区，每组包括至少一个栅极掺杂区。
  7. 根据权利要求6所述的横向扩散金属氧化物半导体场效应管，其特征在于，每组栅极掺杂区包括多个，每组中的每一栅极掺杂区的排列方向为垂直于源极和漏极之间的沟道电流的方向。
  8. 根据权利要求6所述的横向扩散金属氧化物半导体场效应管，其特征在于，每一栅极掺杂区的宽度为1微米~2.5微米。
  9. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，每一栅极掺杂区峰值浓度为1.0 E17/cm³~2.0E17/cm³。
  10. 根据权利要求9所述的横向扩散金属氧化物半导体场效应管，其特征在于，每一栅极掺杂区的注入剂量为0.8E13/cm²~1.5E13/cm²。
  11. 根据权利要求9所述的横向扩散金属氧化物半导体场效应管，其特征在于，每一栅极掺杂区的结深为0.8微米。
  12. 根据权利要求1所述的横向扩散金属氧化物半导体场效应管，其特征在于，所述第一导电类型为N型，所述第二导电类型为P型。
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