CN106571370B - 基于soi工艺的介质电容 - Google Patents

基于soi工艺的介质电容 Download PDF

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CN106571370B
CN106571370B CN201510648134.9A CN201510648134A CN106571370B CN 106571370 B CN106571370 B CN 106571370B CN 201510648134 A CN201510648134 A CN 201510648134A CN 106571370 B CN106571370 B CN 106571370B
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dielectric capacitor
isolation structure
trench isolation
silicon
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刘新新
何小东
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CSMC Technologies Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations

Abstract

本发明涉及一种基于SOI工艺的介质电容，从底部到顶部顺次包括：底层硅；形成于所述底层硅表面的埋氧化层；形成于所述埋氧化层表面的顶层硅；形成于所述顶层硅表面的层间介质层；顺次形成于所述层间介质层上的下极板、绝缘层和上极板；所述下极板、绝缘层和所述上极板构成所述介质电容的主体部分；所述介质电容还包括：形成于所述顶层硅上用于隔离有源区的浅沟槽隔离结构；形成于所述下极板下方且贯穿所述顶层硅从而与所述埋氧化层相连的深槽隔离结构。上述基于SOI工艺的介质电容能够有效降低介质电容的寄生电容效应。

Description

基于SOI工艺的介质电容
技术领域
本发明涉及半导体技术领域，特别是涉及一种基于SOI工艺的介质电容。
背景技术
在半导体制备中，基于SOI(Silicon-On-Insulator，绝缘衬底上的硅)工艺的介质电容广泛应用于模拟射频电路中。传统的基于SOI工艺的介质电容的上极板、下极板与衬底都存在寄生的电容。该寄生电容会对电路设计带来一些未知的影响，从而使得电路性能达不到预期要求。
发明内容
基于此，有必要提供一种可以降低寄生电容效应的基于SOI工艺的介质电容。
一种基于SOI工艺的介质电容，从底部到顶部顺次包括：底层硅；形成于所述底层硅表面的埋氧化层；形成于所述埋氧化层表面的顶层硅；形成于所述顶层硅表面的层间介质层；顺次形成于所述层间介质层上的下极板、绝缘层和上极板；所述下极板、绝缘层和所述上极板构成所述介质电容的主体部分；所述介质电容还包括：形成于所述顶层硅上用于隔离有源区的浅沟槽隔离结构；形成于所述下极板下方且贯穿所述顶层硅从而与所述埋氧化层相连的深槽隔离结构。
在其中一个实施例中，所述深槽隔离结构为多个且间隔分布于所述下极板下方的顶层硅中。
在其中一个实施例中，所述深槽隔离结构的槽宽为0.5微米-0.7微米。
在其中一个实施例中，所述深槽隔离结构的槽宽为0.6微米。
在其中一个实施例中，所述深槽隔离结构之间的间距为1微米-2微米。
在其中一个实施例中，所述深槽隔离结构在所述顶层硅中的分布区域大于所述下极板覆盖所述顶层硅的区域。
在其中一个实施例中，部分所述浅沟槽隔离结构位于所述下极板下方；位于所述下极板下方的深沟槽隔离结构分别与所述浅沟槽隔离结构、所述埋氧化层相连。
在其中一个实施例中，所述浅槽隔离结构和所述深槽隔离结构的材质均为硅的氧化物。
在其中一个实施例中，所述上极板和下极板的材质均为多晶硅或者金属。
在其中一个实施例中，还包括衬底引出区；所述衬底引出区形成于所述顶层硅上且位于所述介质电容的主体部分的四周；所述层间介质层中还形成有位于所述衬底引出区上方的金属接触孔；所述衬底引出区通过所述金属接触孔与外部电路连接。
上述基于SOI工艺的介质电容在极板下方形成有与埋氧化层相连的深槽隔离结构，实现器件的良好隔离，减少了极板与顶层硅(介质电容的衬底)之间的电荷交换，使得极板与衬底之间的电荷交换变得非常困难，从而降低了介质电容的极板与衬底之间的寄生电容。
附图说明
图1为一实施例中的基于SOI工艺的寄生电容的剖面示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
图1为一实施例中的基于SOI工艺的介质电容的剖面示意图，该基于SOI工艺的介质电容的极板与衬底之间的寄生电容较小。参见图1，该基于SOI工艺的介质电容，包括底层硅102、埋氧化层104、顶层硅106、层间介质层108、下极板110、绝缘层112、上极板114、浅沟槽隔离结构116、深沟槽隔离结构118以及衬底引出区120。
介质电容从底部到顶部顺次为顶层硅102、埋氧化层104、顶层硅106、层间介质层108、下极板110、绝缘层112以及上极板114。底层硅(Sub)102，其材质可以为硅、碳化硅、砷化镓、磷化铟等等。埋氧化层(BOX)104和顶层硅(Bulk)106依次形成于底层硅102的表面，从而形成SOI结构。在本实施例中，顶层硅106作为介质电容的衬底，后文中所提及的衬底均指顶层硅106。层间介质层(Interlayer Dielectric，ILD)108形成于顶层硅106的表面。层间介质层108也可以称为绝缘层，用于实现下极板110与顶层硅106之间的隔离。层间介质层108的材质为硅的氮化物，如氮化硅。下极板110、绝缘层112和上极板114依次形成于层间介质层108的表面，并构成介质电容的主体部分。其中，上极板114和下极板110均可以为金属或者多晶硅。即，形成的介质电容可以为PIP(多晶硅-绝缘层-多晶硅)电容、MIM(金属-绝缘层-金属)电容或者金属-绝缘层-多晶硅电容。本实施例中的基于SOI工艺的介质电容以MIM电容为例。浅沟槽隔离结构(STI)116形成于顶层硅106上，用于隔离有源区。
深槽隔离结构(Trench)118形成于下极板110下方且贯穿顶层硅106与埋氧化层104相连。深槽隔离结构118中填充的介质为硅的氧化物，从而使得上极板114、下极板110与衬底之间的电荷交换需要经过一层层氧化层，提高了电荷交换的难度，从而降低了极板与衬底之间的寄生电容，使得得到的介质电容的性能满足电路设计的需求。在本实施例中，深槽隔离结构118在顶层硅106的分布区域面积大于下极板110覆盖的顶层硅106的区域。从而能够充分阻挡极板与衬底之间的电荷交换，降低寄生电容效应。深槽隔离结构118设置有多个且间隔设置于下极板110下方的顶层硅106中。深槽隔离结构118的槽宽以及槽与槽之间的间距可以根据不同的工艺设计规则来设置。以本实施例中的0.18微米的SOI结构为例，槽宽宜在0.5-0.7微米之间，槽间距则应该在1微米-2微米之间。在一实施例中，槽宽可以为0.6微米，槽间距为1微米，从而使得深槽隔离结构118尽可能地密集分布于下极板106的下方，以增加极板与衬底之间电荷交换的难度。在本实施例中，部分浅沟槽隔离结构116位于下极板110下方，因此，位于下极板110下方的深沟槽隔离结构118分别与浅沟槽隔离结构116以及埋氧化层104相连。在本实施例中，浅沟槽隔离结构116和深沟槽隔离结构118以及埋氧化层104的材质均为氮的氧化物。衬底引出区(Bulk引出)120形成于顶层硅106上且位于介质电容的主体部分的四周。衬底引出区120通过形成于层间介质层108中的金属接触孔122与外部电路连接，用于引出衬底电位，以对衬底电位进行控制。
上述基于SOI工艺的介质电容在极板下方形成有与埋氧化层104相连的深槽隔离结构118，实现器件的良好隔离，减少了极板与衬底之间的电荷交换，使得极板与衬底之间的电荷交换变得非常困难，从而降低了介质电容的极板与衬底之间的寄生电容。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

1.一种基于SOI工艺的介质电容，其特征在于，从底部到顶部顺次包括：
底层硅；
形成于所述底层硅表面的埋氧化层；
形成于所述埋氧化层表面的顶层硅；
形成于所述顶层硅表面的层间介质层；
顺次形成于所述层间介质层上的下极板、绝缘层和上极板；所述下极板、绝缘层和所述上极板构成所述介质电容的主体部分；
所述介质电容还包括：
形成于所述顶层硅上用于隔离有源区的浅沟槽隔离结构；
形成于所述下极板下方且贯穿所述顶层硅从而与所述埋氧化层相连的深槽隔离结构。
2.根据权利要求1所述的基于SOI工艺的介质电容，其特征在于，所述深槽隔离结构为多个且间隔分布于所述下极板下方的顶层硅中。
3.根据权利要求2所述的基于SOI工艺的介质电容，其特征在于，所述深槽隔离结构的槽宽为0.5微米-0.7微米。
4.根据权利要求3所述的基于SOI工艺的介质电容，其特征在于，所述深槽隔离结构的槽宽为0.6微米。
5.根据权利要求2所述的基于SOI工艺的介质电容，其特征在于，所述深槽隔离结构之间的间距为1微米-2微米。
6.根据权利要求2所述的基于SOI工艺的介质电容，其特征在于，所述深槽隔离结构在所述顶层硅中的分布区域大于所述下极板覆盖所述顶层硅的区域。
7.根据权利要求1所述的基于SOI工艺的介质电容，其特征在于，部分所述浅沟槽隔离结构位于所述下极板下方；位于所述下极板下方的深沟槽隔离结构分别与所述浅沟槽隔离结构、所述埋氧化层相连。
8.根据权利要求1所述的基于SOI工艺的介质电容，其特征在于，所述浅沟槽隔离结构和所述深槽隔离结构的材质均为硅的氧化物。
9.根据权利要求1所述的基于SOI工艺的介质电容，其特征在于，所述上极板和下极板的材质均为多晶硅或者金属。
10.根据权利要求1所述的基于SOI工艺的介质电容，其特征在于，还包括衬底引出区；所述衬底引出区形成于所述顶层硅上且位于所述介质电容的主体部分的四周；所述层间介质层中还形成有位于所述衬底引出区上方的金属接触孔；所述衬底引出区通过所述金属接触孔与外部电路连接。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106483758B (zh) 2015-09-02 2019-08-20 无锡华润上华科技有限公司 光学邻近效应修正方法和系统
CN106653842B (zh) 2015-10-28 2019-05-17 无锡华润上华科技有限公司 一种具有静电释放保护结构的半导体器件
CN106816468B (zh) 2015-11-30 2020-07-10 无锡华润上华科技有限公司 具有resurf结构的横向扩散金属氧化物半导体场效应管
CN107465983B (zh) 2016-06-03 2021-06-04 无锡华润上华科技有限公司 Mems麦克风及其制备方法
CN111490159A (zh) * 2020-04-17 2020-08-04 思瑞浦微电子科技（苏州）股份有限公司 隔离电容及其制备方法
CN112397478B (zh) * 2020-11-25 2023-05-09 思瑞浦微电子科技（苏州）股份有限公司 隔离电容及其制备方法
JP2024052028A (ja) * 2022-09-30 2024-04-11 株式会社デンソー 半導体装置およびその製造方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007189017A (ja) * 2006-01-12 2007-07-26 Toshiba Corp 半導体装置
US7671394B2 (en) * 2007-10-17 2010-03-02 International Business Machines Corporation Embedded trench capacitor having a high-k node dielectric and a metallic inner electrode

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004228188A (ja) * 2003-01-21 2004-08-12 Renesas Technology Corp 半導体装置
US20120018198A1 (en) * 2010-03-30 2012-01-26 Ibiden Co., Ltd. Electronic component and printed wiring board
US8241981B1 (en) * 2011-01-31 2012-08-14 International Business Machines Corporation Method of fabricating a deep trench (DT) metal-insulator-metal (MIM) capacitor
JP5724934B2 (ja) * 2011-07-05 2015-05-27 株式会社デンソー 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007189017A (ja) * 2006-01-12 2007-07-26 Toshiba Corp 半導体装置
US7671394B2 (en) * 2007-10-17 2010-03-02 International Business Machines Corporation Embedded trench capacitor having a high-k node dielectric and a metallic inner electrode

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