CN105097795B - 具esd保护结构的半导体器件 - Google Patents

具esd保护结构的半导体器件 Download PDF

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CN105097795B
CN105097795B CN201410184376.2A CN201410184376A CN105097795B CN 105097795 B CN105097795 B CN 105097795B CN 201410184376 A CN201410184376 A CN 201410184376A CN 105097795 B CN105097795 B CN 105097795B
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张广胜
张森
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CSMC Technologies Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Microelectronics & Electronic Packaging (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

本发明涉及一种具ESD保护结构的半导体器件，所述半导体器件包括高压功率器件，所述ESD保护结构是NMOS管，所述NMOS管的漏极与所述功率器件的源极共用，功率器件的衬底引出区与NMOS管的衬底引出区和源极连接、作为地线引出。本发明的NMOS管的漏极与功率器件的源极共用，因此加入了ESD保护结构后器件增加的面积较小。且高压功率器件源极处能够得到较低的holding电压，从而保护了栅氧，提高了源极可靠性。

Description

具ESD保护结构的半导体器件
技术领域
本发明涉及半导体器件，特别是涉及一种具ESD保护结构的半导体器件。
背景技术
静电释放(ESD)是当今集成电路重要的可靠性问题之一。传统的高压器件源极的ESD曲线如图1所示，其电压无法维持(holding)，从而可能对器件的栅极产生很大的影响。
常规的高压器件的ESD保护通常是采用器件自保护来实现，从而与器件自身的能力密切相关。对于高压器件源极的ESD保护，通常通过在高压器件的源极处加入保护结构来实现，其会占用较大的器件面积。
发明内容
基于此，有必要提供一种器件的整体面积较小的具ESD保护结构的半导体器件。
一种具ESD保护结构的半导体器件，所述半导体器件包括功率器件，所述ESD保护结构是NMOS管，所述NMOS管的漏极与所述功率器件的源极共用，功率器件的衬底引出区与NMOS管的衬底引出区和源极连接、作为地线引出。
在其中一个实施例中，所述NMOS管的栅极与所述地线引出短接。
在其中一个实施例中，所述NMOS管的栅极受外围控制电路的信号控制其开关。
在其中一个实施例中，所述半导体器件包括第一掺杂类型的衬底，所述衬底上的第一掺杂类型的阱区和第二掺杂类型的漂移区，所述阱区内的衬底引出区和两个第二掺杂类型的引出区，所述漂移区内的漏极，所述阱区上的第一栅极和第二栅极，以及将所述第二栅极和漏极分隔开的氧化层；所述漂移区内的漏极为所述功率器件的漏极；所述两个第二掺杂类型的引出区中的一个作为所述NMOS管的源极引出区，靠近所述衬底引出区并通过金属导线与所述衬底引出区连接作为所述地线引出；所述两个第二掺杂类型的引出区中的另一个靠近所述氧化层，作为所述NMOS管的漏极与所述功率器件的源极被共用；所述第一栅极设于所述两个第二掺杂类型的引出区之间，作为所述NMOS管的栅极，所述第二栅极设于所述功率器件的源极与所述氧化层之间，作为所述功率器件的栅极；所述第一掺杂类型和第二掺杂类型的导电类型相反。
在其中一个实施例中，所述第一掺杂类型为P型，所述第二掺杂类型为N型，所述功率器件的漏极的掺杂类型为N+，所述衬底引出区的掺杂类型为P+。
在其中一个实施例中，所述氧化层位于所述漂移区表面。
上述具ESD保护结构的半导体器件，其NMOS管的漏极与功率器件的源极共用，因此加入了ESD保护结构后器件增加的面积较小。
附图说明
图1是一种传统的高压器件源极的ESD曲线；
图2是一实施例中具ESD保护结构的半导体器件的等效电路图；
图3是一实施例中具ESD保护结构的半导体器件的剖面示意图；
图4是上述具ESD保护结构的半导体器件的源极电压与源极电流的关系曲线，以及源极电流与漏电流的关系曲线。
具体实施方式
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
图2是一实施例中具ESD保护结构的半导体器件的等效电路图，包括耐高压的功率器件101和作为ESD保护结构的NMOS管102，其中功率器件101的漏极103可以承受几十伏特到几百伏特不等的高电压(具体耐压能力取决于器件的设计需求)。功率器件101的栅极105作为控制功率器件101开关的控制端口，NMOS管102的栅极104控制NMOS管102的开关状态。NMOS管102的漏极与功率器件101的源极共用、作为共源漏结构107，即器件上相应的结构既作为NMOS管102的漏极、又作为功率器件101的源极。功率器件101的衬底引出区、NMOS管的衬底引出区、NMOS管的源极106三者相互连接，作为地线引出。
上述具ESD保护结构的半导体器件，其NMOS管102的漏极与功率器件101的源极共用，因此加入了ESD保护结构后器件增加的面积较小。
在使用上述具ESD保护结构的半导体器件的过程中，可以将栅极104与源极106短接(并接地)形成GGMOS，从而保证器件在大电压冲击和静电释放时，能够形成共源漏结构107与地之间的电流通路；也可以采用外围电路通过栅极104控制NMOS管102的开关状态，来保证共源漏结构107与地之间的通路，使得源极电压维持在一个较低的值，保证器件的栅极不会击穿，从而保证功率器件101的源极的可靠性。
图3是一实施例中具ESD保护结构的半导体器件的剖面示意图，用方框示出了NMOS管区域200和功率器件区域300，具体地，器件包括：第一掺杂类型的衬底210，衬底210上的第一掺杂类型的阱区220，衬底210上的第二掺杂类型的漂移区230，阱区220内的衬底引出区206和两个第二掺杂类型的引出区(即引出区202和引出区205)，漂移区230内的漏极201，阱区220上的第一栅极204和第二栅极203，以及位于漂移区230表面、将第二栅极203和漏极201分隔开的氧化层208。
漂移区230内的漏极201为功率器件的漏极。引出区205作为NMOS管的源极引出区，其靠近衬底引出区206并通过金属导线与衬底引出区206连接、作为地线引出。引出区202靠近氧化层208，作为NMOS管的漏极与功率器件的源极被共用，制造方法是将其bonding在一起。第一栅极204设于引出区202和引出区205之间，作为NMOS管的栅极；第二栅极203设于引出区202与氧化层208之间，作为功率器件的栅极。所述第一掺杂类型和第二掺杂类型的导电类型相反。
在本实施例中，第一掺杂类型为P型，第二掺杂类型为N型。功率器件的漏极201的掺杂类型为N+，衬底引出区206的掺杂类型为P+。
第二栅极203主要控制高压功率器件的开关特性。第一栅极204既可以单独作为端口与外围控制电路一起来控制低压NMOS管的开关特性，也可以与引出区205短接形成GGMOS来为高压功率器件提供器件的电流通路，得到源极处较低的holding电压，从而保护了栅氧，提高了源极可靠性。
图4是上述具ESD保护结构的半导体器件的源极电压与源极电流的关系曲线，以及源极电流与漏电流的关系曲线。其中，从原点开始向右边延伸的为源极电压与源极电流的关系曲线，从原点开始向上延伸的为源极电流与漏电流的关系曲线。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (5)

1.一种具ESD保护结构的半导体器件，所述半导体器件包括功率器件，其特征在于，所述ESD保护结构是NMOS管，所述NMOS管的漏极与所述功率器件的源极共用，功率器件的衬底引出区与NMOS管的衬底引出区和源极连接、作为地线引出；
所述半导体器件包括第一掺杂类型的衬底，所述衬底上的第一掺杂类型的阱区和第二掺杂类型的漂移区，所述阱区内的衬底引出区和两个第二掺杂类型的引出区，所述漂移区内的漏极，所述阱区上的第一栅极和第二栅极，以及将所述第二栅极和漏极分隔开的氧化层；
所述漂移区内的漏极为所述功率器件的漏极；所述两个第二掺杂类型的引出区中的一个作为所述NMOS管的源极引出区，靠近所述衬底引出区并通过金属导线与所述衬底引出区连接作为所述地线引出；所述两个第二掺杂类型的引出区中的另一个靠近所述氧化层，作为所述NMOS管的漏极与所述功率器件的源极被共用；所述第一栅极设于所述两个第二掺杂类型的引出区之间，作为所述NMOS管的栅极，所述第二栅极设于所述功率器件的源极与所述氧化层之间，作为所述功率器件的栅极；所述第一掺杂类型和第二掺杂类型的导电类型相反。
2.根据权利要求1所述的具ESD保护结构的半导体器件，其特征在于，所述NMOS管的栅极与所述地线引出短接。
3.根据权利要求1所述的具ESD保护结构的半导体器件，其特征在于，所述NMOS管的栅极受外围控制电路的信号控制其开关。
4.根据权利要求1所述的具ESD保护结构的半导体器件，其特征在于，所述第一掺杂类型为P型，所述第二掺杂类型为N型，所述功率器件的漏极的掺杂类型为N+，所述衬底引出区的掺杂类型为P+。
5.根据权利要求1所述的具ESD保护结构的半导体器件，其特征在于，所述氧化层位于所述漂移区表面。
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PCT/CN2015/078222 WO2015169197A1 (zh) 2014-05-04 2015-05-04 具esd保护结构的半导体器件
JP2016566262A JP6276874B2 (ja) 2014-05-04 2015-05-04 Ｅｓｄ保護構造付き半導体デバイス
US15/308,574 US9953970B2 (en) 2014-05-04 2015-05-04 Semiconductor device having ESD protection structure
KR1020167031533A KR101865492B1 (ko) 2014-05-04 2015-05-04 Esd 보호 구조를 갖는 반도체 디바이스

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