TWI523196B - 高壓金氧半導體電晶體元件及其佈局圖案 - Google Patents

高壓金氧半導體電晶體元件及其佈局圖案 Download PDF

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TWI523196B
TWI523196B TW101106210A TW101106210A TWI523196B TW I523196 B TWI523196 B TW I523196B TW 101106210 A TW101106210 A TW 101106210A TW 101106210 A TW101106210 A TW 101106210A TW I523196 B TWI523196 B TW I523196B
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doped region
discontinuous
mos transistor
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李明宗
楊承樺
李文芳
王智充
許智維
莊柏青
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聯華電子股份有限公司
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Priority to US13/407,722 priority patent/US8692326B2/en
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Description

高壓金氧半導體電晶體元件及其佈局圖案
本發明有關於一種高壓金氧半導體(high voltage metal-oxide-semiconductor，以下簡稱為HV MOS)電晶體元件及其佈局圖案，尤指一種高壓橫向雙擴散金氧半導體(high voltage lateral double-diffused metal-oxide-semiconductor，HV-LDMOS)電晶體元件及其佈局圖案。
在具有高壓處理能力的功率元件中，雙擴散金氧半導體(double-diffused MOS，DMOS)電晶體元件係持續受到重視。常見的DMOS電晶體元件有垂直雙擴散金氧半導體(vertical double-diffused MOS，VDMOS)與橫向雙擴散金氧半導體(LDMOS)電晶體元件。而LDMOS電晶體元件因具有較高的操作頻寬與操作效率，以及易與其他積體電路整合之平面結構，現已廣泛地應用於高電壓操作環境中，如中央處理器電源供應(CPU power supply)、電源管理系統(power management system)、直流/交流轉換器(AC/DC converter)以及高功率或高頻段的功率放大器等等。LDMOS電晶體元件主要的特徵為源極端所設置之低摻雜濃度、大面積的橫向擴散漂移區域，其目的在於緩和源極端與汲極端之間的高電壓，因此可使LDMOS電晶體元件獲得較高的崩潰電壓(breakdown voltage)。
請參閱第1圖，第1圖為一習知HV-LDMOS電晶體元件之剖面示意圖。如第1圖所示，習知HV-LDMOS電晶體元件10係設置於一半導體基底12上，其具有一P型井20、設置於P型井20中的一源極14與一高濃度之P型摻雜區22、一閘極16與一汲極18。汲極18為一高濃度之N型摻雜區，且設置於一N型井30中。此一N型井30即前述之漂移區域，其摻雜濃度與長度影響了HV-LDMOS電晶體元件10的崩潰電壓與導通電阻(ON-resistance，RON)。HV-LDMOS電晶體元件10之閘極16係設置於一閘極介電層40上，且延伸至一場氧化層42上方。
由於HV MOS電晶體元件所追求的兩個主要特性為低導通電阻以及高崩潰電壓，且這兩個要求常常是彼此衝突難以權衡的。因此目前仍需要一種可在高電壓環境下正常運作，且同時滿足低導通電阻以及高崩潰電壓兩個要求的解決途徑。
因此，本發明之一目的係在於提供一提供低導通電阻與高崩潰電壓的HV MOS電晶體元件及其佈局圖案。
根據本發明所提供之申請專利範圍，係提供一種HV MOS電晶體之佈局圖案，該佈局圖案包含有一具有一第一導電型態之第一摻雜區、一具有該第一導電型態之第二摻雜區、以及一不連續形(non-continuous)摻雜區。該不連續形摻雜區係設置於該第一摻雜區與該第二摻雜區之間，且包含複數個間隔(gap)。另外該不連續形摻雜區域包含一第二導電型態，且該第二導電型態與該第一導電型態互補(complementary)。
根據本發明所提供之申請專利範圍，更提供一種HV MOS電晶體元件，包含有一其上形成有一絕緣層之基底、一設置於該基底上且覆蓋部分該絕緣層之閘極、一設置於該基底內且具有一第一導電型態之汲極區域、一設置於該基底內且包含該第一導電型態之源極區域、以及一設置於該源極區域與該汲極區域之間且包含複數個間隔的不連續形摻雜區。該不連續摻雜區包含一第二導電型態，且該第二導電型態與該第一導電型態互補。
根據本發明所提供的HV MOS電晶體元件及其佈局圖案，係利用不連續形摻雜區提升HV MOS電晶體的崩潰電壓。此外本發明所提供的HV MOS電晶體元件及其佈局圖案所提供的不連續形摻雜區內包含有複數個間隔，並藉由該等間隔的插入阻斷降低不連續形摻雜區中摻雜部分的總面積，因此本發明可有效地降低導通電阻。簡單地說，本發明所提供之HV MOS電晶體元件及其佈局圖案係可同時實現高崩潰電壓、低導通電阻的期望。
請參閱第2圖至第6圖，第2圖為本發明所提供之HV MOS電晶體元件之佈局圖案之示意圖，其中第3圖與第4圖分別為沿第2圖中A-A’與B-B’切線所獲得之剖面示意圖。如第2圖至第4圖所示，本較佳實施例所提供之HV MOS電晶體元件100係設置於一基底102，例如一矽基底上。基底102具有一第一導電型態，在本較佳實施例中該第一導電型態為p型。HV MOS電晶體元件100更包含一絕緣層104，但值得注意的是，為了清楚表現HV MOS電晶體元件100中某些特定摻雜區域的相對關係，第2圖中係將絕緣層104省略。
請繼續參閱第2圖至第6圖。本較佳實施例所提供之HV MOS電晶體元件100尚包含一深井區106，深井區106係包含一第二導電型態，第二導電型態係與第一導電型態互補(complementary)，因此在本較佳實施例中第二導電型態為n型。在深井區160中，係形成有一漂移區108(僅示於第3圖與第4圖)與一高壓井區110(亦僅示於第3圖與第4圖)。漂移區108包含第二導電型態；而高壓井區110則包含第一導電型態。換句話說HV MOS電晶體元件100包含一n型的 漂移區108與一p型的高壓井區110。在n型的漂移區108中，係形成有一第一摻雜區112；而在高壓井區110中，則形成有一第二摻雜區114與一第三摻雜區116。第一摻雜區112與第二摻雜區114具有第二導電型態，且分別作為HV MOS電晶體元件100的n型汲極區域與n型源極區域。第三摻雜區116係包含第一導電型態，用以作為HV MOS電晶體元件100的p型基體(body)區域。如第2圖至第4圖所示，基體區域(即第三摻雜區116)係與源極區域(即第二摻雜區114)電性連接。
HV MOS電晶體元件100亦包含一閘極130，但值得注意的是，為了清楚表現HV MOS電晶體元件100中某些特定摻雜區域的相對關係，第2圖中亦將閘極130省略。如第3圖與第4圖所示，閘極130係設置於基底102上，且覆蓋部分絕緣層104。
請仍然參閱第2圖至第4圖。本較佳實施例所提供之HV MOS電晶體元件100更包含一不連續形(non-continuous)摻雜區120，其包含第一導電型態，用以作為一p型摻雜區(又可稱為p-top區域)。如第2圖至第4圖所示，p型的不連續形摻雜區120係設置於汲極區域(第一摻雜區112)與源極區域(第二摻雜區114)之間，且汲極區域(第一摻雜區112)、源極區域(第二摻雜區114)、與該不連續形摻雜區120彼此 分隔設置，並利用深井區106電性隔離汲極區域(第一摻雜區112)、源極區域(第二摻雜區114)、與不連續形摻雜區120。如第2圖與第4圖所示，不連續形摻雜區120內更包含複數個間隔(gap)122，用以切斷(interrupt)p型摻雜區，且間隔122之寬度小於等於9微米(micrometer，μm)。另外如第3圖與第4圖所示，絕緣層104係完全覆蓋不連續形摻雜區120及其間隔122。
請重新參閱第2圖。根據本較佳實施例，設置於絕緣層104下方，且導電型態互補於n型源極區域(第二摻雜區114)與n型汲極區域(第一摻雜區112)的p型的不連續形摻雜區120係可提升HV MOS電晶體元件100的電阻值。當高壓訊號流經此一路徑時，會因為電阻值的增加使得本實施例的壓降能力有效提升，繼而使輸出的訊號成為低壓訊號。換句話說，藉由p型的不連續形摻雜區120的設置，HV MOS電晶體元件100的崩潰電壓係可有效地提升。
然而，HV MOS電晶體元件100的導通電阻的提升並非業者所樂見，因此本較佳實施例更於p型的不連續形摻雜區120中形成複數個切斷p形摻雜區的間隔122。由於間隔122的設置可降低p型的不連續形摻雜區120中摻雜部分的面積，且提供電子一較為簡易的路徑，故可有效地降低RON。值得注意的是，由於高崩潰電壓與低導通電阻係為兩個彼此 衝突的要求，因此本較佳實施例中，間隔122之總面積佔不連續形摻雜區120之面積的百分比小於等於20%，且間隔122之寬度小於等於9微米(μm)，以在降低導通電阻的同時仍然滿足高崩潰電壓的要求。
另外請參閱第5圖。值得注意的是，為清楚表示不連續形摻雜區120的佈局圖案，第5圖中僅繪示出不連續形摻雜區120及其間隔122，然而熟習該項技藝之人士應可根據前述第2圖至第4圖思及不連續形摻雜區120與其他組成元素的空間相對關係。如第5圖所示，在本較佳實施例中，不連續形摻雜區120可更定義包含有一中心部分(inner portion)140與一外圍部分(outer portion)142。詳細地說，不連續形摻雜區120係沿深井區106邊緣排列而呈一跑道形狀或梳子形狀；間隔122亦沿著深井區106邊緣排列並呈一跑道形狀或梳子形狀。且梳子基部、最外側兩梳齒、以及各梳齒前端皆定義為外圍部分142，而內側梳齒以及梳齒底部則定義為中心部分140。值得注意的是，設置於中心部分140的間隔122具有一第一圖案密度D1，設置於外圍部分142之間隔122則具有一第二圖案密度D2，且第一圖案密度D1小於第二圖案密度D2。舉例來說，設置於中心部分140之間隔122之總面積佔不連續形摻雜區120之面積的百分比R1小於等於15%；而設置於外圍部分142之間隔122之總面積佔不連續形摻雜區120之面積的百分比R2小於等於25%，且中心部 分140之間隔122之總面積佔不連續形摻雜區120之面積的百分比R1與外圍部分142之間隔122之總面積佔不連續形摻雜區120之面積的百分比R2之差可為7%，但不限於此。這是因為在HV MOS電晶體元件100中，對應於外圍部分142的n型深井區106會因摻雜製程關係而具有較低的摻雜濃度，而導致HV MOS電晶體100對應於外圍部分142處有較高的導通電阻。因此本較佳實施例提供之設置於外圍部分142之間隔122的第二圖案密度D2較高。換句話說，外圍部分142之間隔122的總面積較大，故可在不影響崩潰電壓的前提下降低HV MOS電晶體元件100對應於外圍部分142的導通電阻。
另外請參閱第6圖。如前所述，為清楚表示不連續形摻雜區120的佈局圖案，第6圖中僅繪示出不連續形摻雜區120及其間隔122，然而熟習該項技藝之人士應可根據前述第2圖至第4圖思及不連續形摻雜區120與其他組成元素的空間相對關係。如第6圖所示，在本較佳實施例中，不連續形摻雜區120可更定義為包含複數個角落部分(corner area)150與複數個直線部分(straight-line area)152。如前所述，不連續形摻雜區120係沿深井區106邊緣排列而呈一梳子形狀，而如第6圖所示，凡具有排列成圓弧形狀的不連續形摻雜區120皆被定義為一角落部分150，而排列成直線的不連續形摻雜區120則被定義為直線部分152。值得注意的是，設置 於角落部分150的間隔122具有一第三圖案密度D3，設置於直線部分152之間隔122則具有一第四圖案密度D4，且第三圖案密度D3大於第四圖案密度D4。這是因為在HV MOS電晶體元件100中，對應於角落部分150的部分具有較大的電場，而導致HV MOS電晶體100在對應角落部分150處有較高的導通電阻。因此本較佳實施例提供之設置於角落部分150之間隔122的第三圖案密度D3較高。換句話說，角落部分150之間隔122的總面積較大，故可在不影響崩潰電壓的前提下降低HV MOS電晶體元件100對應於角落部分150的導通電阻。
綜上所述，根據本發明所提供的HV MOS電晶體元件及其佈局圖案，係利用不連續形摻雜區提升HV MOS電晶體的崩潰電壓。此外由於不連續形摻雜區內包含有複數個間隔，而該等間隔的插入與阻斷降低了不連續形摻雜區中摻雜部分的總面積，因此本發明可有效地降低導通電阻。且該等間隔的圖案密度以及大小係可依據摻雜濃度高低以及電場大小等差異調整，故可在不影響崩潰電壓的前提下，不僅降低HV MOS電晶體元件的導通電阻，更達到平衡HV MOS電晶體元件內部導通電阻之目的。簡單地說，本發明所提供之HV MOS電晶體元件及其佈局圖案係可同時實現高崩潰電壓、低導通電阻的期望。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧高壓橫向雙擴散金氧半導體電晶體元件
12‧‧‧半導體基底
14‧‧‧源極
16‧‧‧閘極
18‧‧‧汲極
20‧‧‧P型井
22‧‧‧P型摻雜區
30‧‧‧N型井
40‧‧‧閘極介電層
42‧‧‧場氧化層
100‧‧‧高壓金氧半導體電晶體元件
102‧‧‧基底
104‧‧‧絕緣層
106‧‧‧深井區
108‧‧‧漂移區
110‧‧‧高壓井區
112‧‧‧第一摻雜區
114‧‧‧第二摻雜區
116‧‧‧第三摻雜區
120‧‧‧不連續形摻雜區
122‧‧‧間隔
130‧‧‧閘極
140‧‧‧中心部分
142‧‧‧外圍部分
150‧‧‧角落部分
152‧‧‧直線部分
第1圖為一習知HV-LDMOS電晶體元件之剖面示意圖。
第2圖至第6圖為本發明所提供之HV MOS電晶體之佈局圖案之示意圖，其中第3圖與第4圖分別為沿第2圖中A-A’與B-B’切線所獲得之剖面示意圖。
100．．．高壓金氧半導體電晶體元件
102．．．基底
112．．．第一摻雜區
114．．．第二摻雜區
116．．．第三摻雜區
120．．．不連續形摻雜區
122．．．間隔

Claims (20)

  1. 一種高壓金氧半導體電晶體之佈局圖案，包含有：一第一摻雜區，具有一第一導電型態；一第二摻雜區，具有該第一導電型態；以及一不連續形(non-continuous)摻雜區，設置於該第一摻雜區與該第二摻雜區之間且包含複數個間隔(gap)，該不連續形摻雜區域包含一第二導電型態，且該第二導電型態與該第一導電型態互補(complementary)。
  2. 如申請專利範圍第1項所述之佈局圖案，其中該第一摻雜區、該第二摻雜區、與該不連續形摻雜區彼此分隔設置。
  3. 如申請專利範圍第1項所述之佈局圖案，其中該等間隔之總面積佔該不連續形摻雜區之面積的百分比小於等於20%。
  4. 如申請專利範圍第1項所述之佈局圖案，其中該等間隔之寬度小於等於9微米((micrometer，μm))。
  5. 如申請專利範圍第1項所述之佈局圖案，其中該不連續形摻雜區更定義有一中心部分(inner portion)與一外圍部分(outer portion)。
  6. 如申請專利範圍第5項所述之佈局圖案，其中設置於該中心部分之該等間隔具有一第一圖案密度，設置於該外圍部分之間隔具有一第二圖案密度，且該第一圖案密度小於該第二圖案密度。
  7. 如申請專利範圍第5項所述之佈局圖案，其中設置於該中心部分之該等間隔之總面積佔該不連續形摻雜區之面積的百分比小於等於15%。
  8. 如申請專利範圍第5項所述之佈局圖案，其中設置於該外圍部分之該等間隔之總面積佔該不連續形摻雜區之面積的百分比小於等於25%。
  9. 如申請專利範圍第1項所述之佈局圖案，其中該不連續形摻雜區更定義有複數個角落部分(corner area)與複數個直線部分(straight-line area)。
  10. 如申請專利範圍第9項所述之佈局圖案，其中設置於該角落部分之該等間隔具有一第三圖案密度，設置於該直線部分之間隔具有一第四圖案密度，且該第三圖案密度大於該第四圖案密度。
  11. 一種高壓金氧半導體(high voltage metal-oxide-semiconductor，HV MOS)電晶體元件，包含有：一基底，其上形成有一絕緣層；一閘極，設置於該基底上，且覆蓋部分該絕緣層；一汲極區域，設置於該基底內，且該汲極區域具有一第一導電型態；一源極區域，設置於該基底內，且該源極區域包含該第一導電型態；以及一不連續形摻雜區，設置於該源極區域與該汲極區域之間，且包含複數個間隔，該不連續形摻雜區包含一第二導電型態，且該第二導電型態與該第一導電型態互補。
  12. 如申請專利範圍第11項所述之HV MOS電晶體元件，其中該等間隔之總面積佔該不連續形摻雜區之面積的百分比小於等於20%。
  13. 如申請專利範圍第11項所述之HV MOS電晶體元件，其中該等間隔之寬度小於等於9微米。
  14. 如申請專利範圍第11項所述之HV MOS電晶體元件，更包含一深井區(deep well)，設置於該基底內，且該深井區包含該第一導電型態。
  15. 如申請專利範圍第14項所述之HV MOS電晶體元件， 其中該源極區域、該汲極區域、與該不連續形摻雜區皆設置於該深井區內。
  16. 如申請專利範圍第15項所述之HV MOS電晶體元件，其中該源極區域、該汲極區域、與該不連續形摻雜區彼此分隔設置。
  17. 如申請專利範圍第15項所述之HV MOS電晶體元件，其中該源極區域、該汲極區域、與該不連續形摻雜區域係藉由該深井區彼此電性隔離。
  18. 如申請專利範圍第15項所述之HV MOS電晶體元件，其中該等間隔係排列呈一梳子狀。
  19. 如申請專利範圍第11項所述之HV MOS電晶體元件，其中該絕緣層係完全覆蓋該不連續形摻雜區域與該等間隔。
  20. 如申請專利範圍第11項所述之HV MOS電晶體元件，更包含一基體(body)區域，與該源極區域電性連接，且該基體區域包含該第一導電型態。
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US20130221438A1 (en) 2013-08-29
US8937352B2 (en) 2015-01-20
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US20140159155A1 (en) 2014-06-12

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