WO2016158109A1 - 撮像用部品およびこれを備える撮像モジュール - Google Patents
撮像用部品およびこれを備える撮像モジュール Download PDFInfo
- Publication number
- WO2016158109A1 WO2016158109A1 PCT/JP2016/055575 JP2016055575W WO2016158109A1 WO 2016158109 A1 WO2016158109 A1 WO 2016158109A1 JP 2016055575 W JP2016055575 W JP 2016055575W WO 2016158109 A1 WO2016158109 A1 WO 2016158109A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- imaging
- electrode pad
- conductor pattern
- imaging component
- laminated substrate
- Prior art date
Links
- 238000003384 imaging method Methods 0.000 title claims abstract description 48
- 239000004020 conductor Substances 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 239000011347 resin Substances 0.000 claims abstract description 9
- 230000005484 gravity Effects 0.000 claims description 10
- 230000008646 thermal stress Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000008602 contraction Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0393—Flexible materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
Definitions
- the present disclosure relates to an imaging component and an imaging module including the imaging component.
- Patent Document 1 As an imaging component, for example, a camera module described in Japanese Patent Application Laid-Open No. 2004-104078 (hereinafter also referred to as Patent Document 1) is known.
- the camera module described in Patent Document 1 includes a flexible sheet and an image sensor mounted on the surface of the flexible sheet.
- the imaging component of the present disclosure includes a multilayer substrate made of a resin material, a plurality of electrode pads provided on an upper surface of the multilayer substrate, on which an imaging element is mounted, and a plurality of the layers provided between the layers of the multilayer substrate.
- a plurality of strip-like conductor patterns respectively connected to any one of the electrode pads, and at least one of the conductor patterns has a portion located immediately below any of the electrode pads that are not connected It has a wide part that is wide.
- the imaging component 10 includes a laminated substrate 1, electrode pads 2 provided on the upper surface of the laminated substrate 1, and conductors provided between the layers of the laminated substrate 1 and electrically connected to the electrode pads 2. Pattern 3 is provided.
- the imaging module 100 includes an imaging component 10 and an imaging element 4 mounted on the electrode pad 2 of the imaging component 10.
- the laminated substrate 1 is made of a resin material.
- an epoxy resin is used as the resin material.
- “consisting of a resin material” does not necessarily mean that the laminated substrate is composed of only a resin material, and may include other materials.
- the glass fiber may be made of so-called glass epoxy or the like in which an epoxy resin is impregnated.
- the laminated substrate 1 can be produced, for example, by laminating glass epoxy substrates.
- the multilayer substrate 1 is, for example, a plate shape whose main surface has a quadrangular shape.
- the dimensions of the laminated substrate 1 can be set, for example, to 15 to 20 mm in length, 15 to 20 mm in width, and 0.5 to 2 mm in thickness when the laminated substrate 1 is rectangular. More specifically, the laminated substrate 1 has a plurality of layers 11. The thickness of each of the plurality of layers 11 is, for example, 0.05 to 0.2 mm.
- the electrode pad 2 is a member for mounting the imaging element 4 on the multilayer substrate 1.
- a plurality of electrode pads 2 are provided on the upper surface of the multilayer substrate 1.
- the electrode pad 2 has, for example, a rectangular shape when viewed in cross section and a circular shape when viewed in plan.
- the surface of the multilayer substrate 1 is drawn through the imaging device 4, the electrode pad 2, and the solder ball 6.
- the electrode pad 2 is made of a metal material such as copper or gold, for example.
- the dimensions of the electrode pad 2 can be set, for example, to a diameter of 0.1 to 1 mm and a thickness of 0.01 to 0.05 mm when the shape of the electrode pad 2 when viewed in plan is a circle.
- a method for mounting the image sensor 4 for example, a ball grid array or the like can be used.
- the imaging device 4 is mounted using a ball grid array, and a plurality of solder balls 6 are formed on the lower surface of the imaging device 4 and the upper surface of the electrode pad 2. It is provided between.
- the conductor pattern 3 is a member for transmitting a signal emitted from the image sensor 4 mounted on the electrode pad 2 to another electronic component 5 such as a monitor.
- the conductor pattern 3 is a strip-shaped member.
- the conductor pattern 3 is provided between the layers of the multilayer substrate 1.
- the conductor pattern 3 is made of a metal material such as copper or gold, for example.
- the imaging component 10 of the present disclosure a part of at least one conductor pattern 3 is located immediately below any of the electrode pads 2 that are not connected.
- a wide portion 31 that is wide is provided.
- the “wide portion” refers to a portion where the width is partially increased in the conductor pattern 3 extending at a constant width.
- the width of the conductor pattern 3 changes from the width of the conductor pattern 3 when viewed in the direction in which the conductor pattern 3 extends.
- An imaginary line perpendicular to the extending direction of the conductor pattern 3 is drawn on the finished portion.
- a region between the two imaginary lines in the conductor pattern 3 can be regarded as the wide portion 31.
- the imaging component 10 includes a laminated substrate 1 in which a plurality of layers 11 made of a resin material are laminated, a plurality of electrode pads 2 provided on the surface of the laminated substrate 1, and a plurality of layers 11. And a plurality of conductor patterns 3 provided.
- the plurality of conductor patterns 3 are strip-shaped. At least one of the plurality of conductor patterns 3 has a first portion 31 and a second portion 32.
- the first portion 31 overlaps one of the plurality of electrode pads 2 and the stacking direction of the plurality of layers 11.
- the second portion 32 does not overlap with the plurality of electrode pads 2 in the stacking direction.
- the width of the first portion 31 is larger than the width of the second portion 32.
- the conductor pattern 3 can be formed by printing on the surface of the plurality of layers 11 when the plurality of layers 11 are laminated.
- the conductor pattern 3 is intentionally simplified and described in a straight line in order to help understanding.
- the conductor pattern 3 may be formed in a complicated shape. Therefore, although FIG. 2 and FIG. 3 have a corresponding relationship, in a strict sense, the arrangement of the conductor pattern 3 in FIG. 1 and the arrangement of the conductor pattern 3 in FIG. 3 do not correspond.
- “any electrode pad 2 that is not connected” here does not mean that the electrode pad 2 and the conductor pattern 3 are completely electrically independent. Specifically, it excludes the case where the wide portion 31 of the conductor pattern 3 and the electrode pad 2 positioned immediately above the conductive pattern 3 are directly connected by a through hole or the like, Etc., it may be indirectly connected because they are common.
- the conductor pattern 3 can be routed at a high density. .
- the imaging component 10 in which the deterioration of the positional accuracy of the imaging element 4 is reduced while the conductor pattern 3 is routed with high density.
- the outer shape of the wide portion 31 may be the same as the outer shape of the electrode pad 2.
- the outer shape of the first portion 31 and the outer shape of the electrode pad 2 overlapping the first portion 31 may be the same when viewed from a direction perpendicular to the surface of the multilayer substrate 1.
- the “same shape” here means that the shape of the portion of the outer shape of the wide portion 31 other than the direction in which the conductor pattern 3 extends is the same shape as the outer shape of the electrode pad.
- the shape of the part other than the direction in which the conductor pattern 3 extends out of the outer shape of the wide portion 31 is circular.
- the electrode pad 2 has a circular shape. That is, in the present disclosure, the wide portion 31 and the electrode pad 2 have the same shape.
- the wide portion 31 of the conductor pattern 3 may be wider than the electrode pad 2.
- the first portion 31 when viewed from a direction perpendicular to the surface of the multilayer substrate 1, the first portion 31 may be wider than the electrode pad 2 that overlaps the first portion 31.
- the conductor pattern 3 can be positioned immediately below the electrode pad 2. More specifically, for example, when the shape of the electrode pad 2 in plan view is circular, the shape of the wide portion of the conductor pattern 3 may be larger than the electrode pad 2.
- the first portion 31 when viewed from a direction perpendicular to the surface of the multilayer substrate 1, the first portion 31 is wider than the electrode pad 2 overlapping the first portion 31, and The center of gravity of each first portion 31 may be located farther from the center of gravity of the multilayer substrate 1 than the center of gravity of each electrode pad 2 overlapping the first portion 31.
- FIG. 5 only the first portion 31 of the conductor pattern 3 is shown to help understanding. More specifically, the center of gravity of the first portion 31 may be located on a straight extension line connecting the center of gravity of the multilayer substrate 1 and the center of gravity of the electrode pad 2.
- the first portion 31 may be located in a bent portion of the conductor pattern 3.
- the width may be increased at the bent portion of the conductor pattern 3.
- a bent portion of the conductor pattern 3 is easily affected by thermal stress from other portions.
- the linear portion of the conductor pattern 3 mainly undergoes thermal expansion in the length direction.
- the bent portion of the conductor pattern 3 receives thermal stress from the two linear portions adjacent to the bent portion, making it difficult to control the direction in which thermal expansion occurs.
- the thermal expansion of the bent portion itself can be increased. Thereby, the possibility that the first portion 31 may thermally expand in an unexpected direction due to the thermal stress generated by the other portions thermally expanding can be reduced. Thereby, the reliability of the imaging component 10 under a heat cycle can be improved.
- the adjacent first portions 31 may be arranged so that the intervals between them are equal.
- the first portions 31 are arranged at equal intervals, it is possible to reduce a possibility that the thermal expansion amount in the laminated substrate 1 under the heat cycle is uneven. Therefore, the possibility that the laminated substrate 1 is distorted can be reduced.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Structure Of Printed Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
11:層
2:電極パッド
3:導体パターン
31:幅広部
4:撮像素子
5:電子部品
10:撮像用部品
100:撮像モジュール
Claims (8)
- 樹脂材料から成る積層基板と、該積層基板の上面に設けられた、撮像素子が実装される複数の電極パッドと、前記積層基板の層間に設けられて複数の前記電極パッドのいずれかにそれぞれ接続された帯状の複数の導体パターンとを備えており、少なくとも1つの該導体パターンの一部は、接続されていないいずれかの前記電極パッドの直下に位置する部位が幅広とされた幅広部を備えている撮像用部品。
- 平面透視において、前記幅広部の外形が、前記電極パッドの外形と同形状である請求項1に記載の撮像用部品。
- 請求項1または請求項2に記載の撮像用部品と、該撮像用部品の前記電極パッドに実装された撮像素子とを備えた撮像モジュール。
- 樹脂材料から成る複数の層が積層された積層基板と、該積層基板の表面上に設けられた複数の電極パッドと、前記複数の層の間に設けられた複数の導体パターンとを備えており、該複数の導体パターンは帯状であって、該複数の導体パターンの少なくとも1つは第1部分および第2部分を有しており、前記第1部分は前記複数の電極パッドの1つと前記複数の層の積層方向に重なっており、前記第2部分は前記複数の電極パッドと前記積層方向に重なっておらず、前記第1部分の幅が前記第2部分の幅よりも大きい撮像用部品。
- 前記表面に対して垂直な方向から見たときに、前記第1部分の外形と前記第1部分に重なる前記電極パッドの外形とが同形状である請求項4に記載の撮像用部品。
- 前記表面に対して垂直な方向から見たときに、前記第1部分が前記第1部分に重なる前記電極パッドよりも幅が大きい請求項4に記載の撮像用部品。
- 前記表面に対して垂直な方向から見たときに、前記第1部分の重心が、前記第1部分に重なる前記電極パッドの重心よりも、前記積層基板の重心から遠くに位置している請求項6に記載の撮像用部品。
- 請求項4乃至請求項7のいずれかに記載の撮像用部品と、該撮像用部品の前記複数の電極パッドに実装された撮像素子とを備えた撮像モジュール。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201680014936.7A CN107409471B (zh) | 2015-03-27 | 2016-02-25 | 摄像用部件以及具备该摄像用部件的摄像模块 |
EP16771993.9A EP3277065B1 (en) | 2015-03-27 | 2016-02-25 | Imaging component, and imaging module provided with same |
US15/561,872 US20180130841A1 (en) | 2015-03-27 | 2016-02-25 | Imaging component and imaging module provided with same |
JP2017509390A JP6454001B2 (ja) | 2015-03-27 | 2016-02-25 | 撮像用部品およびこれを備える撮像モジュール |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015-067248 | 2015-03-27 | ||
JP2015067248 | 2015-03-27 |
Publications (1)
Publication Number | Publication Date |
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WO2016158109A1 true WO2016158109A1 (ja) | 2016-10-06 |
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ID=57005690
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2016/055575 WO2016158109A1 (ja) | 2015-03-27 | 2016-02-25 | 撮像用部品およびこれを備える撮像モジュール |
Country Status (5)
Country | Link |
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US (1) | US20180130841A1 (ja) |
EP (1) | EP3277065B1 (ja) |
JP (1) | JP6454001B2 (ja) |
CN (1) | CN107409471B (ja) |
WO (1) | WO2016158109A1 (ja) |
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DE102017128568A1 (de) * | 2017-12-01 | 2019-06-06 | Infineon Technologies Ag | Halbleiterchip mit einer vielzahl von externen kontakten, chip-anordnung und verfahren zum überprüfen einer ausrichtung einer position eines halbleiterchips |
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2016
- 2016-02-25 US US15/561,872 patent/US20180130841A1/en not_active Abandoned
- 2016-02-25 EP EP16771993.9A patent/EP3277065B1/en active Active
- 2016-02-25 CN CN201680014936.7A patent/CN107409471B/zh active Active
- 2016-02-25 JP JP2017509390A patent/JP6454001B2/ja active Active
- 2016-02-25 WO PCT/JP2016/055575 patent/WO2016158109A1/ja active Application Filing
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Also Published As
Publication number | Publication date |
---|---|
EP3277065A1 (en) | 2018-01-31 |
US20180130841A1 (en) | 2018-05-10 |
CN107409471B (zh) | 2020-07-21 |
JPWO2016158109A1 (ja) | 2017-12-28 |
JP6454001B2 (ja) | 2019-01-16 |
EP3277065A4 (en) | 2018-12-12 |
EP3277065B1 (en) | 2021-08-11 |
CN107409471A (zh) | 2017-11-28 |
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