WO2016155203A1 - 显示基板及其制造方法和显示装置 - Google Patents

显示基板及其制造方法和显示装置 Download PDF

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Publication number
WO2016155203A1
WO2016155203A1 PCT/CN2015/087367 CN2015087367W WO2016155203A1 WO 2016155203 A1 WO2016155203 A1 WO 2016155203A1 CN 2015087367 W CN2015087367 W CN 2015087367W WO 2016155203 A1 WO2016155203 A1 WO 2016155203A1
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Prior art keywords
electrode pattern
metal layer
insulating layer
layer
via hole
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PCT/CN2015/087367
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English (en)
French (fr)
Inventor
封宾
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US14/913,327 priority Critical patent/US9831178B2/en
Publication of WO2016155203A1 publication Critical patent/WO2016155203A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display substrate, a method of manufacturing the same, and a display device.
  • ADSDS Advanced Super-Dimensional Field Conversion Technology
  • the display substrate may include a base substrate 11 and a first metal layer 12 and a second metal layer formed on the base substrate 11. 13.
  • the first insulating layer 16 is located above the first metal layer 12, the active layer 21 is located above the first insulating layer 16, the second metal layer 13 is located above the active layer 21, and the second insulating layer 17 is located at the second metal layer.
  • the second electrode pattern 15 is disposed on the second insulating layer 17.
  • the first insulating layer 16 and the second insulating layer 17 above the first metal layer 12 are provided with a first via hole 19, and the second metal layer 13
  • a second via hole 20 is disposed on the upper second insulating layer 17, and a portion of the second electrode pattern 15 is disposed in the first via hole 19 and the second via hole 20 to realize the first metal layer 12 and the second metal layer 13 connection.
  • the second electrode pattern 15 is used as a connection medium, and a via process is performed at a corresponding position of the metal layer to be connected to achieve conduction between the metal layers.
  • the prior art has the following technical problems:
  • the second electrode pattern 15 as a connection medium has a partial structure located in the second insulating layer 17 except for a partial structure located in the two via holes.
  • the second electrode pattern 15 is made to have a large distance, and the second electrode pattern 15 located at the step around the via hole and at the corner is relatively weak. In the process after the completion of the second electrode pattern production, corrosion is likely to occur particularly during the completion of the production of the product and during use, so that problems such as deterioration of the circuit, line defects, and abnormal display are likely to occur.
  • Embodiments of the present invention provide a display substrate, a method of fabricating the same, and a display device to alleviate or avoid the above-mentioned problems.
  • an embodiment of the present invention provides a display substrate including: a substrate substrate and a first metal layer, a second metal layer, a first electrode pattern, and a first layer formed over the substrate substrate a second electrode pattern, a first insulating layer and a second insulating layer, the first insulating layer is located above the first metal layer, and the second insulating layer is located above the first insulating layer, the first An electrode pattern and the second metal layer are located between the first insulating layer and the second insulating layer;
  • the first insulating layer and the second insulating layer are provided with via holes at positions directly above the first metal layer, and one end of the first electrode pattern is connected to the second metal layer, the first electrode pattern The other end extends into the via, the second electrode pattern is located in the via and connected to the first electrode pattern, and the second electrode pattern is further connected to the first metal layer.
  • the via includes a first sub via disposed in the first insulating layer and a second sub via disposed in the second insulating layer, the first sub via And communicating with the second sub-via; and a width of the second sub-via is greater than a width of the first sub-via;
  • a portion of the first electrode pattern located in the via hole is located in the second sub via hole and above the first insulating layer;
  • One end of the second electrode pattern located in the via hole is located in the first sub via hole, and the other end of the second electrode pattern located in the via hole is located in the second sub via hole and located in the first electrode pattern Above.
  • the side of the via hole adjacent to the second metal layer is stepped.
  • the second metal layer may be under the first electrode pattern, or the second metal layer may be located above the first electrode pattern.
  • the first metal layer is a gate metal layer
  • the second metal layer is a source/drain metal layer
  • the first metal layer is a source/drain metal layer
  • the second metal layer is a gate metal layer.
  • an embodiment of the present invention provides a display device including: a display substrate and a counter substrate disposed opposite to each other, and the display substrate may be a display provided by any of the above embodiments. Substrate.
  • an embodiment of the present invention provides a method of manufacturing a display substrate, including:
  • first metal layer Forming a first metal layer, a first insulating layer, a second metal layer, a first electrode pattern, and a second insulating layer over the base substrate, the first insulating layer being located above the first metal layer, a second insulating layer is located above the first insulating layer, the first electrode pattern and the second metal layer are located between the first insulating layer and the second insulating layer, the first electrode pattern One end is connected to the second metal layer;
  • the second electrode pattern is located in the via hole and connected to the first electrode pattern, and the second electrode pattern is further connected to the first metal layer connection.
  • the step of forming the first metal layer, the first insulating layer, the second metal layer, the first electrode pattern, and the second insulating layer over the substrate may include:
  • the second insulating layer is formed over the first electrode pattern.
  • the step of forming the first metal layer, the first insulating layer, the second metal layer, the first electrode pattern, and the second insulating layer over the substrate may include:
  • the second insulating layer is formed over the second metal layer.
  • the via hole includes a first sub via hole disposed in the first insulating layer and a second sub via hole disposed in the second insulating layer, the first sub via hole and the a second sub via is connected and a width of the second sub via is greater than a width of the first sub via;
  • a portion of the first electrode pattern located in the via hole is located in the second sub via hole and located above the first insulating layer;
  • One end of the second electrode pattern located in the via hole is located in the first sub via hole, and the other end of the second electrode pattern located in the via hole is located in the second sub via hole and located in the first electrode pattern Above.
  • the first insulating layer and the second insulating layer are provided with via holes corresponding to the position directly above the first metal layer, and the first electrode pattern is One end is connected to the second metal layer, the other end of the first electrode pattern extends into the via hole, the second electrode pattern is located in the via hole and is connected to the first electrode pattern, and the second electrode pattern is further connected to the first metal layer to The connection between the first metal layer and the second metal layer is realized.
  • the embodiment of the invention uses a via hole to connect different metal layers, thereby reducing the distribution density of the via holes, thereby reducing various undesirable phenomena in the subsequent process. Probability.
  • only one porous layer is used to connect different metal layers and the second electrode pattern as a connection medium is located in the via hole, so that the second electrode pattern does not need to be located at the step and the corner around the via hole.
  • the phenomenon that the second electrode pattern caused by the steps and the corners around the via hole is corroded can be alleviated or avoided, thereby alleviating or avoiding problems such as deterioration of the second electrode pattern, circuit failure, and abnormal display.
  • FIG. 1 is a schematic structural view of a H-ADSDS display substrate in the prior art
  • FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a display substrate according to another embodiment of the present invention.
  • FIG. 4a is a schematic view of forming a first metal layer in another embodiment of the present invention.
  • FIG. 4b is a schematic view showing the formation of a first insulating layer in another embodiment of the present invention.
  • 4c is a schematic view showing the formation of a second metal layer in another embodiment of the present invention.
  • 4d is a schematic view showing the formation of a first electrode pattern in another embodiment of the present invention.
  • 4e is a schematic view showing the formation of a second insulating layer in another embodiment of the present invention.
  • Figure 4f is a schematic view showing the formation of via holes in another embodiment of the present invention.
  • Figure 5a is a schematic view showing the formation of a first metal layer in still another embodiment of the present invention.
  • Figure 5b is a schematic view showing the formation of a first insulating layer in still another embodiment of the present invention.
  • Figure 5c is a schematic view showing the formation of an active layer in still another embodiment of the present invention.
  • Figure 5d is a schematic view showing the formation of a first electrode pattern in still another embodiment of the present invention.
  • Figure 5e is a schematic view showing the formation of a second metal layer in still another embodiment of the present invention.
  • Figure 5f is a schematic view showing the formation of a second insulating layer in still another embodiment of the present invention.
  • Figure 5g is a schematic illustration of the formation of vias in yet another embodiment of the present invention.
  • the display substrate includes: a substrate substrate 11 and a first metal layer 12 and a second metal formed on the substrate substrate 11.
  • the first insulating layer 16 and the second insulating layer 17 are disposed with a via hole 18 at a position directly above the first metal layer 12, and one end of the first electrode pattern 14 is connected to the second metal layer 13, and the first electrode pattern 14 is further One end extends into the via 18, the second electrode pattern 15 is located in the via 18 and is connected to the first electrode pattern 14, and the second electrode pattern 15 is also connected to the first metal layer 12.
  • the first electrode patterns 14 are respectively connected to the second electrode patterns 15 and the second metal layer 13, and the second electrode patterns 15 are connected to the first metal layer 12, thereby realizing the first metal layer 12 and the second layer.
  • the metal layers 13 are connected.
  • the via 18 may include a first sub via 181 disposed on the first insulating layer 16 and a second sub via 182 disposed on the second insulating layer 17, the first sub via 181 and The second sub vias 182 are in communication and the width of the second sub vias 182 is greater than the width of the first sub vias 181.
  • a portion of the first electrode pattern 14 that is located in the via 18 is located in the second sub via 182 and over the first insulating layer 16.
  • One end of the second electrode pattern 15 located in the via hole 18 is located in the first sub via hole 181, and the other end of the second electrode pattern 15 located in the via hole 18 is located in the second sub via hole 182 and located at the first electrode pattern Above 14.
  • the dotted line in the via 18 of FIG. 2 is for separating the first sub-via 181 and the second sub-pass. Hole 182.
  • the side of the via 18 adjacent to the second metal layer 13 may be stepped.
  • the use of stepped vias can avoid the use of deep holes (ie, deeper vias) that directly tunnel the first insulating layer and the second insulating layer, thereby reducing or avoiding the excessive depth of the deep holes.
  • deep holes ie, deeper vias
  • Various defects in the subsequent process for example, the uneven diffusion of the alignment film in the alignment film process can be avoided, and the occurrence of chamfering of the electrode layer can be effectively prevented, and the phenomenon of disconnection can be alleviated or avoided.
  • the second metal layer 13 is located below the first electrode pattern 14. Specifically, the second metal layer 13 is located above the first insulating layer 16 , and the first electrode pattern 14 is partially located above the second metal layer 13 and partially above the first insulating layer 16 .
  • the first metal layer 12 is a gate metal layer and the second metal layer 13 is a source/drain metal layer.
  • the first metal layer 12 may also be a source/drain metal layer
  • the second metal layer 13 may also be a gate metal layer, which is not specifically illustrated in the drawings.
  • the display substrate may further include an active layer 21.
  • the active layer 21 may be located under the second metal layer 13 and above the first insulating layer 16.
  • the first electrode pattern 14 may be located in the first electrode layer, and the first electrode layer may include a structure as a connection medium and a structure for generating an electric field, wherein the structure as the connection medium is the first electrode pattern 14. Only the first electrode pattern 14 is shown in Fig. 2. The structure for generating an electric field is known in the art and will not be shown here.
  • the second electrode pattern 15 may be located in the second electrode layer, and the second electrode layer may include a structure as a connection medium and a structure for generating an electric field, wherein the structure as the connection medium is the second electrode pattern 15, only the second electrode pattern 15 is shown in Figure 2, and the structure for generating an electric field is known in the art and will not be shown here.
  • the material of the first electrode pattern 14 and the second electrode pattern 15 may be a transparent conductive material such as indium tin oxide (ITO).
  • ITO indium tin oxide
  • the first insulating layer and the second insulating layer are provided with via holes at positions directly above the first metal layer, and one end of the first electrode pattern extends into the via hole, and the first electrode pattern is further One end is connected to the second metal layer, the second electrode pattern is located in the via hole and connected to the first electrode pattern, and the second electrode pattern is further connected to the first metal layer to realize the connection between the first metal layer and the second metal layer.
  • a via is used to connect different metal layers, which can reduce the distribution density of the vias, thereby reducing the subsequent process. The chance of producing various undesirable phenomena.
  • this embodiment only one via is used to connect different metal layers and the second electrode pattern as a connection medium is located in the via, so that the second electrode pattern does not need to be located at the step and the corner around the via, The phenomenon of corrosion of the second electrode pattern caused by the steps and corners around the via hole is avoided, thereby alleviating or avoiding problems such as deterioration of the second electrode pattern, circuit failure, and abnormal display. Therefore, this embodiment has a good effect in the reliability experiment and the yield.
  • FIG. 3 is a schematic structural diagram of a display substrate according to another embodiment of the present invention.
  • the display substrate includes: a base substrate 11 and a first metal layer 12 and a second formed on the base substrate 11. a metal layer 13, a first electrode pattern 14, a second electrode pattern 15, a first insulating layer 16, and a second insulating layer 17, the first insulating layer 16 is over the first metal layer 12, and the second insulating layer 17 is at the first Above the insulating layer 16, the first electrode pattern 14 and the second metal layer 13 are located between the first insulating layer 16 and the second insulating layer 17.
  • the first insulating layer 16 and the second insulating layer 17 are disposed with a via hole 18 corresponding to a position directly above the first metal layer 12, and one end of the first electrode pattern 14 extends into the via hole 18, and the other end of the first electrode pattern 14 Connected to the second metal layer 13, the second electrode pattern 15 is located in the via 18 and connected to the first electrode pattern 14, and the second electrode pattern 15 is also connected to the first metal layer 12.
  • the first electrode patterns 14 are respectively connected to the second electrode patterns 15 and the second metal layer 13, and the second electrode patterns 15 are connected to the first metal layer 12, thereby realizing the first metal layer 12 and the second layer.
  • the metal layers 13 are connected.
  • the via 18 may include a first sub via 181 disposed on the first insulating layer 16 and a second sub via 182 disposed on the second insulating layer 17, the first sub via 181 and The second sub vias 182 are in communication and the width of the second sub vias 182 is greater than the width of the first sub vias 181.
  • a portion of the first electrode pattern 14 that is located in the via 18 is located in the second sub via 182 and over the first insulating layer 16.
  • One end of the second electrode pattern 15 located in the via hole 18 is located in the first sub via hole 181, and the other end of the second electrode pattern 15 located in the via hole 18 is located in the second sub via hole 182 and located at the first electrode pattern Above 14.
  • the dotted line in the via 18 of FIG. 2 is for separating the first sub via 181 and the second sub via 182.
  • the side of the via 18 adjacent to the second metal layer 13 is stepped.
  • the use of stepped vias avoids the use of deep holes that directly tunnel the first insulating layer and the second insulating layer (ie, vias having a large depth), thereby reducing or avoiding the excessive depth of the deep holes.
  • Various defects in the subsequent process for example: alignment film can be avoided The uneven diffusion of the alignment film in the process forms a mura, and thus can effectively prevent the occurrence of chamfering of the electrode layer, and reduce or avoid the occurrence of an open circuit.
  • the second metal layer 13 is located above the first electrode pattern 14. Specifically, the first electrode pattern 14 is located above the first insulating layer 16 and the second insulating layer 17 is located above the second metal layer 13.
  • the first metal layer 12 is a gate metal layer and the second metal layer 13 is a source/drain metal layer.
  • the first metal layer 12 may also be a source/drain metal layer
  • the second metal layer 13 may also be a gate metal layer, which is not specifically illustrated in the drawings.
  • the display substrate may further include an active layer 21.
  • the active layer 21 may be located above the first insulating layer 16 and under the first electrode pattern 14.
  • the first electrode pattern 14 may be located in the first electrode layer, and the first electrode layer may include a structure as a connection medium and a structure for generating an electric field, wherein the structure as the connection medium is the first electrode pattern 14. Only the first electrode pattern 14 is shown in FIG. 3, and the structure for generating an electric field is known in the art and will not be specifically shown here.
  • the second electrode pattern 15 may be located in the second electrode layer, and the second electrode layer may include a structure as a connection medium and a structure for generating an electric field, wherein the structure as the connection medium is a second electrode pattern 15, only the second electrode pattern 15 is shown in Fig. 3.
  • the structure for generating an electric field is known in the art and will not be specifically shown here.
  • the material of the first electrode pattern 14 and the second electrode pattern 15 may be a transparent conductive material such as indium tin oxide (ITO).
  • ITO indium tin oxide
  • the first insulating layer and the second insulating layer are provided with via holes at positions directly above the first metal layer, and one end of the first electrode pattern is connected to the second metal layer, and the first electrode pattern is The other end extends into the via hole, the second electrode pattern is located in the via hole and is connected to the first electrode pattern, and the second electrode pattern is further connected to the first metal layer to realize the connection between the first metal layer and the second metal layer.
  • a via is used to connect different metal layers, which can reduce the distribution density of the vias, thereby reducing the probability of various undesirable phenomena in the subsequent process.
  • Another embodiment of the present invention provides a display device comprising: a display substrate and a counter substrate disposed opposite to each other, wherein the display substrate may be the display substrate provided by any of the above embodiments.
  • the display substrate may be an array substrate, and the opposite substrate may be a color film substrate.
  • the first insulating layer and the second insulating layer are provided with via holes at positions directly above the first metal layer, and one end of the first electrode pattern is connected to the second metal layer, and the first electrode pattern is The other end extends into the via hole, the second electrode pattern is located in the via hole and is connected to the first electrode pattern, and the second electrode pattern is further connected to the first metal layer to realize the connection between the first metal layer and the second metal layer
  • a via is used to connect different metal layers, which can reduce the distribution density of the vias, thereby reducing the probability of various undesirable phenomena in the subsequent process.
  • this embodiment only one via is used to connect different metal layers and the second electrode pattern as a connection medium is located in the via, so that the second electrode pattern does not need to be located at the step and the corner around the via,
  • the phenomenon of corrosion of the second electrode pattern caused by the steps and corners around the via hole is alleviated or avoided, so that problems such as deterioration of the second electrode pattern, line defects, and abnormal display can be alleviated or avoided. Therefore, this embodiment has a good effect in the reliability experiment and the yield.
  • Yet another embodiment of the present invention provides a method of manufacturing a display substrate, the method comprising:
  • Step 101 forming a first metal layer, a first insulating layer, a second metal layer, a first electrode pattern and a second insulating layer over the base substrate, the first insulating layer being located above the first metal layer, and the second insulating layer
  • the layer is located above the first insulating layer, and the first electrode pattern and the second metal layer are located between the first insulating layer and the second insulating layer, and one end of the first electrode pattern is connected to the second metal layer.
  • step 101 includes:
  • Step 1011 forming a first metal layer on the base substrate.
  • FIG. 4a is a schematic view of forming a first metal layer in one embodiment. As shown in FIG. 4a, a first metal layer material layer may be formed on the substrate substrate 11, and a first metal layer material layer is patterned to A first metal layer 12 is formed over the base substrate 11.
  • Step 1012 forming a first insulating layer over the first metal layer.
  • FIG. 4b is a schematic diagram of forming a first insulating layer in one embodiment, as shown in FIG. 4b, a first insulating layer 16 may be deposited over the first metal layer 12.
  • Step 1013 forming an active layer and a second metal layer over the active layer on the first insulating layer.
  • FIG. 4c is a schematic view of forming a second metal layer in one embodiment, and as shown in FIG. 4c, an active layer 21 and a second metal layer 13 may be formed on the first insulating layer 16 by a patterning process. Specifically, an active material layer and a second metal material layer may be successively deposited on the first insulating layer 16, and an active process is performed on the first insulating layer 16 by patterning the active material layer and the second metal material layer. Layer 21 and second metal layer 13. Since the active layer 21 and the second metal layer 13 can be formed by one patterning process.
  • Step 1014 forming a first electrode pattern over the second metal layer.
  • FIG. 4d is a schematic view showing the formation of a first electrode pattern in one embodiment.
  • a first electrode pattern material layer is formed on the substrate substrate 11, and the first electrode pattern material layer is patterned by a patterning process.
  • a first electrode pattern 14 is formed on the base substrate 11. The first electrode pattern 14 is partially located above the second metal layer 13 and partially above the first metal layer 12.
  • Step 1015 forming a second insulating layer over the first electrode pattern.
  • FIG. 4e is a schematic diagram of forming a second insulating layer in one embodiment, as shown in FIG. 4e, depositing a second insulating layer 17 over the first electrode pattern 14.
  • Step 102 forming a via hole at a position directly above the first insulating layer and the second insulating layer corresponding to the first metal layer, and extending the other end of the first electrode pattern into the via hole.
  • FIG. 4f is a schematic view showing the formation of via holes in one embodiment. As shown in FIG. 4f, by patterning the first insulating layer 16 and the second insulating layer 17 to form via holes 18, a portion of the first electrode pattern 14 is located. In the via 18 . In an embodiment, vias 18 may be formed by one patterning process.
  • the via 18 includes a first sub via 181 disposed in the first insulating layer 16 and a second sub via 182 disposed in the second insulating layer 17, the first sub via 181 and the second
  • the sub vias 182 are in communication and the width of the second sub via 182 is greater than the width of the first sub via 181; the portion of the first electrode pattern 14 located in the via 18 is located in the second sub via 182 and is located in the first insulation Above layer 16.
  • the side of the via hole 18 close to the second metal layer 13 is stepped due to the blocking effect of a portion of the first electrode pattern 14.
  • Step 103 forming a second electrode pattern above the substrate, the second electrode pattern
  • the second electrode pattern is also connected to the first metal layer in the via hole and connected to the first electrode pattern.
  • a second electrode pattern material layer is formed over the second insulating layer 17, and a second electrode pattern 15 is formed over the base substrate 11 by patterning the second electrode pattern material layer.
  • the second electrode pattern 15 is located in the via 18 and is connected to the first electrode pattern 14.
  • the second electrode pattern 15 is also connected to the first metal layer 12, thereby connecting the first metal layer 12 and the second metal layer 13.
  • step 1011, step 1013, step 1014, step 102, and step 103 can all be implemented by a patterning process.
  • the manufacturing method of the display substrate provided in this embodiment can be used to manufacture the display substrate provided in the embodiment shown in FIG. 2 .
  • the manufacturing method of the display substrate provided in this embodiment can be used to manufacture the display substrate provided in the embodiment shown in FIG. 2 .
  • the display substrate For a detailed description of the display substrate, refer to the previous embodiment, and details are not described herein again.
  • the first insulating layer and the second insulating layer are provided with via holes at positions directly above the first metal layer, and one end and the second of the first electrode pattern are provided.
  • the metal layer is connected, the other end of the first electrode pattern extends into the via hole, the second electrode pattern is located in the via hole and is connected to the first electrode pattern, and the second electrode pattern is further connected to the first metal layer to realize the first metal
  • the connection between the layer and the second metal layer uses a via to connect different metal layers, which can reduce the distribution density of the vias, thereby reducing the probability of various undesirable phenomena in the subsequent process.
  • this embodiment only one via is used to connect different metal layers and the second electrode pattern as a connection medium is located in the via, so that the second electrode pattern does not need to be located at the step and the corner around the via,
  • the phenomenon of corrosion of the second electrode pattern caused by the steps and corners around the via hole is alleviated or avoided, thereby alleviating or avoiding problems such as deterioration of the second electrode pattern, circuit failure, and abnormal display. Therefore, this embodiment has a good effect in the reliability experiment and the yield.
  • Yet another embodiment of the present invention provides another method of manufacturing a display substrate, the method comprising:
  • Step 201 forming a first metal layer, a first insulating layer, a second metal layer, a first electrode pattern and a second insulating layer over the base substrate, the first insulating layer being located above the first metal layer, and the second insulating layer
  • the layer is located above the first insulating layer, and the first electrode pattern and the second metal layer are located between the first insulating layer and the second insulating layer, and one end of the first electrode pattern is connected to the second metal layer.
  • step 201 may include:
  • Step 2011 forming the first metal layer over the base substrate.
  • FIG. 5a is a schematic view showing the formation of a first metal layer in one embodiment. As shown in FIG. 5a, a first metal layer material layer is formed on the substrate substrate 11, and the first metal layer material layer is patterned to form a liner. A first metal layer 12 is formed on the base substrate 11.
  • Step 2012 forming a first insulating layer over the first metal layer.
  • FIG. 5b is a schematic diagram of forming a first insulating layer in one embodiment, as shown in FIG. 5b, depositing a first insulating layer 16 over the first metal layer 12.
  • Step 2013, forming an active layer over the first insulating layer.
  • an active layer material layer may be formed over the first insulating layer 16, and the active layer material layer may be patterned to form the active layer 21.
  • step 2014 a first electrode pattern is formed over the base substrate.
  • FIG. 5d is a schematic view showing the formation of the first electrode pattern in one embodiment.
  • a first electrode pattern material layer is formed over the base substrate 11, and the first electrode pattern material layer is patterned on the substrate.
  • a first electrode pattern 14 is formed above the substrate 11.
  • the first electrode pattern 14 is located above the first insulating layer 16 and may cover the active layer 21.
  • Step 2015 forming a second metal layer over the first electrode pattern.
  • Figure 5e is a schematic illustration of forming a second metal layer in one embodiment, as shown in Figure 5e, a second metal layer 13 can be formed over the first electrode pattern 14 by a patterning process.
  • a second metal layer material layer may be deposited on the first electrode pattern 14, and a second metal layer 13 may be formed over the first electrode pattern 14 by patterning the second metal layer material layer.
  • Step 2016, forming a second insulating layer over the second metal layer.
  • Figure 5f is a schematic illustration of forming a second insulating layer in one embodiment, as shown in Figure 5f, depositing a second insulating layer 17 over the second metal layer 13.
  • Step 202 forming a via hole on the first insulating layer and the second insulating layer above the first metal layer, and a part of the first electrode pattern is located in the via hole.
  • FIG. 5g is a schematic view showing the formation of via holes in one embodiment.
  • the first insulating layer 16 and the second insulating layer 17 may be patterned to form via holes 18, and some of the first electrode patterns 14 are located.
  • vias 18 may be formed by one patterning process.
  • the via 18 includes a first sub via 181 disposed in the first insulating layer 16 and a second sub via 182 disposed in the second insulating layer 17, the first sub via 181 and the second The sub vias 182 are in communication and the width of the second sub via 182 is greater than the width of the first sub via 181; the portion of the first electrode pattern 14 located in the via 18 is located in the second sub via 182 and is located in the first insulation Above layer 16.
  • the shielding effect of the electrode pattern 14 is such that the side of the via hole 18 adjacent to the second metal layer 13 is stepped.
  • Step 203 forming a second electrode pattern on the substrate, the second electrode pattern is located in the via hole and connected to the first electrode pattern, and the second electrode pattern is further connected to the first metal layer.
  • a second electrode pattern material layer is formed over the second insulating layer 17, and a second electrode pattern 15 is formed over the base substrate 11 by patterning the second electrode pattern material layer.
  • the second electrode pattern 15 is located in the via 18 and is connected to the first electrode pattern 14.
  • the second electrode pattern 15 is also connected to the first metal layer 12, thereby connecting the first metal layer 12 and the second metal layer 13.
  • step 2011, step 2013, step 2014, step 2015, step 202, and step 203 can all be implemented by a patterning process.
  • the manufacturing method of the display substrate provided in this embodiment can be used to manufacture the display substrate provided in the embodiment shown in FIG. 3 .
  • the display substrate For the detailed description of the display substrate, refer to the previous embodiment, and details are not described herein again.
  • the first insulating layer and the second insulating layer are provided with via holes at positions directly above the first metal layer, and one end and the second of the first electrode pattern are provided.
  • the metal layer is connected, the other end of the first electrode pattern extends into the via hole, the second electrode pattern is located in the via hole and is connected to the first electrode pattern, and the second electrode pattern is further connected to the first metal layer to realize the first metal
  • the connection between the layer and the second metal layer uses a via to connect different metal layers, which can reduce the distribution density of the vias, thereby reducing the probability of various undesirable phenomena in the subsequent process.
  • this embodiment only one via is used to connect different metal layers and the second electrode pattern as a connection medium is located in the via, so that the second electrode pattern does not need to be located at the step and the corner around the via,
  • the phenomenon of corrosion of the second electrode pattern caused by the steps and corners around the via hole is alleviated or avoided, so that problems such as deterioration of the second electrode pattern, line defects, and abnormal display can be alleviated or avoided. Therefore, this embodiment has a good effect in the reliability experiment and the yield.

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Abstract

一种显示基板及其制造方法和显示装置。显示基板包括：衬底基板（11）和形成于衬底基板（11）上方的第一金属层（12）、第二金属层（13）、第一电极图形（14）、第二电极图形（15）、第一绝缘层（16）和第二绝缘层（17），第一绝缘层（16）位于第一金属层（12）之上，第二绝缘层（17）位于第一绝缘层（16）的上方，第一电极图形（14）和第二金属层（13）位于第一绝缘层（16）和第二绝缘层（17）之间；第一绝缘层（16）和第二绝缘层（17）对应第一金属层（12）正上方的位置设置有过孔（18），第一电极图形（14）的一端与第二金属层（13）连接，第一电极图形（14）的另一端延伸至过孔（18）内，第二电极图形（15）位于过孔（18）内且与第一电极图形（14）连接，第二电极图形（15）还与第一金属层（12）连接。该显示基板可降低后续工艺中产生各种不良现象的机率，以及减轻或避免第二电极图形（15）发生劣化断路、线路不良和异常显示等问题。

Description

显示基板及其制造方法和显示装置 技术领域
本发明涉及显示技术领域，特别涉及一种显示基板及其制造方法和显示装置。
背景技术
目前，在薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display，简称：TFT-LCD)技术领域中，ADSDS(高级超维场转换技术)显示装置的应用越来越广泛。其中，高开口率H-ADSDS显示装置是ADSDS显示装置中的一种重要类型。
图1为现有技术中H-ADS显示基板的结构示意图，如图1所示，该显示基板可包括衬底基板11和形成于衬底基板11上方的第一金属层12、第二金属层13、第二电极图形15、第一绝缘层16、第二绝缘层17和有源层21。第一绝缘层16位于第一金属层12之上，有源层21位于第一绝缘层16之上，第二金属层13位于有源层21之上，第二绝缘层17位于第二金属层13之上，第二电极图形15位于第二绝缘层17之上，第一金属层12上方的第一绝缘层16和第二绝缘层17上设置有第一过孔19，第二金属层13上方的第二绝缘层17上设置有第二过孔20，部分第二电极图形15设置于第一过孔19和第二过孔20中以实现将第一金属层12和第二金属层13连接。
现有技术中，采用第二电极图形15作为连接介质，并在需要连接的金属层对应位置进行过孔工艺，以实现金属层之间的导通。但是，现有技术存在如下技术问题：
1)需要两个过孔对不同的金属层进行连接，造成过孔的分布密度太高，这样会导致后续的工艺中出现各种不良现象，例如：过孔的分布密度太高使得配向膜工艺中配向膜扩散不均形成斑点(mura)，从而提高了后续工艺中产生各种不良现象的机率。
2)由于需要采用两个过孔对不同的金属层进行连接，因此作为连接介质的第二电极图形15除了部分结构位于两个过孔中之外，还有部分结构位于第二绝缘层17之上，使得第二电极图形15跨越的距离较大，位于过孔周围的台阶处和拐角处的第二电极图形15较为脆弱，导 致第二电极图形制作完成之后的工艺中特别是产品制作完成和使用过程中容易发生腐蚀，从而容易发生劣化断路、线不良和异常显示等问题。
发明内容
本发明的实施例提供一种显示基板及其制造方法和显示装置，以减轻或避免以上提到的问题。
根据本发明的一个方面，本发明的实施例提供了一种显示基板，包括：衬底基板和形成于所述衬底基板上方的第一金属层、第二金属层、第一电极图形、第二电极图形、第一绝缘层和第二绝缘层，所述第一绝缘层位于所述第一金属层之上，所述第二绝缘层位于所述第一绝缘层的上方，所述第一电极图形和所述第二金属层位于所述第一绝缘层和所述第二绝缘层之间；
所述第一绝缘层和第二绝缘层对应所述第一金属层正上方的位置设置有过孔，所述第一电极图形的一端与所述第二金属层连接，所述第一电极图形的另一端延伸至所述过孔内，所述第二电极图形位于所述过孔内且与所述第一电极图形连接，所述第二电极图形还与第一金属层连接。
在一个实施例中，所述过孔包括设置于所述第一绝缘层中的第一子过孔和设置于所述第二绝缘层中的第二子过孔，所述第一子过孔和所述第二子过孔连通且所述第二子过孔的宽度大于所述第一子过孔的宽度；
第一电极图形的位于所述过孔中的部分位于所述第二子过孔中且位于所述第一绝缘层之上；
位于所述过孔中的第二电极图形的一端位于第一子过孔中，位于所述过孔中的第二电极图形的另一端位于第二子过孔中且位于所述第一电极图形之上。
在实施例中，所述过孔靠近所述第二金属层的一侧为台阶状。
在实施例中，所述第二金属层可以位于第一电极图形之下，或者所述第二金属层可以位于所述第一电极图形之上。
在实施例中，所述第一金属层为栅极金属层，所述第二金属层为源/漏金属层；或者，
所述第一金属层为源/漏金属层，所述第二金属层为栅金属层。
根据本发明的另一方面，本发明的实施例提供了一种显示装置，包括：相对设置的显示基板和对置基板，该显示基板可以是以上各实施例中的任一实施例提供的显示基板。
根据本发明的又一方面，本发明的实施例提供了一种显示基板的制造方法，包括：
在衬底基板的上方形成第一金属层、第一绝缘层、第二金属层、第一电极图形和第二绝缘层，所述第一绝缘层位于所述第一金属层之上，所述第二绝缘层位于所述第一绝缘层的上方，所述第一电极图形和所述第二金属层位于所述第一绝缘层和所述第二绝缘层之间，所述第一电极图形的一端与所述第二金属层连接；
在第一绝缘层和第二绝缘层对应所述第一金属层正上方的位置形成过孔，所述第一电极图形的另一端延伸至所述过孔内；
在所述衬底基板的上方形成所述第二电极图形，所述第二电极图形位于所述过孔内且与所述第一电极图形连接，所述第二电极图形还与第一金属层连接。
进一步地，所述在衬底基板的上方形成第一金属层、第一绝缘层、第二金属层、第一电极图形和第二绝缘层的步骤可包括：
在所述衬底基板之上形成所述第一金属层；
在所述第一金属层之上形成所述第一绝缘层；
在所述第一绝缘层上形成有源层和位于有源层之上的第二金属层；
在所述第二金属层之上形成所述第一电极图形；
在所述第一电极图形之上形成所述第二绝缘层。
替代性地，所述在衬底基板的上方形成第一金属层、第一绝缘层、第二金属层、第一电极图形和第二绝缘层的步骤可包括：
在所述衬底基板之上形成所述第一金属层；
在所述第一金属层之上形成所述第一绝缘层；
在所述第一绝缘层之上形成有源层；
在所述有源层的上方形成所述第一电极图形；
在所述第一电极图形之上形成所述第二金属层；
在所述第二金属层之上形成所述第二绝缘层。
进一步地，所述过孔包括设置于所述第一绝缘层中的第一子过孔和设置于所述第二绝缘层中的第二子过孔，所述第一子过孔和所述第二子过孔连通且所述第二子过孔的宽度大于所述第一子过孔的宽度；
所述第一电极图形的位于所述过孔中的部分位于所述第二子过孔中且位于所述第一绝缘层之上；
位于所述过孔中的第二电极图形的一端位于第一子过孔中，位于所述过孔中的第二电极图形的另一端位于第二子过孔中且位于所述第一电极图形之上。
在本发明的实施例提供的显示基板及其制造方法和显示装置的技术方案中，第一绝缘层和第二绝缘层对应第一金属层正上方的位置设置有过孔，第一电极图形的一端与第二金属层连接，第一电极图形的另一端延伸至过孔内，第二电极图形位于过孔内且与第一电极图形连接，第二电极图形还与第一金属层连接，以实现第一金属层和第二金属层的连接，本发明的实施例采用一个过孔对不同的金属层进行连接，降低了过孔的分布密度，从而降低了后续工艺中产生各种不良现象的机率。在本发明的实施例中，仅采用一个多孔对不同的金属层进行连接且作为连接介质的第二电极图形位于过孔中，使得第二电极图形无需位于过孔周围的台阶处和拐角处，可以缓解或避免由过孔周围的台阶处和拐角处引起的第二电极图形发生腐蚀的现象，从而减轻或避免第二电极图形发生劣化断路、线路不良和异常显示等问题。
附图说明
图1为现有技术中H-ADSDS显示基板的结构示意图；
图2为本发明的一个实施例提供的显示基板的结构示意图；
图3为本发明的另一实施例提供的显示基板的结构示意图；
图4a为在本发明的另一实施例中形成第一金属层的示意图；
图4b为在本发明的另一实施例中形成第一绝缘层的示意图；
图4c为在本发明的另一实施例中形成第二金属层的示意图；
图4d为在本发明的另一实施例中形成第一电极图形的示意图；
图4e为在本发明的另一实施例中形成第二绝缘层的示意图；
图4f为在本发明的另一实施例中形成过孔的示意图；
图5a为在本发明的又一实施例中形成第一金属层的示意图；
图5b为在本发明的又一实施例中形成第一绝缘层的示意图；
图5c为在本发明的又一实施例中形成有源层的示意图；
图5d为在本发明的又一实施例中形成第一电极图形的示意图；
图5e为在本发明的又一实施例中形成第二金属层的示意图；
图5f为在本发明的又一实施例中形成第二绝缘层的示意图；
图5g为在本发明的又一实施例中形成过孔的示意图。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图对本发明提供的显示基板及其制造方法和显示装置的实施例进行详细描述。
图2为本发明的一个实施例提供的显示基板的结构示意图，如图2所示，该显示基板包括：衬底基板11和形成于衬底基板11上方的第一金属层12、第二金属层13、第一电极图形14、第二电极图形15、第一绝缘层16和第二绝缘层17，第一绝缘层16位于第一金属层12之上，第二绝缘层17位于第一绝缘层16的上方，第一电极图形14和第二金属层13位于第一绝缘层16和第二绝缘层17之间。第一绝缘层16和第二绝缘层17对应于第一金属层12正上方的位置设置有过孔18，第一电极图形14的一端与第二金属层13连接，第一电极图形14的另一端延伸至过孔18内，第二电极图形15位于过孔18内且与第一电极图形14连接，第二电极图形15还与第一金属层12连接。
本实施例中，第一电极图形14分别与第二电极图形15和第二金属层13连接，且第二电极图形15与第一金属层12连接，从而实现了第一金属层12和第二金属层13连接。
在一个实施例中，过孔18可包括设置于第一绝缘层16上的第一子过孔181和设置于第二绝缘层17上的第二子过孔182，第一子过孔181和第二子过孔182连通且第二子过孔182的宽度大于第一子过孔181的宽度。第一电极图形14的位于过孔18中的部分位于第二子过孔182中且位于第一绝缘层16之上。位于过孔18中的第二电极图形15的一端位于第一子过孔181中，位于过孔18中的第二电极图形15的另一端位于第二子过孔182中且位于第一电极图形14之上。需要说明的是：图2的过孔18中的虚线是为了分隔第一子过孔181和第二子过 孔182。
在另一实施例中，过孔18靠近第二金属层13的一侧可以为台阶状。采用台阶状的过孔，可以避免采用直接隧穿第一绝缘层和第二绝缘层的深刻孔(即深度较大的过孔)，从而可以减轻或避免由于深刻孔的深度过大而导致的后续工艺中的各种不良，例如：可以避免配向膜工艺中配向膜扩散不均形成斑点(mura)，并且可以有效地预防电极层倒角的出现，缓解或避免发生断路的现象。
在一个实施例中，第二金属层13位于第一电极图形14之下。具体地，第二金属层13位于第一绝缘层16的上方，第一电极图形14部分位于第二金属层13之上且部分位于第一绝缘层16之上。
在一个实施例中，第一金属层12为栅极金属层，第二金属层13为源/漏金属层。替代性地，在实际应用中，第一金属层12还可以为源/漏金属层，第二金属层13还可以为栅金属层，此种情况不再具体用附图示出。
进一步地，该显示基板还可以包括有源层21。有源层21可以位于第二金属层13之下，且位于第一绝缘层16之上。
在一个实施例中，第一电极图形14可以位于第一电极层中，第一电极层可包括作为连接介质的结构和用于产生电场的结构，其中，作为连接介质的结构为第一电极图形14，图2中仅示出了第一电极图形14，用于产生电场的结构在本领域中是已知的，在此不再图示。
在一个实施例中，第二电极图形15可以位于第二电极层中，第二电极层可包括作为连接介质的结构和用于产生电场的结构，其中，作为连接介质的结构为第二电极图形15，图2中仅示出了第二电极图形15，用于产生电场的结构在本领域中是已知的，在此不再图示。
在一个实施例中，第一电极图形14和第二电极图形15的材料可以为透明导电材料，例如：铟锡氧化物(ITO)。
本实施例提供的显示基板中，第一绝缘层和第二绝缘层对应第一金属层正上方的位置设置有过孔，第一电极图形的一端延伸至过孔内，第一电极图形的另一端与第二金属层连接，第二电极图形位于过孔内且与第一电极图形连接，第二电极图形还与第一金属层连接，以实现第一金属层和第二金属层的连接，本实施例采用一个过孔对不同的金属层进行连接，可以降低过孔的分布密度，从而可以降低后续工艺中 产生各种不良现象的机率。在本实施例中，仅采用一个过孔对不同的金属层进行连接且作为连接介质的第二电极图形位于过孔中，使得第二电极图形无需位于过孔周围的台阶处和拐角处，可以避免由过孔周围的台阶处和拐角处引起的第二电极图形发生腐蚀的现象，从而减轻或避免第二电极图形发生劣化断路、线路不良和异常显示等问题。因此，本实施例在信赖性实验和良率方面均有较好的效果。
图3为本发明的另一实施例提供的显示基板的结构示意图，如图3所示，该显示基板包括：衬底基板11和形成于衬底基板11上方的第一金属层12、第二金属层13、第一电极图形14、第二电极图形15、第一绝缘层16和第二绝缘层17，第一绝缘层16位于第一金属层12之上，第二绝缘层17位于第一绝缘层16的上方，第一电极图形14和第二金属层13位于第一绝缘层16和第二绝缘层17之间。第一绝缘层16和第二绝缘层17对应于第一金属层12正上方的位置设置有过孔18，第一电极图形14的一端延伸至过孔18内，第一电极图形14的另一端与第二金属层13连接，第二电极图形15位于过孔18内且与第一电极图形14连接，第二电极图形15还与第一金属层12连接。
本实施例中，第一电极图形14分别与第二电极图形15和第二金属层13连接，且第二电极图形15与第一金属层12连接，从而实现了第一金属层12和第二金属层13连接。
在一个实施例中，过孔18可包括设置于第一绝缘层16上的第一子过孔181和设置于第二绝缘层17上的第二子过孔182，第一子过孔181和第二子过孔182连通且第二子过孔182的宽度大于第一子过孔181的宽度。第一电极图形14的位于过孔18中的部分位于第二子过孔182中且位于第一绝缘层16之上。位于过孔18中的第二电极图形15的一端位于第一子过孔181中，位于过孔18中的第二电极图形15的另一端位于第二子过孔182中且位于第一电极图形14之上。需要说明的是：图2的过孔18中的虚线是为了分隔第一子过孔181和第二子过孔182。
在一个实施例中，过孔18靠近第二金属层13的一侧为台阶状。采用台阶状的过孔，可以避免采用直接隧穿第一绝缘层和第二绝缘层的深刻孔，(即深度较大的过孔)，从而可以减轻或避免由于深刻孔的深度过大而导致的后续工艺中的各种不良，例如：可以避免配向膜 工艺中配向膜扩散不均形成斑点(mura)，并且从而可以有效预防电极层倒角的出现，减轻或避免发生断路的现象。
本实施例中，第二金属层13位于第一电极图形14之上。具体地，第一电极图形14位于第一绝缘层16之上，第二绝缘层17位于第二金属层13之上。
在一个实施例中，第一金属层12为栅极金属层，第二金属层13为源/漏金属层。替代性地，在实际应用中，第一金属层12还可以为源/漏金属层，第二金属层13还可以为栅金属层，此种情况不再具体用附图示出。
进一步地，该显示基板还可以包括有源层21。有源层21可以位于第一绝缘层16之上，且位于第一电极图形14之下。
在一个实施例中，第一电极图形14可位于第一电极层中，第一电极层可包括作为连接介质的结构和用于产生电场的结构，其中，作为连接介质的结构为第一电极图形14，图3中仅示出了第一电极图形14，用于产生电场的结构在本领域中是已知的，在此不再具体示出。
在一个实施例中，第二电极图形15可位于第二电极层中，第二电极层可包括作为连接介质的结构和用于产生电场的结构，其中，作为连接介质的结构为第二电极图形15，图3中仅示出了第二电极图形15，用于产生电场的结构在本领域中是已知的，在此不再具体示出。
在一个实施例中，第一电极图形14和第二电极图形15的材料可以为透明导电材料，例如：铟锡氧化物(ITO)。
本实施例提供的显示基板中，第一绝缘层和第二绝缘层对应第一金属层正上方的位置设置有过孔，第一电极图形的一端与第二金属层连接，第一电极图形的另一端延伸至过孔内，第二电极图形位于过孔内且与第一电极图形连接，第二电极图形还与第一金属层连接，以实现第一金属层和第二金属层的连接，本实施例采用一个过孔对不同的金属层进行连接，可以降低过孔的分布密度，从而可以降低后续工艺中产生各种不良现象的机率。在本实施例中，仅采用一个多孔对不同的金属层进行连接且作为连接介质的第二电极图形位于过孔中，使得第二电极图形无需位于过孔周围的台阶处和拐角处，可以减轻或避免由过孔周围的台阶处和拐角处引起的第二电极图形发生腐蚀的现象，从而可以减轻或避免第二电极图形发生劣化断路、线路不良和异常显 示等问题。因此，本实施例在信赖性实验和良率方面均有较好的效果。
本发明的另一实施例提供了一种显示装置，该显示装置包括：相对设置的显示基板和对置基板，其中，显示基板可以是上述实施例中任一实施例提供的显示基板。
在一个实施例中，显示基板可以为阵列基板，对置基板可以为彩膜基板。
在本实施例提供的显示装置中，第一绝缘层和第二绝缘层对应第一金属层正上方的位置设置有过孔，第一电极图形的一端与第二金属层连接，第一电极图形的另一端延伸至过孔内，第二电极图形位于过孔内且与第一电极图形连接，第二电极图形还与第一金属层连接，以实现第一金属层和第二金属层的连接，本实施例采用一个过孔对不同的金属层进行连接，可以降低过孔的分布密度，从而可以降低后续工艺中产生各种不良现象的机率。在本实施例中，仅采用一个过孔对不同的金属层进行连接且作为连接介质的第二电极图形位于过孔中，使得第二电极图形无需位于过孔周围的台阶处和拐角处，可以减轻或避免由过孔周围的台阶处和拐角处引起的第二电极图形发生腐蚀的现象，从而可以减轻或避免第二电极图形发生劣化断路、线路不良和异常显示等问题。因此，本实施例在信赖性实验和良率方面均有较好的效果。
本发明的又一实施例提供了一种显示基板的制造方法，该方法包括：
步骤101、在衬底基板的上方形成第一金属层、第一绝缘层、第二金属层、第一电极图形和第二绝缘层，第一绝缘层位于第一金属层之上，第二绝缘层位于第一绝缘层的上方，第一电极图形和第二金属层位于第一绝缘层和第二绝缘层之间，第一电极图形的一端与第二金属层连接。
具体地，步骤101包括：
步骤1011、在衬底基板之上形成第一金属层。
图4a为在一个实施例中形成第一金属层的示意图，如图4a所示，可以在衬底基板11之上形成第一金属层材料层，对第一金属层材料层进行构图工艺以在衬底基板11之上形成第一金属层12。
步骤1012、在第一金属层之上形成第一绝缘层。
图4b为在一个实施例中形成第一绝缘层的示意图，如图4b所示，可以在第一金属层12之上沉积第一绝缘层16。
步骤1013、在第一绝缘层上形成有源层和位于有源层之上的第二金属层。
图4c为在一个实施例中形成第二金属层的示意图，如图4c所示，可通过构图工艺在第一绝缘层16上形成有源层21和第二金属层13。具体地，可以在第一绝缘层16上连续沉积有源材料层和第二金属材料层，通过对有源材料层和第二金属材料层进行构图工艺以在第一绝缘层16上形成有源层21和第二金属层13。由于有源层21和第二金属层13可以通过一次构图工艺而形成。
步骤1014、在第二金属层之上形成第一电极图形。
图4d为在一个实施例中形成第一电极图形的示意图，如图4d所示，在衬底基板11之上形成第一电极图形材料层，通过对第一电极图形材料层进行构图工艺在衬底基板11之上形成第一电极图形14。该第一电极图形14部分位于第二金属层13之上且部分位于第一金属层12的上方。
步骤1015、在第一电极图形之上形成第二绝缘层。
图4e为在一个实施例中形成第二绝缘层的示意图，如图4e所示，在第一电极图形14之上沉积第二绝缘层17。
步骤102、在第一绝缘层和第二绝缘层对应所述第一金属层正上方的位置形成过孔，第一电极图形的另一端延伸至过孔内。
图4f为在一个实施例中形成过孔的示意图，如图4f所示，通过对第一绝缘层16和第二绝缘层17进行构图工艺以形成过孔18，第一电极图形14的一部分位于过孔18中。在实施例中，可以通过一次构图工艺形成过孔18。本实施例中，过孔18包括设置于第一绝缘层16中的第一子过孔181和设置于第二绝缘层17中的第二子过孔182，第一子过孔181和第二子过孔182连通且第二子过孔182的宽度大于第一子过孔181的宽度；第一电极图形14的位于过孔18中的部分位于第二子过孔182中且位于第一绝缘层16之上。在过孔18中，由于第一电极图形14的一部分的遮挡作用，使得过孔18的靠近第二金属层13的一侧为台阶状。
步骤103、在衬底基板的上方形成第二电极图形，第二电极图形位 于过孔内且与第一电极图形连接，第二电极图形还与第一金属层连接。
如图2所示，在第二绝缘层17之上形成第二电极图形材料层，通过对第二电极图形材料层进行构图工艺在衬底基板11的上方形成第二电极图形15。第二电极图形15位于过孔18内且与第一电极图形14连接，第二电极图形15还与第一金属层12连接，从而实现第一金属层12和第二金属层13连接。
在上述实施例中，步骤1011、步骤1013、步骤1014、步骤102和步骤103均可通过构图工艺实现。
本实施例提供的显示基板的制造方法可用于制造上述的如图2所示的实施例提供的显示基板，对显示基板的具体描述可参见之前的实施例，此处不再赘述。
采用本实施例提供的显示基板的制造方法制造出的显示基板中，第一绝缘层和第二绝缘层对应第一金属层正上方的位置设置有过孔，第一电极图形的一端与第二金属层连接，第一电极图形的另一端延伸至过孔内，第二电极图形位于过孔内且与第一电极图形连接，第二电极图形还与第一金属层连接，以实现第一金属层和第二金属层的连接，本实施例采用一个过孔对不同的金属层进行连接，可以降低过孔的分布密度，从而可以降低后续工艺中产生各种不良现象的机率。在本实施例中，仅采用一个过孔对不同的金属层进行连接且作为连接介质的第二电极图形位于过孔中，使得第二电极图形无需位于过孔周围的台阶处和拐角处，可以减轻或避免由过孔周围的台阶处和拐角处引起的第二电极图形发生腐蚀的现象，从而减轻或避免第二电极图形发生劣化断路、线路不良和异常显示等问题。因此，本实施例在信赖性实验和良率方面均有较好的效果。
本发明的又一实施例提供了另一种显示基板的制造方法，该方法包括：
步骤201、在衬底基板的上方形成第一金属层、第一绝缘层、第二金属层、第一电极图形和第二绝缘层，第一绝缘层位于第一金属层之上，第二绝缘层位于第一绝缘层的上方，第一电极图形和第二金属层位于第一绝缘层和第二绝缘层之间，第一电极图形的一端与第二金属层连接。具体地，步骤201可包括：
步骤2011、在衬底基板之上形成所述第一金属层。
图5a为在一个实施例中形成第一金属层的示意图，如图5a所示，在衬底基板11之上形成第一金属层材料层，对第一金属层材料层进行构图工艺以在衬底基板11之上形成第一金属层12。
步骤2012、在第一金属层之上形成第一绝缘层。
图5b为在一个实施例中形成第一绝缘层的示意图，如图5b所示，在第一金属层12之上沉积第一绝缘层16。
步骤2013、在第一绝缘层之上形成有源层。
具体地，如图5c所示，可以在第一绝缘层16之上形成有源层材料层，对有源层材料层进行构图工艺形成有源层21。
步骤2014、在衬底基板的上方形成第一电极图形。
图5d为一个实施例中形成第一电极图形的示意图，如图5d所示，在衬底基板11的上方形成第一电极图形材料层，通过对第一电极图形材料层进行构图工艺在衬底基板11的上方形成第一电极图形14。该第一电极图形14位于第一绝缘层16之上，且可以覆盖有源层21。
步骤2015、在第一电极图形之上形成第二金属层。
图5e为在一个实施例中形成第二金属层的示意图，如图5e所示，可通过构图工艺在第一电极图形14之上形成第二金属层13。例如，，可以在第一电极图形14上沉积第二金属层材料层，通过对第二金属层材料层进行构图工艺以在第一电极图形14之上形成第二金属层13。
步骤2016、在第二金属层之上形成第二绝缘层。
图5f为在一个实施例中形成第二绝缘层的示意图，如图5f所示，在第二金属层13之上沉积第二绝缘层17。
步骤202、在第一金属层上方的第一绝缘层和第二绝缘层上形成过孔，部分第一电极图形位于过孔中。
图5g为一个实施例中形成过孔的示意图，如图5g所示，可以通过对第一绝缘层16和第二绝缘层17进行构图工艺以形成过孔18，部分第一电极图形14位于过孔18中。在实施例中，可以通过一次构图工艺形成过孔18。本实施例中，过孔18包括设置于第一绝缘层16中的第一子过孔181和设置于第二绝缘层17中的第二子过孔182，第一子过孔181和第二子过孔182连通且第二子过孔182的宽度大于第一子过孔181的宽度；第一电极图形14的位于过孔18中的部分位于第二子过孔182中且位于第一绝缘层16之上。在过孔18中由于部分第 一电极图形14的遮挡作用，使得过孔18的靠近第二金属层13的一侧为台阶状。
步骤203、在衬底基板的上方形成第二电极图形，第二电极图形位于过孔内且与第一电极图形连接，第二电极图形还与第一金属层连接。
如图3所示，在第二绝缘层17之上形成第二电极图形材料层，通过对第二电极图形材料层进行构图工艺在衬底基板11的上方形成第二电极图形15。第二电极图形15位于过孔18内且与第一电极图形14连接，第二电极图形15还与第一金属层12连接，从而实现第一金属层12和第二金属层13连接。
本实施例中，步骤2011、步骤2013、步骤2014、步骤2015、步骤202和步骤203均可通过构图工艺实现。
本实施例提供的显示基板的制造方法可用于制造上述的如图3所示的实施例提供的显示基板，对显示基板的具体描述可参见之前的实施例，此处不再赘述。
采用本实施例提供的显示基板的制造方法制造出的显示基板中，第一绝缘层和第二绝缘层对应第一金属层正上方的位置设置有过孔，第一电极图形的一端与第二金属层连接，第一电极图形的另一端延伸至过孔内，第二电极图形位于过孔内且与第一电极图形连接，第二电极图形还与第一金属层连接，以实现第一金属层和第二金属层的连接，本实施例采用一个过孔对不同的金属层进行连接，可以降低过孔的分布密度，从而可以降低后续工艺中产生各种不良现象的机率。在本实施例中，仅采用一个过孔对不同的金属层进行连接且作为连接介质的第二电极图形位于过孔中，使得第二电极图形无需位于过孔周围的台阶处和拐角处，可以减轻或避免由过孔周围的台阶处和拐角处引起的第二电极图形发生腐蚀的现象，从而可以减轻或避免第二电极图形发生劣化断路、线路不良和异常显示等问题。因此，本实施例在信赖性实验和良率方面均有较好的效果。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。
在权利要求中，词语“包括”并未排除除了权利要求中所列举的那些之外的元件或步骤的存在。元件之前的词语“一”或“一个”并未排除多个这样的元件的存在。某些特征被记载在相互不同从属权利要求中这一纯粹事实并不意味着这些特征的组合不能被有利地使用。

Claims (10)

  1. 一种显示基板，包括：衬底基板和形成于所述衬底基板上方的第一金属层、第二金属层、第一电极图形、第二电极图形、第一绝缘层和第二绝缘层，其中所述第一绝缘层位于所述第一金属层之上，所述第二绝缘层位于所述第一绝缘层的上方，所述第一电极图形和所述第二金属层位于所述第一绝缘层和所述第二绝缘层之间；
    所述第一绝缘层和第二绝缘层对应所述第一金属层正上方的位置设置有过孔，所述第一电极图形的一端与所述第二金属层连接，所述第一电极图形的另一端延伸至所述过孔内，所述第二电极图形位于所述过孔内且与所述第一电极图形连接，所述第二电极图形还与第一金属层连接。
  2. 根据权利要求1所述的显示基板，其中所述过孔包括设置于所述第一绝缘层中的第一子过孔和设置于所述第二绝缘层中的第二子过孔，所述第一子过孔和所述第二子过孔连通且所述第二子过孔的宽度大于所述第一子过孔的宽度；
    所述第一电极图形的位于所述过孔中的部分位于所述第二子过孔中且位于所述第一绝缘层之上；
    位于所述过孔中的第二电极图形的一端位于第一子过孔中，位于所述过孔中的第二电极图形的另一端位于第二子过孔中且位于所述第一电极图形之上。
  3. 根据权利要求2所述的显示基板，其中所述过孔靠近所述第二金属层的一侧为台阶状。
  4. 根据权利要求1所述的显示基板，其中所述第二金属层位于第一电极图形之下，或者所述第二金属层位于所述第一电极图形之上。
  5. 根据权利要求1所述的显示基板，其中所述第一金属层为栅极金属层，所述第二金属层为源/漏金属层；或者，
    所述第一金属层为源/漏金属层，所述第二金属层为栅金属层。
  6. 一种显示装置，包括：相对设置的显示基板和对置基板，所述显示基板是上述权利要求1至5任一所述的显示基板。
  7. 一种显示基板的制造方法，包括：
    在衬底基板的上方形成第一金属层、第一绝缘层、第二金属层、 第一电极图形和第二绝缘层，所述第一绝缘层位于所述第一金属层之上，所述第二绝缘层位于所述第一绝缘层的上方，所述第一电极图形和所述第二金属层位于所述第一绝缘层和所述第二绝缘层之间，所述第一电极图形的一端与所述第二金属层连接；
    在第一绝缘层和第二绝缘层对应所述第一金属层正上方的位置形成过孔，所述第一电极图形的另一端延伸至所述过孔内；
    在所述衬底基板的上方形成所述第二电极图形，所述第二电极图形位于所述过孔内且与所述第一电极图形连接，所述第二电极图形还与第一金属层连接。
  8. 根据权利要求7所述的显示基板的制造方法，其中所述在衬底基板的上方形成第一金属层、第一绝缘层、第二金属层、第一电极图形和第二绝缘层的步骤包括：
    在所述衬底基板之上形成所述第一金属层；
    在所述第一金属层之上形成所述第一绝缘层；
    在所述第一绝缘层上形成有源层和位于有源层之上的第二金属层；
    在所述第二金属层之上形成所述第一电极图形；
    在所述第一电极图形之上形成所述第二绝缘层。
  9. 根据权利要求7所述的显示基板的制造方法，其中所述在衬底基板的上方形成第一金属层、第一绝缘层、第二金属层、第一电极图形和第二绝缘层的步骤包括：
    在所述衬底基板之上形成所述第一金属层；
    在所述第一金属层之上形成所述第一绝缘层；
    在所述第一绝缘层之上形成有源层；
    在所述衬底基板的上方形成所述第一电极图形；
    在所述第一电极图形之上形成所述第二金属层；
    在所述第二金属层之上形成所述第二绝缘层。
  10. 根据权利要求7所述的显示基板的制造方法，其中所述过孔包括设置于所述第一绝缘层中的第一子过孔和设置于所述第二绝缘层中的第二子过孔，所述第一子过孔和所述第二子过孔连通且所述第二子过孔的宽度大于所述第一子过孔的宽度；
    所述第一电极图形的位于所述过孔中的部分位于所述第二子过孔 中且位于所述第一绝缘层之上；
    位于所述过孔中的第二电极图形的一端位于第一子过孔中，位于所述过孔中的第二电极图形的另一端位于第二子过孔中且位于所述第一电极图形之上。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111799301A (zh) * 2019-04-02 2020-10-20 三星显示有限公司 显示装置

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104678671B (zh) * 2015-03-30 2018-12-21 京东方科技集团股份有限公司 显示基板及其制造方法和显示装置
CN107168582B (zh) * 2017-05-25 2019-11-12 上海天马微电子有限公司 一种触控显示面板
CN107564922B (zh) * 2017-09-19 2020-03-13 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN107591417B (zh) * 2017-09-22 2020-12-04 京东方科技集团股份有限公司 阵列基板及其制备方法
CN113327944A (zh) * 2021-06-02 2021-08-31 福建华佳彩有限公司 一种tft基板及其制造方法
CN114509902B (zh) * 2022-01-27 2023-01-31 绵阳惠科光电科技有限公司 阵列基板及其制备方法、显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011212869A (ja) * 2010-03-31 2011-10-27 Seiko Epson Corp 圧電アクチュエータ、液滴噴射ヘッドおよび液滴噴射装置
CN103474472A (zh) * 2013-09-10 2013-12-25 深圳市华星光电技术有限公司 一种薄膜晶体管、阵列基板及显示面板
CN103872061A (zh) * 2012-12-10 2014-06-18 乐金显示有限公司 阵列基板及其制造方法
CN104678671A (zh) * 2015-03-30 2015-06-03 京东方科技集团股份有限公司 显示基板及其制造方法和显示装置
CN204557028U (zh) * 2015-03-30 2015-08-12 京东方科技集团股份有限公司 显示基板和显示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5943559A (en) * 1997-06-23 1999-08-24 Nec Corporation Method for manufacturing liquid crystal display apparatus with drain/source silicide electrodes made by sputtering process
KR100620847B1 (ko) * 2001-06-05 2006-09-13 엘지.필립스 엘시디 주식회사 액정표시장치의 어레이기판 및 그의 제조방법
JP4275038B2 (ja) * 2004-09-01 2009-06-10 シャープ株式会社 アクティブマトリクス基板およびそれを備えた表示装置
CN101526707B (zh) * 2008-03-07 2011-10-12 北京京东方光电科技有限公司 Tft-lcd阵列基板制造方法
CN102280436B (zh) * 2010-06-09 2014-08-06 北京京东方光电科技有限公司 薄膜金属层接线结构及其制造方法和阵列基板
CN102692771B (zh) * 2011-05-09 2014-12-17 京东方科技集团股份有限公司 一种液晶显示器、薄膜晶体管阵列基板及其制造方法
CN103715135B (zh) * 2013-12-16 2016-04-06 京东方科技集团股份有限公司 一种过孔及其制作方法、阵列基板
CN103715267A (zh) * 2013-12-30 2014-04-09 京东方科技集团股份有限公司 薄膜晶体管、tft阵列基板及其制造方法和显示装置
CN203941365U (zh) * 2014-07-09 2014-11-12 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置
CN104183607A (zh) * 2014-08-14 2014-12-03 深圳市华星光电技术有限公司 阵列基板及其制造方法、显示装置
CN104269413B (zh) * 2014-09-22 2017-08-11 京东方科技集团股份有限公司 阵列基板及其制作方法、液晶显示装置
CN104392990B (zh) * 2014-11-25 2018-07-13 合肥鑫晟光电科技有限公司 一种阵列基板及显示装置
CN104465510A (zh) * 2014-12-11 2015-03-25 京东方科技集团股份有限公司 一种阵列基板及其制作方法和显示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011212869A (ja) * 2010-03-31 2011-10-27 Seiko Epson Corp 圧電アクチュエータ、液滴噴射ヘッドおよび液滴噴射装置
CN103872061A (zh) * 2012-12-10 2014-06-18 乐金显示有限公司 阵列基板及其制造方法
CN103474472A (zh) * 2013-09-10 2013-12-25 深圳市华星光电技术有限公司 一种薄膜晶体管、阵列基板及显示面板
CN104678671A (zh) * 2015-03-30 2015-06-03 京东方科技集团股份有限公司 显示基板及其制造方法和显示装置
CN204557028U (zh) * 2015-03-30 2015-08-12 京东方科技集团股份有限公司 显示基板和显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111799301A (zh) * 2019-04-02 2020-10-20 三星显示有限公司 显示装置

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