WO2017156877A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2017156877A1
WO2017156877A1 PCT/CN2016/083644 CN2016083644W WO2017156877A1 WO 2017156877 A1 WO2017156877 A1 WO 2017156877A1 CN 2016083644 W CN2016083644 W CN 2016083644W WO 2017156877 A1 WO2017156877 A1 WO 2017156877A1
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Prior art keywords
conductive
conductive pattern
forming
pillar
insulating layer
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PCT/CN2016/083644
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English (en)
French (fr)
Inventor
任锦宇
王丹
徐长健
马国靖
周波
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/512,582 priority Critical patent/US10871688B2/en
Publication of WO2017156877A1 publication Critical patent/WO2017156877A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • an array substrate including a first conductive pattern, an insulating layer covering the first conductive pattern, and a second conductive pattern on the insulating layer, the insulating layer including a useful to connect the first And a conductive via and a via of the second conductive pattern, wherein the via is formed with a conductive pillar connected to the first conductive pattern and the second conductive pattern.
  • the conductive pillar is made of an organic conductive polymer or a metal.
  • the conductive post is composed of a resin pillar and a conductive material encasing the resin pillar.
  • an outer surface of the conductive post is in contact with the entire inner surface of the via.
  • the first conductive pattern is a drain of the thin film transistor; and the second conductive pattern is a pixel electrode.
  • the pixel electrode covers an upper surface of the conductive pillar.
  • the insulating layer includes a passivation layer.
  • first conductive pattern is a common electrode line; and the second conductive pattern is a common electrode.
  • the common electrode covers an upper surface of the conductive pillar.
  • the insulating layer includes a gate insulating layer and a passivation layer.
  • Embodiments of the present disclosure also provide a display device including the array substrate as described above.
  • the embodiment of the present disclosure further provides a method for fabricating an array substrate, the array substrate includes a first conductive pattern, an insulating layer covering the first conductive pattern, and a second conductive pattern on the insulating layer, the insulating layer A via is included to connect the first conductive pattern and the second conductive pattern, the method comprising:
  • the first conductive pattern is a drain of the thin film transistor
  • the second conductive pattern is a pixel electrode
  • the insulating layer includes a passivation layer
  • a pixel electrode is formed, the pixel electrode being connected to the conductive pillar.
  • the first conductive pattern is a drain of the thin film transistor
  • the second conductive pattern is a pixel electrode
  • the insulating layer includes a passivation layer
  • a pixel electrode is formed, the pixel electrode being connected to the conductive pillar.
  • the first conductive pattern is a common electrode line
  • the second conductive pattern is a common electrode
  • the insulating layer includes a gate insulating layer and a passivation layer
  • a common electrode is formed, the common electrode being connected to the conductive post.
  • a conductive pillar is formed at the via hole in the insulating layer, and the conductive pillar is respectively connected to the first conductive pattern and the second conductive pattern located in different film layers, thereby passing the first conductive pattern and the first conductive pattern through the conductive pillar
  • the conductive pattern is turned on, and since the conductive pillar can fill the via hole, planarization at the via hole can be realized, and the recess at the via hole can be avoided, thereby solving the diffusion of the alignment film at the via hole.
  • the poor Mura caused by the unevenness improves the display effect of the display device.
  • FIG. 1 is a schematic diagram of a pixel electrode via in an array substrate in the related art
  • FIG. 2 is a schematic view of a common electrode via in an array substrate in the related art
  • FIG. 3 is a schematic structural diagram of an array substrate in at least some embodiments of the present disclosure.
  • FIG. 4 is a schematic flow chart of a method for fabricating the array substrate shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram of an array substrate in at least some embodiments of the present disclosure.
  • FIG. 6 is a schematic flow chart of a method for fabricating the array substrate shown in FIG. 5;
  • FIG. 7 is a schematic structural diagram of an array substrate in at least some embodiments of the present disclosure.
  • FIG. 8 is a schematic flow chart of a method of fabricating the array substrate shown in FIG. 7.
  • FIG. 8 is a schematic flow chart of a method of fabricating the array substrate shown in FIG. 7.
  • the embodiments of the present disclosure are directed to the prior art that the recess is easily formed at the via hole, which causes the alignment film to easily spread unevenly at the via hole when the alignment film is coated on the array substrate, and provides an array substrate and the fabrication thereof.
  • the method and the display device can solve the Mura defect caused by the uneven diffusion of the alignment film at the via hole, and improve the display effect of the display device.
  • the via holes include pixel electrodes that connect the pixel electrodes 6 and the drains of the thin film transistors.
  • the via hole 7 further includes a common electrode via hole 9 connecting the common electrode 8 and the common electrode connection line.
  • the size of the via hole is generally 7 ⁇ m*7 ⁇ m, and the via holes are generally narrow and deep, so that it is easy at the via hole.
  • the embodiment provides an array substrate, including a first conductive pattern, an insulating layer covering the first conductive pattern, and a second conductive pattern on the insulating layer, wherein the insulating layer includes And connecting via holes of the first conductive pattern and the second conductive pattern, wherein the via holes are formed with conductive pillars connected to the first conductive pattern and the second conductive pattern.
  • a conductive pillar is formed at the via hole in the insulating layer, and the conductive pillar is respectively connected to the first conductive pattern and the second conductive pattern located in different film layers, thereby passing the first conductive pattern and the second through the conductive pillar
  • the conductive pattern is turned on. Since the conductive pillar can fill the via hole, the planarization of the via hole can be realized, and the recess at the via hole can be avoided, thereby solving the Mura defect caused by the uneven diffusion of the alignment film at the via hole, and improving the display. The display effect of the device.
  • the level of the upper surface of the conductive post is not lower than the level of the upper surface of the insulating layer, so that the recess at the via hole can be avoided.
  • the level of the upper surface of the conductive post coincides with the level of the upper surface of the insulating layer, which enables the via to be flat.
  • the conductive pillars may be made of an organic conductive polymer or metal.
  • the main body of the conductive pillar may be a resin pillar, and a conductive material is wrapped around the resin pillar.
  • At least some embodiments of the present disclosure provide a method of fabricating an array substrate, the array substrate including a first conductive pattern, an insulating layer covering the first conductive pattern, and a second conductive pattern on the insulating layer;
  • the layer includes vias that are used to connect the first conductive pattern and the second conductive pattern.
  • the method includes forming a conductive pillar connected to the first conductive pattern in the via hole before forming the second conductive pattern, and forming a second conductive pattern connected to the conductive pillar.
  • a conductive pillar is formed at the via hole in the insulating layer, and the conductive pillar is connected with the first conductive pattern under the insulating layer, thereby passing the conductive pillar
  • the first conductive pattern and the second conductive pattern are turned on. Since the conductive pillar can fill the via hole, planarization at the via hole can be realized, and the recess at the via hole can be avoided, thereby solving the uneven diffusion of the alignment film at the via hole.
  • the resulting Mura is poor, improving the display effect of the display device.
  • the first conductive pattern is a drain of the thin film transistor
  • the second conductive pattern is a pixel electrode
  • the manufacturing method specifically includes:
  • a pixel electrode is formed, the pixel electrode being connected to the conductive pillar.
  • the source and the drain of the conductive pillar and the thin film transistor are simultaneously formed by one patterning process, and the conductive pillar can be formed without increasing the number of patterning processes, thereby simplifying the fabrication process of the array substrate.
  • the first conductive pattern is a drain of the thin film transistor
  • the second conductive pattern is a pixel electrode
  • the manufacturing method specifically includes:
  • a pixel electrode is formed, the pixel electrode being connected to the conductive pillar.
  • the gates of the conductive pillars and the thin film transistors are simultaneously formed by one patterning process, and the conductive pillars can be formed without increasing the number of patterning processes, thereby simplifying the fabrication process of the array substrate.
  • the first conductive pattern is a common electrode line
  • the second conductive pattern is a common electrode
  • the manufacturing method specifically includes:
  • a common electrode is formed, the common electrode being connected to the conductive post.
  • the gate and the common electrode line of the conductive pillar and the thin film transistor are simultaneously formed by one patterning process, and the conductive pillar can be formed without increasing the number of patterning processes, thereby simplifying the fabrication process of the array substrate.
  • At least some embodiments of the present disclosure provide a method of fabricating an array substrate, as shown in FIGS. 3-4, which includes the following steps 31-35.
  • Step 31 A base substrate 1 is provided. On the base substrate 1, a conductive pillar 10 and a gate line formed by the gate metal layer 2, a common electrode line, and a gate electrode are formed, and the conductive pillar 10 is connected to the common electrode line.
  • the base substrate 1 may be a glass substrate or a quartz substrate.
  • the conductive pillar 10 can be made of the same material as the gate metal layer, such that the conductive pillar 10 can be formed simultaneously with the gate line, the common electrode line, and the gate by one patterning process.
  • the conductive pillar 10 can also be made of an organic conductive polymer.
  • the main body of the conductive pillar 10 may be a resin pillar, and a conductive material is wrapped around the resin pillar.
  • the conductive pillar 10 and the gate line, the common electrode line, and the gate of the thin film transistor are formed by different patterning processes.
  • a resin pillar may be prepared in advance at a predetermined position, and then a gate metal layer or a source/drain metal on the resin pillar may be left when a gate metal layer or a source/drain metal layer is subsequently formed.
  • the layer serves as a conductive material that encapsulates the resin pillars.
  • Step 32 A pattern of the gate insulating layer 3 and the active layer is formed on the base substrate 1 subjected to the step 31, and the gate insulating layer 3 is etched to expose the conductor post 10.
  • Step 33 forming a drain, a source, and a data line of a thin film transistor composed of a source/drain metal layer on the base substrate 1 subjected to the step 32.
  • Step 34 Forming a passivation layer 5 on the substrate 1 through the step 33, and etching the passivation layer 5 to expose the conductive pillars 10.
  • the gate insulating layer 3 may not be etched first, and after the passivation layer 5 is formed, the gate insulating layer 3 and the passivation layer 5 are etched together to expose the conductive pillars 10;
  • Step 35 A common electrode 8 is formed on the base substrate 1 which has passed through step 34, and the common electrode 8 is connected to the conductive post 10 to form a structure as shown in FIG.
  • the conductive pillar 10 can fill the via hole connecting the common electrode and the common electrode line, planarization at the via hole can be realized, and the recess at the via hole can be avoided, thereby solving the problem that the alignment film at the via hole is not diffused.
  • the Mura caused by the failure is improved, and the display effect of the display device is improved.
  • At least some embodiments of the present disclosure also provide a method for fabricating an array substrate. As shown in FIGS. 5-6, the embodiment includes the following steps 41-45.
  • Step 41 providing a substrate 1 on which a conductive pillar 10 and a gate line composed of a gate metal layer and a gate of a thin film transistor are formed;
  • the base substrate 1 may be a glass substrate or a quartz substrate.
  • the conductive pillar 10 can be made of the same material as the gate metal layer, such that the conductive pillar 10 can be formed simultaneously with the gate line and the gate of the thin film transistor by one patterning process; the conductive pillar 10 can also be made of an organic conductive polymer.
  • the main body of the conductive pillar 10 may be a resin pillar, and a conductive material is wrapped around the resin pillar.
  • the conductive pillar 10 and the gate line and the gate of the thin film transistor are formed by different patterning processes.
  • a resin pillar may be prepared in advance at a predetermined position, and then a gate metal layer or a source/drain metal on the resin pillar may be left when a gate metal layer or a source/drain metal layer is subsequently formed.
  • the layer serves as a conductive material that encapsulates the resin pillars.
  • Step 42 A pattern of the gate insulating layer 3 and the active layer is formed on the base substrate 1 subjected to the step 41, and the gate insulating layer 3 is etched to expose the conductor post 10.
  • Step 43 The drain, the source, and the data line of the thin film transistor composed of the source/drain metal layer 4 are formed on the base substrate 1 subjected to the step 42, and the drain of the thin film transistor is connected to the conductive post 10.
  • Step 44 Forming a passivation layer 5 on the base substrate 1 through the step 43 and etching the passivation layer 5 to expose the conductive pillars 10.
  • Step 45 Forming a pixel electrode 6 on the base substrate 1 through the step 44, and the pixel electrode 6 is connected to the conductive pillar 10 to form a structure as shown in FIG. 5.
  • the pixel electrode 6 is realized by the conductive pillar 10 and the drain of the thin film transistor. Electrical connection.
  • the conductive pillar 10 can fill the via hole connecting the pixel electrode and the drain of the thin film transistor, planarization at the via hole can be realized, and the recess at the via hole can be avoided, thereby solving the alignment film at the via hole.
  • the poor Mura caused by uneven diffusion improves the display effect of the display device.
  • At least some embodiments of the present disclosure also provide a method for fabricating an array substrate. As shown in FIGS. 7-8, the embodiment includes the following steps 51-55.
  • Step 51 A substrate 1 is provided, and a gate line and a gate electrode composed of the gate metal layer 2 are formed on the base substrate 1.
  • the base substrate 1 may be a glass substrate or a quartz substrate.
  • Step 52 A pattern of the gate insulating layer 3 and the active layer is formed on the base substrate 1 subjected to the step 51.
  • Step 53 forming a drain pillar, a source, and a data line of the conductive pillar 10 and the thin film transistor composed of the source/drain metal layer 4 on the base substrate 1 through the step 52, and connecting the drain of the thin film transistor to the conductive pillar 10;
  • the pillar 10 can be made of the same material as the source/drain metal layer 4, such that the conductive pillar 10 can be formed simultaneously with the drain, source and data lines of the thin film transistor by one patterning process; the conductive pillar 10 can also be made of an organic conductive polymer. .
  • the main body of the conductive pillar 10 may be a resin pillar, and a conductive material is wrapped around the resin pillar.
  • the conductive pillar 10 and the drain, the source and the data line of the thin film transistor are formed by different patterning processes.
  • a resin pillar may be prepared in advance at a predetermined position, and then a gate metal layer or a source/drain metal on the resin pillar may be left when a gate metal layer or a source/drain metal layer is subsequently formed.
  • the layer serves as a conductive material that encapsulates the resin pillars.
  • Step 54 Forming a passivation layer 5 on the base substrate 1 through the step 53, and etching the passivation layer 5 to expose the conductive pillars 10.
  • Step 55 Form the pixel electrode 6 on the substrate 1 through the step 54. As shown in FIG. 7, the pixel electrode 6 is connected to the conductive pillar 10, and the electrical connection with the drain of the thin film transistor is realized by the conductive pillar 10.
  • the conductive pillar 10 can fill the via hole connecting the pixel electrode and the drain of the thin film transistor, planarization at the via hole can be realized, and the recess at the via hole can be avoided, thereby solving the alignment film at the via hole.
  • the poor Mura caused by uneven diffusion improves the display effect of the display device.
  • the display device may be any product or component having a display function, such as a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device further includes a flexible circuit board, a printed circuit board, and a backboard.

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Abstract

一种阵列基板及其制作方法、显示装置。阵列基板包括第一导电图形（2）、覆盖该第一导电图形的绝缘层（3/5）、位于该绝缘层上的第二导电图形（8），该绝缘层包括有用以连接该第一导电图形和该第二导电图形的过孔（9），该过孔内形成有与该第一导电图形和第二导电图形连接的导电柱（10）。

Description

阵列基板及其制作方法、显示装置
相关申请的交叉引用
本申请主张在2016年3月14日在中国提交的中国专利申请号No.201610143214.3的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别是指一种阵列基板及其制作方法、显示装置。
背景技术
阵列基板中，为了将位于不同膜层的图形导通，需要制作过孔，过孔包括将像素电极和薄膜晶体管的漏极连接起来的像素电极导通过孔，还包括将公共电极与公共电极连接线连接起来的公共电极导通过孔，这些过孔一般都比较窄并且深，这样在过孔处容易出现凹陷，导致在阵列基板上涂覆配向膜时，配向膜容易在过孔处易发生扩散不均，导致最终的显示面板出现Mura(光斑)不良。
发明内容
本公开要解决的技术问题是提供一种阵列基板及其制作方法、显示装置，能够解决过孔处配向膜扩散不均引起的Mura不良，改善显示装置的显示效果。
为解决上述技术问题，本公开的实施例提供技术方案如下：
一方面，提供一种阵列基板，包括第一导电图形、覆盖所述第一导电图形的绝缘层、位于所述绝缘层上的第二导电图形，所述绝缘层包括有用以连接所述第一导电图形和所述第二导电图形的过孔，所述过孔内形成有与所述第一导电图形和第二导电图形连接的导电柱。
进一步地，所述导电柱上表面的水平高度不低于所述绝缘层上表面的水平高度。
进一步地，所述导电柱上表面的水平高度与所述绝缘层上表面的水平高 度一致。
进一步地，所述导电柱为采用有机导电聚合物或金属制成。
进一步地，所述导电柱由树脂柱状物和包裹所述树脂柱状物的导电材料组成。
进一步地，所述导电柱的外表面与所述过孔的整个内表面接触。
进一步地，所述第一导电图形为薄膜晶体管的漏极；所述第二导电图形为像素电极。
进一步地，所述像素电极覆盖所述导电柱的上表面。
进一步地，所述绝缘层包括钝化层。
进一步地，所述第一导电图形为公共电极线；所述第二导电图形为公共电极。
进一步地，所述公共电极覆盖所述导电柱的上表面。
进一步地，所述绝缘层包括栅绝缘层和钝化层。
本公开实施例还提供了一种显示装置，包括如上所述的阵列基板。
本公开实施例还提供了一种阵列基板的制作方法，阵列基板包括第一导电图形、覆盖所述第一导电图形的绝缘层、位于所述绝缘层上的第二导电图形，所述绝缘层包括有用以连接所述第一导电图形和所述第二导电图形的过孔，所述方法包括：
在形成所述第二导电图形之前，在所述过孔内形成与所述第一导电图形连接的导电柱；
形成与所述导电柱连接的第二导电图形。
进一步地，所述第一导电图形为薄膜晶体管的漏极，所述第二导电图形为像素电极，所述绝缘层包括钝化层；所述制作方法具体包括：
提供一衬底基板；
在所述衬底基板上形成薄膜晶体管的栅极；
形成栅绝缘层；
形成有源层的图形；
通过一次构图工艺同时形成薄膜晶体管的源极、漏极和所述导电柱，所述导电柱与所述漏极连接；
形成钝化层，并对所述钝化层进行刻蚀暴露出所述导电柱；
形成像素电极，所述像素电极与所述导电柱连接。
进一步地，所述第一导电图形为薄膜晶体管的漏极，所述第二导电图形为像素电极，所述绝缘层包括钝化层；所述制作方法具体包括：
提供一衬底基板；
在所述衬底基板上通过一次构图工艺同时形成薄膜晶体管的栅极和所述导电柱；
形成栅绝缘层；
形成有源层的图形，并对所述栅绝缘层和有源层进行刻蚀暴露出所述导电柱；
形成薄膜晶体管的源极和漏极，所述漏极与所述导电柱连接；
形成钝化层，并对所述钝化层进行刻蚀暴露出所述导电柱；
形成像素电极，所述像素电极与所述导电柱连接。
进一步地，所述第一导电图形为公共电极线，所述第二导电图形为公共电极，所述绝缘层包括栅绝缘层和钝化层；所述制作方法具体包括：
提供一衬底基板；
在所述衬底基板上通过一次构图工艺同时形成薄膜晶体管的栅极、公共电极线和所述导电柱，所述导电柱与所述公共电极线连接；
形成栅绝缘层；
形成有源层的图形；
形成薄膜晶体管的源极和漏极；
形成钝化层，并对所述栅绝缘层和所述钝化层进行刻蚀暴露出所述导电柱；
形成公共电极，所述公共电极与所述导电柱连接。
本公开的实施例具有以下有益效果：
上述方案中，在绝缘层内的过孔处制作一个导电柱，该导电柱分别与位于不同膜层的第一导电图形和第二导电图形连接，从而通过该导电柱将第一导电图形和第二导电图形导通，由于该导电柱能够对过孔进行填充，因此可以实现过孔处的平坦化，避免过孔处出现凹陷，从而解决过孔处配向膜扩散 不均引起的Mura不良，改善显示装置的显示效果。
附图说明
图1为相关技术中的阵列基板中像素电极过孔的示意图；
图2为相关技术中的阵列基板中公共电极过孔的示意图；
图3为本公开至少一些实施例中的阵列基板的结构示意图；
图4为图3所示阵列基板的制作方法的流程示意图；
图5为本公开至少一些实施例中的阵列基板的结构示意图；
图6为图5所示阵列基板的制作方法的流程示意图；
图7为本公开至少一些实施例中的阵列基板的结构示意图；
图8为图7所示阵列基板的制作方法的流程示意图。
附图标记
1 衬底基板    2 栅金属层    3 栅绝缘层    4 源漏金属层
5 钝化层      6 像素电极    7 像素电极过孔   8 公共电极
9 公共电极过孔   10 导电柱
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
本公开的实施例针对相关技术中过孔处容易出现凹陷，导致在阵列基板上涂覆配向膜时，配向膜容易在过孔处易发生扩散不均的问题，提供一种阵列基板及其制作方法、显示装置，能够解决过孔处配向膜扩散不均引起的Mura不良，改善显示装置的显示效果。
如图1和图2所示，相关技术的阵列基板中，为了将位于不同膜层的图形导通，需要制作过孔，过孔包括将像素电极6和薄膜晶体管的漏极连接起来的像素电极过孔7，还包括将公共电极8与公共电极连接线连接起来的公共电极过孔9，过孔的尺寸一般为7μm*7μm，这些过孔一般都比较窄并且深，这样在过孔处容易出现凹陷，导致在阵列基板上涂覆配向膜时，配向膜容易在过孔处易发生扩散不均，导致最终的显示面板出现Mura不良。
为了解决上述问题，本实施例提供一种阵列基板，包括第一导电图形、覆盖所述第一导电图形的绝缘层、位于所述绝缘层上的第二导电图形，所述绝缘层包括有用以连接所述第一导电图形和所述第二导电图形的过孔，所述过孔内形成有与所述第一导电图形和第二导电图形连接的导电柱。
本实施例在绝缘层内的过孔处制作一个导电柱，该导电柱分别与位于不同膜层的第一导电图形和第二导电图形连接，从而通过该导电柱将第一导电图形和第二导电图形导通，由于该导电柱能够对过孔进行填充，因此可以实现过孔处的平坦化，避免过孔处出现凹陷，从而解决过孔处配向膜扩散不均引起的Mura不良，改善显示装置的显示效果。
可选地，导电柱上表面的水平高度不低于绝缘层上表面的水平高度，这样可以避免过孔处出现凹陷。
可选地，导电柱上表面的水平高度与绝缘层上表面的水平高度一致，这样能够使得过孔处平坦。
具体实施例中，导电柱可以采用有机导电聚合物或金属制成。
另一具体实施例中，导电柱的主体可以为树脂柱状物，在树脂柱状物外包裹有导电材料。
本公开至少一些实施例提供了一种阵列基板的制作方法，阵列基板包括第一导电图形、覆盖所述第一导电图形的绝缘层以及位于所述绝缘层上的第二导电图形；所述绝缘层包括有用以连接所述第一导电图形和所述第二导电图形的过孔。所述方法包括：在形成所述第二导电图形之前，在所述过孔内形成与所述第一导电图形连接的导电柱；形成与所述导电柱连接的第二导电图形。
本实施例中，在形成绝缘层上的第二导电图形之前，在绝缘层内的过孔处制作一个导电柱，该导电柱与绝缘层下的第一导电图形连接，从而通过该导电柱将第一导电图形和第二导电图形导通，由于该导电柱能够对过孔进行填充，因此可以实现过孔处的平坦化，避免过孔处出现凹陷，从而解决过孔处配向膜扩散不均引起的Mura不良，改善显示装置的显示效果。
进一步地，所述第一导电图形为薄膜晶体管的漏极，所述第二导电图形为像素电极，所述制作方法具体包括：
提供一衬底基板；
在所述衬底基板上形成薄膜晶体管的栅极；
形成栅绝缘层；
形成有源层的图形；
通过一次构图工艺同时形成薄膜晶体管的源极、漏极和所述导电柱，所述导电柱与所述漏极连接；
形成钝化层，并对所述钝化层进行刻蚀暴露出所述导电柱；
形成像素电极，所述像素电极与所述导电柱连接。
上述步骤中，导电柱和薄膜晶体管的源极、漏极通过一次构图工艺同时形成，可以在不增加构图工艺次数的前提下形成导电柱，简化阵列基板的制作工艺。
进一步地，所述第一导电图形为薄膜晶体管的漏极，所述第二导电图形为像素电极，所述制作方法具体包括：
提供一衬底基板；
在所述衬底基板上通过一次构图工艺同时形成薄膜晶体管的栅极和所述导电柱；
形成栅绝缘层；
形成有源层的图形，并对所述栅绝缘层和有源层进行刻蚀暴露出所述导电柱；
形成薄膜晶体管的源极和漏极，所述漏极与所述导电柱连接；
形成钝化层，并对所述钝化层进行刻蚀暴露出所述导电柱；
形成像素电极，所述像素电极与所述导电柱连接。
上述步骤中，导电柱和薄膜晶体管的栅极通过一次构图工艺同时形成，可以在不增加构图工艺次数的前提下形成导电柱，简化阵列基板的制作工艺。
进一步地，所述第一导电图形为公共电极线，所述第二导电图形为公共电极，所述制作方法具体包括：
提供一衬底基板；
在所述衬底基板上通过一次构图工艺同时形成薄膜晶体管的栅极、公共电极线和所述导电柱，所述导电柱与所述公共电极线连接；
形成栅绝缘层；
形成有源层的图形；
形成薄膜晶体管的源极和漏极；
形成钝化层，并对所述栅绝缘层和所述钝化层进行刻蚀暴露出所述导电柱；
形成公共电极，所述公共电极与所述导电柱连接。
上述步骤中，导电柱和薄膜晶体管的栅极、公共电极线通过一次构图工艺同时形成，可以在不增加构图工艺次数的前提下形成导电柱，简化阵列基板的制作工艺。
本公开至少一些实施例提供了一种阵列基板的制作方法，如图3-4所示，所述制作方法包括以下步骤31-35。
步骤31：提供一衬底基板1，在衬底基板1上形成导电柱10以及由栅金属层2形成的栅线、公共电极线、栅极，导电柱10与公共电极线连接。
其中，衬底基板1可为玻璃基板或石英基板。导电柱10可以采用与栅金属层同样的材料，这样导电柱10可以与栅线、公共电极线、栅极通过一次构图工艺同时形成。导电柱10还可以采用有机导电聚合物制成。
此外，导电柱10的主体可以为树脂柱状物，在树脂柱状物外包裹有导电材料，此时，导电柱10与栅线、公共电极线、薄膜晶体管的栅极通过不同构图工艺形成。在导电柱10的主体为树脂柱状物时，可以在预设位置事先制作树脂柱状物，然后在后续形成栅金属层或源漏金属层时，保留树脂柱状物上的栅金属层或源漏金属层作为包裹树脂柱状物的导电材料。
步骤32：在经过步骤31的衬底基板1上形成栅绝缘层3和有源层的图形，对栅绝缘层3进行刻蚀，暴露出导体柱10。
步骤33：在经过步骤32的衬底基板1上形成由源漏金属层组成的薄膜晶体管的漏极、源极和数据线。
步骤34：在经过步骤33的衬底基板1上形成钝化层5，对钝化层5进行刻蚀暴露出导电柱10。
进一步地，在步骤32中也可以先不对栅绝缘层3进行刻蚀，而在形成钝化层5之后对栅绝缘层3和钝化层5一起进行刻蚀，暴露出导电柱10；
步骤35：在经过步骤34的衬底基板1上形成公共电极8，公共电极8与导电柱10连接，形成如图3所示的结构。
本实施例中，由于导电柱10能够对连接公共电极与公共电极线的过孔进行填充，因此可以实现过孔处的平坦化，避免过孔处出现凹陷，从而解决过孔处配向膜扩散不均引起的Mura不良，改善显示装置的显示效果。
本公开至少一些实施例还提供了一种阵列基板的制作方法，如图5-6所示，本实施例包括以下步骤41-45。
步骤41：提供一衬底基板1，在衬底基板1上形成导电柱10以及由栅金属层组成的栅线、薄膜晶体管的栅极；
其中，衬底基板1可为玻璃基板或石英基板。导电柱10可以采用与栅金属层同样的材料，这样导电柱10可以与栅线、薄膜晶体管的栅极通过一次构图工艺同时形成；导电柱10还可以采用有机导电聚合物制成。
此外，导电柱10的主体可以为树脂柱状物，在树脂柱状物外包裹有导电材料，此时，导电柱10与栅线、薄膜晶体管的栅极通过不同构图工艺形成。在导电柱10的主体为树脂柱状物时，可以在预设位置事先制作树脂柱状物，然后在后续形成栅金属层或源漏金属层时，保留树脂柱状物上的栅金属层或源漏金属层作为包裹树脂柱状物的导电材料。
步骤42：在经过步骤41的衬底基板1上形成栅绝缘层3和有源层的图形，对栅绝缘层3进行刻蚀，暴露出导体柱10。
步骤43：在经过步骤42的衬底基板1上形成由源漏金属层4组成的薄膜晶体管的漏极、源极和数据线，薄膜晶体管的漏极与导电柱10连接。
步骤44：在经过步骤43的衬底基板1上形成钝化层5，对钝化层5进行刻蚀暴露出导电柱10。
步骤45：在经过步骤44的衬底基板1上形成像素电极6，像素电极6与导电柱10连接，形成如图5所示的结构，像素电极6通过导电柱10实现与薄膜晶体管的漏极的电连接。
本实施例中，由于导电柱10能够对连接像素电极与薄膜晶体管的漏极的过孔进行填充，因此可以实现过孔处的平坦化，避免过孔处出现凹陷，从而解决过孔处配向膜扩散不均引起的Mura不良，改善显示装置的显示效果。
本公开至少一些实施例还提供了一种阵列基板的制作方法，如图7-8所示，本实施例包括以下步骤51-55。
步骤51：提供一衬底基板1，在衬底基板1上形成由栅金属层2组成的栅线、栅极。
其中，衬底基板1可为玻璃基板或石英基板。
步骤52：在经过步骤51的衬底基板1上形成栅绝缘层3和有源层的图形。
步骤53：在经过步骤52的衬底基板1上形成导电柱10以及由源漏金属层4组成的薄膜晶体管的漏极、源极和数据线，薄膜晶体管的漏极与导电柱10连接；导电柱10可以采用与源漏金属层4同样的材料，这样导电柱10可以与薄膜晶体管的漏极、源极和数据线通过一次构图工艺同时形成；导电柱10还可以采用有机导电聚合物制成。
此外，导电柱10的主体可以为树脂柱状物，在树脂柱状物外包裹有导电材料，此时，导电柱10与薄膜晶体管的漏极、源极和数据线通过不同构图工艺形成。在导电柱10的主体为树脂柱状物时，可以在预设位置事先制作树脂柱状物，然后在后续形成栅金属层或源漏金属层时，保留树脂柱状物上的栅金属层或源漏金属层作为包裹树脂柱状物的导电材料。
步骤54：在经过步骤53的衬底基板1上形成钝化层5，对钝化层5进行刻蚀暴露出导电柱10。
步骤55：在经过步骤54的衬底基板1上形成像素电极6，如图7所示，像素电极6与导电柱10连接，通过导电柱10实现与薄膜晶体管的漏极的电连接。
本实施例中，由于导电柱10能够对连接像素电极与薄膜晶体管的漏极的过孔进行填充，因此可以实现过孔处的平坦化，避免过孔处出现凹陷，从而解决过孔处配向膜扩散不均引起的Mura不良，改善显示装置的显示效果。
本公开至少一些实施例还提供了一种显示装置，包括如上所述的阵列基板。所述显示装置可以为：液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (17)

  1. 一种阵列基板，包括第一导电图形、覆盖所述第一导电图形的绝缘层、位于所述绝缘层上的第二导电图形，所述绝缘层包括有用以连接所述第一导电图形和所述第二导电图形的过孔，其中，所述阵列基板还包括导电柱；所述导电柱位于所述过孔内并与所述第一导电图形和第二导电图形连接。
  2. 根据权利要求1所述的阵列基板，其中，所述导电柱上表面的水平高度不低于所述绝缘层上表面的水平高度。
  3. 根据权利要求1所述的阵列基板，其中，所述导电柱上表面的水平高度与所述绝缘层上表面的水平高度一致。
  4. 根据权利要求1所述的阵列基板，其中，所述导电柱为采用有机导电聚合物或金属制成。
  5. 根据权利要求1所述的阵列基板，其中，所述导电柱由树脂柱状物和包裹所述树脂柱状物的导电材料组成。
  6. 根据权利要求1所述的阵列基板，其中，所述导电柱的外表面与所述过孔的整个内表面接触。
  7. 根据权利要求1所述的阵列基板，其中，所述第一导电图形为薄膜晶体管的漏极；所述第二导电图形为像素电极。
  8. 根据权利要求7所述的阵列基板，其中，所述像素电极覆盖所述导电柱的上表面。
  9. 根据权利要求7所述的阵列基板，其中，所述绝缘层包括钝化层。
  10. 根据权利要求1所述的阵列基板，其中，所述第一导电图形为公共电极线；所述第二导电图形为公共电极。
  11. 根据权利要求10所述的阵列基板，其中，所述公共电极覆盖所述导电柱的上表面。
  12. 根据权利要求10所述的阵列基板，其中，所述绝缘层包括栅绝缘层和钝化层。
  13. 一种显示装置，其中，包括如权利要求1-12中任一项所述的阵列基板。
  14. 一种阵列基板的制作方法，所述阵列基板包括第一导电图形、覆盖所述第一导电图形的绝缘层和位于所述绝缘层上的第二导电图形，所述绝缘层包括有用以连接所述第一导电图形和所述第二导电图形的过孔，其中，所述方法包括：
    在形成所述第二导电图形之前，在所述过孔内形成与所述第一导电图形连接的导电柱；
    形成与所述导电柱连接的第二导电图形。
  15. 根据权利要求14所述的阵列基板的制作方法，其中，所述第一导电图形为薄膜晶体管的漏极，所述第二导电图形为像素电极，所述绝缘层包括钝化层；
    在所述过孔内形成与所述第一导电图形连接的导电柱之前，所述制作方法还包括：
    提供一衬底基板；
    在所述衬底基板上形成薄膜晶体管的栅极；
    形成栅绝缘层；
    形成有源层的图形；
    在所述过孔内形成与所述第一导电图形连接的导电柱包括：
    通过一次构图工艺同时形成薄膜晶体管的源极、漏极和所述导电柱，所述导电柱与所述漏极连接；
    形成钝化层，并对所述钝化层进行刻蚀暴露出所述导电柱；
    形成与所述导电柱连接的第二导电图形包括：
    形成像素电极，所述像素电极与所述导电柱连接。
  16. 根据权利要求14所述的阵列基板的制作方法，其中，所述第一导电图形为薄膜晶体管的漏极，所述第二导电图形为像素电极，所述绝缘层包括钝化层；
    在所述过孔内形成与所述第一导电图形连接的导电柱包括：
    提供一衬底基板；
    在所述衬底基板上通过一次构图工艺同时形成薄膜晶体管的栅极和所述导电柱；
    形成栅绝缘层；形成有源层的图形，并对所述栅绝缘层和有源层进行刻蚀暴露出所述导电柱；
    形成薄膜晶体管的源极和漏极，所述漏极与所述导电柱连接；
    形成钝化层，并对所述钝化层进行刻蚀暴露出所述导电柱；
    形成与所述导电柱连接的第二导电图形包括：
    形成像素电极，所述像素电极与所述导电柱连接。
  17. 根据权利要求14所述的阵列基板的制作方法，其中，所述第一导电图形为公共电极线，所述第二导电图形为公共电极，所述绝缘层包括栅绝缘层和钝化层；
    在所述过孔内形成与所述第一导电图形连接的导电柱包括：
    提供一衬底基板；
    在所述衬底基板上通过一次构图工艺同时形成薄膜晶体管的栅极、公共电极线和所述导电柱，所述导电柱与所述公共电极线连接；
    形成栅绝缘层；
    形成有源层的图形；
    形成薄膜晶体管的源极和漏极；
    形成钝化层，并对所述栅绝缘层和所述钝化层进行刻蚀暴露出所述导电柱；
    形成与所述导电柱连接的第二导电图形包括：
    形成公共电极，所述公共电极与所述导电柱连接。
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