WO2016023243A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2016023243A1
WO2016023243A1 PCT/CN2014/085123 CN2014085123W WO2016023243A1 WO 2016023243 A1 WO2016023243 A1 WO 2016023243A1 CN 2014085123 W CN2014085123 W CN 2014085123W WO 2016023243 A1 WO2016023243 A1 WO 2016023243A1
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Prior art keywords
metal pattern
drain
array substrate
via hole
pattern
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PCT/CN2014/085123
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English (en)
French (fr)
Inventor
赵国
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深圳市华星光电技术有限公司
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Priority to US14/417,955 priority Critical patent/US20160254284A1/en
Publication of WO2016023243A1 publication Critical patent/WO2016023243A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers

Definitions

  • the present invention relates to the field of display technologies, and in particular to an array substrate, a method of manufacturing the same, and a display device.
  • liquid crystal displays Unlike the development of display technology, liquid crystal displays have become the most common flat panel display devices.
  • a liquid crystal display is usually composed of an array substrate, a color filter substrate, and the like.
  • the array substrate is provided with a layer structure such as a gate metal layer, a source/drain metal layer, a transparent electrode layer, a passivation layer, and the like, and different layers are connected to each other through via holes.
  • a via hole 6 is formed in the passivation layer 4 between the drain 3 (located on the source/drain metal layer) and the pixel electrode 5 (located on the transparent electrode layer) of the thin film transistor (TFT).
  • TFT thin film transistor
  • the drain 3 of the TFT is also likely to be partially etched, which causes the contact angle between the pixel electrode 5 and the drain 3 of the TFT. Very steep. It is also possible to cause the drain 3 of the TFT to be etched to have an upper width and a lower chamfer, thereby causing the pixel electrode 5 to be broken. The above situation causes the contact resistance between the pixel electrode 5 and the drain 3 of the TFT to become large, which affects the display effect of the liquid crystal display. Summary of the invention
  • An object of the present invention is to provide an array substrate, a method for fabricating the same, and a display device for solving the problem of a large contact impedance between a pixel electrode and a drain of a TFT.
  • the present invention provides an array substrate comprising a metal pattern, an insulating layer overlying the metal pattern, and an electrode pattern formed on the insulating layer;
  • a via hole is disposed on the insulating layer, and the electrode pattern is electrically connected to the metal pattern through the via hole; A portion of the area where the via is located coincides with the metal pattern, and the remaining portion of the area where the via is located is outside the metal pattern.
  • the area where the via hole is located corresponds to an edge of the metal pattern.
  • the width of the area where the via hole is located is greater than the width of the metal pattern
  • the middle portion of the region where the via hole is located coincides with the metal pattern, and both end portions of the region where the via hole is located are located outside the metal pattern.
  • the metal pattern is a drain of the TFT, and the electrode pattern is a pixel electrode.
  • the invention also provides a method for manufacturing an array substrate, comprising:
  • the area where the via hole is located corresponds to the edge of the metal pattern.
  • a width of a region where the via hole is located is greater than a width of the metal pattern
  • the middle portion of the region where the via hole is located coincides with the metal pattern, and both end portions of the region where the via hole is located are located outside the metal pattern.
  • the metal pattern is a drain of the TFT, and the electrode pattern is a pixel electrode.
  • the present invention also provides a display device comprising a color filter substrate and the above array substrate.
  • the electrode pattern is electrically connected to the metal pattern through the via hole on the insulating layer, a part of the region where the via hole is located overlaps with the metal pattern, and the remaining portion is located outside the metal pattern.
  • the via is etched on the insulating layer, the metal pattern is engraved with a relatively gentle bevel, which is the contact surface between the metal pattern and the electrode pattern.
  • the contact surface between the metal pattern and the electrode pattern is a relatively gentle slope, and the pixel electrode can be prevented from being broken, and the contact resistance between the metal pattern and the electrode pattern can be reduced, thereby enabling
  • the technical problem of affecting the display effect is affected by the large contact impedance between the pixel electrode and the drain of the TFT.
  • FIG. 1 is a partial schematic view of a conventional array substrate
  • Figure 2 is a cross-sectional view taken along line ⁇ - ⁇ in Figure 1;
  • FIG. 3 is a partial schematic view of an array substrate according to Embodiment 1 of the present invention.
  • Figure 4 is a cross-sectional view taken along line ⁇ - ⁇ in Figure 3;
  • FIG. 5 is a partial schematic view of an array substrate according to Embodiment 2 of the present invention.
  • Figure 6 is a cross-sectional view taken along line ⁇ - ⁇ in Figure 5;
  • FIG. 7 is a partial schematic view of an array substrate according to Embodiment 3 of the present invention.
  • Figure 8 is a cross-sectional view taken along line A- ⁇ of Figure 7;
  • Figure 9 is a cross-sectional view taken along line B-B of Figure 7. detailed description
  • Embodiments of the present invention provide an array substrate including a metal pattern, an insulating layer overlying the metal pattern, and an electrode pattern formed on the insulating layer.
  • a via hole is formed in the insulating layer, and the electrode pattern is electrically connected to the metal pattern through the pupil.
  • a portion of the area where the via is located coincides with the metal pattern, and the rest of the area where the via is located is outside the metal pattern.
  • the electrode pattern is electrically connected to the metal pattern through a via hole on the insulating layer, a portion of the region where the via hole is located overlaps with the metal pattern, and the remaining portion is located outside the metal pattern.
  • Etched on the insulating layer At the time of the hole, the metal pattern is etched into a relatively gentle bevel, which is the contact surface between the metal pattern and the electrode pattern. Therefore, in the technical solution provided by the embodiment of the present invention, the contact surface between the metal pattern and the electrode pattern is a relatively gentle slope, and the pixel electrode is prevented from being broken, thereby reducing the contact resistance between the metal pattern and the electrode pattern. Therefore, it is possible to solve the technical problem that the display effect is affected by the large contact impedance between the pixel electrode and the drain of the TFT in the prior art.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • the array substrate provided by the embodiment of the present invention includes a»electrode metal layer (not shown) formed on the base substrate 1, a gate insulating layer 2, and a data line metal layer (including The data line, the source of the TFT, the drain 3, and the like, the passivation layer 4, the pixel electrode 5, and the like.
  • a via hole 6 is formed in the passivation layer 4, and the pixel electrode 5 is electrically connected to the drain 3 of the TFT through the via hole 6. Moreover, the area of the via 6 corresponds to the edge of the drain 3, such that a portion of the region where the via 6 is located coincides with the drain 3, and the remaining portion of the region where the via 6 is located is outside the drain 3.
  • the pixel electrode 5 is electrically connected to the drain 3 through the via 6 on the passivation layer 4, and the region where the via 6 is located corresponds to the edge of the drain 3.
  • the drain 3 is engraved with a horizontal plane or a relatively gentle slope which is the contact surface between the drain 3 and the pixel electrode 5.
  • the drain 3 is not etched or etched when the via 6 is etched, the area of the via 6 will expose the horizontal upper surface of the drain 3, and the pixel electrode 5 and the drain The contact surface between the poles 3 is the horizontal plane.
  • the contact surface between the drain 3 and the pixel electrode 5 is a horizontal plane or a relatively gentle slope, and the pixel electrode 5 can be prevented from being broken, thereby lowering the drain 3 and the pixel.
  • the contact resistance between the electrodes 5 can solve the technical problem that the display effect is affected by the large contact impedance between the pixel electrode and the drain of the TFT in the prior art.
  • S3 forming a data line metal layer on the gate insulating layer 2 by using a patterning process, including a data line, a source of the TFT, a drain 3, and the like.
  • S4 covering the passivation layer 4 on the data line metal layer.
  • S5 The passivation layer 4 is etched by a patterning process to form via holes 6.
  • the area of the via 6 corresponds to the edge of the drain 3, such that a portion of the region where the via 6 is located coincides with the drain 3, and the remaining portion of the region where the via 6 is located is outside the drain 3.
  • the drain 3 is etched to a horizontal plane or a relatively gentle slope. If the drain 3 is not etched or etched very little, then the area of the via 6 will expose the horizontal upper surface of the drain 3.
  • the pixel electrode 5 is formed on the passivation layer 4 by a patterning process, and the pixel electrode 5 is electrically connected to the drain electrode 3 through the via hole 6.
  • the array substrate provided in this embodiment can be formed through some subsequent conventional steps.
  • the contact surface between the drain 3 and the pixel electrode 5 is a horizontal plane or a relatively gentle slope, and the pixel electrode 5 can be prevented from being broken, thereby reducing the contact between the drain 3 and the pixel electrode 5.
  • the impedance can solve the technical problem that the display effect is affected in the prior art because the contact between the pixel electrode and the drain of the TFT is relatively large.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the array substrate provided by the embodiment of the present invention includes a gate metal layer (not shown) formed on the substrate substrate 1 , a gate insulating layer 2 , and a data line metal layer (including The data line, the source of the TFT, the drain 3, and the like), the passivation layer 4, the pixel electrode 5, and the like.
  • a via hole 6 is formed in the passivation layer 4, and the pixel electrode 5 is electrically connected to the drain 3 of the TFT through the via hole 6.
  • the width of the via hole 6 is increased, and the width of the drain electrode 3 can be appropriately reduced, so that the width of the region where the via hole 6 is located is larger than the width of the drain electrode 3, and the middle portion and the drain region of the region where the via hole 6 is located.
  • the poles 3 are coincident, and both ends of the region where the via holes 6 are located are located outside the drain 3.
  • the pixel electrode 5 is electrically connected to the drain 3 through the via 6 on the passivation layer 4, and both ends of the via 6 are wider than the edge of the drain 3.
  • the drain 3 is etched out to a large horizontal plane, which is the contact surface between the drain 3 and the pixel electrode 5.
  • the drain 3 is not etched or etched very little when the via 6 is etched, the area of the via 6 will expose the horizontal upper surface of the drain 3, and the pixel electrode 5 and the drain The contact surface between the poles 3 is also a horizontal plane.
  • the contact surface between the drain 3 and the pixel electrode 5 is a large horizontal surface, which not only increases the contact area between the drain 3 and the pixel electrode 5, but also enables The pixel electrode 5 is prevented from being broken, thereby reducing the contact between the drain electrode 3 and the pixel electrode 5, thereby solving the problem in the prior art that the contact between the pixel electrode and the drain of the TFT is relatively large. , and the technical problem that affects the display effect.
  • a method for manufacturing an array substrate provided by an embodiment of the present invention includes:
  • a polar metal layer is formed on the base substrate 1 by a patterning process.
  • S3 forming a data line metal layer on the gate insulating layer 2 by using a patterning process, including a data line, a source of the TFT, a drain 3, and the like.
  • the passivation layer 4 is etched by a patterning process to form a pupil 6.
  • the width of the region where the via 6 is located is larger than the width of the drain 3, so that the middle portion of the region where the via 6 is located coincides with the drain 3, and both ends of the region where the via 6 is located are located at the drain 3.
  • the drain 3 is etched to a larger horizontal plane. If the drain 3 is not etched or etched very little while the via 6 is being etched, the area of the via 6 will expose the horizontal upper surface of the drain 3.
  • the pixel electrode 5 is formed on the passivation layer 4 by a patterning process, and the pixel electrode 5 is electrically connected to the drain electrode 3 through the via hole 6.
  • the array substrate provided in this embodiment can be formed through some subsequent conventional steps.
  • the contact surface between the drain 3 and the pixel electrode 5 is a large horizontal plane, which not only increases the contact entanglement between the drain 3 and the pixel electrode 5, but also prevents the pixel electrode 5 from occurring.
  • the rupture thus reducing the contact resistance between the drain 3 and the pixel electrode 5, can solve the technical problem that the display effect is affected by the large contact impedance between the pixel electrode and the drain of the TFT in the prior art.
  • an embodiment of the present invention provides an array substrate.
  • the array substrate includes a gate metal layer (not shown) formed on the base substrate 1, a gate insulating layer 2, a data line metal layer (including a data line, a source of the TFT, a drain 3, etc.), The structure of the purification layer 4, the pixel electrode 5, and the like.
  • a via hole 6 is formed in the passivation layer 4, and the pixel electrode 5 is electrically connected to the drain 3 of the TFT through the via hole 6.
  • the region where the via 6 is located corresponds to the edge of the drain 3, and the width of the region where the via 6 is located is larger than the width of the drain 3, so that both ends of the region where the via 6 is located are located outside the drain 3.
  • the middle portion of the region where the via 6 is located also has a portion located outside the drain 3 and the other portion coincides with the drain 3.
  • the contact surface between the drain 3 and the pixel electrode 5 is a large horizontal plane or a slope, and the pixel electrode 5 can be prevented from being broken, thereby reducing the drain 3 and the pixel electrode 5.
  • the contact impedance between the two can solve the technical problem that the display effect is affected by the large contact impedance between the pixel electrode and the drain of the TFT in the prior art.
  • connection between the drain of the TFT and the pixel electrode in the pixel unit is taken as an example.
  • the via holes may be disposed in the same manner to achieve electrical connection, thereby solving the metal pattern and the electrode pattern.
  • the contact between the 13 ⁇ 4 is more resistant and affects the technical problem of the display effect.
  • Embodiment 4 The embodiment of the present invention provides a display device, which may specifically be a liquid crystal television, a liquid crystal display, a mobile phone, a tablet computer, or the like.
  • the display device comprises a color film substrate, and the array substrate in the first embodiment, the second embodiment or the third embodiment.
  • the display device provided in this embodiment has the same technical features as the array substrate provided in the above embodiments, so that the same technical problem can be solved and the same technical effects can be achieved. While the embodiments of the present invention have been described above, the described embodiments are merely for the purpose of understanding the invention and are not intended to limit the invention. Modifications and variations of the form and details of the invention may be made by those skilled in the art without departing from the scope of the invention. It is still subject to the scope defined by the appended claims.

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Abstract

一种阵列基板及其制造方法、显示装置，属于显示技术领域。该阵列基板（1），包括金属图形（3）、覆盖在金属图形（3）上的绝缘层（4）、形成于绝缘层（4）上的电极图形（5）；绝缘层（4）上开设有过孔（6），电极图形（5）通过过孔（6）与金属图形（3）电连接；过孔（6）所在区域的一部分与金属图形（3）重合，其余部分位于金属图形（3）之外。该阵列基板及其制造方法解决了像素电极与TFT的漏极之间的接触阻抗较大的技术问题，可用于液晶电视、液晶显示器、手机、平板电脑等显示装置。

Description

本申请要求享有 2014年 8月 14 日提交的名称为 "阵列基板及其制造方法、 显示装 置" 的中国专利申请 CN201410399880.4的优先权， 其全部内容通过引用并入本文中。
本发明涉及显示技术领域， 具体地说， 涉及一种阵列基板及其制造方法、 显示装置。
不 随着显示技术的发展， 液晶显示器己经成为最为常见的平板显示装置。
液晶显示器通常由阵列基板、彩膜基板等部件构成。其中， 阵列基板上设置有栅极金 属层、源漏极金属层、 透明电极层、 钝化层等图层结构， 并且不同的图层之间还会通 ϋ过 孔相互连接。 例如图 1和图 2所示， 薄膜晶体管 （TFT) 的漏极 3 (位于源漏极金属层） 与像素电极 5 (位于透明电极层） 之间的钝化层 4上开设有过孔 6, 像素电极 5通过该过 孔 6与 TFT的漏极 3电连接。
但是， 在钝化层 4上刻蚀过孔 6的时候， TFT的漏极 3也很有可能会被刻蚀掉一部 分， 会使像素电极 5与 TFT的漏极 3之间的接触靣的角度很陡。 还有可能使 TFT的漏极 3被刻蚀出上宽下窄的倒角， 使像素电极 5发生断裂。 以上情况都会导致像素电极 5与 TFT的漏极 3之间的接触阻抗变大， 而影响液晶显示器的显示效果。 发明内容
本发明的目的在于提供一种阵列基板及其制造方法、 显示装置， 以解决像素电极与 TFT的漏极之间的接触阻抗较大的技术 |5]题。 本发明提供一种阵列基板， 包括金属图形、覆盖在所述金属图形上的绝缘层、形成于 所述绝缘层上的电极图形；
所述绝缘层上幵设有过孔， 所述电极图形通过所述过孔与所述金属图形电连接； 所述过孔所在区域的一部分与所述金属图形重合，所述过孔所在区域的其余部分位于 所述金属图形之外。
优选的， 所述过孔所在区域对应于所述金属图形的边缘。
优选的， 所述过孔所在区域的宽度大亍所述金属图形的宽度；
所述过孔所在区域的中部与所述金属图形重合，所述过孔所在区域的两端部位于所述 金属图形之外。
优选的， 所述金属图案为 TFT的漏极， 所述电极图形为像素电极。
本发明还提供一种阵列基板的制造方法， 包括：
形成金属图案；
在所述金属图案上覆盖绝缘层；
对所述绝缘层进行刻蚀，形成过孔,所述过孔所在区域的一部分与所述金属图形重合， 所述过孔所在区域的其余部分位于所述金属图形之外- 在所述绝缘层上形成电极图形， 使所述电极图形通过所述过孔与所述金属图形电连 接。
优选的， 所述过孔所在区域对应亍所述金属图形的边缘。
优选的， 所述过孔所在区域的宽度大于所述金属图形的宽度；
所述过孔所在区域的中部与所述金属图形重合,所述过孔所在区域的两端部位于所述 金属图形之外。
优选的， 所述金属图案为 TFT的漏极， 所述电极图形为像素电极。
本发明还提供一种显示装置， 包括彩膜基板和上述的阵列基板。
本发明带来了以下有益效果： 本发明提供的阵列基板中， 电极图形通过绝缘层上的过 孔与金属图形电连接，过孔所在区域的一部分与金属图形重合，其余部分位于金属图形之 外。在绝缘层上刻蚀过孔的时候， 金属图形会被刻饨出一个较为平缓的斜靣， 该斜靣即为 金属图形与电极图形之间的接触面。 因此， 本发明提供的技术方案中， 金属图形与电极图 形之间的接触面是一个较为平缓的斜面，并能够防止像素电极发生断裂， 降低了金属图形 与电极图形之间的接触阻抗， 从而能够解决现有技术中， 由亍像素电极与 TFT的漏极之 间的接触阻抗较大， 而影响显示效果的技术问题。 本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显 而易见， 或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要 求书以及附图中所特别指出的结构来实现和获得。 附圏说明
为了更清楚地说明本发明实施 ί到中的技术方案，下面将对实施例描述中所需要的 图 做简单的介绍- 图 1是现有的阵列基板的局部示意图；
图 2是图 1中沿 Α-Α方向的剖面图；
图 3是本发明实施例一提供的阵列基板的局部示意图；
图 4是图 3中沿 Α-Α方向的剖面图；
图 5是本发明实施例二提供的阵列基板的局部示意图；
图 6是图 5中沿 Β- Β方向的剖面图；
图 7是本发明实施例三提供的阵列基板的局部示意图；
图 8是图 7中沿 A- Α方向的剖面图；
图 9是图 7中沿 B-B方向的剖面图。 具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术 手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是， 只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形 成的技术方案均在本发明的保护范围之内。
本发明实施例提供一种阵列基板， 包括金属图形、覆盖在金属图形上的绝缘层、 形成 于绝缘层上的电极图形。绝缘层上开设有过孔， 电极图形通过 ϋ孔与金属图形电连接。过 孔所在区域的一部分与金属图形重合， 过孔所在区域的其余部分位于金属图形之外。
本发明实施例提供的阵列基板中， 电极图形通过绝缘层上的过孔与金属图形电连接， 过孔所在区域的一部分与金属图形重合，其余部分位于金属图形之外。在绝缘层上刻蚀过 孔的时候，金属图形会被刻蚀出一个较为平缓的斜靣，该斜面即为金属图形与电极图形之 间的接触面。 因此， 本发明实施例提供的技术方案中， 金属图形与电极图形之间的接触面 是一个较为平缓的斜面，并能够防止像素电极发生断裂， 因此降低了金属图形与电极图形 之间的接触阻抗， 从而能够解决现有技术中， 由于像素电极与 TFT的漏极之间的接触阻 抗较大， 而影响显示效果的技术问题。
实施例一：
如图 3和图 4所示，本发明实施例提供的阵列基板，包括形成在衬底基板 1上的 »极 金属层 （图中未示出） 、 栅绝缘层 2、 数据线金属层 （包括数据线、 TFT的源极、 漏极 3 等） 、 钝化层 4、 像素电极 5等结构。
钝化层 4上开设有过孔 6, 像素电极 5通过过孔 6与 TFT的漏极 3电连接。 并 , 过孔 6所在区域对应于漏极 3的边缘， 使过孔 6所在区域的一部分与漏极 3重合， 过孔 6 所在区域的其余部分位于漏极 3之外。
本发明实施例提供的阵列基板中，像素电极 5通过钝化层 4上的过孔 6与漏极 3电连 接， 过孔 6所在区域对应于漏极 3的边缘。在钝化层 4上刻饨过孔 6的时候， 漏极 3会被 刻饨出一个水平面或较为平缓的斜面,该水平面或斜面即为漏极 3与像素电极 5之间的接 触面。
如果在刻蚀过孔 6的时候， 漏极 3没有被刻蚀， 或被刻饨的很少， 那么过孔 6所在区 域将会露出漏极 3的水平的上表面， 则像素电极 5与漏极 3之间的接触面即为水平面。
因此，本发明实施例提供的阵列基板中，漏极 3与像素电极 5之间的接触面是一个水 平面或较为平缓的斜面，并能够防止像素电极 5发生断裂， 因此降低了漏极 3与像素电极 5之间的接触阻抗， 从而能够解决现有技术中， 由于像素电极与 TFT的漏极之间的接触 阻抗较大， 而影响显示效果的技术问题。
本发明实施例提供的阵列基板的制造方法包括：
S1 : 利用构图工艺， 在衬底基板〗上形成極极金属层。
S2: 在栅极金属层上覆盖栅绝缘层 2。
S3： 利用构图工艺， 在栅绝缘层 2上形成数据线金属层， 其中包括数据线、 TFT的 源极、 漏极 3等结构。
S4: 在数据线金属层上覆盖钝化层 4。 S5 : 利用构图工艺， 对钝化层 4进行刻蚀， 形成过孔 6。
其中， 过孔 6所在区域对应于漏极 3的边缘， 使过孔 6所在区域的一部分与漏极 3 重合， 过孔 6所在区域的其余部分位亍漏极 3之外。
在刻蚀过孔 6的时候， 漏极 3会被刻蚀出一个水平面或较为平缓的斜面。 如果漏极 3 没有被刻蚀， 或被刻蚀的很少， 那么过孔 6所在区域将会露 ¾漏极 3的水平的上表面。
S6: 利用构图工艺， 在钝化层 4上形成像素电极 5， 使像素电极 5通过过孔 6与漏极 3电连接。 再经过后续的一些常规步骤， 即可形成本实施例提供的阵列基板。 在该阵列基板中， 漏极 3与像素电极 5之间的接触面是一个水平面或较为平缓的斜面，并能够防止像素电极 5发生断裂，因此降低了漏极 3与像素电极 5之间的接触阻抗，从而能够解决现有技术中， 由于像素电极与 TFT的漏极之间的接触 |¾抗较大， 而影响显示效果的技术问题。
实施例二：
如图 5和图 6所示，本发明实施例提供的阵列基板，包括形成在衬底基板 1上的栅极 金属层 （图中未示出） 、 栅绝缘层 2、 数据线金属层 （包括数据线、 TFT的源极、 漏极 3 等） , 钝化层 4、 像素电极 5等结构。
钝化层 4上开设有过孔 6, 像素电极 5通过过孔 6与 TFT的漏极 3电连接。 本实施 例中， 增大了过孔 6的宽度， 同时还可以适当缩小漏极 3的宽度， 使过孔 6所在区域的宽 度大于漏极 3的宽度，并且过孔 6所在区域的中部与漏极 3重合，过孔 6所在区域的两端 部位于漏极 3之外。
本发明实施例提供的阵列基板中，像素电极 5通过钝化层 4上的过孔 6与漏极 3电连 接， 过孔 6的两端宽出漏极 3的边缘。在纯化层 4上刻蚀出过孔 6的 ίίί候， 漏极 3会被刻 蚀出一个较大的水平面， 该水平面即为漏极 3与像素电极 5之间的接触面。
如果在刻蚀过孔 6的时候， 漏极 3没有被刻蚀， 或被刻蚀的很少， 那么过孔 6所在区 域将会露出漏极 3的水平的上表面， 则像素电极 5与漏极 3之间的接触面也为水平面。
因此，本发明实施例提供的阵列基板中，漏极 3与像素电极 5之间的接触面是一个较 大的水平面， 不仅增大了漏极 3与像素电极 5之间的接触面积， 还能够防止像素电极 5 发生断裂， 因此降低了漏极 3与像素电极 5之间的接触 |¾抗， 从而能够解决现有技术中， 由于像素电极与 TFT的漏极之间的接触 |¾抗较大， 而影响显示效果的技术问题。 本发明实施例提供的阵列基板的制造方法包括；
S1 : 利用构图工艺， 在衬底基板 1上形成極极金属层。
S2: 在栅极金属层上覆盖栅绝缘层 2。
S3 : 利用构图工艺， 在栅绝缘层 2上形成数据线金属层， 其中包括数据线、 TFT的 源极、 漏极 3等结构。
84： 在数据线金属层上覆盖钝化层 4。
S5 : 利用构图工艺， 对钝化层 4进行刻蚀， 形成 ϋ孔 6。
其中， 过孔 6所在区域的宽度大于漏极 3的宽度， 使过孔 6所在区域的中部与漏极 3 重合， 过孔 6所在区域的两端部位于漏极 3之夕卜。
在刻蚀过孔 6的时候，漏极 3会被刻蚀出一个较大的水平面。如果在刻蚀过孔 6的时 候， 漏极 3没有被刻蚀， 或被刻蚀的很少， 那么过孔 6所在区域将会露出漏极 3的水平的 上表面。
S6: 利用构图工艺， 在钝化层 4上形成像素电极 5 , 使像素电极 5通过过孔 6与漏极 3电连接。
再经过后续的一些常规步骤， 即可形成本实施例提供的阵列基板。 在该阵列基板中， 漏极 3与像素电极 5之间的接触面是一个较大的水平面，不仅增大了漏极 3与像素电极 5 之间的接触靣积，还能够防止像素电极 5发生断裂， 因此降低了漏极 3与像素电极 5之间 的接触阻抗， 从而能够解决现有技术中， 由于像素电极与 TFT的漏极之间的接触阻抗较 大， 而影响显示效果的技术问题。
实施例 Ξ:
如图 7、 图 8和图 9所示， 本发明实施例提供一种阵列基板， 本实施 ί到中， 对实施例 一与实施例二进行结合。该阵列基板， 包括形成在衬底基板 1上的栅极金属层（图中未示 出） 、 栅绝缘层 2、 数据线金属层 （包括数据线、 TFT的源极、 漏极 3等） 、 纯化层 4、 像素电极 5等结构。
钝化层 4上开设有过孔 6, 像素电极 5通过过孔 6与 TFT的漏极 3电连接。 本实施 例中，过孔 6所在区域对应亍漏极 3的边缘，并且过孔 6所在区域的宽度大于漏极 3的宽 度，使过孔 6所在区域的两端部位于漏极 3之外，而过孔 6所在区域的中部也有一部分位 于漏极 3之外， 另一部分与漏极 3重合。 本发明实施例提供的阵列基板中，漏极 3与像素电极 5之间的接触面是一个较大的水 平面或斜面，并能够防止像素电极 5发生断裂， 因此降低了漏极 3与像素电极 5之间的接 触阻抗， 从而能够解决现有技术中， 由于像素电极与 TFT的漏极之间的接触阻抗较大， 而影响显示效果的技术问题。
应当说明的是， 上述三个实施例中， 均以像素单元中的 TFT的漏极与像素电极之间 的连接为例。 当然， 在阵列基板上其他部分（例如板边走线区域、 阻抗测试区域） 的金属 图形与电极图形之间，也可以采用相同的方式设置过孔以实现电连接，从而解决金属图形 与电极图形之间的接触 1¾抗较大， 影响显示效果的技术问题。
实施例四： 本发明实施例提供一种显示装置， 具体可以是液晶电视、 液晶显示器、 手机、 平板电 脑等。该显示装置包括彩膜基板，以及上述实施例一、实施例二或实施例三中的阵列基板。 本实施例提供的显示装置，与上述实施例提供的阵列基板具有相同的技术特征，所以 也能解决相同的技术问题， 达到相同的技术效果。 虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的 实施方式， 并非用以限定本发明。任何本发明所属技术领域内的技术人员， 在不脱离本发 明所公开的精神和范围的前提下，可以在实施的形式上及细节上作 何的修改与变化，但 本发明的专利保护范围， 仍须以所附的权利要求书所界定的范围为准。

Claims

扠利耍求书
1、 一种阵列基板， 包括金属图形、 覆盖在所述金属图形上的绝缘层、 形成于所述绝 缘层上的电极图形；
所述绝缘层上开设有过孔， 所述电极图形通过所述过孔与所述金属图形电连接； 所述过孔所在区域的一部分与所述金属图形重合,所述过孔所在区域的其余部分位于 所述金属图形之外。
2、 如权利要求 1所述的阵列基板， 其中， 所述过孔所在区域对应于所述金属图形的 边缘。
3、 如权利要求 1所述的阵列基板， 其中， 所述过孔所在区域的宽度大于所述金属图 形的宽度；
所述过孔所在区域的中部与所述金属图形重合,所述过孔所在区域的两端部位于所述 金属图形之外。
4、 如权利要求 1所述的阵列基板， 其中， 所述金属图案为 TFT的漏极， 所述电极图 形为像素电极。
5、 一种阵列基板的制造方法， 包括- 形成金属图案；
在所述金属图案上覆盖绝缘层；
对所述绝缘层进行刻蚀,形成过孔，所述过孔所在区域的一部分与所述金属图形重合, 所述过孔所在区域的其余部分位于所述金属图形之外；
在所述绝缘层上形成电极图形， 使所述电极图形通过所述过孔与所述金属图形电连 接。
6、如权利要求 5所述的方法， 其中， 所述过孔所在区域对应亍所述金属图形的边缘。
7、 如权利要求 5所述的方法， 其中， 所述过孔所在区域的宽度大于所述金属图形的 宽度；
所述 ϋ孔所在区域的中部与所述金属图形重合,所述 ϋ孔所在区域的两端部位于所述 金属图形之外。
8、 如权利要求 5所述的方法， 其中， 所述金属图案为 TFT的漏极， 所述电极图形为 像素电极。
9、 一种显示装置， 包括彩膜基板和阵列基板；
所述阵列基板包括金属图形、覆盖在所述金属图形上的绝缘层、形成于所述绝缘层上 的电极图形：
所述绝缘层上开设有过孔， 所述电极图形通过所述过孔与所述金属图形电连接； 所述过孔所在区域的一部分与所述金属图形重合,所述过孔所在区域的其余部分位于 所述金属图形之外。
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