WO2016125669A1 - Module à semi-conducteur - Google Patents

Module à semi-conducteur Download PDF

Info

Publication number
WO2016125669A1
WO2016125669A1 PCT/JP2016/052445 JP2016052445W WO2016125669A1 WO 2016125669 A1 WO2016125669 A1 WO 2016125669A1 JP 2016052445 W JP2016052445 W JP 2016052445W WO 2016125669 A1 WO2016125669 A1 WO 2016125669A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor module
sealing resin
insulating base
semiconductor
lead terminals
Prior art date
Application number
PCT/JP2016/052445
Other languages
English (en)
Japanese (ja)
Inventor
山本　祐樹
要一 守屋
Original Assignee
株式会社村田製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社村田製作所 filed Critical 株式会社村田製作所
Priority to JP2016573311A priority Critical patent/JP6447842B2/ja
Publication of WO2016125669A1 publication Critical patent/WO2016125669A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor module, and more particularly to a semiconductor module in which a lead terminal is bonded to an insulating base material and then sealed with a sealing resin.
  • Semiconductor modules such as inverters are used as power sources for in-vehicle equipment and industrial equipment.
  • a semiconductor module is configured by a combination of a plurality of semiconductor switching elements or a combination of a plurality of switching elements and a plurality of free-wheeling diodes.
  • FIG. 14A and 14B show a semiconductor module (semiconductor device) 500 disclosed in Patent Document 1.
  • FIG. 14A is a plan view of the semiconductor module 500 in which a sealing resin 108 and a heat radiating plate 107a described later are omitted.
  • FIG. 14B is a cross-sectional view of the semiconductor module 500, and shows a portion XX in FIG.
  • the semiconductor module 500 is a three-phase output inverter, and three sets of circuits Cir1, Cir2, and Cir3 having the same configuration are connected in parallel.
  • the circuit Cir1 will be described as an example. 14B shows a cross section of the circuit Cir1 portion of the semiconductor module 500.
  • the circuit Cir1 includes two semiconductor switching elements (IGBT) 101a and 101b, two diodes 102a and 102b, lead terminals 105a, 105b, 105c, 105d, and 105e, and heat sinks (heat sinks) 107a and 107b. It is configured.
  • IGBT semiconductor switching elements
  • one power electrode pad (not shown) of the semiconductor switching element 101 a is joined to the lead terminal 105 a by the solder 104, and the other power electrode pad (not shown) is joined to the heat radiating plate 107 a by the solder 104. It is joined to.
  • a signal electrode pad (not shown) of the semiconductor switching element 101a is wire-bonded to the lead terminal 105b by a wire 103a.
  • a diode 102a is connected in parallel with the semiconductor module 101a between the lead terminal 105a and the heat sink 107a.
  • one power electrode pad (not shown) of the semiconductor switching element 101b is joined to the lead terminal 105a by the solder 104, and the other power electrode pad (not shown) is joined to the heat sink 107b by the solder 104.
  • a signal electrode pad (not shown) of the semiconductor switching element 101b is wire-bonded to the lead terminal 105c by a wire 103b.
  • a diode 102b is connected in parallel with the semiconductor module 101b between the lead terminal 105a and the heat dissipation plate 107b.
  • the remaining two sets of circuits Cir2 and Cir3 also have the same structure as the circuit Cir1 described above. Therefore, in the semiconductor module 500, three sets of circuits Cir1, Cir2, and Cir3 are connected in parallel between the heat sinks 107a and 107b. As common lead terminals, the lead terminal 105d is connected to the heat radiating plate 107a, and the lead terminal 105e is connected to the heat radiating plate 107b.
  • a structure S in which three sets of circuits Cir1, Cir2, and Cir3 are connected in parallel between a heat sink 107a to which the lead terminal 105d is connected and a heat sink 107b to which the lead terminal 105e is connected is made of a sealing resin 108 is sealed.
  • Lead terminals 105a, 105b, 105c, 105d, and 105e are led out from the side surface of the sealing resin. Further, the heat radiating plates 107 a and 107 b are exposed on both main surfaces of the sealing resin 108.
  • a large number of lead terminals are led out from the sealing resin 108. That is, at least the lead terminals 105a, 105b, and 105c connected to the circuit Cir1, the lead terminals 105a, 105b, and 105c connected to the circuit Cir2, and the lead terminals 105a, 105b, and 105c connected to the circuit Cir3 are common. Lead terminals 105d and 105e are led out from the sealing resin 108 to the outside.
  • the semiconductor module 500 having a structure in which the large number of lead terminals 105a to 105e are arranged in the sealing resin 108 without being fixed is difficult to manufacture and easily causes poor quality such as poor connection.
  • the signal electrode pad (not shown) of the semiconductor switching element 101a and the lead terminal 105b are wire-bonded by the wire 103a, and the signal electrode pad (semiconductor switching element 101b) (Not shown) and the lead terminal 105c are wire-bonded by the wire 103b.
  • the lead terminals 105b and 105c are not fixed to something, the wire bonding is difficult, and the quality defect due to poor connection is also caused. Easy to wake up.
  • the sealing resin 108 is formed in the manufacturing process of the semiconductor module 500 by three sets of circuits Cir1 between the heat sink 107a to which the lead terminal 105d is connected and the heat sink 107b to which the lead terminal 105e is connected.
  • the structure S in which Cir2 and Cir3 are connected in parallel is housed in a mold (not shown) with the lead terminals 105a, 105b, 105c, 105d, and 105e led out to the outside, and resin is placed in the mold.
  • a method of forming by transfer molding is common.
  • the lead terminals 105a to 105e are not fixed, the lead terminals 105a to 105e are pushed and moved by the resin when the sealing resin 108 is formed by transfer molding the resin in the mold. Wire bonding by 103a and 103b may be disconnected, or bonding by the solder 104 may be disconnected, resulting in poor quality due to poor connection.
  • wire bonding between the lead terminal 105b by the wire 103a and the signal electrode pad of the semiconductor switching element 101a or wire bonding between the lead terminal 105c by the wire 103b and the signal electrode pad of the semiconductor switching element 101b may be disconnected. was there. Further, there is a possibility that the bonding between the lead terminal 105a and the other electrode pad of the semiconductor switching element 101a, the one electrode pad of the semiconductor switching element 101b, and the diodes 102a and 102b due to the solder 104 may be broken. Further, there is a possibility that the bonding between the lead terminal 105d and the heat radiating plate 107a and the bonding between the lead terminal 105e and the heat radiating plate 107b are disconnected by solder (not shown).
  • the semiconductor module 500 having a structure in which a large number of lead terminals 105a to 105e are not fixed and disposed in the sealing resin 108 is difficult to manufacture and easily causes poor quality such as poor connection. It was.
  • the semiconductor module of the present invention includes at least a plurality of semiconductor switching elements and a plurality of lead terminals in a sealing resin.
  • the sealing resin is further sealed with a plurality of plate-like insulating base materials, lead terminals are joined to the insulating base material, and the insulating base material is vertically moved in the sealing resin.
  • the lead terminals are also arranged in at least three layers at intervals in the vertical direction in the sealing resin by being arranged in at least three layers with a gap therebetween, and the semiconductor switching element is The signal electrode pad and one power electrode pad are formed on one main surface, the other power electrode pad is formed on the other main surface, and the power electrode pads formed on both main surfaces of the semiconductor switching element are directly Or indirectly, the signal electrode pad bonded to the predetermined lead terminal and formed on one main surface of the semiconductor switching element is wire-bonded to the predetermined lead terminal by a wire, and at least a part of the lead terminal is The lead is led out from the sealing resin.
  • an opening penetrating between both main surfaces is formed in the insulating base material, and at least a part of the lead terminal joined to the insulating base material is disposed in the opening.
  • a lead terminal joined to the insulating base material and a member arranged on the main surface side where the lead terminal of the insulating base material is not joined for example, a metal block, Bonding with solder or the like can be performed.
  • the insulating base material can be made of a resin containing a filler, and the sealing resin can be made of a resin not containing a filler.
  • the insulating base material and the sealing resin are made of a resin containing a filler, and the content volume ratio of the filler of the sealing resin can be lower than the content volume ratio of the filler of the insulating base material.
  • the insulating base material can be formed of a resin having a high strength and containing a sufficient amount of filler, and the sealing resin can be formed of a resin having high fluidity and easy to transfer mold. .
  • the insulating base is made of ceramic
  • the lead terminal is bonded to the insulating substrate through an alloy containing at least an active metal that reacts with the ceramic components, Ag, and Cu. Can do.
  • the lead terminal can be firmly bonded to the insulating substrate having high strength.
  • the lead terminals arranged in at least three layers are joined to two different insulating substrates on both main surfaces, and the two insulations
  • the sealing resin can be filled between the substrates.
  • the insulating base is formed of a resin containing a filler and the sealing resin is formed of a resin not containing a filler, or the insulating base and the sealing resin are resins containing a filler.
  • the volume fraction of filler in the insulating base material is higher than the volume fraction of filler in the sealing resin, the linear expansion coefficient of the insulating base material and the linear expansion coefficient of the sealing resin And will be different.
  • the linear expansion coefficient of the insulating base material is smaller than the linear expansion coefficient of the sealing resin.
  • the semiconductor switching element generates heat in the semiconductor module, if the linear expansion coefficient of the insulating base material and the linear expansion coefficient of the sealing resin are different, the interface between the two may be peeled off. If the interface between the insulating substrate and the sealing resin is peeled off, the wire bonding may be disconnected or the bonding by solder may be disconnected, resulting in a quality defect due to poor connection.
  • the lead terminal is bonded to two different insulating bases on both main surfaces and the sealing resin is filled between the two insulating bases, the lead terminal is sealed with the insulating base due to the difference in linear expansion coefficient. Separation of the interface with the stop resin can be suppressed.
  • a power electrode pad formed on one main surface of at least one semiconductor switching element may be bonded to a predetermined lead terminal via a metal block.
  • the distance between the semiconductor switching element and the lead terminal can be increased, wire bonding between the signal electrode pad of the semiconductor switching element and another lead terminal by a wire is facilitated.
  • the heat radiating plate may be exposed from at least one main surface of the sealing resin. In this case, the heat generated by the semiconductor switching element can be diffused efficiently.
  • a passive element may be further sealed in the sealing resin.
  • a passive element if a shunt resistor element is inserted between a semiconductor switching element and an intermediate terminal and sealed with a sealing resin, the voltage between both electrodes of the shunt resistor element is monitored. Abnormal current can be detected. Alternatively, abnormal heat generation of the semiconductor switching element can be detected by sealing a thermistor element connected to another circuit system with a sealing resin as a passive element.
  • a reflux diode may be further sealed in the sealing resin.
  • the semiconductor module can be an inverter, for example.
  • the semiconductor module of the present invention is easy to manufacture because the lead terminal is bonded to the insulating base material and then sealed with the sealing resin. For example, the process of wire bonding to the lead terminal and the process of forming the sealing resin by transfer molding are easy.
  • the semiconductor module of the present invention is sealed with the sealing resin after the lead terminals are bonded to the insulating base material, in the manufacturing process, the connection failure due to the disconnection of the wire bonding or the disconnection of the solder bonding Is less likely to occur and is highly reliable.
  • FIG. 1A is a perspective view showing the semiconductor module 100 according to the first embodiment.
  • FIG. 1B is a cross-sectional view showing the semiconductor module 100 and shows a portion XX in FIG.
  • FIG. 2 is an exploded perspective view showing the semiconductor module 100.
  • FIG. 3 is an equivalent circuit diagram of the semiconductor module 100.
  • 4 (A) and 4 (B) show the case where the insulating base is formed of one insulating base 6x having a large thickness and the case where the insulating base is formed of two insulating bases 6b and 6c having a small thickness. It is explanatory drawing which shows each interface stress.
  • FIG. 5 is a perspective view showing steps applied in an example of a method for manufacturing the semiconductor module 100.
  • FIG. 5 is a perspective view showing steps applied in an example of a method for manufacturing the semiconductor module 100.
  • FIG. 6 is a perspective view showing a process applied in an example of a manufacturing method of the semiconductor module 100.
  • FIG. 7 is a perspective view showing steps applied in an example of a method for manufacturing the semiconductor module 100.
  • FIG. 8 is a perspective view showing steps applied in an example of a method for manufacturing the semiconductor module 100.
  • FIG. 9 is a perspective view showing steps applied in an example of a method for manufacturing the semiconductor module 100.
  • FIG. 10 is a perspective view showing steps applied in an example of a method for manufacturing the semiconductor module 100.
  • FIG. 11 is a cross-sectional view showing a semiconductor module 200 according to the second embodiment.
  • FIG. 12 is a perspective view showing a semiconductor module 300 according to the third embodiment.
  • FIG. 13A is a perspective view showing a semiconductor module 400 according to the fourth embodiment.
  • FIG. 13B is an equivalent circuit diagram of the semiconductor module 400.
  • FIG. 14A is a plan view showing a conventional semiconductor module 500 disclosed in Patent Document 1.
  • FIG. 14B is a cross-sectional view showing the semiconductor module 500, and shows a portion XX in FIG.
  • First Embodiment 1A, 1B, 2 and 3 show a semiconductor module 100 according to a first embodiment of the present invention.
  • FIG. 1A is a perspective view of the semiconductor module 100.
  • FIG. 1B is a cross-sectional view of the semiconductor module 100 and shows a portion XX in FIG. Note that FIG. In (B), illustration of the sealing resin 8 described later is omitted, and the portion is indicated by a broken line.
  • FIG. 2 is an exploded perspective view of the semiconductor module 100.
  • the sealing resin 8 is not shown.
  • FIG. 3 is an equivalent circuit diagram of the semiconductor module 100.
  • the semiconductor module 100 is an inverter.
  • the semiconductor module 100 includes four rectangular and plate-like insulating bases 6a, 6b, and 6c6d.
  • the insulating bases 6a to 6d are made of, for example, a resin such as epoxy or polyimide filled with a filler for increasing the strength.
  • a rectangular opening 7a is formed so as to penetrate between both main surfaces.
  • Two rectangular openings 7b and 7c are formed in the central portion of the insulating base 6b so as to penetrate between both main surfaces.
  • a rectangular opening 7d is formed in the central portion of the insulating base 6c so as to penetrate between both main surfaces.
  • Two rectangular openings 7e and 7f are formed in the central portion of the insulating base 6d so as to penetrate between both main surfaces.
  • the opening areas of the openings 7a, 7b, 7d, and 7e are larger than the opening areas of the openings 7c and 7f.
  • An L-shaped plate-like lead terminal 51a is fixed to one main surface (the upper main surface in FIG. 2) of the insulating base 6a.
  • the lead terminal 51a is exposed from the opening 7a to the other main surface (lower main surface in FIG. 2) of the insulating base 6a.
  • the insulating base 6b and the insulating base 6c are integrated by fixing six lead terminals 52a, 52b, 52c, 52d, 52e, 52f between them.
  • the widths of the lead terminals 52a, 52b, and 52c are larger than the widths of the lead terminals 52d, 52e, and 52f.
  • the lead terminals 52a, 52b, 52c are led out from the insulating bases 6b and 6c along one side of the insulating bases 6b and 6c, and the other ends are exposed from the openings 7b and 7d.
  • the lead terminals 52d, 52e, 52f have one end led out from the insulating bases 6b and 6c along the other side of the insulating bases 6b and 6c, and the other end exposed from the opening 7c. It is fixed.
  • An L-shaped plate-like lead terminal 53a is fixed to the other main surface (lower main surface in FIG. 2) of the insulating base 6d.
  • the lead terminal 53a is exposed from the opening 7e to the one main surface (upper main surface in FIG. 2) side of the insulating base 6d.
  • three lead terminals 53b, 53c, 53d are fixed to the other main surface of the insulating base 6d.
  • the widths of the lead terminals 53b, 53c, and 53d are the same as the widths of the lead terminals 52d, 52e, and 52f.
  • the lead terminals 53b, 53c, 53d have one end led out from the insulating base 6d along one side of the insulating base 6d, and the other end of the lead terminals 53b, 53c, 53d from the opening 7f.
  • the main surface is exposed and fixed.
  • metals such as Cu, Fe, Ni, Sn, Mg, Al, Cr, and Zr are used.
  • the semiconductor module 100 includes six semiconductor switching elements 1a, 1b, 1c, 1d, 1e, and 1f.
  • MOSFETs are used as the semiconductor switching elements 1a to 1f. Since the semiconductor module 100 uses MOSFETs for the semiconductor switching elements 1a to 1f, an inverter is configured without using a free-wheeling diode.
  • Each of the semiconductor switching elements 1a to 1f has one main surface (upper main surface in FIG. 2), one power electrode pad (not shown), and a signal electrode pad (shown with reference numerals).
  • the other power supply electrode pad (not shown) is formed on the other main surface (the lower main surface in FIG. 2).
  • the other power electrode pad is joined to the lead terminal 52a fixed between the insulating bases 6b and 6c at the opening 7b portion by the solder 4.
  • the other power electrode pad is joined to the lead terminal 52b fixed between the insulating bases 6b and 6c at the opening 7b portion by the solder 4.
  • the other power electrode pad is joined by solder 4 to a lead terminal 52c fixed between the insulating bases 6b and 6c at the opening 7b portion.
  • the semiconductor switching elements 1d, 1e, and 1f are joined to the lead terminals 53a fixed to the insulating base 6d by the solder 4 at the openings 7e.
  • the signal electrode pad of the semiconductor switching element 1a is wire-bonded to the lead terminal 52d fixed between the insulating bases 6b and 6c at the opening 7c portion by the wire 3a.
  • the signal electrode pad of the semiconductor switching element 1b is wire-bonded to the lead terminal 52e fixed between the insulating base materials 6b and 6c at the opening 7c portion by the wire 3b.
  • the signal electrode pad of the semiconductor switching element 1c is wire-bonded to the lead terminal 52f fixed between the insulating base materials 6b and 6c at the opening 7c portion by the wire 3c.
  • the signal electrode pad of the semiconductor switching element 1d is wire-bonded to the lead terminal 53b fixed to the insulating base 6d at the opening 7f portion by the wire 3d.
  • the signal electrode pad of the semiconductor switching element 1e is wire-bonded to the lead terminal 53c fixed to the insulating base 6d at the opening 7f portion by the wire 3e.
  • the signal electrode pad of the semiconductor switching element 1f is wire-bonded to the lead terminal 53d fixed to the insulating base 6d at the opening 7f by the wire 3f.
  • a metal such as Al, Au, or Cu is used.
  • a rectangular parallelepiped metal block 2 a is joined to one power supply electrode pad of the semiconductor switching element 1 a by solder 4.
  • a rectangular parallelepiped metal block 2b is joined to one power supply electrode pad of the semiconductor switching element 1b by solder 4.
  • a rectangular parallelepiped metal block 2c is joined to one power electrode pad of the semiconductor switching element 1c by solder 4.
  • a rectangular parallelepiped metal block 2d is joined by solder 4 to one power supply electrode pad of the semiconductor switching element 1d.
  • a rectangular parallelepiped metal block 2e is joined by solder 4 to one power supply electrode pad of the semiconductor switching element 1e.
  • a rectangular parallelepiped metal block 2 f is joined to one power supply electrode pad of the semiconductor switching element 1 f by solder 4.
  • metals such as Cu, Al, Fe, and Ag are used.
  • the metal blocks 2a, 2b, and 2c are joined by solder 4 to the lead terminals 51a fixed to the insulating base 6a at the opening 7a portion.
  • the metal block 2d is joined to the lead terminal 52a fixed between the insulating base materials 6b and 6c by the solder 4 at the opening 7d portion.
  • the metal block 2e is joined to the lead terminal 52b fixed between the insulating base materials 6b and 6c by the solder 4 at the opening 7d portion.
  • the metal block 2f is joined to the lead terminal 52c fixed between the insulating base materials 6b and 6c by the solder 4 at the opening 7d portion.
  • the semiconductor switching elements 1a to 1f, the metal blocks 2a to 2f, the lead terminals 51a to 53d, the insulating bases 6a to 6d, and the like are integrated to form the structure S.
  • the structure S is sealed in the sealing resin 8 with the lead terminals 51a to 53d led out from the side.
  • the sealing resin 8 for example, epoxy, polyimide or the like is used.
  • the sealing resin 8 Since the sealing resin 8 is formed by transfer molding as described later, high fluidity is required. Therefore, the sealing resin 8 does not contain a filler, or even if contained, the volume content of the filler of the sealing resin 8 is the content volume of the filler of the resin used for the insulating base materials 6a to 6d. It is set lower than the rate.
  • the sealing resin 8 is also filled between the insulating base 6b and the insulating base 6c.
  • This structure has a function of preventing peeling at the interface between the insulating bases 6b and 6c and the sealing resin 8.
  • the resin used for the insulating bases 6a to 6d is filled with a filler to increase the strength.
  • the filler does not contain, or even if contained, the volume ratio of the filler is the insulating base materials 6a to 6d. It is set lower than the content volume ratio of the filler of the resin used.
  • a difference occurs between the linear expansion coefficient of the insulating base materials 6a to 6d and the linear expansion coefficient of the sealing resin 8.
  • the linear expansion coefficient of the insulating base materials 6a to 6d is about 10 to 15 ppm / ° C.
  • the linear expansion coefficient of the sealing resin 8 is 20 ppm / ° C. or more.
  • the insulating base 6x is divided into two insulating bases 6b and 6c having a small thickness and sealed between the insulating bases 6b and 6c. Resin 8 was filled. As a result, the difference in volume displacement between the sealing resin 8 and the insulating base materials 6b and 6c is reduced, and the interface stress is reduced, so that the insulating base materials 6b and 6c are prevented from peeling off from the sealing resin 8. If the interface between the insulating bases 6b and 6c and the sealing resin 8 is peeled off, the wire bondings 3a to 3f may be disconnected or the bonding by the solder 4 may be disconnected, resulting in poor connection. There is no such fear.
  • the semiconductor module 100 according to the first embodiment of the present invention having the above structure constitutes an inverter having the equivalent circuit shown in FIG.
  • the lead terminal 53a corresponds to the P-side terminal
  • the lead terminal 51a corresponds to the N-side terminal
  • the lead terminals 52a, 52b, and 52c correspond to intermediate terminals, respectively.
  • the lead terminals 52d, 52e, 52f, 53b, 53c, and 53d correspond to gate terminals, respectively.
  • the semiconductor module 100 according to the first embodiment can be manufactured by, for example, the method shown in FIGS. 5 to 10 are perspective views.
  • insulating base materials 6a to 6d and lead terminals 51a to 53d are prepared.
  • An opening 7a is previously formed in the insulating base 6a.
  • Openings 7b and 7c are formed in the insulating base 6b in advance.
  • An opening 7d is formed in advance in the insulating base 6d.
  • Openings 7e and 7f are formed in advance in the insulating base 6d.
  • the lead terminals 51a to 53d are fixed to the insulating bases 6a to 6d. Fixing is performed by, for example, an adhesive. The state after fixing is shown in FIG.
  • the semiconductor switching elements 1a to 1f are prepared. Subsequently, as shown in FIG. 7, the other power supply electrode pads (formed on the lower main surface of the semiconductor switching elements 1a to 1f in FIG. 7) of the semiconductor switching elements 1a to 1f are soldered (see FIG. 7). To the lead terminals 52a to 52c and 53a. More specifically, in the opening 7b, the other power electrode pad of the semiconductor switching element 1a is used as the lead terminal 52a, the other power electrode pad of the semiconductor switching element 1b is used as the lead terminal 52b, and the other power supply of the semiconductor switching element 1c is used. The electrode pads are bonded to the lead terminals 52c, respectively. Further, in the opening 7e, the other power electrode pads of the semiconductor switching elements 1d to 1f are respectively joined to the lead terminals 53a.
  • the lead terminals 52a to 52c are fixed to the insulating bases 6b and 6c in advance and the lead terminal 53a is fixed to the insulating base 6d, the lead terminals are arranged individually without being fixed.
  • the semiconductor switching elements 1a to 1f are more easily joined to the lead terminals 52a to 52c and 53a than in the case of the above. That is, the semiconductor module 100 is easier to manufacture than the conventional one.
  • the metal blocks 2a to 2f are prepared. Subsequently, as shown in FIG. 8, solder (not shown) is applied to one power supply electrode pad (formed on the upper main surface of each semiconductor switching element 1a to 1f in FIG. 8) of the semiconductor switching elements 1a to 1f.
  • the metal blocks 2a to 2f are joined together. More specifically, the metal block 2a is provided on one power electrode pad of the semiconductor switching element 1a, the metal block 2b is provided on one power electrode pad of the semiconductor switching element 1b, and the metal block is provided on one power electrode pad of the semiconductor switching element 1c.
  • the signal electrode pads (not shown but provided with reference numerals) of the semiconductor switching elements 1a to 1f and the lead terminals 52d to 52f and 53b to 53d are connected to the wires 3a to 3d. Wire bonding is performed by 3f. More specifically, in the opening 7c portion, the signal electrode pad of the semiconductor switching element 1a and the lead terminal 52d are connected by the wire 3a, and the signal electrode pad of the semiconductor switching element 1b and the lead terminal 52e are connected by the wire 3b, thereby the semiconductor switching element 1c. The signal electrode pads and the lead terminals 52f are wire-bonded with the wires 3c.
  • the signal electrode pad of the semiconductor switching element 1d and the lead terminal 53b are connected by the wire 3d
  • the signal electrode pad of the semiconductor switching element 1e and the lead terminal 53c are connected by the wire 3e and the signal electrode of the semiconductor switching element 1f.
  • the pad and the lead terminal 53d are wire-bonded with the wire 3f.
  • the lead terminals 52a to 52f are fixed to the insulating bases 6b and 6c in advance, and the lead terminals 53a to 53d are fixed to the insulating base 6d.
  • wire bonding of the wires 3a to 3f is easier than in the case where the semiconductor switching element is bonded to such a lead terminal. That is, the semiconductor module 100 is easier to manufacture than the conventional one.
  • the metal blocks 2a to 2f and the lead terminals 51a and 52a to 52c are joined by solder (not shown). More specifically, the metal blocks 2a to 2c and the lead terminal 51a are joined to each other at the opening 7b. Further, in the openings 7b and 7d, the metal block 2d and the lead terminal 52a, the metal block 2e and the lead terminal 52b, and the metal block 2f and the lead terminal 52c are joined, respectively. As a result, the insulating bases 6a to 6d to which the lead terminals 51a to 53d are fixed, the semiconductor switching elements 1a to 1f, the metal blocks 2a to 2f, and the like are integrated to form the structure S.
  • the metal blocks 2d to 2f and the metal blocks 2d to 2f are used rather than the case where the lead terminals are individually arranged without being fixed. It is easy to join the lead terminals 52a to 52c with solder. That is, the semiconductor module 100 is easier to manufacture than the conventional one.
  • the structure S is housed in a mold with the lead terminals 51a to 53d led out to the outside. Subsequently, the resin is transfer-molded in the mold to form the sealing resin 8, the lead terminals 51a to 53d are led out to the outside, and the structure S is sealed in the sealing resin 8, The semiconductor module 100 according to one embodiment is completed.
  • the lead terminal 51a is fixed to the insulating base 6a in advance, the lead terminals 52a to 52f are fixed to the insulating bases 6b and 6c, and the lead terminals 53a to 53d are fixed to the insulating base 6d. Therefore, it is easy to accommodate them in the mold. Further, by being fixed to the insulating bases 6a to 6d, the lead terminals 51a to 53d are restrained from being moved by being pushed by the resin when the resin is transfer-molded into the mold, and wire bonding is prevented. The disconnection or the disconnection by soldering is suppressed. That is, the semiconductor module 100 is easier to manufacture and more reliable than the conventional one.
  • FIG. 11 shows a semiconductor module 200 according to the second embodiment.
  • FIG. 11 is a cross-sectional view of the semiconductor module 200.
  • MOSFETs are used for the semiconductor switching elements 1a to 1s. Therefore, in the semiconductor module 100, an inverter is configured without using a reflux diode.
  • IGBTs Insulated Gate Bipolar Transistors
  • diodes 9a to 9f are used in the semiconductor module 200 (only the diodes 9c and 9f are shown in FIG. 11).
  • lead terminals 51s and 51t are fixed to the insulating base 6a. Also, lead terminals 52s and 52t are fixed between the insulating bases 6b and 6c. Furthermore, lead terminals 53s, 53t, and 53u are fixed to the insulating base 6d.
  • a semiconductor switching element (IGBT) 1c having a metal block 2c fixed thereto is inserted between the lead terminals 51t and 52s.
  • a signal electrode pad (not shown) of the semiconductor switching element 1c is wire-bonded to the lead terminal 52t by a wire 3c.
  • a semiconductor switching element (IGBT) 1f to which a metal block 2f is fixed is inserted between the lead terminals 52s and 53t.
  • a signal electrode pad (not shown) of the semiconductor switching element 1f is wire-bonded to the lead terminal 53u by a wire 3f.
  • a diode 9c having a metal block 12c fixed by solder 4 is inserted between the lead terminals 51s and 52s.
  • a diode 9f having a metal block 12f fixed by solder 4 is inserted between the lead terminals 52s and 53s.
  • the inverter is configured by using IGBTs for the semiconductor switching elements 1a to 1s and further using the diodes 9a to 9f.
  • FIG. 12 is a cross-sectional view of the semiconductor module 300.
  • the heat sinks 10a and 10b are added to the semiconductor module 100 according to the first embodiment shown in FIGS.
  • the insulating base 6f is newly fixed to the main surface of the lead terminal 51a of the semiconductor module 100 where the insulating base 6a is not fixed, and the heat radiating plate 10a is fixed to the insulating base 6f.
  • the heat sink 10 a is exposed to the outside from the upper main surface of the sealing resin 8.
  • the insulating base 6g was newly fixed on the main surface of the lead terminals 53a and 53d of the semiconductor module 100 where the insulating base 6d is not fixed, and the heat sink 10b was fixed to the insulating base 6g.
  • the heat radiating plate 10 b is exposed to the outside from the lower main surface of the sealing resin 8.
  • the other configuration of the semiconductor module 300 is the same as the configuration of the semiconductor module 100.
  • the heat sinks 10a and 10b are provided as in the semiconductor module 300, the heat generated by the switching elements 1a to 1f can be efficiently dissipated.
  • FIGS. 13A is a cross-sectional view of the semiconductor module 400.
  • FIG. 13B is an equivalent circuit diagram of the semiconductor module 400.
  • the semiconductor module 400 In the semiconductor module 400 according to the fourth embodiment, three shunt resistor elements 20 are added to the semiconductor module 100 according to the first embodiment shown in FIGS. Specifically, as shown in FIG. 13A, the semiconductor module 400 has a shunt resistor element 20 added thereto.
  • the semiconductor module 400 shortens one lead terminal 52c that is fixed between the insulating bases 6b and 6c in the semiconductor module 100 according to the first embodiment, A lead terminal 52g is newly fixed between the lead terminals 52c and 52f.
  • a shunt resistance element 20 having a pair of electrode pads formed on the bottom surface is prepared, and one electrode pad is joined to the lead terminal 52c and the other electrode pad is joined to the lead terminal 52g by the solder 4.
  • the other power electrode pad (not shown) of the semiconductor switching element 1c is joined to the lead terminal 52g instead of the lead terminal 52c joined in the semiconductor module 100 according to the first embodiment.
  • Two more shunt resistor elements 20 are also added to the semiconductor module 400 by the same method.
  • the semiconductor module 400 includes an equivalent circuit shown in FIG. That is, the shunt resistor element 20 is inserted between the connection point of the semiconductor switching elements 1a and 1d and the lead terminal 52a that is an intermediate terminal. Further, the shunt resistor element 20 is inserted between the connection point of the semiconductor switching elements 1b and 1e and the lead terminal 52b which is an intermediate terminal. Further, the shunt resistor element 20 is inserted between the connection point of the semiconductor switching elements 1c and 1f and the lead terminal 52c which is an intermediate terminal.
  • the semiconductor module 400 can detect the occurrence of an abnormal current by monitoring the voltage between both power supply electrode pads of each shunt resistance element 20.
  • the material of the components of the semiconductor module 100 according to the first embodiment is partially changed. Since the structure itself is not changed, the semiconductor module 500 will be described with reference to FIGS. 1 and 2 illustrating the semiconductor module 100.
  • a resin such as epoxy or polyimide filled with filler is used for the insulating bases 6a to 6d.
  • ceramics are used for the insulating bases 6a to 6d. More specifically, for example, a ceramic mainly composed of silicon nitride, aluminum nitride, alumina, or the like is used as the ceramic constituting the insulating bases 6a to 6d.
  • an adhesive is used for joining the lead terminals 51a, 52a to 52f, 53a to 53d to the insulating bases 6a to 6d.
  • an alloy (not shown) containing at least an active metal that reacts with the constituent components of the ceramic, Ag, and Cu is used for bonding of this portion.
  • Ti is contained in the alloy as an active metal that reacts with the constituent components of the ceramic.
  • the active metal that reacts with the components contained in the ceramic is not limited to Ti, and may be other metals such as Zr.
  • the active metal which reacts with the structural component of ceramics, the alloy containing Ag and Cu may be called an active metal brazing material.
  • Ti, Zn, Sn, In, Ni, Mn, Cd, etc. are used to adjust the melting point as necessary.
  • One or more selected metals may be added.
  • Ti added as an active component that reacts with components contained in the ceramic also plays a role of adjusting the melting point.
  • the addition amount of Ti is 3 weight% or less with respect to the total weight of an alloy. This is because if the Ti content exceeds 3% by weight, the alloy itself may become brittle.
  • the compounding ratio of the alloy 6 is set to Ag 60 to 80% by weight, Cu 20 to 40% by weight, and Ti 1 to 3% by weight.
  • the other configuration of the semiconductor module 500 is the same as that of the semiconductor module 100.
  • a paste made of an active metal brazing material is applied to the lead terminals 51a, 52a to 52f, 53a to 53d in advance.
  • the coating can be performed by bringing the coated surface into contact with the insulating substrates 6a to 6d and performing a heat treatment at a temperature equal to or higher than the melting point of the active metal brazing material.
  • An alloy containing an active metal that reacts with the components of the ceramic, Ag, and Cu firmly bonds the lead terminals 51a, 52a to 52f, and 53a to 53d to the insulating bases 6a to 6d.
  • silicon nitride is used for the insulating bases 6a to 6d
  • Cu is used for the lead terminals 51a, 52a to 52f, 53a to 53d, and both are joined by an alloy containing Ag and Cu to which Ti is added, TiN and MN are formed in the vicinity of the alloy insulating substrates (silicon nitride substrates) 6a to 6d (where M is an alloy of Si, Cu, and Ti).
  • the Ti concentration in the vicinity of the insulating substrates 6a to 6d of the alloy is higher than the Ti concentration in other portions of the alloy.
  • the lead terminals 2a to 2e and the insulating substrates 6a to 6d are bonded with high strength.
  • an alloy containing an active metal that reacts with a constituent component of ceramic, Ag, and Cu generally has a higher thermal conductivity than an adhesive. Therefore, the semiconductor module 500 is more efficient for the heat generated by the semiconductor switching elements 1a to 1f via the lead terminals 51a, 52a to 52f, 53a to 53d, and further via the insulating bases 6a to 6d. Can be dissipated.
  • the lead terminals 51a, 52a to 52f, and 53a to 53d are formed on the insulating bases 6a to 6d made of ceramics having high strength, and the ceramic components are included. Since it is firmly joined through an alloy containing an active metal that reacts, Ag, and Cu, it has high strength. Moreover, it is excellent also in heat dissipation.
  • the circuit configuration of the semiconductor module of the present invention is arbitrary, and is not limited to the equivalent circuit of the semiconductor modules 100 to 500.
  • the shunt resistor element 20 is additionally sealed in the sealing resin 8 as a passive element.
  • a thermistor element for monitoring abnormal heat generation is used as the sealing resin. 8 may be sealed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Inverter Devices (AREA)

Abstract

L'invention porte sur un module à semi-conducteur qui est facile à fabriquer et qui est peu susceptible de présenter une qualité médiocre résultant de connexions défectueuses. Dans ce module à semi-conducteur, des éléments de commutation à semi-conducteur 1a à 1f et des bornes de sortie 52a à 53d sont enrobés par une résine d'étanchéité 8, et des substrats isolants en forme de plaque 6a à 6d sont également enrobés dans la résine d'étanchéité 8. Les bornes de sortie 52a à 53d sont collées aux substrats isolants 6a à 6d, si bien que, par agencement des substrats isolants 6a à 6d dans la résine d'étanchéité 8 de sorte qu'ils sont divisés en au moins trois couches et verticalement séparés par des espaces, les bornes de sortie 52a à 53d sont également agencées dans la résine d'étanchéité 8 de sorte qu'elles sont divisées en au moins trois couches et verticalement séparées par des espaces.
PCT/JP2016/052445 2015-02-02 2016-01-28 Module à semi-conducteur WO2016125669A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2016573311A JP6447842B2 (ja) 2015-02-02 2016-01-28 半導体モジュール

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015018713 2015-02-02
JP2015-018713 2015-08-26

Publications (1)

Publication Number Publication Date
WO2016125669A1 true WO2016125669A1 (fr) 2016-08-11

Family

ID=56564017

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2016/052445 WO2016125669A1 (fr) 2015-02-02 2016-01-28 Module à semi-conducteur

Country Status (2)

Country Link
JP (1) JP6447842B2 (fr)
WO (1) WO2016125669A1 (fr)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004193405A (ja) * 2002-12-12 2004-07-08 Mitsubishi Electric Corp 半導体パワーモジュール
JP2007059860A (ja) * 2004-11-30 2007-03-08 Toshiba Corp 半導体パッケージ及び半導体モジュール
JP2009252838A (ja) * 2008-04-02 2009-10-29 Mitsubishi Electric Corp 半導体装置
WO2009150875A1 (fr) * 2008-06-12 2009-12-17 株式会社安川電機 Module d'alimentation et son procédé de commande
JP2012164697A (ja) * 2011-02-03 2012-08-30 Mitsubishi Electric Corp 電力用パワーモジュール及び電力用半導体装置
JP2013030710A (ja) * 2011-07-29 2013-02-07 Sanyo Electric Co Ltd 半導体モジュール
WO2013038749A1 (fr) * 2011-09-15 2013-03-21 住友電気工業株式会社 Borne d'électrode à feuille de câblage, corps de structure de câblage, dispositif à semi-conducteur, et procédé de fabrication dudit dispositif à semi-conducteur
JP2014154613A (ja) * 2013-02-06 2014-08-25 Mitsubishi Electric Corp 半導体装置およびその製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004193405A (ja) * 2002-12-12 2004-07-08 Mitsubishi Electric Corp 半導体パワーモジュール
JP2007059860A (ja) * 2004-11-30 2007-03-08 Toshiba Corp 半導体パッケージ及び半導体モジュール
JP2009252838A (ja) * 2008-04-02 2009-10-29 Mitsubishi Electric Corp 半導体装置
WO2009150875A1 (fr) * 2008-06-12 2009-12-17 株式会社安川電機 Module d'alimentation et son procédé de commande
JP2012164697A (ja) * 2011-02-03 2012-08-30 Mitsubishi Electric Corp 電力用パワーモジュール及び電力用半導体装置
JP2013030710A (ja) * 2011-07-29 2013-02-07 Sanyo Electric Co Ltd 半導体モジュール
WO2013038749A1 (fr) * 2011-09-15 2013-03-21 住友電気工業株式会社 Borne d'électrode à feuille de câblage, corps de structure de câblage, dispositif à semi-conducteur, et procédé de fabrication dudit dispositif à semi-conducteur
JP2014154613A (ja) * 2013-02-06 2014-08-25 Mitsubishi Electric Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JPWO2016125669A1 (ja) 2017-10-12
JP6447842B2 (ja) 2019-01-09

Similar Documents

Publication Publication Date Title
US10559538B2 (en) Power module
US10510640B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP4438489B2 (ja) 半導体装置
TW201626519A (zh) 附冷卻器電力模組用基板及其製造方法
JP2011114176A (ja) パワー半導体装置
JP6685470B2 (ja) 半導体装置およびその製造方法、ならびに電力変換装置
JP2019216214A (ja) 半導体装置、リードフレーム及び半導体装置の製造方法
JP2017188517A (ja) 電力半導体装置
EP1729343B1 (fr) Dispositif à haute prestation
JP2017123360A (ja) 半導体モジュール
JP5267021B2 (ja) 半導体装置およびそれを用いたインバータ回路
JP6380561B2 (ja) 半導体モジュール
WO2014021077A1 (fr) Substrat multicouche et module d'alimentation utilisant un substrat multicouche
JP2017135183A (ja) 半導体装置
JP6972174B2 (ja) 半導体装置および半導体装置の製造方法
JP6447842B2 (ja) 半導体モジュール
JP2014072314A (ja) 半導体装置、及び半導体装置の製造方法
JP2014143342A (ja) 半導体モジュール及びその製造方法
JP2015026667A (ja) 半導体モジュール
JP7183722B2 (ja) 板はんだおよび半導体装置の製造方法
WO2016125673A1 (fr) Module à semi-conducteurs, et unité de commande de puissance
JP6794734B2 (ja) 半導体装置及び半導体装置の製造方法
CN117083708A (zh) 半导体装置及半导体装置的制造方法
JP2013161996A (ja) 半導体装置
JP2015037149A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16746500

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2016573311

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16746500

Country of ref document: EP

Kind code of ref document: A1