WO2016123962A1 - 移位寄存器单元及其驱动方法、栅极扫描电路 - Google Patents

移位寄存器单元及其驱动方法、栅极扫描电路 Download PDF

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Publication number
WO2016123962A1
WO2016123962A1 PCT/CN2015/087661 CN2015087661W WO2016123962A1 WO 2016123962 A1 WO2016123962 A1 WO 2016123962A1 CN 2015087661 W CN2015087661 W CN 2015087661W WO 2016123962 A1 WO2016123962 A1 WO 2016123962A1
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Prior art keywords
module
reset
control
output
level
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PCT/CN2015/087661
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English (en)
French (fr)
Inventor
李全虎
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京东方科技集团股份有限公司
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Priority to US14/906,369 priority Critical patent/US9818339B2/en
Publication of WO2016123962A1 publication Critical patent/WO2016123962A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a shift register unit, a driving method thereof, and a gate scanning circuit.
  • OLED Organic Light Emitting Diode
  • PMOLED Passive Matrix Driving OLED
  • AMOLED Active Matrix Driving OLED
  • an AMOLED display panel generally needs to be driven using a gate driving signal having a plurality of pulses.
  • a gate driving signal having a plurality of pulses in order to ensure more charging, it is also required to drive using a gate driving signal having a plurality of pulses.
  • a gate drive signal having a plurality of pulses cannot be generated by one shift register unit.
  • An object of the present invention is to provide a shift register unit capable of outputting a shift signal having a plurality of pulses to output a gate drive signal having a plurality of pulses through one shift register unit.
  • the present invention provides a shift register unit including an input module for receiving a signal to be shifted, wherein the shift register further includes:
  • An output module, a reset module, and a reset control module wherein an output end of the input module, a control end of the output module, and an output end of the reset module are connected to the first node, and an output end of the reset control module and a control end of the reset module Connected, adapted to enable the reset module to reset the first node under control of a control signal accessed by a control terminal of the reset control module, such that before resetting the first node
  • the output module outputs a shift signal having a plurality of pulses.
  • control end of the reset control module includes a first control end and a second control end, and is adapted to close the reset module when the first control end accesses the first level, and access the first control end When the second level and the second control end are connected to the first level, the reset module is turned on to reset the first node.
  • the output end of the input module is adapted to set the first node to an output turn-on level capable of turning on the output module when the received signal to be shifted is at a pulse level;
  • the output module is adapted to output a shift signal when the level of the first node is an output on level
  • the reset module is adapted to reset a level of the first node to an output off level that enables the output module to be turned off after the output module outputs a shift signal.
  • the shift register unit further includes:
  • level maintaining module being coupled to the first node, adapted to maintain a level of the first node when both the input module and the reset module are turned off.
  • the first control end of the reset control module is connected to the signal input end to be shifted, and the second control end is connected to the shift signal output end of the shift register unit of the next stage, in the signal to be shifted and the shift signal
  • the pulse level coincides with the first level
  • the non-pulse level in the signal to be shifted and the shifted signal coincides with the second level.
  • the reset control module has a first access end and a second access end, and the second access end is configured to access a reset enable level that enables the reset module to be turned on, the first connection
  • the ingress is used to access a reset-off level capable of turning off the reset module
  • the reset control module is configured to: when the first control end accesses the first level, turn on the first access end and the output end, and when the second control end accesses the first level, the second access end is When the output end is turned on, and the output end is both on the first access end and the second access end, the level of the output end is consistent with the first access end.
  • the first access end of the reset control module is connected to the first common electrode, or the first clock signal input end, or the shift signal output end of the shift register unit, the level of the first common electrode Consistent with the reset off level, the clock signal input by the first clock signal input terminal is reset and closed when the first access end of the reset control module is turned on with the output end of the reset control module.
  • the second access end of the reset control module is connected to the second common electrode, or is connected to the shift signal output end of the next stage shift register unit, or is connected to the second clock signal input end, and the second common electrode is electrically connected Leveling is consistent with the reset on-level, and the clock signal input by the second clock signal input terminal is reset when the second access end of the reset control module is turned on with the output end of the reset control module. Turn on the level.
  • the reset control module includes a first transistor and a second transistor, and the first transistor and the second transistor are both turned off when the control terminal is connected to the first level, and turned off when the second level is turned on, wherein ,
  • the first end of the first transistor is connected to the first access end of the reset control module, the control end is connected to the first control end of the reset control module, and the second end is connected to the output end of the reset control module;
  • the first end of the second transistor is connected to the second access end of the reset control module, the control end is connected to the second control end of the reset control module, and the second end is connected to the output end of the reset control module,
  • the channel width to length ratio of the first transistor is greater than the channel width to length ratio of the second transistor.
  • the shift register unit further includes: a reset enhancement module and a reset enhancement control module;
  • An output end of the reset enhancement module is connected to the first node, and is adapted to reset a level of the first node;
  • An output end of the reset enhancement control module is connected to a control end of the reset enhancement module, and is adapted to be controlled by the reset module under control of a control signal accessed by a control end of the reset enhancement control module After the level of the first node is reset to the output off level, the reset enhancement module is turned on to continue resetting the first node.
  • the reset enhancement control module has a first access terminal and a second access terminal, a first control terminal, and a second control terminal, where the second access terminal is configured to enable the reset enhancement module to be enabled.
  • the reset strengthens the turn-on level, and the first access terminal is configured to access a reset boost-off level capable of turning off the reset enhancement module;
  • the first control end of the reset enhancement control module is connected to the first node, and is adapted to turn on the first access end and the output end when the first node is in the output enable level, and access the corresponding effective end in the second control end
  • the second access end is connected to the output end, and when the output end is connected to the first access end and the second access end, the level of the output end is consistent with the first access end.
  • the reset enhancement control module further includes a third control terminal and a third access terminal, wherein the third access terminal is configured to access a reset enhanced ON level, and the reset enhancement control module is adapted to be at the third control end.
  • the third access end and the output end are turned on, and when the output end is connected to the first access end and the third access end, the level of the output end and the first access The ends are consistent.
  • the reset enhancement control module includes a third transistor, a fourth transistor, and a fifth transistor, and a control end of the third transistor is connected to the first control end of the reset enhancement control module, and the first end is connected to the reset Reinforcing a first access end of the module, the second end is connected to an output end of the reset enhancement control module, and when the first control end of the reset enhancement control module is connected to the output enable level, the first end of the third transistor
  • the second end of the fourth transistor is connected to the second end of the reset enhancement control module, and the first end is connected to the second access end of the reset enhancement control module, and the second end is connected.
  • the output end of the reset enhancement control module; the control end of the fifth transistor is connected to the third control end of the reset enhancement control module, the first end is connected to the third access end of the reset enhancement control module, and the second end is connected The output of the reset enhancement control module; the fourth crystal
  • the effective level of the tube and the fifth transistor are opposite, or the second access terminal and the third access terminal are both used to access the clock signal, and the phase of the clock signal connected to the second access terminal is The clock signals connected to the three access terminals have opposite phases.
  • the shift register unit further includes: a load module, wherein the control end of the load module is connected to the first node, and is adapted to output a shift signal when the level of the first node is an output turn-on level.
  • the load module includes a transistor, the first end of the transistor is connected to the input end of the load module, the second end is connected to the output end of the load module, and the control end and the control end of the load module Connected.
  • the shift register unit further includes a pinch-off module for turning on when the output shift signal is at a pulse level, clamping the input module and/or the reset module and/or the reset enhancement module Broken.
  • the shift register unit further includes:
  • An auxiliary output module wherein the control end of the auxiliary output module is connected to the first node, and is adapted to output a shift signal when the level of the first node is an output open level, a pulse level of the shift signal and the output The turn-on level is consistent;
  • the input module, the reset module and the reset enhancement module each comprise a transistor combination consisting of two transistors connected in series;
  • a control end of the pinch-off module is connected to an output end of the load module, an input end is connected to an output end of the auxiliary output module, and an output end is connected to a series connection between two transistors in the transistor combination.
  • the pinch-off module includes a transistor, a first end of the transistor is connected to an input end of the pinch-off module, a second end is connected to an output end of the pinch-off module, and the control end is pinched off The control terminals of the modules are connected.
  • the auxiliary output module includes a transistor, and the transistor is first The terminal is connected to the input end of the auxiliary output module, the second end is connected to the output end of the auxiliary output module, and the control end is connected to the control end of the auxiliary output module.
  • the shift register unit further includes three reset modules, and the three reset modules are respectively used to load the output ends of the output module, the load module, and the auxiliary output module after the output module outputs the shift signal. Set so that the level of each output is reset to a non-pulse level.
  • control ends of the three reset modules are connected to the output end of the reset enhancement control module, and the input ends are used for accessing non-pulse levels, and the output ends are correspondingly connected with the output module, the load module, and the auxiliary output module.
  • the output terminals are connected, and when the reset enhancement control module turns on the reset enhancement module, the input terminal and the output terminal of the reset module are turned on.
  • each of the reset modules includes a transistor, a first end of the transistor is connected to an input end of the reset module, a second end is connected to an output end of the reset module, and the control end is The control terminals of the reset module are connected.
  • each transistor included in the shift register unit is an N-type transistor.
  • the present invention also provides a gate driving circuit comprising the shift register unit of any one of the above, further comprising at least one clock signal line, wherein the input end of the output module of each shift register unit is connected to the same clock signal line.
  • an input end of the input module of the first stage shift register unit of the plurality of shift register units is connected to the start signal input end.
  • the second access end of the reset control module of each shift register unit is connected to the second control end.
  • each shift register unit includes a transistor combination composed of two transistors connected in series
  • the control terminal of the transistor connected to the first node in the input module is connected to another clock signal line, and the other
  • the phase of the clock signal in the clock signal line is opposite to the phase of the clock signal in the clock signal line to which the output module is connected.
  • the present invention also provides a method of driving the shift register unit of any of the above, comprising:
  • the method specifically includes:
  • the first control terminal After outputting the same pulse number of shift signals for the received multi-pulse signals to be shifted, the first control terminal is connected to the second level and the second control terminal is connected to the first level.
  • the method specifically includes: connecting the first control end of the reset control module to the signal to be shifted, And the second control end of the reset control module is connected to the shift signal output by the next stage shift register unit, and when the first control end is connected to the pulse level, the first access end is connected to the reset and the power is turned off. Ping, when the first control terminal is connected to the non-pulse level and the second control terminal is connected to the pulse level, the second access terminal is connected to the reset on level.
  • the method further includes:
  • the reset module After the reset module resets the level of the first node to an output off level capable of turning off the output module, applying a control signal to the control end of the reset enhancement control module to strengthen the reset
  • the control module is turned on.
  • the method further includes:
  • the second control end of the reset enhancement control module is connected to the third clock signal input end, and the third control end is connected to the fourth clock signal input end, so that the output end of the reset enhancement control module and the reset strengthen control The first access end and the second access end of the module are alternately turned on.
  • the method further includes: applying a control signal to turn the pinch-off module on when the shift signal output by the shift register unit is at a pulse level.
  • the shift register unit provided by the invention comprises an input module, an output module, a reset module and a reset control module, wherein an output end of the input module, a control end of the output module, The output end of the reset module is connected to the first node, and the output end of the reset control module is connected to the control end of the reset module, and is adapted to be turned on under the control of the control signal accessed by the control end of the reset control module.
  • the reset module resets the first node such that the output module outputs a shift signal having a plurality of pulses before resetting the first node.
  • a gate driving signal having a plurality of pulses can be output through one shift register unit.
  • FIG. 1A is a schematic structural diagram of a shift register unit according to Embodiment 1 of the present invention.
  • FIG. 1B is a schematic structural diagram of another shift register unit according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural diagram of a possible reset control module according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic structural diagram of a possible reset enhancement control module according to Embodiment 1 of the present invention.
  • FIG. 4 is a circuit structural diagram of a shift register unit according to Embodiment 2 of the present invention.
  • Figure 5 is a timing diagram of key signals and node levels for the circuit of Figure 4 in operation.
  • a first embodiment of the present invention provides a shift register unit.
  • the shift register unit includes an input module 104, an output module 101, a reset module 102, and a reset control module 103.
  • the input module 104 The output end of the output module 101 and the output end of the reset module 102 are connected to the first node Q.
  • the input end of the input module 104 is used to receive the signal to be shifted, and the output of the reset control module 103 and the control of the reset module 102 are controlled.
  • the terminals are connected such that under the control of the control signal accessed by the control terminal of the reset control module 103, the reset module 102 resets the first node Q to cause the output module 101 to output a shift signal having a plurality of pulses.
  • a control signal is applied to the control end of the reset control module 103.
  • the reset module 102 is turned on to reset the first node Q such that the output module 101 can output a plurality of pulses before resetting the first node Q.
  • control end of each module is denoted as C
  • the input or access end is denoted as I
  • the output end is denoted as O
  • the xth input or access end is denoted as Ix
  • the xth control The end is denoted as Cx.
  • the shift register unit provided by the present invention is capable of outputting a shift signal having a plurality of pulses as a gate drive signal.
  • the control end of the reset control module 103 includes a first control terminal C1 and a second control terminal C2, so that when the first control terminal C1 accesses the first level, the control reset module 102 is turned off, at the first control end.
  • the control reset module 102 is turned on to reset the first node Q, so that the reset node 102 performs the first node Q.
  • the output module 101 outputs a shift signal having a plurality of pulses. Shown in Fig. 1A is a case where the reset control module 103 has two control terminals (C1, C2) and two access terminals (I1, I2).
  • the control reset module 102 when the first control terminal C1 of the reset control module 103 is connected to the first level, the control reset module 102 is not turned on, and the first control terminal C1 of the reset control module 103 is connected to the second level and is When the second control terminal C2 is connected to the second level, its control reset mode
  • the block 102 is also not turned on, and only when the first control terminal C1 of the reset control module 103 is connected to the second level and the second control terminal C2 is connected to the first level, the control reset module 102 is turned on. In this way, the first control terminal C1 can be connected to the signal to be shifted, and the second control terminal C2 can be connected to the shift signal output by the shift register unit of the next stage.
  • the shift signal outputted by the shift register unit of this stage is input to the input terminal of the shift register unit of the next stage.
  • the pulse level of the shift signal output by the signal to be shifted and the shift register unit of the next stage is the first level, and the non-pulse level is the second level, and the signal to be shifted is pulsed.
  • the reset module 102 is turned off, and the shift of the output of the next stage shift register unit is performed in the 2Nth stage where the signal to be shifted is a non-pulse level.
  • the bit signal is also a non-pulse level (the signal to be shifted input to the current stage is different from the shift signal output by the shift register unit of the next stage by two clocks), and the reset module 102 is still not turned on. If and only if the output module 101 outputs the 2N+1th stage after the N pulses, at this time, the signal to be shifted is a non-pulse level, and the shift signal outputted by the shift register unit of the next stage is the last. A pulse level causes the reset module 102 to turn on. Thus, the shift register unit of the present stage outputs a shift signal having a plurality of pulses before the reset module 102 is turned on to reset the first node Q.
  • the output module 101 herein can be identical to the output module of the prior art shift register unit, and both refer to a module for outputting a shift signal.
  • the input terminal I of the output module 101 is generally connected to a clock.
  • the signal when the first node Q is set to a level at which the output module 101 can be turned on, a clock signal is intercepted and output, and the part of the clock signal constitutes a shift signal. Thereafter, when the first node Q is reset, the output module 101 is turned off, and the shift signal is no longer output.
  • the output module 101 can also be other modules capable of outputting a shift signal, and the present invention will not be described in detail.
  • the reset module 102 herein may also be the same as the reset module in the prior art, and both refer to a module for resetting the first node Q.
  • the access terminal I of the reset module 102 can be connected.
  • the output module 101 is turned off by the output off level. When the reset module 102 is turned on, the output off level is applied to the first node Q, at which time the first node Q is reset, whereby the output module 101 is turned off.
  • the output terminal O of the input module 104 included in the shift register unit is connected to the first node Q, so that when the received signal to be shifted is at a pulse level, the first node Q is set to The output that can be turned on by the output module 101 is turned on.
  • the shift register unit may further include a level maintaining module 105 shown in FIG. 1A, and the level maintaining module 105 is connected to the first node Q, and is adapted to be in the input module 104 and the reset module. When 102 is off, the level of the first node Q is maintained.
  • the pulse level referred to in the present invention may specifically refer to a level corresponding to a pulse of the shift signal. For example, if the pulse of the shift signal is a positive pulse, the pulse level refers to a high level, correspondingly, non- The pulse level is low. If the pulse of the shift signal is a negative pulse, the pulse level refers to a low level, and the non-pulse level is a high level.
  • the level maintaining module 105 can record the pulse level in the shift signal and cause the output module 101 to be in an on state according to the recorded pulse level to output a shift signal.
  • the first control terminal C1 of the reset control module 103 is connected to the signal input terminal to be shifted for accessing the signal to be shifted STU, and the second control terminal C2 is connected to the shift of the shift register unit of the next stage.
  • a bit signal output terminal for accessing the shift signal STD of the next-stage shift register output, the pulse level in the signal to be shifted and the shift signal is consistent with the first level, and the signal to be shifted and shifted The non-pulse level in the bit signal coincides with the second level.
  • the reset connected to the first access terminal I1 of the reset control module 103 is turned off.
  • the level is turned on to the control terminal of the reset module 102, so that the reset module 102 is turned off;
  • the signal to be shifted input to the shift register unit of the present stage is a non-pulse level, and the shift signal output by the shift register unit of the next stage is When it is also a non-pulse level, the reset module 102 cannot be turned on; when the shift signal outputted by the shift register unit of the next stage is at the last pulse level, the signal to be shifted input to the shift register unit of the stage is no longer
  • the pulse level at this time, the reset ON level of the second access terminal I2 of the reset control module 103 is turned on to the control terminal C of the reset module 102, so that the reset module 102 is turned on, and the reset module 102 is connected to
  • the shift register unit of this stage The output module 101 is turned off and the pulse level is no longer output. In this way, the first node Q can be allowed to conduct in a plurality of clocks, so that the output module 101 outputs a plurality of pulses before the first node Q is reset.
  • the first access terminal I1 of the reset control module 103 is connected to the first common electrode, or the first clock signal input end, or the shift signal output end of the shift register unit, the first common
  • the level of the electrode is consistent with the reset-off level
  • the clock signal input by the first clock signal input terminal is at the first access terminal I1 of the reset control module 103 and the output of the reset control module 103.
  • the terminal O When the terminal O is turned on, it is a reset-off level; the second access terminal I2 of the reset control module 103 is connected to the second common electrode, or the shift signal output end of the next-stage shift register unit, or the second clock signal.
  • the input end, the level of the second common electrode is consistent with the reset on level, and the clock signal input by the second clock signal input end is at the second access end I2 of the reset control module 103 When the output terminal O of the reset control module 103 is turned on, it is a reset on level.
  • the first access terminal I1 of the reset control module 103 can also be connected to other input terminals, as long as the first access terminal I1 and the output terminal O of the reset control module 103 can be turned on.
  • An access terminal I1 is a reset-off level, and the corresponding technical solutions can implement the technical solution of the present invention.
  • the corresponding technical solutions should also fall within the protection scope of the present invention.
  • the specific structure of the above-mentioned reset control module 103 can refer to FIG. 2, which includes: a transistor T1 and a transistor T2, both of which are turned on when the gate (control terminal) is connected to the first level.
  • the second level is turned off, the first end of the transistor T1 is connected to the first access end I1 of the reset control module 103, and the control end is connected to the first control end C1 of the reset control module 103, the second end Connecting the output terminal O of the reset control module 103; the first end of the transistor T2 is connected to the second access terminal I2 of the reset control module 103, and the control terminal is connected to the second control terminal C2 of the reset control module 103, The two ends are connected to the output terminal O of the reset control module 103; the channel width to length ratio of the transistor T1 is larger than the channel width to length ratio of the transistor T2.
  • the level of the output terminal O of the reset control module 103 is the same as the level of the first access terminal I1 connected to the transistor T1, that is, the reset off level; the transistor T1 is turned off and the transistor T2 is turned on.
  • the level of the output terminal O of the reset control module 103 will coincide with the level of the second access terminal I2.
  • the reset control module 103 can also adopt other structures, and the structure shown in FIG. 2 should not be construed as limiting the scope of the present invention.
  • the shift register unit may further include the reset enhancement module 106 and the reset enhancement control module 107 shown in FIG. 1B, wherein: the output of the reset enhancement module 106 is connected to the first node Q. Suitable for resetting the level of the first node Q to reset the level of the first node Q to an output off level; the output of the reset enhancement control module 107 and the control end of the reset enhancement module 106 Connected, adapted to be controlled by the control signal accessed by the control terminal of the reset enhancement control module 107, after the reset module 102 resets the level of the first node Q to an output off level, The reset enhancement module 106 continues to reset the first node Q.
  • the first node Q can be reset by the reset enhancement module 106 after the reset module 102 resets the first node Q to reset the level of the first node Q to the output off level.
  • the level of the first node Q can be prevented from being reset to the output enable level due to leakage of the input module 104, and the output module 101 is guaranteed to shift at the output.
  • the pulse level is no longer output after the signal.
  • the reset enhancement control module 107 may have a first access terminal and a second access terminal, a first control terminal, and a second control terminal, where the second access terminal is configured to enable the resetting
  • the reset enhancement level of the boost module 106 is turned on, and the first access end is used to access a reset boost off level that enables the reset enhancement module 106 to be turned off.
  • the first control end of the reset enhancement control module 107 is connected to the first node Q, and is adapted to conduct the first access end and the output end when the first node Q is the output enable level, and access the second control end. Corresponding effective level, the second access end and the output end are turned on, and when the output end is connected to the first access end and the second access end, the level of the output end is first connected The input is consistent.
  • the level of the output end of the boost control module 107 is reset when the output module 101 outputs the shift signal. Consistent with the level of the first access terminal, the first node Q is not reset. After the reset module 102 resets the level of the first node Q to the output off level, the first access terminal and the output terminal of the reset enhancement control module 107 are no longer turned on, and according to the signal applied by the second control terminal, The second access terminal and the output terminal are timely turned on. At this time, the level of the output of the reset enhancement control module 107 is the reset enhanced ON level, so that the reset enhancement module 106 is turned on, and the first node Q is continuously reset.
  • the second access end and the second control end of the reset enhancement control module 107 can access a clock signal, and when the clock signal is at the reset enhanced on level, the second access end and the output end are turned on.
  • the reset enhancement control module 107 may further include a third control terminal and a third access terminal, where the third access terminal is configured to access a reset enhanced ON level, and the reset enhancement control module 107 is adapted to be at the third control end.
  • the third access end and the output end are turned on, and when the output end is connected to the first access end and the third access end, the level of the output end and the first access The ends are consistent.
  • the reset enhancement control module 107 including the third control terminal and the third access terminal may include a transistor T3, a transistor T4, and a transistor T5.
  • the control terminal of the transistor T3 is connected to the first control terminal C1 of the reset enhancement control module 107, the first terminal is connected to the first access terminal I1 of the reset enhancement control module 107, and the second terminal is connected to the reset enhancement control.
  • the output terminal O of the module 107 when the first control terminal C1 of the reset enhancement control module 107 is connected to the output enable level, the first end and the second end of the transistor T3 are turned on; the control terminal of the transistor T4 is connected to the reset
  • the second control terminal C2 of the control module 107 is connected, the first end is connected to the second access terminal I2 of the reset enhancement control module 107, and the second end is connected to the output terminal O of the reset enhancement control module 107;
  • the control of the transistor T5 Connected to the third control end C3 of the reset enhancement control module 107, the first end is connected to the third access end I3 of the reset enhancement control module 107, and the second end is connected to the reset enhanced control
  • the output terminal O of the module 107 wherein the effective level of the transistor T4 and the transistor T5 are opposite, or the second access terminal I2 and the third access terminal I3 are both used for accessing the clock signal, and the second access terminal
  • the phase of the clock signal accessed by I2 is opposite to the
  • the shift register unit may further include: a load module 108, the control end of the load module 108 is connected to the first node Q, and is adapted to be electrically connected to the first node Q.
  • the output shift signal is output when the output is turned on.
  • the structure of the load module 108 may be consistent with the structure of the output module 101 described above.
  • the advantage of this is that the shift signal output by the load module 108 can be used for other control terminals (such as the input end of the shift register unit of the next stage), and other control terminals are prevented from being connected to the output end of the output module 101.
  • the pulse level output by the output module 101 is weakened.
  • the load module 108 can include a transistor having a first end coupled to the input of the load module 108 and a second end coupled to the output of the load module 108, the control terminal (gate) Connected to the control end of the load module 108.
  • the shift register unit may further include a pinch-off module 109 shown in FIG. 1B for resetting the input module 104 and/or the reset signal when the output shift signal is at a pulse level.
  • Module 102 and/or the reset enhancement module 106 are pinched off.
  • the level of the first node Q ensures that the pulse level output by the output module 101 has a better waveform.
  • the shift register unit may further include an auxiliary output module 110 shown in FIG. 1B, and the control end of the auxiliary output module 110 is connected to the first node Q, and is adapted to be at the first node Q.
  • the input module 104, the reset module 102, and the reset enhancement module may each include a transistor combination in which two transistors are connected in series.
  • An output of block 108 is coupled, an input coupled to an output of said auxiliary output module 110, and an output coupled to a series connection between two transistors in a transistor combination for said load module 108 and said auxiliary output
  • the shift signal outputted by the output of the module 110 is a pulse level
  • the input end and the output end of the pinch-off module 109 are turned on, so that the level of the series connection between the two transistors in the transistor combination is the same as The output turns on at the same level.
  • the pinch-off module 109 can include a transistor having a first end coupled to the input of the pinch-off module 109, a second end coupled to the output of the pinch-off module 109, and a control terminal coupled to the control terminal of the pinch-off module 109.
  • the auxiliary output module 110 can include a transistor having a first end connected to the input end of the auxiliary output module 110, a second end connected to the output end of the auxiliary output module 110, and a control end and a control end of the auxiliary output module 110. Connected.
  • the above shift register unit may further include three reset modules 111 shown in FIG. 1B, and the three reset modules 111 are respectively used for the output module 101 and the load module 108 after the output module 101 outputs a shift signal.
  • the output of the auxiliary output module 110 is reset so that the levels of the respective outputs are reset to non-pulse levels.
  • control ends of the three reset modules 111 are connected to the output ends of the reset enhancement control module 107, and the input terminals are used to access the level opposite to the pulse level, and the output terminals correspond to the output modules.
  • the output terminals of the load module 108 and the auxiliary output module 110 are connected to be turned on when the reset enhancement module 106 is turned on by the reset enhancement control module 107.
  • each reset module 111 may include a transistor, the first end of the transistor is connected to the input end of the reset module 111, the second end is connected to the output end of the reset module 111, and the control end is The control terminals of the reset module 111 are connected.
  • the input module 104 and the output module 101 may both be transistors.
  • Each of the transistors included in the shift register unit may be an N-type transistor, and the level maintaining module 105 may be a capacitor. At this time, the turn-on level of each module is high level, and the turn-off level is low level.
  • each transistor in the above-mentioned reset control module 103 is a P-type transistor, and the present invention can also be implemented.
  • the technical solution should also fall within the scope of protection of the present invention.
  • the present invention provides a method for driving the shift register unit of any of the above, the method comprising: outputting the same number of pulses for the received multi-pulse signal to be shifted After shifting the signal, a control signal is applied to the control terminal of the reset control module 103 to enable the reset module 102 to reset the first node Q.
  • the reset module 102 is turned on in time to reset the first node Q.
  • the output module 101 is allowed to output a shift signal having a plurality of pulses before the first node Q is reset.
  • the foregoing method specifically includes: outputting the same number of pulses in the signal to be shifted for the received multi-pulse After the bit signal, the first control terminal C1 is connected to the second level and the second control terminal C2 is connected to the first level.
  • the method may specifically include: connecting the first control end C1 of the reset control module 103.
  • the second control terminal C2 of the reset control module 103 is connected to the shift signal outputted by the next-stage shift register, and is connected to the pulse at the first control terminal C1 of the reset control module 103.
  • the first access terminal I1 of the reset control module 103 is connected to the reset-off level, and the first control terminal C1 of the reset control module 103 is connected to the non-pulse level, and the second control terminal C2 is connected.
  • the second access terminal I2 of the reset control module 103 is connected to the reset on level.
  • the method further includes resetting, at the reset module 102, the level of the first node Q to enable the output module After the 101 off output is turned off, at The control terminal of the reset enhancement control module 107 applies a control signal to turn the reset enhancement control module 107 on.
  • the process of resetting the first node Q by the reset module 102 is relatively short, and after the first node Q is reset, the reset module 102 is no longer turned on.
  • the input module 104 may leak and cause the level of the first node Q to change, which in turn causes the output module 101 to turn on again to output a pulse.
  • the reset enhancement module 106 and the reset enhancement control module 107 it is possible to continue the operation after the reset module 102 resets the level of the first node Q to an output off level capable of turning off the output module 101.
  • the first node Q is reset to avoid a change in the level of the first node Q.
  • the foregoing method further includes: inputting the second control terminal of the reset enhancement control module 107 to the second clock signal input
  • the third control terminal is connected to the third clock signal input end, so that the output end of the reset enhancement control module 107 and the first access terminal and the second access terminal of the reset enhancement control module 107 are alternately turned on.
  • the above method further includes: applying a control to the pinch-off module 109 when the shift signal output by the shift register unit is at a pulse level A signal is applied to cause the pinch-off module 109 to be turned on.
  • the shift register unit provided by the present invention may include 18 N-type transistors and A capacitor C.
  • the input module 104 in FIG. 1A is formed by connecting two transistors T6-1 and T6-2 in series, and the source of the transistor T6-1 (shown as S in the figure) is connected to the transistor T6-2.
  • the drain shown as D in the figure
  • the drain of T6-1 is connected to the input end of the signal to be shifted, for receiving the signal STU to be shifted, and the gate is also connected to the input end of the signal to be shifted; transistor T6-2
  • the gate is connected to a clock signal input for accessing the clock signal CLKA, and the source of the transistor T6-2 is connected to the node Q.
  • the output module 101 includes a transistor T7 whose drain is connected to another clock signal input terminal for accessing the clock signal CLKB, the source of the transistor T7 is connected to the node OUT for outputting a shift signal, and the gate is connected to the node Q.
  • CLKA and CLKB are clock signals of opposite phases.
  • the reset module 102 includes two transistors T8-1 and T8-2.
  • the source of the transistor T8-2 is connected to the drain of the transistor T8-1, and the source connection of T8-1 can reset the node Q to a low level.
  • the voltage electrode VGL, the drain of the transistor T8-2, is connected to the node Q.
  • the gates of transistors T8-1 and T8-2 are connected to node DD.
  • the reset control module 103 includes transistors T1 and T2, wherein the channel width to length ratio of the transistor T1 is greater than the channel width to length ratio of the transistor T2, the source of the transistor T1 is connected to the common low voltage electrode VGL, and the gate is also connected to the signal input to be shifted.
  • the terminal receives the signal to be shifted STU; the source and the gate of the transistor T2 are connected to the output of the shift signal of the next stage shift register unit to access the shift signal STD output by the shift register unit of the next stage.
  • the drains of transistors T1 and T2 are both connected to node DD.
  • the structure of the reset enhancement module 106 and the reset enhancement control module 107 is also shown in FIG. 4, similar to the structure of the reset module 102, which includes transistors T9-1 and T9-2, the source of the transistor T9-2. Connecting the drain of the transistor T9-1, the source connection of T9-1 can reset the first node Q to the common low voltage electrode VGL of the low level, and the drain of the transistor T9-2 is connected to the first node Q, the transistor T9- Both the gates of 1 and T9-2 are connected to node Qb.
  • the reset enhancement control module 107 includes transistors T3, T4, and T5, wherein the gate of the transistor T3 is connected to the node Q, the drain is connected to the node Qb, and the source is connected to the common low voltage electrode VGL; the gate and the drain of the T4 are connected to the clock signal input terminal.
  • the source is connected to the node Qb; the gate and the drain of the T5 are connected to another clock signal input for access
  • the clock signal CLKB and the source are connected to the node Qb.
  • the channel width to length ratio of the transistor T3 is larger than the channel width to length ratio of the transistor T4 and the transistor T5.
  • the load module 108 includes a transistor T10 having a drain connected to another clock signal input for accessing the clock signal CLKB, the source of the transistor T10.
  • the pole is connected to the load output terminal CR for outputting a shift signal.
  • the source of the transistor T10 is also connected to a pole of the capacitor C that is not connected to the node Q.
  • the auxiliary output module 110 includes a transistor T11.
  • the drain of the transistor T11 is connected to another clock signal input terminal for accessing the clock signal.
  • CLKB the source of the transistor T11 is connected to the node N1.
  • the structure of the pinch-off module 109 is also shown in the circuit of FIG. 4.
  • the pinch-off module 109 includes a transistor T12 whose source is connected to the node N1, the load output terminal CR in the gate connection diagram, and the drain of the T12.
  • the series connection between the pole and the two transistors in the reset module 102 (the junction between the source of the transistor T8-2 and the drain of the transistor T8-1), the series connection between the two transistors in the input module 104
  • the junction (the junction between the source of transistor T6-1 and the drain of transistor T6-2), the series connection between the two transistors in reset enhancement module 106 (source and transistor of transistor T9-2)
  • the junction between the drains of T9-1 is connected).
  • the circuit in FIG. 4 further includes a structure constituting three reset modules 111, which respectively correspond to transistors T13-1, T13-2, T13-3, wherein the drain and load output of the transistor T13-1
  • the terminal CR is connected, the source is connected to the common low voltage electrode VGL, the gate is connected to the node Qb in the figure; the drain of the transistor T13-2 is connected to the node N1, and the source is connected to the common low voltage electrode VGL, in the gate connection diagram
  • the node Qb; the drain of the transistor T13-3 is connected to the node OUT, the source is connected to the common low voltage electrode VGL, and the gate is connected to the node Qb in the figure.
  • FIG. 5 shows the timing of each key node in the shift register unit circuit of FIG. Sequence diagram. It is assumed that the signal to be shifted STU having three pulses is shifted by the circuit in FIG. 4 to obtain a shift signal having three pulses, wherein the pulse of the shift signal has a high level.
  • the signal to be shifted STU is high level
  • the output shift signal OUT is low level
  • CLKA is high level
  • CLKB is low level
  • STD is Low level
  • both transistors T6-1 and T6-2 are turned on, and the high pulse level of STU is written to node Q.
  • the pull-up of the node Q causes the transistor T3 to be turned on.
  • the transistor T4 is also turned on, since the channel width-to-length ratio is smaller than the channel width of the transistor T3, the level of the node Qb is pulled down to the common low-voltage electrode.
  • the level of VGL causes transistors T9-1 and T9-2 to turn off.
  • the level of the DD point is the level of the low voltage electrode VGL, and the transistors T8-1 and T8-2 are also turned off, so that the level of the node Q is not affected by the reset module 102, The effect of the boost module 106 is reset.
  • the level of the node Qb is low, T13-1, T13-2, and T13-3 are also turned off.
  • the pull-up of the node Q also causes the transistors T7, T10, and T11 to be turned on, but since CLKB is at a low level, the levels of the outputs of the nodes OUT, N1, and CR are all at a low level.
  • the signal to be shifted STU is low, the output shift signal OUT is high, CLKA is low, CLKB is high, and STD is low. Since STU is low and CLKA is low, both transistors T6-1 and T6-2 in input module 104 are turned off. In addition, in reset control module 103, T1 is turned off, because STD is low. T2 is also turned off, and the level of DD is still low. Correspondingly, T8-1 and T8-2 will not be turned on, and the level of node Q is still unaffected.
  • the transistors T7, T10, and T11 continue to be turned on, and the levels of the outputs of the nodes OUT, N1, and CR coincide with CKLB, and both are high. Since the level of node Q is high, the level of node Qb is still low, causing T13-1, T13-2, and T13-3 to remain off, avoiding affecting OUT, N1, and CR output high levels. Meanwhile, in the second stage S2, since the levels of the load output terminal CR and the node N1 are both high, T12 is turned on, and the level of the source is high, resulting in the source of the transistor T6-1 and the transistor T6-2.
  • the levels are all high, so there is not enough potential difference between the node Q and these connections.
  • the transistors T6-1, T8-2, and T9-2 are pinched off, and the power of the node Q is not affected. level.
  • the level of the output terminal CR is further increased, and the node Q is capacitively bootstrapped, further improving the node.
  • the level of Q the ideal value of the level of the node Q at this time is the absolute value of the difference between the high level of the clock signal and the low level of the clock signal. Since the low level of the clock signal is generally negative, the node Q The level is higher than the high level of the clock signal to ensure the conduction of the transistor T7.
  • the signal to be shifted STU is at a high level
  • the output shift signal OUT is at a low level
  • CLKA is at a high level
  • STD is at a high level.
  • the level of the node Q is high
  • the level of the node Qb is low
  • the output of OUT is still low
  • the transistors T9-1, T9-2 are turned off
  • the transistors T13-1, T13 -2, T13-3 are all turned off.
  • STU is high
  • the level of DD is set to low.
  • Transistors T8-1, T8-2 are still not turned on, and node Q remains high.
  • the switching states of the respective transistors in the fifth stage S5 and the level states of the respective key nodes are identical to those in the third stage S3.
  • the switching states of the respective transistors in the fourth stage S4 and the sixth stage S6 and the level states of the respective key nodes are identical to those in the second stage S2.
  • OUT, N1, and CR each output one pulse in the fourth stage S4, and one pulse is output again in the sixth stage S6.
  • the number of pulses output reaches three, which is consistent with the number of pulses of the STU.
  • both STU and STD are low level
  • CLKA is also low level
  • transistors T6-1 and T6-2 are both turned off, and the level of node Q cannot be pulled high.
  • Such a transistor T3 will not be turned on. Since CLKB is high at this time, transistor T5 is turned on, the level of node Qb is still high, and transistors T9-1 and T9-2 continue to be turned on, so that the level of node Q is high. Continue to be pulled low.
  • the level of the node Q will not be pulled high again, the transistor T3 will not be turned on, and since the transistors T4 and T5 are alternately turned on, the level of the node Qb is always high. Leveling causes transistors T9-1 and T9-2 to continue to conduct, ensuring that the level of node Q is continuously pulled low. In addition, the level of the node Qb is always high, and the transistors T13-1, T13-2, and T13-3 are all turned on, further ensuring that the levels of the respective output terminals CR, N1, and OUT are pulled low.
  • the present invention also provides a gate scan circuit including a plurality of cascaded shift register units, which may be any one of the shift registers in the above embodiments. unit.
  • the input end of the input module in the shift register unit of the current stage is connected to the output module of the shift register unit of the previous stage or the output end of the load module or the auxiliary output module, and the first control end of the control module is reset. Also connected to the output module of the shift register unit of the previous stage, or the output of the load module or the auxiliary output module, the output of the second control terminal and the output module of the shift register unit of the next stage, or the output of the load module or the auxiliary output module Connected to the end.
  • the second access terminal of the reset control module of each shift register unit can be connected to its second control terminal.
  • the drain of the transistor T6-1 and the gate of the transistor T1 are both connected to the shift signal STU outputted by the shift register unit of the first stage, and the gate of the transistor T2 is connected.
  • the source of the transistor T2 may be connected to the gate of the transistor T2 or may be directly connected to the common high level electrode.
  • the input end of the first stage shift register unit of the plurality of shift register units is connected to the start signal input end, and the output end of the output module of the last stage shift register unit is not connected to the other Shift register unit.

Abstract

一种移位寄存器单元及其驱动方法、栅极扫描电路，该移位寄存器单元包括：用于接收待移位信号的输入模块(104)、输出模块(101)、复位模块(102)和复位控制模块(103)，其中，输入模块(104)的输出端、输出模块(101)的控制端、复位模块(102)的输出端连接第一节点，所述复位控制模块(103)的输出端与所述复位模块(102)的控制端相连，适于在所述复位控制模块(103)的控制端所接入的控制信号的控制下，开启所述复位模块(102)来对所述第一节点（Q）进行复位，以使得在对所述第一节点（Q）进行复位之前，所述输出模块（101）输出具有多个脉冲的移位信号。该技术方案能够通过一个移位寄存器单元输出具有多个脉冲的栅极驱动信号。

Description

移位寄存器单元及其驱动方法、栅极扫描电路 技术领域
本发明涉及显示技术领域，具体涉及移位寄存器单元及其驱动方法、栅极扫描电路。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)作为一种电流型发光器件，因其所具有的自发光、快速响应、宽视角和可制作在柔性衬底上等特点而越来越多地被应用于高性能显示领域当中。OLED显示器按照驱动方式的不同可分为PMOLED(Passive Matrix Driving OLED，无源矩阵驱动有机发光二极管)显示器和AMOLED(Active Matrix Driving OLED，有源矩阵驱动有机发光二极管)显示器两种。由于AMOLED显示器具有低制造成本、高应答速度、省电、可在直流驱动便携式设备中使用、工作温度范围大等优点而可望成为取代LCD(liquid crystal display，液晶显示器)的下一代新型平面显示器，因此，AMOLED显示面板已得到越来越多人们的青睐。
然而，AMOLED显示面板一般需要使用具有多个脉冲的栅极驱动信号进行驱动，另外，在LCD面板中，为了保证使充电更充分，也需要使用具有多个脉冲的栅极驱动信号进行驱动。但是，现有技术中不能通过一个移位寄存器单元产生具有多个脉冲的栅极驱动信号。
发明内容
本发明的一个目的提供一种能够输出具有多个脉冲的移位信号的移位寄存器单元，以通过一个移位寄存器单元输出具有多个脉冲的栅极驱动信号。
本发明提供了一种移位寄存器单元，包括用于接收待移位信号的输入模块，其中，所述移位寄存器还包括：
输出模块、复位模块和复位控制模块，其中，输入模块的输出端、输出模块的控制端、复位模块的输出端连接第一节点，所述复位控制模块的输出端与所述复位模块的控制端相连，适于在所述复位控制模块的控制端所接入的控制信号的控制下，开启所述复位模块来对所述第一节点进行复位，以使得在对所述第一节点进行复位之前，所述输出模块输出具有多个脉冲的移位信号。
进一步的，所述复位控制模块的控制端包括第一控制端和第二控制端，适于在第一控制端接入第一电平时，关闭所述复位模块，在第一控制端接入第二电平且第二控制端接入第一电平时，开启所述复位模块来对所述第一节点进行复位。
进一步的，所述输入模块的输出端适于在接收到的待移位信号处于脉冲电平时，将所述第一节点置为能够使所述输出模块开启的输出开启电平；
所述输出模块适于在所述第一节点的电平为输出开启电平时输出移位信号；
所述复位模块适于在所述输出模块输出移位信号之后将所述第一节点的电平复位为能够使所述输出模块关闭的输出关闭电平。
进一步的，所述移位寄存器单元还包括：
电平维持模块，所述电平维持模块与所述第一节点相连，适于在所述输入模块和所述复位模块均关闭时，维持第一节点的电平。
进一步的，所述复位控制模块的第一控制端连接待移位信号输入端，第二控制端连接下一级移位寄存器单元的移位信号输出端，待移位信号和移位信号中的脉冲电平与所述第一电平一致，待移位信号和移位信号中的非脉冲电平与所述第二电平一致。
进一步的，所述复位控制模块具有第一接入端和第二接入端，第二接入端用于接入能够使所述复位模块开启的复位开启电平，第一接 入端用于接入能够使所述复位模块关闭的复位关闭电平；
所述复位控制模块适于在第一控制端接入第一电平时，将第一接入端与输出端导通，在第二控制端接入第一电平时，将第二接入端与输出端导通，且在输出端与第一接入端和第二接入端均导通时，输出端的电平与第一接入端保持一致。
进一步的，所述复位控制模块的第一接入端连接第一公共电极、或者第一时钟信号输入端、或者该移位寄存器单元的移位信号输出端，所述第一公共电极的电平与所述复位关闭电平一致，所述第一时钟信号输入端所接入的时钟信号在所述复位控制模块的第一接入端与所述复位控制模块的输出端导通时为复位关闭电平；
所述复位控制模块的第二接入端连接第二公共电极、或者连接下一级移位寄存器单元的移位信号输出端、或者连接第二时钟信号输入端，所述第二公共电极的电平与所述复位开启电平一致，所述第二时钟信号输入端所接入的时钟信号在所述复位控制模块的第二接入端与所述复位控制模块的输出端导通时为复位开启电平。
进一步的，所述复位控制模块包括第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管均在控制端接入第一电平时导通、接入第二电平时关闭，其中，
所述第一晶体管的第一端连接所述复位控制模块的第一接入端，控制端连接所述复位控制模块的第一控制端，第二端连接所述复位控制模块的输出端；所述第二晶体管的第一端连接所述复位控制模块的第二接入端，控制端连接所述复位控制模块的第二控制端，第二端连接所述复位控制模块的输出端，所述第一晶体管的沟道宽长比大于所述第二晶体管的沟道宽长比。
进一步的，所述移位寄存器单元还包括：复位加强模块和复位加强控制模块；
所述复位加强模块的输出端与所述第一节点相连，适于对第一节点的电平进行复位；
所述复位加强控制模块的输出端与所述复位加强模块的控制端相连，适于在所述复位加强控制模块的控制端所接入的控制信号的控制下，在所述复位模块将所述第一节点的电平复位为输出关闭电平之后，开启所述复位加强模块继续对所述第一节点进行复位。
进一步的，所述复位加强控制模块具有第一接入端和第二接入端、第一控制端和第二控制端，第二接入端用于接入能够使所述复位加强模块开启的复位加强开启电平，第一接入端用于接入能够使所述复位加强模块关闭的复位加强关闭电平；
所述复位加强控制模块的第一控制端连接第一节点，适于在第一节点为输出开启电平时，将第一接入端与输出端导通，在第二控制端接入对应的有效电平时，将第二接入端与输出端导通，且在输出端与第一接入端和第二接入端均导通时，输出端的电平与第一接入端保持一致。
进一步的，所述复位加强控制模块还包括第三控制端和第三接入端，第三接入端用于接入复位加强开启电平，所述复位加强控制模块适于在第三控制端接入对应的有效电平时，使第三接入端与输出端导通，且在输出端与第一接入端和第三接入端均导通时，输出端的电平与第一接入端保持一致。
进一步的，所述复位加强控制模块包括第三晶体管、第四晶体管和第五晶体管，所述第三晶体管的控制端连接所述复位加强控制模块的第一控制端，第一端连接所述复位加强模块的第一接入端，第二端连接所述复位加强控制模块的输出端，在所述复位加强控制模块的第一控制端接入所述输出开启电平时，第三晶体管的第一端和第二端导通；所述第四晶体管的控制端连接所述复位加强控制模块的第二控制端，第一端连接所述复位加强控制模块的第二接入端，第二端连接所述复位加强控制模块的输出端；第五晶体管的控制端连接所述复位加强控制模块的第三控制端，第一端连接所述复位加强控制模块的第三接入端，第二端连接所述复位加强控制模块的输出端；所述第四晶体 管和所述第五晶体管对应的有效电平相反，或者第二接入端和第三接入端均用于接入时钟信号，且第二接入端所接入的时钟信号的相位与第三接入端所接入的时钟信号的相位相反。
进一步的，所述移位寄存器单元还包括：负载模块，所述负载模块的控制端与第一节点相连，适于在所述第一节点的电平为输出开启电平时输出移位信号。
进一步的，所述负载模块包括一个晶体管，该晶体管的第一端与所述负载模块的输入端相连，第二端与所述负载模块的输出端相连，控制端与所述负载模块的控制端相连。
进一步的，所述移位寄存器单元还包括夹断模块，用于在输出的移位信号处于脉冲电平时开启，将所述输入模块和/或所述复位模块和/或所述复位加强模块夹断。
进一步的，所述移位寄存器单元还包括：
辅助输出模块，所述辅助输出模块的控制端与第一节点相连，适于在所述第一节点的电平为输出开启电平时输出移位信号，移位信号的脉冲电平与所述输出开启电平一致；
所述输入模块、所述复位模块和所述复位加强模块均包括由两个晶体管串联在一起组成的晶体管组合；
所述夹断模块的控制端与所述负载模块的输出端相连，输入端与所述辅助输出模块的输出端相连，输出端与所述晶体管组合中两个晶体管之间的串联连接处相连，在所述负载模块和所述辅助输出模块的输出端输出的是移位信号中的脉冲电平时，所述夹断模块的输入端和输出端导通，使得所述晶体管组合中两个晶体管之间的串联连接处的电平与所述输出开启电平一致。
进一步的，所述夹断模块包括一个晶体管，该晶体管的第一端与所述夹断模块的输入端相连，第二端与所述夹断模块的输出端相连，控制端与所述夹断模块的控制端相连。
进一步的，所述辅助输出模块包括一个晶体管，该晶体管的第一 端与所述辅助输出模块的输入端相连，第二端与所述辅助输出模块的输出端相连，控制端与所述辅助输出模块的控制端相连。
进一步的，所述移位寄存器单元还包括三个重置模块，三个重置模块分别用于在所述输出模块输出移位信号之后对输出模块、负载模块、辅助输出模块的输出端进行重置，使各个输出端的电平被重置为非脉冲电平。
进一步的，三个重置模块的控制端与所述复位加强控制模块的输出端相连，输入端均用于接入非脉冲电平，输出端对应地与输出模块、负载模块、辅助输出模块的输出端相连，在所述复位加强控制模块开启所述复位加强模块时，重置模块的输入端和输出端被导通。
进一步的，每个所述重置模块包括一个晶体管，该晶体管的第一端与所述重置模块的输入端相连，第二端与所述重置模块的输出端相连，控制端与所述重置模块的控制端相连。
进一步的，所述输出模块为晶体管，且所述移位寄存器单元所包含的各个晶体管均为N型晶体管。
本发明还提供了一种栅极驱动电路，包括多个上述任一项所述的移位寄存器单元，还包括至少一条时钟信号线，各个移位寄存器单元的输出模块的输入端连接同一时钟信号线。
进一步的，所述多个移位寄存器单元中的第一级移位寄存器单元的输入模块的输入端连接起始信号输入端。
进一步的，各个移位寄存器单元的复位控制模块的第二接入端与第二控制端连接。
进一步的，当各个移位寄存器单元的输入模块包括由两个晶体管串联在一起组成的晶体管组合时，输入模块中与第一节点相连的晶体管的控制端连接另一时钟信号线，所述另一时钟信号线中的时钟信号的相位与所述输出模块所连接的时钟信号线中的时钟信号的相位相反。
本发明还提供了一种驱动上述任一项所述的移位寄存器单元的方法，包括：
在针对接收到的多脉冲的待移位信号而输出相同脉冲个数的移位信号之后，在复位控制模块的控制端施加控制信号来开启所述复位模块，以对所述第一节点进行复位。
进一步的，当所述移位寄存器单元为包括第一控制端和第二控制端时，所述方法具体包括：
在针对接收到的多脉冲的待移位信号而输出相同脉冲个数的移位信号之后，在第一控制端接入第二电平且第二控制端接入第一电平。
进一步的，所述第一电平与脉冲电平一致，第二电平与非脉冲电平一致，所述方法具体包括：将所述复位控制模块的第一控制端接入待移位信号，将所述复位控制模块的第二控制端接入下一级移位寄存器单元所输出的移位信号，且在第一控制端接入脉冲电平时，在第一接入端接入复位关闭电平，在第一控制端接入非脉冲电平且第二控制端接入脉冲电平时，在第二接入端接入复位开启电平。
进一步的，当所述移位寄存器单元包括复位加强模块和复位加强控制模块时，所述方法还包括：
在所述复位模块将所述第一节点的电平复位为能够使所述输出模块关闭的输出关闭电平之后，在所述复位加强控制模块的控制端施加控制信号，以将所述复位加强控制模块开启。
进一步的，当所述移位寄存器单元具有第三控制端时，所述方法还包括：
将所述复位加强控制模块的第二控制端接入第三时钟信号输入端，第三控制端接入第四时钟信号输入端，使所述复位加强控制模块的输出端与所述复位加强控制模块的第一接入端和第二接入端交替导通。
进一步的，当所述移位寄存器单元包括夹断模块时，所述方法还包括：在所述移位寄存器单元输出的移位信号处于脉冲电平时，施加控制信号使所述夹断模块开启。
本发明提供的移位寄存器单元包括输入模块、输出模块、复位模块和复位控制模块，其中，输入模块的输出端、输出模块的控制端、 复位模块的输出端连接第一节点，所述复位控制模块的输出端与所述复位模块的控制端相连，适于在所述复位控制模块的控制端所接入的控制信号的控制下，开启所述复位模块来对所述第一节点进行复位，以使得在对所述第一节点进行复位之前，所述输出模块输出具有多个脉冲的移位信号。根据本发明的技术方案，能够通过一个移位寄存器单元输出具有多个脉冲的栅极驱动信号。
附图说明
图1A为本发明的实施例一提供的一种移位寄存器单元的结构示意图；
图1B为本发明的实施例一提供的另一种移位寄存器单元的结构示意图；
图2为本发明的实施例一中的一种可能的复位控制模块的结构示意图；
图3为本发明的实施例一中的一种可能的复位加强控制模块的结构示意图；
图4为本发明的实施例二提供的一种移位寄存器单元的电路结构图；
图5为图4中的电路在工作时的关键信号和节点电平的时序图。
具体实施方式
为使本发明的实施例的目的、技术方案和优点更加清楚，下面将结合本发明的实施例中的附图，对本发明的实施例中的技术方案进行清楚、完整的描述，显然，所描述的实施例仅仅是本发明的一部分实施例，而不是全部的实施例。基于本发明的实施例，本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他的实施例都属于本发明保护的范围。
实施例一
本发明的实施例一提供了一种移位寄存器单元，如图1A所示，该移位寄存器单元包括：输入模块104、输出模块101、复位模块102和复位控制模块103，其中，输入模块104的输出端、输出模块101的控制端、复位模块102的输出端连接第一节点Q，输入模块104的输入端用于接收待移位信号，复位控制模块103的输出端与复位模块102的控制端相连，使得在复位控制模块103的控制端所接入的控制信号的控制下，复位模块102对第一节点Q进行复位，以使输出模块101输出具有多个脉冲的移位信号。
在具体实施时，可以在移位寄存器单元中的输出模块101针对接收到的多脉冲的待移位信号输出相同脉冲个数的移位信号之后，在复位控制模块103的控制端施加控制信号来开启所述复位模块102对所述第一节点Q进行复位，这样，使得在对所述第一节点Q进行复位之前，输出模块101能够输出多个脉冲。
为了便于区分，附图中，各个模块的控制端表示为C、输入端或接入端表示为I、输出端表示为O，第x个输入端或接入端表示为Ix，第x个控制端表示为Cx。
本发明提供的移位寄存器单元能够输出具有多个脉冲的移位信号作为栅极驱动信号。
在具体实施时，复位控制模块103的控制端包括第一控制端C1和第二控制端C2，使得在第一控制端C1接入第一电平时，控制复位模块102关闭，在第一控制端C1接入第二电平且第二控制端C2接入第一电平时，控制复位模块102开启以对所述第一节点Q进行复位，以使得在复位模块102对所述第一节点Q进行复位之前，输出模块101输出具有多个脉冲的移位信号。图1A中示出的是复位控制模块103具有两个控制端(C1，C2)和两个接入端(I1，I2)的一种情况。
具体实施时，在复位控制模块103的第一控制端C1接入第一电平时，其控制复位模块102不被开启，在复位控制模块103的第一控制端C1接入第二电平且第二控制端C2接入第二电平时，其控制复位模 块102也不被开启，仅在复位控制模块103的第一控制端C1接入第二电平且第二控制端C2接入第一电平时，才控制复位模块102被开启。这样，可以将第一控制端C1接入待移位信号，将第二控制端C2接入下一级移位寄存器单元输出的移位信号。这里，本级移位寄存器单元所输出的移位信号接入下一级移位寄存器单元的输入端。以待移位信号和下一级移位寄存器单元输出的移位信号的脉冲电平为第一电平、非脉冲电平为第二电平来说，在待移位信号为脉冲电平的第2N-1(假设N为待移位信号的脉冲的个数)阶段，复位模块102关闭，在待移位信号为非脉冲电平的第2N阶段，下一级移位寄存器单元输出的移位信号也为非脉冲电平(输入到本级的待移位信号与下一级移位寄存器单元输出的移位信号相差两个时钟)，此时复位模块102仍不会开启。当且仅当在输出模块101输出了N个脉冲之后的第2N+1个阶段，此时，待移位信号为非脉冲电平，而下一级移位寄存器单元输出的移位信号为最后一个脉冲电平，使得复位模块102开启。这样，使得在复位模块102开启而对所述第一节点Q进行复位之前，本级移位寄存器单元输出具有多个脉冲的移位信号。
这里的输出模块101可以与现有技术中的移位寄存器单元的输出模块一致，均是指用于输出移位信号的模块，在具体实施时，这里的输出模块101的输入端I一般连接时钟信号，在第一节点Q被置为能够使该输出模块101开启的电平时，一段时钟信号被截取而输出，这部分时钟信号构成移位信号。之后，在第一节点Q被复位时，输出模块101关闭，不再输出移位信号。当然，在实际应用中，该输出模块101也可以为能够输出移位信号的其他模块，本发明不再详细说明。
这里的复位模块102也可以与现有技术中的复位模块一致，均是指用于对第一节点Q进行复位的模块，在具体实施时，该复位模块102的接入端I可以连接能够使输出模块101关闭的输出关闭电平，在复位模块102开启时，将输出关闭电平施加到第一节点Q，此时第一节点Q被复位，由此输出模块101被关闭。
此时，上述的移位寄存器单元包括的输入模块104的输出端O与所述第一节点Q相连，使得在接收到的待移位信号处于脉冲电平时，将所述第一节点Q置为能够使所述输出模块101开启的输出开启电平。
进一步的，该移位寄存器单元还可以包括图1A中示出的电平维持模块105，电平维持模块105与所述第一节点Q相连，适于在所述输入模块104和所述复位模块102均关闭时，维持第一节点Q的电平。
本发明中所指的脉冲电平可以具体指移位信号的脉冲所对应的电平，举例来说，如果移位信号的脉冲为正脉冲，则脉冲电平指高电平，相应的，非脉冲电平为低电平，如果移位信号的脉冲为负脉冲，则脉冲电平指低电平，非脉冲电平为高电平。
通过这种方式，电平维持模块105能够记录移位信号中的脉冲电平，并根据该记录的脉冲电平使输出模块101处于开启状态，以输出移位信号。
在具体实施时，所述复位控制模块103的第一控制端C1连接待移位信号输入端，用于接入待移位信号STU，第二控制端C2连接下一级移位寄存器单元的移位信号输出端，用于接入下一级移位寄存输出的移位信号STD，待移位信号和移位信号中的脉冲电平与所述第一电平一致，待移位信号和移位信号中的非脉冲电平与所述第二电平一致。
在本级移位寄存器单元输出移位信号的阶段，在输入到本级移位寄存器单元的待移位信号为脉冲电平时，复位控制模块103的第一接入端I1所接入的复位关闭电平导通到复位模块102的控制端，使复位模块102关闭；在输入到本级移位寄存器单元的待移位信号为非脉冲电平、下一级移位寄存器单元输出的移位信号也为非脉冲电平时，复位模块102仍然无法被开启；在下一级移位寄存器单元输出的移位信号处于最后一个脉冲电平时，输入到本级移位寄存器单元的待移位信号不再为脉冲电平，此时复位控制模块103的第二接入端I2所接入的复位开启电平导通到复位模块102的控制端C，使复位模块102开启，复位模块102对第一节点Q进行复位。之后，本级移位寄存器单元的 输出模块101被关闭，不再输出脉冲电平。通过这种方式，可以允许第一节点Q在多个时钟内导通，从而输出模块101在第一节点Q被复位之前输出多个脉冲。
在具体实施时，所述复位控制模块103的第一接入端I1连接第一公共电极、或者第一时钟信号输入端、或者该移位寄存器单元的移位信号输出端，所述第一公共电极的电平与所述复位关闭电平一致，所述第一时钟信号输入端所接入的时钟信号在所述复位控制模块103的第一接入端I1与所述复位控制模块103的输出端O导通时为复位关闭电平；所述复位控制模块103的第二接入端I2连接第二公共电极、或者下一级移位寄存器单元的移位信号输出端、或者第二时钟信号输入端，所述第二公共电极的电平与所述复位开启电平一致，所述第二时钟信号输入端所接入的时钟信号在所述复位控制模块103的第二接入端I2与所述复位控制模块103的输出端O导通时为复位开启电平。
当然在实际应用中，这里的复位控制模块103的第一接入端I1也可以接入其他输入端，只要能够在复位控制模块103的第一接入端I1与输出端O导通时，第一接入端I1为复位关闭电平，其对应的技术方案均能实现本发明的技术方案，相应的，其对应的技术方案也应该落入本发明的保护范围。
在具体实施时，上述的复位控制模块103的具体结构可以参考图2，其包括：晶体管T1和晶体管T2，晶体管T1和晶体管T2均在栅极(控制端)接入第一电平时导通，接入第二电平时关闭，其中，晶体管T1的第一端连接所述复位控制模块103的第一接入端I1，控制端连接所述复位控制模块103的第一控制端C1，第二端连接所述复位控制模块103的输出端O；晶体管T2的第一端连接所述复位控制模块103的第二接入端I2，控制端连接所述复位控制模块103的第二控制端C2，第二端连接所述复位控制模块103的输出端O；晶体管T1的沟道宽长比大于晶体管T2的沟道宽长比。
由于晶体管T1的沟道宽长比较大，则在晶体管T1导通时，无论 晶体管T2是否导通，复位控制模块103的输出端O的电平都会与晶体管T1所连接的第一接入端I1的电平一致，即为复位关闭电平；在晶体管T1关闭且晶体管T2导通时，复位控制模块103的输出端O的电平才会与第二接入端I2的电平一致。
当然，在实际应用中，复位控制模块103也可以采用其他的结构，图2所示的结构不应该理解为对本发明保护范围的限定。
在具体实施时，上述的移位寄存器单元还可以包括图1B中示出的复位加强模块106和复位加强控制模块107，其中：所述复位加强模块106的输出端与所述第一节点Q相连，适于对第一节点Q的电平进行复位，以将第一节点Q的电平复位为输出关闭电平；所述复位加强控制模块107的输出端与所述复位加强模块106的控制端相连，适于在所述复位加强控制模块107的控制端所接入的控制信号的控制下，在所述复位模块102将所述第一节点Q的电平复位为输出关闭电平之后，开启所述复位加强模块106继续对所述第一节点Q进行复位。
这样做的好处是，能够在复位模块102对第一节点Q进行一次复位而将第一节点Q的电平复位为输出关闭电平之后，通过复位加强模块106继续对第一节点Q进行复位，以保证第一节点Q的电平为输出关闭电平，这样能够避免因为输入模块104漏电而导致第一节点Q的电平被重置为输出开启电平，保证了输出模块101在输出移位信号之后不再输出脉冲电平。
在具体实施时，所述复位加强控制模块107可以具有第一接入端和第二接入端、第一控制端和第二控制端，第二接入端用于接入能够使所述复位加强模块106开启的复位加强开启电平，第一接入端用于接入能够使所述复位加强模块106关闭的复位加强关闭电平。
所述复位加强控制模块107的第一控制端连接第一节点Q，适于在第一节点Q为输出开启电平时，将第一接入端与输出端导通，在第二控制端接入对应的有效电平时，将第二接入端与输出端导通，且在输出端与第一接入端和第二接入端均导通时，输出端的电平与第一接 入端保持一致。
由于复位加强控制模块107在第一节点Q为输出开启电平时，将第一接入端与输出端导通，这样在输出模块101输出移位信号时，复位加强控制模块107的输出端的电平与第一接入端的电平一致，不会将第一节点Q复位。而在复位模块102将第一节点Q的电平复位到输出关闭电平后，复位加强控制模块107的第一接入端与输出端不再导通，而根据第二控制端施加的信号，第二接入端与输出端适时导通，此时，复位加强控制模块107输出端的电平即为复位加强开启电平，使得复位加强模块106开启，继续对第一节点Q进行复位。
在具体实施时，复位加强控制模块107的第二接入端和第二控制端可以接入时钟信号，在该时钟信号处于复位加强开启电平时，第二接入端和输出端导通。
所述复位加强控制模块107还可以包括第三控制端和第三接入端，第三接入端用于接入复位加强开启电平，所述复位加强控制模块107适于在第三控制端接入对应的有效电平时，使第三接入端与输出端导通，且在输出端与第一接入端和第三接入端均导通时，输出端的电平与第一接入端保持一致。
在具体实施时，如图3所示，包括第三控制端和第三接入端的复位加强控制模块107可以包括：晶体管T3、晶体管T4和晶体管T5。所述晶体管T3的控制端连接所述复位加强控制模块107的第一控制端C1，第一端连接所述复位加强控制模块107的第一接入端I1，第二端连接所述复位加强控制模块107的输出端O，在所述复位加强控制模块107的第一控制端C1接入输出开启电平时，晶体管T3的第一端和第二端导通；晶体管T4的控制端连接所述复位加强控制模块107的第二控制端C2，第一端连接所述复位加强控制模块107的第二接入端I2，第二端连接所述复位加强控制模块107的输出端O；晶体管T5的控制端连接所述复位加强控制模块107的第三控制端C3，第一端连接所述复位加强控制模块107的第三接入端I3，第二端连接所述复位加强控 制模块107的输出端O，其中，晶体管T4和晶体管T5对应的有效电平相反，或者第二接入端I2和第三接入端I3均用于接入时钟信号、且第二接入端I2所接入的时钟信号的相位与第三接入端I3所接入的时钟信号的相位相反。这里的有效电平是指使对应的晶体管开启的电平。
在具体实施时，上述的移位寄存器单元还可以包括图1B中示出的：负载模块108，该负载模块108的控制端与第一节点Q相连，适于在所述第一节点Q的电平为输出开启电平时输出移位信号。
在具体实施时，负载模块108的结构可以与上述的输出模块101的结构一致。这样做的好处是，能够将该负载模块108所输出的移位信号用于其他控制端(比如下一级移位寄存器单元的输入端)，避免其他控制端接入到输出模块101的输出端上而削弱输出模块101所输出的脉冲电平。
在具体实施时，负载模块108可以包括一个晶体管，该晶体管的第一端与所述负载模块108的输入端相连，第二端与所述负载模块108的输出端相连，控制端(栅极)与所述负载模块108的控制端相连。
在具体实施时，该移位寄存器单元还可以包括图1B中示出的：夹断模块109，用于在输出的移位信号处于脉冲电平时，将所述输入模块104和/或所述复位模块102和/或所述复位加强模块106夹断。
这样做的好处是，避免在输出模块101或者负载模块108输出脉冲电平时，电平维持模块105所维持的第一节点Q的电荷向输入模块104/复位模块102/复位加强模块106流动而影响第一节点Q的电平，保证了输出模块101输出的脉冲电平具有较好的波形。
更进一步的，该移位寄存器单元还可以包括图1B中示出的：辅助输出模块110，所述辅助输出模块110的控制端与第一节点Q相连，适于在所述第一节点Q的电平为输出开启电平时输出移位信号，移位信号的脉冲电平与所述输出开启电平一致。此时，所述输入模块104、所述复位模块102和所述复位加强模块均可以包括由两个晶体管串联在一起组成的晶体管组合。所述夹断模块109的控制端与所述负载模 块108的输出端相连，输入端与所述辅助输出模块110的输出端相连，输出端与晶体管组合中两个晶体管之间的串联连接处相连，以在所述负载模块108和所述辅助输出模块110的输出端输出的移位信号为脉冲电平时，将所述夹断模块109的输入端和输出端导通，使晶体管组合中两个晶体管之间的串联连接处的电平与所述输出开启电平一致。
夹断模块109可以包括一个晶体管，该晶体管的第一端与夹断模块109的输入端相连，第二端与夹断模块109的输出端相连，控制端与夹断模块109的控制端相连。
辅助输出模块110可以包括一个晶体管，该晶体管的第一端与辅助输出模块110的输入端相连，第二端与辅助输出模块110的输出端相连，控制端与所述辅助输出模块110的控制端相连。
上述的移位寄存器单元还可以包括图1B中示出的三个重置模块111，三个重置模块111分别用于在所述输出模块101输出移位信号之后对输出模块101、负载模块108、辅助输出模块110的输出端进行重置，使各个输出端的电平被重置为非脉冲电平。
在具体实施时，三个重置模块111的控制端与所述复位加强控制模块107的输出端相连，输入端均用于接入与脉冲电平相反的电平，输出端对应地与输出模块101、负载模块108、辅助输出模块110的输出端相连，以在所述复位加强控制模块107开启所述复位加强模块106时，重置模块111的输入端和输出端导通。
在具体实施时，每个重置模块111可以包括一个晶体管，该晶体管的第一端与所述重置模块111的输入端相连，第二端与重置模块111的输出端相连，控制端与重置模块111的控制端相连。
所述输入模块104和所述输出模块101可以均为晶体管。
所述移位寄存器单元所包含的各个晶体管可以均为N型晶体管，电平维持模块105可以为电容。此时，各个模块的开启电平为高电平，关闭电平为低电平。
这样，能够统一制作工艺，降低制作难度。
当然实际应用中，其中的一部分晶体管采用P型晶体管也能实现本发明的技术方案，比如本发明的实施例中，上述的复位控制模块103中的各个晶体管均为P型晶体管也可以实现本发明的技术方案，相应也应该落入本发明的保护范围。
另一方面，本发明还提供了一种用于驱动上述任一项所述的移位寄存器单元的方法，该方法包括：针对接收到的多脉冲的待移位信号而输出相同脉冲个数的移位信号之后，在复位控制模块103的控制端施加控制信号来开启所述复位模块102对所述第一节点Q进行复位。
通过这种方式，在输出的移位信号的脉冲个数与待移位信号的脉冲个数相同时，及时开启复位模块102以对第一节点Q进行复位。这样，允许在第一节点Q被复位之前，输出模块101输出具有多个脉冲的移位信号。
在具体实施时，当所述复位控制模块103包括两个控制端(C1，C2)时，上述的方法具体包括：在针对接收到的多脉冲的待移位信号而输出相同脉冲个数的移位信号之后，在第一控制端C1接入第二电平且在第二控制端C2接入第一电平。
进一步的，所述第一电平与脉冲电平一致，第二电平与非脉冲电平一致，此时上述的方法可以具体包括：将所述复位控制模块103的第一控制端C1接入待移位信号，将所述复位控制模块103的第二控制端C2接入下一级移位寄存器输出的移位信号，且在所述复位控制模块103的第一控制端C1接入脉冲电平时，在所述复位控制模块103的第一接入端I1接入复位关闭电平，在所述复位控制模块103的第一控制端C1接入非脉冲电平、第二控制端C2接入脉冲电平时，在所述复位控制模块103的第二接入端I2接入复位开启电平。
这样能够降低复位控制的复杂度。
当所述移位寄存器单元包括复位加强模块106和复位加强控制模块107时，所述方法还包括：在所述复位模块102将所述第一节点Q的电平复位为能够使所述输出模块101关闭的输出关闭电平之后，在 所述复位加强控制模块107的控制端施加控制信号以将所述复位加强控制模块107开启。
一般的，复位模块102对第一节点Q进行复位的过程比较短暂，在第一节点Q被复位之后，复位模块102不再开启。但是，由于器件本身的问题，输入模块104可能漏电而导致第一节点Q的电平改变，进而导致输出模块101再次开启而输出脉冲。通过设置复位加强模块106和复位加强控制模块107，能够在所述复位模块102将所述第一节点Q的电平复位为能够使所述输出模块101关闭的输出关闭电平之后，继续对所述第一节点Q进行复位，避免了第一节点Q的电平发生改变。
具体的，当所述复位加强控制模块107还包括第三控制端和第三接入端时，上述的方法还包括：将所述复位加强控制模块107的第二控制端接第二时钟信号输入端，第三控制端接第三时钟信号输入端，使所述复位加强控制模块107的输出端与所述复位加强控制模块107的第一接入端和第二接入端交替导通。
这样做的好处是，能够在所述复位模块102将所述第一节点Q的电平复位为能够使所述输出模块101关闭的输出关闭电平之后，使复位加强模块106持续开启，以将第一节点Q的电平持续置为输出关闭电平。
在具体实施时，当移位寄存器单元还包括夹断模块109时，上述的方法还包括：在所述移位寄存器单元输出的移位信号处于脉冲电平时，对所述夹断模块109施加控制信号来使所述夹断模块109开启。
实施例二
下面结合具体的电路以及一种可能的驱动方法对本发明提供的一种移位寄存器单元的工作原理进行说明，如图4所示，本发明提供的移位寄存器单元可以包括18个N型晶体管和一个电容C。
如图4所示，图1A中的输入模块104由两个晶体管T6-1和T6-2串联而成，晶体管T6-1的源极(图中表示为S)连接晶体管T6-2的 漏极(图中表示为D)，T6-1的漏极连接待移位信号的输入端，用于接收待移位信号STU，栅极也连接待移位信号的输入端；晶体管T6-2的栅极连接一个时钟信号输入端，用于接入时钟信号CLKA，晶体管T6-2的源极连接节点Q。
输出模块101包括晶体管T7，晶体管T7的漏极连接另一个时钟信号输入端，用于接入时钟信号CLKB，晶体管T7的源极连接节点OUT，用于输出移位信号，栅极连接节点Q。这里的CLKA和CLKB为相位相反的时钟信号。
复位模块102包括两个晶体管T8-1和T8-2，晶体管T8-2的源极连接晶体管T8-1的漏极，T8-1的源极连接可以将节点Q复位成低电平的公共低电压电极VGL，晶体管T8-2的漏极连接节点Q。晶体管T8-1和T8-2的栅极均连接节点DD。
复位控制模块103包括晶体管T1和T2，其中晶体管T1的沟道宽长比大于晶体管T2的沟道宽长比，晶体管T1的源极连接公共低电压电极VGL，栅极也连接待移位信号输入端以接收待移位信号STU；晶体管T2的源极和栅极连接下一级移位寄存器单元移位信号的输出端，以接入下一级移位寄存器单元输出的移位信号STD。晶体管T1和T2的漏极均连接节点DD。
图4中还示出了复位加强模块106和复位加强控制模块107的结构，与复位模块102的结构类似，该复位加强模块106包括晶体管T9-1和T9-2，晶体管T9-2的源极连接晶体管T9-1的漏极，T9-1的源极连接可以将第一节点Q复位成低电平的公共低电压电极VGL，晶体管T9-2的漏极连接第一节点Q，晶体管T9-1和T9-2的栅极均连接节点Qb。
复位加强控制模块107包括晶体管T3、T4、T5，其中晶体管T3的栅极连接节点Q，漏极连接节点Qb，源极连接公共低电压电极VGL；T4的栅极和漏极连接时钟信号输入端，用于接入时钟信号CLKA，源极连接节点Qb；T5的栅极和漏极连接另一时钟信号输入端，用于接入 时钟信号CLKB，源极连接节点Qb。晶体管T3的沟道宽长比大于晶体管T4以及晶体管T5的沟道宽长比。
图4中的电路中还示出了负载模块108的结构，该负载模块108包括一个晶体管T10，晶体管T10的漏极连接另一个时钟信号输入端，用于接入时钟信号CLKB，晶体管T10的源极连接节点负载输出端CR，用于输出移位信号。同时，晶体管T10的源极还连接电容C的不与节点Q相连的一极。
相类似的，图4中的电路中还示出了辅助输出模块110的结构，该辅助输出模块110包括一个晶体管T11，晶体管T11的漏极连接另一个时钟信号输入端，用于接入时钟信号CLKB，晶体管T11的源极连接节点N1。
图4中的电路中还示出了夹断模块109的结构，该夹断模块109包括一个晶体管T12，晶体管T12的源极连接节点N1，栅极连接图中的负载输出端CR，T12的漏极与复位模块102中两个晶体管之间的串联连接处(晶体管T8-2的源极与晶体管T8-1的漏极之间的连接处)、输入模块104中的两个晶体管之间的串联连接处(晶体管T6-1的源极与晶体管T6-2的漏极之间的连接处)、复位加强模块106中的两个晶体管之间的串联连接处(晶体管T9-2的源极与晶体管T9-1的漏极之间的连接处)相连。
图4中的电路还包括构成三个重置模块111的结构，三个重置模块111分别对应于晶体管T13-1、T13-2、T13-3，其中晶体管T13-1的漏极与负载输出端CR相连，源极与公共低电压电极VGL相连，栅极连接图中的节点Qb；晶体管T13-2的漏极与节点N1相连，源极与公共低电压电极VGL相连，栅极连接图中的节点Qb；晶体管T13-3的漏极与节点OUT相连，源极与公共低电压电极VGL相连，栅极连接图中的节点Qb。
下面结合图5对图4的电路的一种驱动方法进行详细说明，图5所示为图4中的移位寄存器单元电路在工作时各个关键节点电平的时 序图。假设，利用图4中的电路对具有三个脉冲的待移位信号STU进行移位以得到具有三个脉冲的移位信号，其中，移位信号的脉冲具有高电平。
在第一阶段S1(每一个阶段对应于一个时钟)，待移位信号STU为高电平，输出的移位信号OUT为低电平，CLKA为高电平，CLKB为低电平，STD为低电平，此时，两个晶体管T6-1和T6-2均导通，STU的高脉冲电平写入到节点Q。节点Q的拉高导致晶体管T3导通，虽然晶体管T4也导通，但是由于其沟道宽长比小于晶体管T3的沟道宽长，此时节点Qb的电平被拉低为公共低电压电极VGL的电平，导致晶体管T9-1、T9-2关断。另外，由于STU为高电平，导致DD点的电平为低电压电极VGL的电平，晶体管T8-1、T8-2也均关断，这样节点Q的电平不会受到复位模块102、复位加强模块106的影响。同时，由于节点Qb的电平为低，导致T13-1、T13-2、T13-3也均关断。另外，节点Q的拉高还导致晶体管T7、T10、T11导通，但是由于CLKB为低电平，此时节点OUT、N1和CR输出的电平均为低电平。
在第二阶段S2，待移位信号STU为低电平，输出移位信号OUT为高电平，CLKA为低电平，CLKB为高电平，STD也为低电平。由于STU为低电平，CLKA为低电平，输入模块104中的两个晶体管T6-1和T6-2均关断，另外，在复位控制模块103中，T1关闭，由于STD为低电平，T2也关闭，DD点的电平仍为低电平，相应的，T8-1、T8-2也不会被导通，节点Q的电平仍不受影响。此时，晶体管T7、T10、T11继续导通，节点OUT、N1和CR输出的电平与CKLB一致，均为高电平。由于节点Q的电平为高，节点Qb的电平仍为低，导致T13-1、T13-2、T13-3仍关闭，避免影响OUT、N1和CR输出高电平。同时，在该第二阶段S2，由于负载输出端CR和节点N1的电平均为高，T12导通，其源极的电平为高，导致晶体管T6-1的源极与晶体管T6-2的漏极之间的连接处、晶体管T9-2的源极与晶体管T9-1的漏极之间的连接处、以及晶体管T8-2的源极与晶体管T8-1的漏极之间的连接处 的电平均为高电平，这样节点Q与这些连接处之间没有足够的电势差，相应的，导致晶体管T6-1、T8-2、T9-2均被夹断，不会影响节点Q的电平。另外，在该第二阶段S2，由于将负载输出端CR与电容C的不与节点Q相连的一端相连，导致输出端CR的电平进一步升高，节点Q发生电容自举，进一步提高了节点Q的电平，此时节点Q的电平的理想值为时钟信号高电平和时钟信号低电平之间的差值的绝对值，由于时钟信号低电平一般为负值，则节点Q的电平大于时钟信号高电平，保证了晶体管T7的导通。
在第三阶段S3，待移位信号STU为高电平，输出移位信号OUT为低电平，CLKA为高电平，STD为高电平。此时，与第一阶段S1类似，节点Q的电平为高，节点Qb的电平为低，OUT仍输出低电平，晶体管T9-1、T9-2关断、晶体管T13-1、T13-2、T13-3均关断，由于STU为高电平，DD点的电平被置为低电平。晶体管T8-1、T8-2仍不会被开启，节点Q仍维持为高电平。相应的，第五阶段S5中各个晶体管的开关状态、各个关键节点的电平状态与第三阶段S3中的一致。
类似的，第四阶段S4、第六阶段S6中各个晶体管的开关状态、各个关键节点的电平状态与第二阶段S2中的一致。OUT、N1和CR在第四阶段S4均输出一个脉冲，在第六阶段S6再次输出一个脉冲。在第六阶段S6后，输出的脉冲的个数达到三个，与STU的脉个数一致。
在第七阶段S7，STU为低电平，CLKA为高电平，CLKB为低电平，STD为高电平，此时晶体管T1关断，晶体管T2开启，导致节点DD的电平被拉高。晶体管T8-1、T8-2导通，使得节点Q的电平被拉低，完成了对节点Q的复位。由于节点Q为低电平，导致晶体管T3关断，相应的节点Qb的电平取决于晶体管T4和T5，由于CLKA为高电平，晶体管T4导通，节点Qb的电平被拉高，晶体管T9-1和T9-2导通，进一步保证了节点Q的电平被拉低。
在第八阶段S8，STU和STD均为低电平，CLKA也为低电平，晶体管T6-1和T6-2均关断，节点Q的电平仍无法被拉高。这样晶体管 T3也不会被导通，由于此时CLKB为高，因此晶体管T5导通，节点Qb的电平仍为高电平，晶体管T9-1和T9-2继续导通，使节点Q的电平继续被拉低为低电平。
在第九阶段S9，STU和STD均为低电平，晶体管T6-1关断，节点Q的电平仍无法被拉高，晶体管T3仍不会被导通。由于此时CLKA为高电平，晶体管T4导通，节点Qb的电平仍为高电平，晶体管T9-1和T9-2继续导通，使节点Q的电平继续被拉低为低电平。
可见，在同一帧内，第七阶段S7之后，节点Q的电平不会被再次拉高，晶体管T3不会导通，由于晶体管T4和T5交替导通，节点Qb的电平一直为高电平，使晶体管T9-1和T9-2继续导通，保证了节点Q的电平被持续拉低为低电平。另外，节点Qb的电平一直为高电平也会使得晶体管T13-1、T13-2、T13-3均导通，进一步保证了各个输出端CR、N1、OUT的电平被拉低。
另一方面，本发明还提供了一种栅极扫描电路，该栅极扫描电路包括多个级联的移位寄存器单元，该移位寄存器单元可以为上述实施例中的任意一种移位寄存器单元。
在具体实施时，本级移位寄存器单元中的输入模块的输入端与上一级移位寄存器单元的输出模块、或者负载模块或辅助输出模块的输出端相连，复位控制模块的第一控制端也与上一级移位寄存器单元的输出模块、或者负载模块或辅助输出模块的输出端相连，第二控制端与下一级移位寄存器单元的输出模块、或者负载模块或辅助输出模块的输出端相连。各个移位寄存器单元的复位控制模块的第二接入端可以与其第二控制端连接。
具体到图4中所示的移位寄存器单元电路，晶体管T6-1的漏极和晶体管T1的栅极均连接上一级移位寄存器单元输出的移位信号STU，晶体管T2的栅极连接下一级移位寄存器单元输出的移位信号STD。晶体管T2的源极可以与晶体管T2的栅极连接，也可以直接连接公共高电平电极。
在上述的栅极扫描电路中，多个移位寄存器单元中的第一级移位寄存器单元的输入端连接起始信号输入端，最后一级移位寄存器单元的输出模块的输出端不连接其他移位寄存器单元。
以上所述仅给出了本发明的部分具体实施方式，但是，本发明的保护范围不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内可轻易想到的变化或替代，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (32)

  1. 一种移位寄存器单元，包括用于接收待移位信号的输入模块，其中，所述移位寄存器还包括：
    输出模块、复位模块和复位控制模块，其中，输入模块的输出端、输出模块的控制端、复位模块的输出端连接第一节点，所述复位控制模块的输出端与所述复位模块的控制端相连，适于在所述复位控制模块的控制端所接入的控制信号的控制下，开启所述复位模块来对所述第一节点进行复位，以使得在对所述第一节点进行复位之前，所述输出模块输出具有多个脉冲的移位信号。
  2. 如权利要求1所述的移位寄存器单元，其中，
    所述复位控制模块的控制端包括第一控制端和第二控制端，适于在第一控制端接入第一电平时，关闭所述复位模块，在第一控制端接入第二电平且第二控制端接入第一电平时，开启所述复位模块来对所述第一节点进行复位。
  3. 如权利要求1所述的移位寄存器单元，其中，所述输入模块的输出端适于在在接收到的待移位信号处于脉冲电平时，将所述第一节点置为能够使所述输出模块开启的输出开启电平；
    所述输出模块适于在所述第一节点的电平为输出开启电平时输出移位信号；
    所述复位模块适于在所述输出模块输出移位信号之后将所述第一节点的电平复位为能够使所述输出模块关闭的输出关闭电平。
  4. 如权利要求1所述的移位寄存器单元，还包括：
    电平维持模块，所述电平维持模块与所述第一节点相连，适于在 所述输入模块和所述复位模块均关闭时，维持第一节点的电平。
  5. 如权利要求2所述的移位寄存器单元，其特征在于，所述复位控制模块的第一控制端连接待移位信号输入端，第二控制端连接下一级移位寄存器单元的移位信号输出端，待移位信号和移位信号中的脉冲电平与所述第一电平一致，待移位信号和移位信号中的非脉冲电平与所述第二电平一致。
  6. 如权利要求2所述的移位寄存器单元，其中，所述复位控制模块具有第一接入端和第二接入端，第二接入端用于接入能够使所述复位模块开启的复位开启电平，第一接入端用于接入能够使所述复位模块关闭的复位关闭电平；
    所述复位控制模块适于在第一控制端接入第一电平时，将第一接入端与输出端导通，在第二控制端接入第一电平时，将第二接入端与输出端导通，且在输出端与第一接入端和第二接入端均导通时，输出端的电平与第一接入端保持一致。
  7. 如权利要求6所述的移位寄存器单元，其特征在于，所述复位控制模块的第一接入端连接第一公共电极、或者第一时钟信号输入端、或者该移位寄存器单元的移位信号输出端，所述第一公共电极的电平与所述复位关闭电平一致，所述第一时钟信号输入端所接入的时钟信号在所述复位控制模块的第一接入端与所述复位控制模块的输出端导通时为复位关闭电平；
    所述复位控制模块的第二接入端连接第二公共电极、或者连接下一级移位寄存器单元的移位信号输出端、或者连接第二时钟信号输入端，所述第二公共电极的电平与所述复位开启电平一致，所述第二时钟信号输入端所接入的时钟信号在所述复位控制模块的第二接入端与所述复位控制模块的输出端导通时为复位开启电平。
  8. 如权利要求6所述的移位寄存器单元，其特征在于，所述复位控制模块包括第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管均在控制端接入第一电平时导通、接入第二电平时关闭，其中，
    所述第一晶体管的第一端连接所述复位控制模块的第一接入端，控制端连接所述复位控制模块的第一控制端，第二端连接所述复位控制模块的输出端；所述第二晶体管的第一端连接所述复位控制模块的第二接入端，控制端连接所述复位控制模块的第二控制端，第二端连接所述复位控制模块的输出端，
    所述第一晶体管的沟道宽长比大于所述第二晶体管的沟道宽长比。
  9. 如权利要求3所述的移位寄存器单元，还包括：复位加强模块和复位加强控制模块；
    所述复位加强模块的输出端与所述第一节点相连，适于对第一节点的电平进行复位；
    所述复位加强控制模块的输出端与所述复位加强模块的控制端相连，适于在所述复位加强控制模块的控制端所接入的控制信号的控制下，在所述复位模块将所述第一节点的电平复位为输出关闭电平之后，开启所述复位加强模块继续对所述第一节点进行复位。
  10. 如权利要求9所述的移位寄存器单元，其中，所述复位加强控制模块具有第一接入端和第二接入端、第一控制端和第二控制端，第二接入端用于接入能够使所述复位加强模块开启的复位加强开启电平，第一接入端用于接入能够使所述复位加强模块关闭的复位加强关闭电平；
    所述复位加强控制模块的第一控制端连接第一节点，适于在第一节点为输出开启电平时，将第一接入端与输出端导通，在第二控制端接入对应的有效电平时，将第二接入端与输出端导通，且在输出端与 第一接入端和第二接入端均导通时，输出端的电平与第一接入端保持一致。
  11. 如权利要求10所述的移位寄存器单元，其中，所述复位加强控制模块还包括第三控制端和第三接入端，第三接入端用于接入复位加强开启电平，所述复位加强控制模块适于在第三控制端接入对应的有效电平时，使第三接入端与输出端导通，且在输出端与第一接入端和第三接入端均导通时，输出端的电平与第一接入端保持一致。
  12. 如权利要求11所述的移位寄存器单元，其中，所述复位加强控制模块包括第三晶体管、第四晶体管和第五晶体管，所述第三晶体管的控制端连接所述复位加强控制模块的第一控制端，第一端连接所述复位加强模块的第一接入端，第二端连接所述复位加强控制模块的输出端，在所述复位加强控制模块的第一控制端接入所述输出开启电平时，第三晶体管的第一端和第二端导通；所述第四晶体管的控制端连接所述复位加强控制模块的第二控制端，第一端连接所述复位加强控制模块的第二接入端，第二端连接所述复位加强控制模块的输出端；第五晶体管的控制端连接所述复位加强控制模块的第三控制端，第一端连接所述复位加强控制模块的第三接入端，第二端连接所述复位加强控制模块的输出端；
    所述第四晶体管和所述第五晶体管对应的有效电平相反，或者第二接入端和第三接入端均用于接入时钟信号，且第二接入端所接入的时钟信号的相位与第三接入端所接入的时钟信号的相位相反。
  13. 如权利要求9所述的移位寄存器单元，还包括：负载模块，所述负载模块的控制端与第一节点相连，适于在所述第一节点的电平为输出开启电平时输出移位信号。
  14. 如权利要求13所述移位寄存器单元，其中，所述负载模块包括一个晶体管，该晶体管的第一端与所述负载模块的输入端相连，第二端与所述负载模块的输出端相连，控制端与所述负载模块的控制端相连。
  15. 如权利要求13所述的移位寄存器单元，还包括夹断模块，用于在输出的移位信号处于脉冲电平时开启，将所述输入模块和/或所述复位模块和/或所述复位加强模块夹断。
  16. 如权利要求15所述的移位寄存器单元，还包括：
    辅助输出模块，所述辅助输出模块的控制端与第一节点相连，适于在所述第一节点的电平为输出开启电平时输出移位信号，移位信号的脉冲电平与所述输出开启电平一致；
    所述输入模块、所述复位模块和所述复位加强模块均包括由两个晶体管串联在一起组成的晶体管组合；
    所述夹断模块的控制端与所述负载模块的输出端相连，输入端与所述辅助输出模块的输出端相连，输出端与所述晶体管组合中两个晶体管之间的串联连接处相连，在所述负载模块和所述辅助输出模块的输出端输出的移位信号为脉冲电平时，所述夹断模块的输入端和输出端导通，使得所述晶体管组合中两个晶体管之间的串联连接处的电平与所述输出开启电平一致。
  17. 如权利要求15所述的移位寄存器单元，其中，所述夹断模块包括一个晶体管，该晶体管的第一端与所述夹断模块的输入端相连，第二端与所述夹断模块的输出端相连，控制端与所述夹断模块的控制端相连。
  18. 如权利要求16所述的移位寄存器单元，其中，所述辅助输出 模块包括一个晶体管，该晶体管的第一端与所述辅助输出模块的输入端相连，第二端与所述辅助输出模块的输出端相连，控制端与所述辅助输出模块的控制端相连。
  19. 如权利要求16所述的移位寄存器单元，还包括三个重置模块，三个重置模块分别用于在所述输出模块输出移位信号之后对输出模块、负载模块、辅助输出模块的输出端进行重置，使各个输出端的电平被重置为非脉冲电平。
  20. 如权利要求19所述的移位寄存器单元，其中，三个重置模块的控制端与所述复位加强控制模块的输出端相连，输入端均用于接入非脉冲电平，输出端对应地与输出模块、负载模块、辅助输出模块的输出端相连，以在所述复位加强控制模块开启所述复位加强模块时，重置模块的输入端和输出端导通。
  21. 如权利要求19所述的移位寄存器单元，其中，每个所述重置模块包括一个晶体管，该晶体管的第一端与所述重置模块的输入端相连，第二端与所述重置模块的输出端相连，控制端与所述重置模块的控制端相连。
  22. 如权利要求21所述的移位寄存器单元，其特征在于，所述输出模块为晶体管，且所述移位寄存器单元所包含的各个晶体管均为N型晶体管。
  23. 一种栅极驱动电路，包括多个如权利要求1-22中任一项所述的移位寄存器单元，还包括至少一条时钟信号线，各个移位寄存器单元的输出模块的输入端连接同一时钟信号线。
  24. 如权利要求23所述的栅极驱动电路，其中，所述多个移位寄存器单元的每一个为如权利要求3所述的移位寄存器单元时，第一级移位寄存器单元的输入模块的输入端连接起始信号输入端。
  25. 如权利要求23所述的栅极驱动电路，其中，所述多个移位寄存器单元的每一个为如权利要求6所述的移位寄存器单元时，各个移位寄存器单元的复位控制模块的第二接入端与第二控制端连接。
  26. 如权利要求24所述的栅极驱动电路，其中，当各个移位寄存器单元的输入模块包括由两个晶体管串联在一起组成的晶体管组合时，输入模块中与第一节点相连的晶体管的控制端连接另一时钟信号线，所述另一时钟信号线中的时钟信号的相位与所述输出模块所连接的时钟信号线中的时钟信号的相位相反。
  27. 一种驱动如权利要求1-22中任一项所述的移位寄存器单元的方法，包括：
    在针对接收到的多脉冲的待移位信号而输出相同脉冲个数的移位信号之后，在复位控制模块的控制端施加控制信号来开启所述复位模块，以对所述第一节点进行复位。
  28. 如权利要求27所述的方法，其中，当所述移位寄存器单元为如权利要求2所述的移位寄存器单元时，所述方法包括：
    在针对接收到的多脉冲的待移位信号而输出相同脉冲个数的移位信号之后，在第一控制端接入第二电平且第二控制端接入第一电平。
  29. 如权利要求27所述的方法，其中，当所述移位寄存器单元为如权利要求6所述的移位寄存器单元时，所述方法包括：将所述复位控制模块的第一控制端接入待移位信号，将所述复位控制模块的第二 控制端接入下一级移位寄存器单元所输出的移位信号，且在第一控制端接入第一电平时，在第一接入端接入复位关闭电平，在第一控制端接入第二电平且第二控制端接入第一电平时，在第二接入端接入复位开启电平。
  30. 如权利要求27所述的方法，其中，当所述移位寄存器单元为如权利要求9所述的移位寄存器单元时，所述方法还包括：
    在所述复位模块将所述第一节点的电平复位为能够使所述输出模块关闭的输出关闭电平之后，在所述复位加强控制模块的控制端施加控制信号，以将所述复位加强控制模块开启。
  31. 如权利要求27所述的方法，其中，当所述移位寄存器单元为如权利要求11所述的移位寄存器单元时，所述方法还包括：
    将所述复位加强控制模块的第二控制端接入第三时钟信号输入端，第三控制端接入第四时钟信号输入端，使所述复位加强控制模块的输出端与所述复位加强控制模块的第一接入端和第二接入端交替导通。
  32. 如权利要求27所述的方法，其中，当所述移位寄存器单元为如权利要求15所述的移位寄存器单元时，所述方法还包括：在所述移位寄存器输出的移位信号为脉冲电平时，施加控制信号使所述夹断模块开启。
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