WO2016123933A1 - 一种阵列基板的制作方法、显示基板及显示装置 - Google Patents

一种阵列基板的制作方法、显示基板及显示装置 Download PDF

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WO2016123933A1
WO2016123933A1 PCT/CN2015/085294 CN2015085294W WO2016123933A1 WO 2016123933 A1 WO2016123933 A1 WO 2016123933A1 CN 2015085294 W CN2015085294 W CN 2015085294W WO 2016123933 A1 WO2016123933 A1 WO 2016123933A1
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pattern
substrate
passivation layer
forming
layer
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PCT/CN2015/085294
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English (en)
French (fr)
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崔承镇
金熙哲
崔贤植
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京东方科技集团股份有限公司
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Priority to US15/122,168 priority Critical patent/US9865629B2/en
Priority to EP15880882.4A priority patent/EP3098840B1/en
Publication of WO2016123933A1 publication Critical patent/WO2016123933A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an array substrate, a display substrate, and a display device.
  • the liquid crystal display panel for displaying pictures mainly includes an array substrate for driving a display screen of a display panel, and a color film substrate for realizing color display, and filling.
  • HADS high-intensity high-precision field switching
  • the structure mainly includes: a gate line, an active layer, a source/drain electrode, a pixel electrode, a passivation layer and a common electrode; and in fabricating the above array substrate, a passivation layer is usually formed by a resin process, thereby reducing source and drain electrodes The capacitance between the pixel electrode and the pixel electrode, thereby reducing the RC delay of the source and drain electrodes, thereby reducing the power consumption of the display panel. Therefore, in the specific fabrication process of the array substrate, the gate electrode, the active layer, the source and drain electrodes, the pixel electrode, the resin layer, and the common electrode need to be sequentially patterned, so that at least six mask processes are required to complete the array substrate. Production, such a production method, the cost is higher, the process is more complicated.
  • the embodiment of the invention provides a method for fabricating an array substrate, a display substrate and a display device, which are used to solve the problem that the number of masks used in the fabrication process of the array substrate existing in the prior art is large, resulting in a manufacturing process of the array substrate. complicated question.
  • a method of fabricating an array substrate is provided.
  • the method of fabricating the array substrate includes the steps of: forming a pattern including an active layer and source and drain electrodes on a base substrate; forming a first transparent electrode and a passivation layer by one patterning process a pattern; and processing the base substrate on which the passivation layer pattern is formed such that the material of the passivation layer is at least partially filled in the slit in the first transparent electrode pattern.
  • the step of forming a pattern of the first transparent electrode and the passivation layer by one patterning process includes: sequentially forming a transparent conductive layer film layer and a passivation layer film layer; The layer film layer is patterned to form the passivation layer pattern; and the transparent conductive layer film layer is patterned by using the formed passivation layer pattern as a mask to form a pattern of the first transparent electrode.
  • the step of processing the base substrate on which the passivation layer pattern is formed includes annealing the base substrate on which the passivation layer pattern is formed.
  • the material of the passivation layer is a resin material.
  • the step of annealing the base substrate on which the passivation layer pattern is formed includes: forming the base substrate on which the passivation layer pattern is formed at a temperature of 200 ° C to 250 ° C Heat treatment in the environment.
  • the passivation layer pattern has a thickness of 0.5 ⁇ m to 1 ⁇ m, and the heat treatment has a duration of 20 minutes to 60 minutes.
  • the method for fabricating the array substrate further includes: forming a pattern of the second transparent electrode on the substrate after processing the substrate formed with the passivation layer pattern.
  • the step of forming a pattern of an active layer and a source and drain on a base substrate includes sequentially forming an active layer film layer and a source/drain electrode layer film layer on the base substrate And patterning the active layer film layer and the source/drain electrode layer film layer with a mask to form a pattern of the active layer and the source and drain electrodes.
  • the method for fabricating the above array substrate further includes the step of forming a pattern of a gate on the substrate, wherein: forming a pattern of the active layer and the source and drain on the substrate Previously, a pattern of gate electrodes is formed on the base substrate; or an active layer is formed on the base substrate After the step of patterning the source and drain electrodes, a pattern of gate electrodes is formed on the base substrate on which the patterns of the active layer and the source and drain are formed.
  • a display substrate is provided.
  • the display substrate includes an array substrate fabricated by using the fabrication method of the array substrate provided by any of the above embodiments.
  • a display substrate is also provided.
  • the display device includes the display substrate provided in accordance with the above embodiments.
  • Embodiments of the present invention provide a method for fabricating an array substrate, a display substrate, and a display device.
  • the method for fabricating the array substrate includes forming a pattern including an active layer and source and drain electrodes on a substrate; a pattern of a transparent electrode and a passivation layer; processing the base substrate on which the passivation layer pattern is formed, so that the material of the passivation layer is at least partially filled in the gap in the first transparent electrode pattern, wherein the patterning process is performed once Forming the pattern of the first transparent electrode and the passivation layer can reduce the manufacturing process of the array substrate, and the embodiment of the present invention provides a pattern of forming the first transparent electrode and the passivation layer by two patterning processes in the prior art.
  • the method for fabricating the array substrate can form a pattern of the first transparent electrode and the passivation layer by using a mask plate in one patterning process, thereby reducing the number of mask plates used in the process of fabricating the array substrate, thereby simplifying the fabrication process of the array substrate , thereby reducing the production cost of the array substrate.
  • FIG. 1 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention
  • FIG. 2a is a schematic structural view of a substrate after deposition of a transparent conductive layer according to an embodiment of the present invention
  • FIG. 2b is a schematic structural diagram of a substrate substrate forming a passivation layer pattern according to an embodiment of the present invention
  • 2c is a schematic structural diagram of a substrate substrate forming a first transparent electrode pattern according to an embodiment of the present invention
  • 3a is a schematic structural diagram of a substrate after annealing treatment according to an embodiment of the present invention.
  • 3b is a second schematic structural diagram of a substrate after annealing treatment according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a base substrate forming a second transparent electrode pattern according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a substrate for forming a gate according to an embodiment of the present invention.
  • FIG. 5b is a schematic structural diagram of a substrate substrate forming a source/drain electrode according to an embodiment of the present invention.
  • FIG. 5c is a schematic structural diagram of a substrate for forming a via hole according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a substrate for forming a passivation layer according to an embodiment of the present invention.
  • FIG. 5e is a schematic structural diagram of a substrate for forming a second transparent electrode according to an embodiment of the present invention.
  • the embodiment of the invention provides a method for fabricating an array substrate, as shown in FIG. 1 , which can be specifically implemented by the following steps:
  • the first transparent electrode may be a pixel electrode
  • the array substrate fabrication process may be simplified by forming the pattern of the pixel electrode and the passivation layer only by one patterning process.
  • the method for fabricating the pattern of the pixel electrode and the passivation layer by the two patterning processes can adopt a patterning process and adopt only one mask. Both the pattern of the pixel electrode and the passivation layer are formed, so that the number of masks used in the fabrication of the array substrate can be reduced, thereby simplifying the fabrication process of the array substrate, thereby reducing the production cost of the array substrate.
  • the patterning process includes any form of patterning, for example, by using a photoresist to expose the developing etching.
  • the steps specifically included in the method include, but are not limited to, coating a photoresist, exposing with a mask, developing, The film layer to be patterned is etched to form a corresponding pattern.
  • the patterning process for the passivation layer may include coating photoresist, exposure, development, etching, and patterning the transparent conductive layer. The process only includes the etching process.
  • step S102 may be specifically implemented in the following manner:
  • a transparent conductive layer film layer and a passivation layer film layer in sequence, that is, forming a transparent conductive layer film layer 03 on the substrate substrate on which the active layer 01 and the source/drain electrode layer 02 are formed, as shown in FIG. 2a. And then forming a passivation layer film layer on the base substrate on which the transparent conductive layer film layer 03 is formed;
  • the passivation layer is patterned to form a passivation layer pattern, that is, a patterned substrate is formed by using a mask to form a passivation layer 04, as shown in FIG. 2b. Shown
  • the transparent conductive layer film layer 03 is patterned by using the pattern of the passivation layer formed as a mask to form a pattern of the first transparent electrode 05, that is, the patterned passivation layer 04 is used as a mask to the transparent conductive layer film.
  • the layer 03 is subjected to a patterning process to form a pattern of the first transparent electrode 05, thereby forming a substrate having a pattern of the first transparent electrode 05 and the passivation layer 04, as shown in Fig. 2c.
  • the first transparent electrode 05 may be a pixel electrode.
  • the pattern of the passivation layer is formed by patterning the passivation layer by using a mask, and then the pattern of the passivation layer is used as a mask to be transparent.
  • the conductive layer is patterned to form a pattern of pixel electrodes, so in the process step of forming a pattern of the pixel electrode and the passivation layer, only one mask is used.
  • the method for fabricating the array substrate provided by the embodiment of the present invention can reduce the process of fabricating the array substrate, as compared with the prior art process of forming a pattern of the pixel electrode and the passivation layer by using two masks by two patterning processes. The number of masks used, which in turn simplifies the fabrication process of the array substrate, thereby reducing the production cost of the array substrate.
  • Method for fabricating the above array substrate provided by an embodiment of the present invention, according to an exemplary embodiment
  • the passivation layer it is necessary to process the underlying substrate on which the passivation layer pattern is formed so that the material of the passivation layer is at least partially filled in the gap in the first transparent electrode pattern.
  • the processing method provided by the embodiment of the present invention is that the base substrate formed with the passivation layer pattern is annealed, such that after the annealing treatment, the material of the passivation layer on the base substrate is at least partially filled with the first transparent electrode pattern. In the gap, as shown in Figure 3a.
  • the gap in the first transparent electrode pattern may be completely filled with the passivation layer material, thereby forming an entire passivation layer, and the entire passivation layer can achieve its insulating function.
  • the material of the passivation layer may be partially filled in the gap in the first transparent electrode pattern by processing the base substrate on which the passivation layer pattern is formed, as shown in FIG. 3b.
  • the material of the passivation layer 04 does not completely fill the gap in the pattern of the first transparent electrode 05, but leaves a gap to form a via via, so that the second transparent electrode 06 formed in the subsequent process may be a pixel. electrode.
  • the pixel electrode 06 can be connected to the drain through a via-channel that is not filled with the material of the passivation layer 04, and the first transparent electrode 05 serves as a common electrode to provide a voltage signal to the pixel electrode, thereby driving the pixel electrode to realize an image display function. This will be explained in detail below.
  • the material of the passivation layer may be a resin material, or one or more of insulating materials such as silicon nitride and silicon oxide, which are not limited herein.
  • the resin is used as the material of the passivation layer, the function of insulating the passivation layer can be achieved, and the capacitance between the source and drain electrodes and the pixel electrode can be reduced, thereby reducing the RC delay of the source and drain electrodes, and thus Reduce the power consumption of the array substrate.
  • the material of the passivation layer may be any material having an insulating property, which is not limited herein.
  • the annealing process of the substrate substrate formed with the passivation layer pattern described above may specifically include: the substrate substrate on which the passivation layer pattern is formed is at a temperature of 200 ° C to 250 ° C.
  • the heat treatment is performed in the environment, and the passivation layer material is melted by heat, and then flow-filled into the gap of the passivation layer pattern on the substrate substrate without the first transparent electrode material.
  • the base substrate forming the passivation layer pattern is annealed After that, the thickness of the passivation layer is generally reduced to about 80%. Since the annealing treatment is limited by the starting voltage, the thickness of the passivation layer may not be too thick, and generally it is preferably 1 ⁇ m or less.
  • the thickness of the passivation layer pattern is 0.5 ⁇ m to 1 ⁇ m, and the heat treatment is performed for 20 minutes to 60 minutes during the annealing process, so that the The layer pattern is annealed so that the material of the passivation layer is at least partially filled in the gap in the first transparent electrode pattern.
  • the substrate may be further formed on the substrate after processing the substrate on which the pattern of the passivation layer 04 is formed.
  • the pattern of the two transparent electrodes 06 is as shown in FIG. That is, a transparent conductive layer film layer is deposited on the base substrate after the annealing treatment, and a second transparent electrode 06 is formed by patterning the transparent conductive layer film layer.
  • the formed second transparent electrode 06 may be a common electrode. Since the process of forming the common electrode is the same as the prior art, it will not be described in detail herein.
  • a common electrode is formed over the passivation layer. When the array substrate is applied to an actual product, the common electrode can transmit a voltage signal to the pixel electrode, and drive the pixel electrode to realize an image display function.
  • the step of forming a pattern of the active layer and the source and drain on the base substrate may be specifically implemented as follows:
  • the active layer film layer and the source/drain electrode layer film layer are patterned by a mask to form a pattern of the active layer and the source and drain electrodes.
  • the pattern of the active layer and the source and drain can be formed by performing a patterning process on the substrate by using one mask, thereby simplifying the fabrication process of the array substrate, thereby reducing the production cost of the array substrate.
  • the method further includes the step of forming a gate. in particular:
  • a pattern of a gate electrode is formed on the base substrate, and then a pattern of the active layer and the source and drain electrodes is formed on the base substrate on which the pattern of the gate is formed. That is, before step S101, first on the substrate base A pattern of gates is formed on the board. In this way, a bottom gate type array substrate can be formed.
  • a pattern of gate electrodes is further formed on the base substrate on which the patterns of the active layer and the source and drain are formed after step S101, thereby forming a top gate type array substrate.
  • the method for fabricating the array substrate provided by the present invention can be applied to the fabrication of the top gate type array substrate, and can also be applied to the fabrication of the bottom gate type array substrate. Therefore, the corresponding production process can be performed according to actual needs, and the practical application is widely used. .
  • the method for fabricating the above array substrate provided by the embodiment of the present invention may be implemented in the following specific manner:
  • a pattern of the active layer 01, the source electrode 021, and the drain electrode 022 is formed by a patterning process on the base substrate on which the pattern of the gate electrode 07 is formed, wherein the source electrode 021 is formed while the source and the source are formed.
  • a via hole process is performed on the drain electrode 022 to form a via hole 09 electrically connected to the first transparent electrode 05, as shown in FIG. 5c.
  • step S102 On the base substrate on which the via hole 09 is formed, a pattern of the passivation layer 04 and the first transparent electrode 05 is formed by one patterning process, and a process of forming a pattern of the first transparent electrode 05 and the passivation layer 04 is described in the present The specific implementation process of step S102 provided by the embodiment of the present invention is not described in detail herein;
  • the base substrate forming the passivation layer 04 and the first transparent electrode 05 is annealed, so that the material of the passivation layer is at least partially filled in the gap in the pattern of the first transparent electrode 05, as shown in FIG. 5d;
  • a pattern of the second transparent electrode 06 is formed by a patterning process, as shown in FIG. 5e.
  • the first transparent electrode 05 is formed by a patterning process using the pattern of the passivation layer 04 formed as a mask, thereby reducing the fabrication process of the array substrate.
  • the number of masks used in the array simplifies the fabrication process of the array substrate, thereby reducing the production cost of the array substrate.
  • an embodiment of the present invention provides a display substrate including an array substrate fabricated by the method for fabricating the array substrate provided by the embodiment of the present invention. Since the principle of solving the problem of the display substrate is similar to that of the array substrate, the implementation of the display substrate can be referred to the implementation of the above array substrate, and the repeated description is omitted.
  • an embodiment of the present invention provides a display device, which can be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Since the principle of solving the problem is similar to that of the display substrate, the implementation of the display device can be referred to the implementation of the above display substrate, and the repeated description is omitted.
  • Embodiments of the present invention provide a method for fabricating an array substrate, a display substrate, and a display device.
  • the method for fabricating the array substrate includes forming a pattern including an active layer and source and drain electrodes on a substrate; a pattern of a transparent electrode and a passivation layer; processing the base substrate on which the passivation layer pattern is formed, so that the material of the passivation layer is at least partially filled in the gap in the first transparent electrode pattern, wherein the patterning process is performed once Forming the pattern of the first transparent electrode and the passivation layer can reduce the number of mask plates used in the fabrication process of the array substrate, and respectively form the patterns of the first transparent electrode and the passivation layer by two patterning processes in the prior art.
  • the pattern of the first transparent electrode and the passivation layer is formed by one patterning process, thereby reducing the number of mask plates used in the process of fabricating the array substrate, thereby simplifying the fabrication process of the array substrate. , thereby reducing the production cost of the array substrate.

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Abstract

一种阵列基板的制作方法、显示基板及显示装置，该阵列基板的制作方法包括在衬底基板上形成包括有源层（01）和源漏电极（02）的图案；通过一次构图工艺形成第一透明电极（05）和钝化层（04）的图案；对形成有钝化层（04）图案的衬底基板进行处理，使钝化层（04）的材料至少部分填充于第一透明电极（05）图案中的缝隙处，其中，通过一次构图工艺形成第一透明电极（05）和钝化层（04）的图案，可以减少阵列基板制作过程中使用的掩膜板数量，可以减少阵列基板制作过程中使用的掩膜板数量，进而简化阵列基板的制作工艺，从而降低阵列基板的生产成本。

Description

一种阵列基板的制作方法、显示基板及显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板的制作方法、显示基板及显示装置。
背景技术
目前，液晶显示技术被广泛应用于电视、手机以及公共信息的显示，用于显示画面的液晶显示面板主要包括驱动显示面板显示画面的阵列基板，和用于实现彩色显示的彩膜基板，以及填充于阵列基板与彩膜基板之间的液晶，其中，阵列基板为多膜层结构，以高开口率高级超维场转换(High Advanced Super Dimension Switch，HADS)模式液晶显示面板为例，其阵列基板的结构主要包括：栅线、有源层、源漏电极、像素电极、钝化层和公共电极；而在制作上述阵列基板时，通常采用树脂工艺制作钝化层，这样可以减小源漏电极与像素电极之间的电容，进而减小源漏电极的RC延迟，从而减小显示面板的功耗。因此，在阵列基板的具体制作过程中，需要对栅极、有源层、源漏极、像素电极、树脂层和公共电极依次进行构图工艺，因此至少需要六次掩模工艺来完成阵列基板的制作，这样的制作方式，成本较高，工艺较复杂。
因此，如何减少阵列基板制作过程中的掩膜次数，进而简化阵列基板的制作工艺，从而降低阵列基板的生产成本，是本领域技术人员亟待解决的问题。
发明内容
本发明实施例提供了一种阵列基板的制作方法、显示基板及显示装置，用以解决现有技术中存在的阵列基板的制作过程中使用的掩膜次数较多，造成阵列基板的制作工艺较复杂的问题。
根据本发明的一个方面，提供了一种阵列基板的制作方法。
根据一个示例性的实施例，所述阵列基板的制作方法包括以下步骤：在衬底基板上形成包括有源层和源漏电极的图案；通过一次构图工艺形成第一透明电极和钝化层的图案；和对形成有钝化层图案的衬底基板进行处理，使钝化层的材料至少部分填充于第一透明电极图案中的缝隙处。
在一种示例性的实施方式中，所述通过一次构图工艺形成第一透明电极和钝化层的图案的步骤包括：依次形成透明导电层膜层和钝化层膜层；对所述钝化层膜层进行构图工艺，形成所述钝化层图案；和以形成的钝化层图案为掩膜板对所述透明导电层膜层进行构图工艺，形成第一透明电极的图案。
在一种示例性的实施方式中，所述对形成有钝化层图案的衬底基板进行处理的步骤包括：对形成有钝化层图案的衬底基板进行退火处理。
在一种示例性的实施方式中，所述钝化层的材料为树脂材料。
在一种示例性的实施方式中，所述对形成有钝化层图案的衬底基板进行退火处理的步骤包括：将形成有钝化层图案的衬底基板在温度为200℃～250℃的环境中进行加热处理。
在一种示例性的实施方式中，所述钝化层图案的厚度为0.5μm～1μm，所述加热处理的时长为20分钟～60分钟。
在一种示例性的实施方式中，上述阵列基板的制作方法还包括：在对形成有钝化层图案的衬底基板进行处理之后，在衬底基板上形成第二透明电极的图案。
在一种示例性的实施方式中，所述在衬底基板上形成有源层和源漏极的图案的步骤包括：在衬底基板上依次形成有源层膜层和源漏电极层膜层；和采用一掩膜板对所述有源层膜层和所述源漏电极层膜层进行构图工艺，形成有源层和源漏极的图案。
在一种示例性的实施方式中，上述阵列基板的制作方法还包括在衬底基板上形成栅极的图案的步骤，其中：在衬底基板上形成有源层和源漏极的图案的步骤之前，在衬底基板上形成栅极的图案；或，在衬底基板上形成包括有源层 和源漏电极的图案的步骤之后，在形成有源层和源漏极的图案的衬底基板上形成栅极的图案。
根据本发明的另一方面，提供了一种显示基板。
根据一个示例性的实施例，所述显示基板包括通过采用上述任一实施例提供的阵列基板的制作方法制作的阵列基板。
根据本发明的又一个方面，还提供了一种显示基板。
根据一个示例性的实施例，所述显示装置包括根据上述实施例提供的显示基板。
本发明实施例的有益效果包括：
本发明实施例提供了一种阵列基板的制作方法、显示基板及显示装置，该阵列基板的制作方法包括在衬底基板上形成包括有源层和源漏电极的图案；通过一次构图工艺形成第一透明电极和钝化层的图案；对形成有钝化层图案的衬底基板进行处理，使钝化层的材料至少部分填充于第一透明电极图案中的缝隙处，其中，通过一次构图工艺形成第一透明电极和钝化层的图案，可以减少阵列基板的制工艺，相较于现有技术中通过两次构图工艺分别形成第一透明电极和钝化层的图案，本发明实施例提供的阵列基板的制作方法，通过一次构图工艺采用一个掩膜板可以形成第一透明电极和钝化层的图案，可以减少阵列基板制作过程中使用的掩膜板数量，进而简化阵列基板的制作工艺，从而降低阵列基板的生产成本。
附图说明
图1为本发明实施例提供的阵列基板的制作方法的流程图；
图2a为本发明实施例提供的沉积透明导电层之后的衬底基板结构示意图；
图2b为本发明实施例提供的形成钝化层图案的衬底基板结构示意图；
图2c为本发明实施例提供的形成第一透明电极图案的衬底基板结构示意图；
图3a为本发明实施例提供的退火处理后的衬底基板结构示意图之一；
图3b为本发明实施例提供的退火处理后的衬底基板结构示意图之二；
图4为本发明实施例提供的形成第二透明电极图案的衬底基板结构示意图；
图5a为本发明实施例提供的形成栅极的衬底基板结构示意图；
图5b为本发明实施例提供的形成源漏电极的衬底基板结构示意图；
图5c为本发明实施例提供的形成过孔的衬底基板结构示意图；
图5d为本发明实施例提供的形成钝化层的衬底基板结构示意图；
图5e为本发明实施例提供的形成第二透明电极的衬底基板结构示意图。
具体实施方式
下面结合附图，对本发明实施例提供的阵列基板的制作方法、显示基板及显示装置的具体实施方式进行详细地说明。
本发明实施例提供了一种阵列基板的制作方法，如图1所示，可以具体采用以下步骤实现：
S101、在衬底基板上形成包括有源层和源漏电极的图案；
S102、通过一次构图工艺形成第一透明电极和钝化层的图案；和
S103、对形成有钝化层图案的衬底基板进行处理，使钝化层的材料至少部分填充于第一透明电极图案中的缝隙处。
在步骤S102中，第一透明电极可以为像素电极，而仅通过一次构图工艺即形成像素电极和钝化层的图案可以简化阵列基板制作工艺。与现有技术中通过两次构图工艺分别形成像素电极和钝化层的图案的工艺相比，本发明实施例提供的上述阵列基板的制作方法能够通过一次构图工艺并且仅采用一个掩膜板就形成像素电极和钝化层的图案二者，从而可以减少阵列基板制作过程中使用的掩膜板数量，进而简化阵列基板的制作工艺，从而降低阵列基板的生产成本。
需要说明的是，本发明实施例提供的上述阵列基板的制作方法中，所采用 构图工艺，包括任何形式的构图方式，例如通过利用光刻胶曝光显影刻蚀的方式，此方式中具体包括的步骤有且不限于：涂覆光刻胶、用掩膜板进行曝光、显影、对需要形成图案的膜层进行刻蚀从而形成相应的图案。对于多次出现的构图工艺，并不限定其包含完全相同的工艺步骤，例如对钝化层的构图工艺可包括涂覆光刻胶、曝光、显影、刻蚀，而对该透明导电层的构图工艺只包括刻蚀工艺即可。
在具体实施时，上述步骤S102可以具体采用以下方式实现：
依次形成透明导电层膜层和钝化层膜层，即在形成有有源层01和源漏电极层02的图案的衬底基板上先形成一层透明导电层膜层03，如图2a所示，然后在形成透明导电层膜层03的衬底基板上再形成一层钝化层膜层；
对钝化层膜层进行构图工艺，形成钝化层的图案，即采用掩膜板对形成钝化层膜层的衬底基板进行构图工艺，形成的具有图案的钝化层04，如图2b所示；
以形成的钝化层的图案为掩膜板对透明导电层膜层03进行构图工艺，形成第一透明电极05的图案，即以具有图案的钝化层04为掩膜板对透明导电层膜层03进行构图工艺，形成第一透明电极05的图案，从而形成具有第一透明电极05和钝化层04的图案的衬底基板，如图2c所示。其中，如上文所述，第一透明电极05可以为像素电极。
具体地，在根据本发明实施例的上述阵列基板的制作方法中，由于采用掩膜板对钝化层进行构图工艺形成钝化层的图案，再以钝化层的图案为掩膜板对透明导电层进行构图工艺形成像素电极的图案，因此在形成像素电极和钝化层的图案的工艺步骤中，只采用了一个掩膜板。与现有技术中采用两个掩膜板通过两次构图工艺分别形成像素电极和钝化层的图案的工艺相比，本发明实施例提供的阵列基板的制作方法，可以减少阵列基板制作过程中使用的掩膜板数量，进而简化阵列基板的制作工艺，从而降低阵列基板的生产成本。
根据一个示例性的实施例，本发明实施例提供的上述阵列基板的制作方法 中，为了使钝化层具有绝缘功能，需要对形成有钝化层图案的衬底基板进行处理，使钝化层的材料至少部分填充于第一透明电极图案中的缝隙处。本发明实施例提供的处理方式为，对形成有钝化层图案的衬底基板进行退火处理，这样经过退火处理后，衬底基板上钝化层的材料至少部分地填充于第一透明电极图案中的缝隙处，如图3a所示。根据一个示例性的实施例，第一透明电极图案中的缝隙处可以完全被钝化层材料填满，进而形成一整层的钝化层，整层化的钝化层可以实现其绝缘的功能。在实际生产过程中为了形成整层化的钝化层而采取的处理方式可以有多种，在此不作限定。
根据另一示例性的实施例，也可以通过对形成有钝化层图案的衬底基板进行处理使得钝化层的材料部分地填充于第一透明电极图案中的缝隙处，如图3b所示。其中，钝化层04的材料并未完全填满第一透明电极05图案中的间隙，而是留有空隙以形成一道过孔通道，这样在后续工艺中形成的第二透明电极06可以为像素电极。该像素电极06可通过钝化层04的材料未填满的过孔通道与漏极相连，并且第一透明电极05作为公共电极，为像素电极提供电压信号，从而驱动像素电极实现图像显示功能。这将在下文中具体说明。
在示例性的实施例中，钝化层的材料可以为树脂材料，也可以为氮化硅、氧化硅等绝缘材料中的一种或多种，在此不作限定。当采用树脂作为钝化层的材料时，既能实现钝化层绝缘的功能，同时又可以减小源漏电极与像素电极之间的电容，从而可以减小源漏电极的RC延迟，进而可以降低阵列基板的功耗。然而，在实际生产过程中，钝化层的材料可以为具有绝缘性质的任一材料，在此不作限定。
根据一个示例性的实施例，上文所述的对形成有钝化层图案的衬底基板进行退火处理可以具体包括：将形成有钝化层图案的衬底基板在温度为200℃～250℃的环境中进行加热处理，通过加热，钝化层材料受热融化，进而流动填充到衬底基板上钝化层图案中没有第一透明电极材料的间隙处。
根据一个示例性的实施例，在对形成钝化层图案的衬底基板进行退火处理 后，钝化层的厚度一般减小到原来的80％左右。由于退火处理受到启动电压的限制，因此钝化层的厚度不可以太厚，一般在1μm以下比较合适。在本发明实施例提供的上述阵列基板的制作方法中，形成的钝化层图案的厚度为0.5μm～1μm，在退火处理过程中进行加热处理的时长为20分钟～60分钟，这样通过对钝化层图案进行退火处理，可使钝化层的材料至少部分填充于第一透明电极图案中的缝隙处。
根据一个示例性的实施例，本发明实施例提供的上述阵列基板的制作方法中，在对形成有钝化层04的图案的衬底基板进行处理之后的衬底基板上，还可以包括形成第二透明电极06的图案，如图4所示。即，在完成退火处理后的衬底基板上沉积透明导电层膜层，通过对透明导电层膜层进行构图工艺，进而形成第二透明电极06。根据一个示例，所形成的第二透明电极06可以为公共电极。由于形成公共电极的过程与现有技术相同，在此不作详述。通过在衬底基板上形成钝化层之后，在钝化层之上形成公共电极，当阵列基板应用于实际产品时，公共电极可以为像素电极传输电压信号，驱动像素电极实现图像显示功能。
根据一个示例性的实施例，在衬底基板上形成有源层和源漏极的图案的步骤可以具体采用如下方式实现：
在衬底基板上依次形成有源层膜层和源漏电极层膜层；和
采用一掩膜板对有源层膜层和源漏电极层膜层进行构图工艺，形成有源层和源漏极的图案。这样，在衬底基板上通过使用一个掩膜板进行一次构图工艺就可以形成有源层和源漏极的图案，从而能够简化阵列基板的制作工艺，进而降低阵列基板的生产成本。
在本发明实施例提供的上述阵列基板的制作方法中，还包括形成栅极的步骤。具体而言：
首先在衬底基板上形成栅极的图案，然后在形成有栅极的图案的衬底基板上形成有源层和源漏极的图案。也就是说，在步骤S101之前，首先在衬底基 板上形成栅极的图案。通过这种方式能够形成底栅型的阵列基板。
或者，在步骤S101之后进一步在形成有源层和源漏极的图案的衬底基板上形成栅极的图案，从而形成顶栅型的阵列基板。
这样，本发明提供的阵列基板的制作方法既可适用于顶栅型的阵列基板制作，也可以适用于底栅型的阵列基板的制作，因此可根据实际需要进行相应的生产工艺，实际应用广泛。
根据一个示例性的实施例，本发明实施例提供的上述阵列基板的制作方法，可以按如下具体方式实现：
1、在衬底基板上通过构图工艺形成的栅极07，形成的栅极07的图案如图5a所示，其中，栅极07与栅线相连；
2、在形成有栅极07的图案的衬底基板上通过一次构图工艺形成有源层01、源极021和漏极022的图案，其中在形成源极021的同时，还形成了与源极021电性相连的数据线08，如图5b所示；
3、在形成有源极021和漏极022的衬底基板上，对漏极022进行过孔工艺，形成了漏极022与第一透明电极05电性相连的过孔09，如图5c所示；
4、在形成过孔09的衬底基板上，通过一次构图工艺形成了钝化层04和第一透明电极05的图案，其中形成第一透明电极05和钝化层04的图案的过程参见本发明实施例提供的步骤S102的具体实施过程，在此不作详述；
5、对形成钝化层04和第一透明电极05的衬底基板进行退火处理，使钝化层的材料至少部分填充于第一透明电极05图案中的缝隙处，如图5d所示；
6、在经过退火处理后的衬底基板上，通过构图工艺形成第二透明电极06的图案，如图5e所示。
具体地，如上文所述，在根据本发明实施例提供的上述制作方法中，以形成的钝化层04的图案为掩膜板通过构图工艺形成第一透明电极05，可以减少阵列基板制作过程中使用的掩膜板数量，进而简化阵列基板的制作工艺，从而降低阵列基板的生产成本。
基于同一发明构思，本发明实施例提供了一种显示基板，其包括采用本发明实施例提供的上述阵列基板的制作方法制作的阵列基板。由于该显示基板解决问题的原理与阵列基板相似，因此该显示基板的实施可以参见上述阵列基板的实施，重复之处不再赘述。
基于同一发明构思，本发明实施例提供了一种显示装置，该显示装置可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置解决问题的原理与显示基板相似，因此该显示装置的实施可以参见上述显示基板的实施，重复之处不再赘述。
本发明实施例提供了一种阵列基板的制作方法、显示基板及显示装置，该阵列基板的制作方法包括在衬底基板上形成包括有源层和源漏电极的图案；通过一次构图工艺形成第一透明电极和钝化层的图案；对形成有钝化层图案的衬底基板进行处理，使钝化层的材料至少部分填充于第一透明电极图案中的缝隙处，其中，通过一次构图工艺形成第一透明电极和钝化层的图案，可以减少阵列基板制作过程中使用的掩膜板数量，相较于现有技术中通过两次构图工艺分别形成第一透明电极和钝化层的图案，本发明实施例提供的阵列基板的制作方法，通过一次构图工艺形成第一透明电极和钝化层的图案，可以减少阵列基板制作过程中使用的掩膜板数量，进而简化阵列基板的制作工艺，从而降低阵列基板的生产成本。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (11)

  1. 一种阵列基板的制作方法，其特征在于，包括以下步骤：
    在衬底基板上形成包括有源层和源漏电极的图案；
    通过一次构图工艺形成第一透明电极和钝化层的图案；和
    对形成有钝化层图案的衬底基板进行处理，使钝化层的材料至少部分填充于所述第一透明电极图案中的缝隙处。
  2. 如权利要求1所述的方法，其特征在于，所述通过一次构图工艺形成第一透明电极和钝化层的图案的步骤包括：
    依次形成透明导电层膜层和钝化层膜层；
    对所述钝化层膜层进行构图工艺，形成所述钝化层的图案；和
    以形成的钝化层图案为掩膜板对所述透明导电层膜层进行构图工艺，形成第一透明电极的图案。
  3. 如权利要求1所述的方法，其特征在于，所述对形成有钝化层图案的衬底基板进行处理的步骤包括：
    对形成有钝化层图案的衬底基板进行退火处理。
  4. 如权利要求3所述的方法，其特征在于，所述钝化层的材料为树脂材料。
  5. 如权利要求4所述的方法，其特征在于，所述对形成有钝化层图案的衬底基板进行退火处理的步骤包括：
    将形成有钝化层图案的衬底基板在温度为200℃～250℃的环境中进行加热处理。
  6. 如权利要求5所述的方法，其特征在于，所述钝化层图案的厚度为0.5μm～1μm，所述加热处理的时长为20分钟～60分钟。
  7. 如权利要求1-6任一项所述的方法，其特征在于，还包括：
    在对形成有钝化层图案的衬底基板进行处理之后，在衬底基板上形成第二 透明电极的图案。
  8. 如权利要求1-6任一项所述的方法，其特征在于，所述在衬底基板上形成有源层和源漏极的图案的步骤包括：
    在衬底基板上依次形成有源层膜层和源漏电极层膜层；和
    采用一掩膜板对所述有源层膜层和所述源漏电极层膜层进行构图工艺，形成有源层和源漏极的图案。
  9. 如权利要求8所述的方法，还包括在衬底基板上形成栅极的图案的步骤，其中：
    在衬底基板上形成有源层和源漏极的图案的步骤之前，在衬底基板上形成栅极的图案；或，
    在衬底基板上形成包括有源层和源漏电极的图案的步骤之后，在形成有源层和源漏极的图案的衬底基板上形成栅极的图案。
  10. 一种显示基板，其特征在于，包括采用权利要求1-9中任一项所述的方法制作的阵列基板。
  11. 一种显示装置，其特征在于，包括如权利要求10所述的显示基板。
PCT/CN2015/085294 2015-02-05 2015-07-28 一种阵列基板的制作方法、显示基板及显示装置 WO2016123933A1 (zh)

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