WO2016110128A1 - 高压p型横向双扩散金属氧化物半导体场效应管 - Google Patents

高压p型横向双扩散金属氧化物半导体场效应管 Download PDF

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WO2016110128A1
WO2016110128A1 PCT/CN2015/089807 CN2015089807W WO2016110128A1 WO 2016110128 A1 WO2016110128 A1 WO 2016110128A1 CN 2015089807 W CN2015089807 W CN 2015089807W WO 2016110128 A1 WO2016110128 A1 WO 2016110128A1
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Prior art keywords
field effect
oxide semiconductor
metal oxide
semiconductor field
effect transistor
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PCT/CN2015/089807
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English (en)
French (fr)
Inventor
张广胜
张森
卞鹏
胡小龙
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无锡华润上华半导体有限公司
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Application filed by 无锡华润上华半导体有限公司 filed Critical 无锡华润上华半导体有限公司
Priority to US15/541,661 priority Critical patent/US20180190815A1/en
Priority to EP15876629.5A priority patent/EP3242329A4/en
Priority to KR1020177021628A priority patent/KR101951825B1/ko
Priority to JP2017535885A priority patent/JP6401394B2/ja
Publication of WO2016110128A1 publication Critical patent/WO2016110128A1/zh

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Definitions

  • the present invention relates to the field of semiconductor fabrication technology, and in particular to a high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor.
  • P-type lateral double-diffused metal oxide semiconductor field effect transistor P type Lateral Double-diffused Metal Oxide Semiconductor field effect The transistor (PLDMOS) structure needs to have a low-doping P-type drift region of a certain length to achieve high voltage withstand voltage. Therefore, in the high-voltage NLDMOS (N-type lateral double-diffused metal oxide semiconductor field effect transistor) and PLDMOS high-voltage integration process, it needs to be increased once. Low-doping P-type lithography increases process complexity and process cost.
  • the gate of the P-type metal oxide semiconductor field effect transistor serves as a gate of the high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor;
  • the drain of the P-type metal oxide semiconductor field effect transistor a drain of the high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor;
  • a source of the N-type lateral double-diffused metal oxide semiconductor field effect transistor as the high-voltage P-type lateral double-diffused metal oxide semiconductor The source of the FET.
  • the high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor is provided with a P-type metal oxidizing field effect transistor at the drain of the N-type lateral double-diffused metal oxide semiconductor field effect transistor, thereby ensuring that the device possesses when turned on.
  • the performance of the P-type metal oxide semiconductor field effect transistor is withstand voltage through the N-type lateral double-diffused metal oxide semiconductor field effect transistor during turn-off, thereby achieving the resistance of the high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor. Pressure performance.
  • the high-voltage P-type lateral double-diffused metal-oxide-semiconductor field effect transistor does not need to have a low-doped P-type drift region inside thereof to achieve withstand voltage, so there is no need to increase the lithography level and the number of injections in the integration process, and the preparation process is simple and cost-effective. Lower.
  • FIG. 1 is a schematic structural view of a high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor in an embodiment
  • FIG. 2 is an equivalent structure of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor of FIG.
  • reference numerals N and P assigned to layers or regions mean that the layers or regions respectively include a large number of electrons or holes. Further, the reference marks + and - assigned to N or P indicate that the concentration of the dopant is higher or lower than the concentration in the layer which is not thus assigned to the mark. In the following description of the preferred embodiments and the drawings, like components are assigned like reference numerals and their redundant description is omitted.
  • a high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor comprising: a substrate, an N-type lateral double-diffused metal oxide semiconductor field effect transistor (NLDMOS transistor) formed on the substrate, and A P-type metal oxide semiconductor field effect transistor (PMOS transistor) formed on a drain of the N-type lateral double-diffused metal oxide semiconductor field effect transistor.
  • the N-type lateral double-diffused metal oxide semiconductor field effect transistor and the P-type metal oxide semiconductor field effect transistor can all adopt the field effect tube structure commonly used in the art, and are not limited to a specific field effect tube structure.
  • the gate of the P-type MOSFET is used as the gate of the high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor; the drain of the P-type MOSFET is used as the high voltage The drain of the P-type lateral double-diffused metal oxide semiconductor field effect transistor; the source of the N-type lateral double-diffused metal oxide semiconductor field effect transistor serves as the source of the high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor.
  • the high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor is provided with a P-type metal oxidizing field effect transistor at the drain of the N-type lateral double-diffused metal oxide semiconductor field effect transistor, thereby ensuring that the device possesses when turned on.
  • the performance of the P-type metal oxide semiconductor field effect transistor is withstand voltage through the N-type lateral double-diffused metal oxide semiconductor field effect transistor during turn-off, thereby achieving the resistance of the high-voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor. Pressure performance.
  • the high-voltage P-type lateral double-diffused metal-oxide-semiconductor field effect transistor does not need to have a low-doped P-type drift region inside thereof to achieve withstand voltage, so there is no need to increase the lithography level and the number of injections in the integration process, and the preparation process is simple and cost-effective. Lower.
  • a high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor 10 includes a substrate 100, and an N-type lateral double-diffused metal oxide semiconductor field effect transistor (NLDMOS) on the substrate 100. And a portion of the P-type metal oxide semiconductor field effect transistor (PMOS transistor) 300 located at the drain of the N-type lateral double diffusion book oxide semiconductor field effect transistor 200.
  • high voltage PLDMOS transistor high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor
  • NLDMOS N-type lateral double-diffused metal oxide semiconductor field effect transistor
  • the substrate 100 is a P-type substrate.
  • the resistivity of the substrate 100 is usually large for the withstand voltage of the real device.
  • the substrate 100 has a resistivity of 50 ⁇ •cm to 95 ⁇ •cm. It can be understood that in other embodiments, the resistivity of the substrate 100 can be determined according to the specific requirements of the device.
  • the NLDMOS transistor 200 portion includes: a P well 202 on the substrate 100 and a first N well 204; a first source extraction region 206 on the P well 202; a field oxide layer 208 on the first N well 204;
  • the first well oxide layer 210 extends from the surface of the P well 202 to the surface of the first N well 204; the first polysilicon gate 212 is located on the surface of the first gate oxide layer 210 and the field oxide layer 208.
  • the first source lead-out area 206 includes a first N-type lead-out area and a first P-type lead-out area, and is connected by the metal electrode 20 to be taken as a source of the NLDMOS transistor 200, and also serves as a source of the high-voltage PLDMOS tube 10.
  • the first polysilicon gate 212 is taken out through the metal electrode 20 to serve as the gate of the NLDMOS transistor 200.
  • P-well 202 is used to provide a device conductive trench for the NLDMOS transistor 200 portion to control the switching of the device through its gate.
  • the doping concentration of the P well 202 is higher than the doping concentration of the first N well 204 to further improve the withstand voltage performance of the PLDMOS transistor 10.
  • the doping concentration of the P well 202 may also be equal to or lower than the doping concentration of the first N well 204, and it is only necessary to ensure that the doping concentration of the P well 202 is within a certain reasonable range.
  • the doping concentration of the P well 202 is 1 ⁇ 10 12 cm -3 to 1 ⁇ 10 13 cm -3 .
  • the gate of the NLDMOS transistor 200 is set to a high level.
  • the first N-well 204 serves as a withstand voltage region of the PLDMOS transistor, and when the PLDMOS transistor 10 is turned off, it can provide a required withstand voltage for the device.
  • the length of the first N-well 204 can be set according to the withstand voltage requirement of the PLDMOS transistor 10.
  • the first P-type lead-out area on the first source lead-out area 206 is a P+ lead-out area, and the first N-type lead-out area is an N+ lead-out area.
  • the PMOS transistor 300 portion includes: a second N-well 302 on the substrate 100; a drain lead-out region 304 on the second N-well 302 and a second source lead-out region 306; on the surface of the second N-well 302 and located in the drain A second gate oxide layer 308 between the pole extraction region 304 and the second source lead-out region 306; and a second polysilicon gate 310 on the surface of the second gate oxide layer 308.
  • the second drain lead-out region 304 is taken out as the drain of the PMOS transistor 300 through the metal electrode 20 and also serves as the drain D of the PLDMOS transistor 10.
  • the second polysilicon gate 310 is taken out as the gate of the PMOS transistor 300 through the metal electrode 20, and also serves as the gate G of the PLDMOS transistor 10.
  • the second source lead-out region 306 includes a second P-type lead-out region and a second N-type lead-out region, and is connected as a source of the PMOS transistor 300 through the metal electrode 20.
  • the second N well 302 is a channel region of the PMOS transistor 300, and controls the turn-off and turn-on of the entire PLDMOS transistor 10 through the gate of the PMOS transistor 300.
  • the doping concentration of the second N well 302 is higher than the doping concentration of the first N well 204 and is in contact with the first N well 204 to improve the conductivity of the channel.
  • the doping concentration of the second N well 302 is 1 ⁇ 10 12 cm -3 to 1 ⁇ 10 13 cm -3 .
  • the increase in the well depth of the second N-well 302 increases the overlapping area of the gate of the PMOS transistor 10 with the source lead-out region and the drain lead-out region, thereby causing an increase in parasitic capacitance and affecting the performance of the entire PLDMOS transistor 10. Therefore, the well depth of the second N-well 302 should not be set too deep. In the present embodiment, the well depth of the second N-well 302 is smaller than the well depth of the first N-well 204 to reduce parasitic capacitance.
  • the well depth of the second N-well 302 may also be equal to or greater than the well depth of the first N-well 204. In the present embodiment, the well depth of the second N-well 302 is 4 micrometers to 6 micrometers.
  • the drain lead-out area 304 is a P+ lead-out area
  • the second P-type lead-out area in the second source lead-out area 306 is a P+ lead-out area
  • the second N-type lead-out area is an N+ lead-out area.
  • Field oxide layer 208 extends from the surface of first N-well 204 to the surface of second N-well 302.
  • FIG. 3 is an equivalent structural view of a high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor in the embodiment shown in FIG. 2.
  • the gate of the NLDMOS transistor 200 is set to a high level. It can be seen from the connection relationship in FIG. 3 that the switching characteristic of NLDMOS_G is the same as that of the PMOS (the same on and off), thereby ensuring that only the gate G of the PMOS transistor 300 is the control terminal.
  • PMOS_D is the drain of PLDMOS transistor 10, which is an ultra-high voltage when the device is operating;
  • NLDMOS_S is the source of PLDMOS transistor 10.
  • the device when the gate G of the high voltage PLDMOS transistor 10 is at a high potential, the device is turned off, and the device is subjected to a withstand voltage through the longer first N well 204 as a drift region; when the gate of the high voltage PLDMOS transistor 10 is at a low potential, The device is turned on, and the device current flows through the second N-well 302 and flows to the first N-well 204 region to form a current path.
  • the high-voltage PLDMOS transistor 10 is provided with a PMOS transistor 300 at the drain of the NLDMOS transistor 200, so that the device can have the performance of the PMOS transistor 200 when it is turned on, and the withstand voltage is passed through the NLDMOS transistor 200 during the turn-off, thereby realizing the high-voltage PLDMOS transistor. 10 withstand voltage performance. Also, the fabrication of the PMOS transistor 300 is performed in synchronization with the preparation of the NLDMOS transistor 200 without adding additional process steps.
  • the high-voltage PLDMOS transistor 10 described above does not need to have a low-doping P-type drift region inside thereof to achieve withstand voltage, so there is no need to increase the lithography level and the number of injections in the integration process, and the preparation process is simple and the cost is low.

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Abstract

一种高压P型横向双扩散金属氧化物半导体场效应管（10），包括衬底（100），还包括形成于衬底（100）上的N型横向双扩散金属氧化物半导体场效应管（200），以及形成于N型横向双扩散金属氧化物半导体场效应管（200）的漏极的P型金属氧化物半导体场效应管（300）；P型金属氧化物半导体场效应管（300）的栅极作为高压P型横向双扩散金属氧化物半导体场效应管（10）的栅极；P型金属氧化物半导体场效应管（300）的漏极作为高压P型横向双扩散金属氧化物半导体场效应管（10）的漏极；N型横向双扩散金属氧化物半导体场效应管（200）的源极作为高压P型横向双扩散金属氧化物半导体场效应管（10）的源极。

Description

高压P型横向双扩散金属氧化物半导体场效应管
【技术领域】
本发明涉及半导体制备技术领域，特别是涉及一种高压P型横向双扩散金属氧化物半导体场效应管。
【背景技术】
传统的P型横向双扩散金属氧化物半导体场效应管（P type Lateral Double-diffused Metal Oxide Semiconductor field effect transistor，PLDMOS）结构需要以一定长度的低掺杂P型漂移区来实现耐高压，因此在高压NLDMOS（N型横向双扩散金属氧化物半导体场效应管）与PLDMOS高压集成过程中，需要增加一次低掺杂P型区光刻，从而增加了工艺复杂性与工艺成本。
【发明内容】
基于此，有必要提供一种工艺简单且成本较低的可实现器件的耐高压性能的高压P型横向双扩散金属氧化物半导体场效应管。
一种高压P型横向双扩散金属氧化物半导体场效应管，包括：
衬底；
形成于所述衬底上的N型横向双扩散金属氧化物半导体场效应管；以及
形成于所述N型横向双扩散金属氧化物半导体场效应管的漏极的P型金属氧化物半导体场效应；
其中，所述P型金属氧化物半导体场效应管的栅极作为所述高压P型横向双扩散金属氧化物半导体场效应管的栅极；所述P型金属氧化物半导体场效应管的漏极作为所述高压P型横向双扩散金属氧化物半导体场效应管的漏极；所述N型横向双扩散金属氧化物半导体场效应管的源极作为所述高压P型横向双扩散金属氧化物半导体场效应管的源极。
上述高压P型横向双扩散金属氧化物半导体场效应管通过在N型横向双扩散金属氧化物半导体场效应管的漏极设置有P型金属氧化性场效应管，能够保证器件在导通时拥有P型金属氧化物半导体场效应管的性能，在关断时通过N型横向双扩散金属氧化物半导体场效应管进行耐压，从而实现高压P型横向双扩散金属氧化物半导体场效应管的耐压性能。上述高压P型横向双扩散金属氧化物半导体场效应管无需在其内部设置低掺杂P型漂移区来实现耐压，因此在集成过程中无需增加光刻层次和注入次数，制备工艺简单且成本较低。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例中的高压P型横向双扩散金属氧化物半导体场效应管的结构示意图；
图2为图1中的高压P型横向双扩散金属氧化物半导体场效应管的等效结构。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
在本说明书和附图中，分配给层或区域的参考标记N和P表示这些层或区域分别包括大量电子或空穴。进一步地，分配给N或P的参考标记＋和－表示掺杂剂的浓度高于或低于没有这样分配到标记的层中的浓度。在下文的优选实施例的描述和附图中，类似的组件分配有类似的参考标记且该处省略其冗余说明。
一种高压P型横向双扩散金属氧化物半导体场效应管(PLDMOS管)，包括：衬底、形成于所述衬底上的N型横向双扩散金属氧化物半导体场效应管（NLDMOS管）以及形成于所述N型横向双扩散金属氧化物半导体场效应管的漏极的P型金属氧化物半导体场效应管（PMOS管）。其中，N型横向双扩散金属氧化物半导体场效应管和P型金属氧化物半导体场效应管均可以采用本领域常用的场效应管结构，并不限于某一具体的场效应管结构。在本实施例中，P型金属氧化物半导体场效应管的栅极作为高压P型横向双扩散金属氧化物半导体场效应管的栅极；P型金属氧化物半导体场效应管的漏极作为高压P型横向双扩散金属氧化物半导体场效应管的漏极；N型横向双扩散金属氧化物半导体场效应管的源极作为高压P型横向双扩散金属氧化物半导体场效应管的源极。
上述高压P型横向双扩散金属氧化物半导体场效应管通过在N型横向双扩散金属氧化物半导体场效应管的漏极设置有P型金属氧化性场效应管，能够保证器件在导通时拥有P型金属氧化物半导体场效应管的性能，在关断时通过N型横向双扩散金属氧化物半导体场效应管进行耐压，从而实现高压P型横向双扩散金属氧化物半导体场效应管的耐压性能。上述高压P型横向双扩散金属氧化物半导体场效应管无需在其内部设置低掺杂P型漂移区来实现耐压，因此在集成过程中无需增加光刻层次和注入次数，制备工艺简单且成本较低。
下面结合一具体实施例来对本实施例中的高压P型横向双扩散金属氧化物半导体场效应管做进一步详细说明。
图1为一实施例中的高压P型横向双扩散金属氧化物半导体场效应管10的结构示意图。如图1所示，高压P型横向双扩散金属氧化物半导体场效应管（高压PLDMOS管）10包括衬底100、位于衬底100上的N型横向双扩散金属氧化物半导体场效应管（NLDMOS管）200部分以及位于N型横向双扩散书氧化物半导体场效应管200的漏极的P型金属氧化物半导体场效应管（PMOS管）300部分。
在本实施例中，衬底100为P型衬底。为了实器件的耐压，衬底100的电阻率通常较大。在本实施例中，衬底100的电阻率为50Ω•cm～95Ω•cm。可以理解，在其他的实施例中，衬底100的电阻率大小可以根据器件的具体要求来进行确定。
NLDMOS管200部分包括：位于衬底100上的P阱202以及第一N阱204；位于P阱202上的第一源极引出区206；位于第一N阱204上的场氧化层208；从P阱202表面延伸至第一N阱204表面的第一栅氧化层210；位于第一栅氧化层210以及场氧化层208表面的第一多晶硅栅212。其中，第一源极引出区206包括第一N型引出区和第一P型引出区，并通过金属电极20连接后引出作为NLDMOS管200的源极，同时也作为高压PLDMOS管10的源极S。第一多晶硅栅212通过金属电极20引出后作为NLDMOS管200的栅极。P阱202用于为NLDMOS管200部分提供器件导电沟槽，从而通过其栅极来控制器件的开关。在本实施例中，P阱202的掺杂浓度高于第一N阱204的掺杂浓度，以进一步提高PLDMOS管10的耐压性能。在其他的实施例中，P阱202的掺杂浓度也可以等于或者低于第一N阱204的掺杂浓度，只需保证P阱202的掺杂浓度在一定的合理范围内即可。在本实施例中，P阱202的掺杂浓度为1×1012㎝-3～1×1013㎝-3。在PLDMOS管10中，为保证作为耐压部分的NLDMOS管200保持常开，故将NLDMOS管200的栅极设为高电平。第一N阱204作为PLDMOS管的耐压区域，在PLDMOS管10关断时，能够为器件提供需要的耐压。第一N阱204的长度可以根据PLDMOS管10的耐压要求进行设定。第一源极引出区206上的第一P型引出区为P+引出区，而第一N型引出区则为N+引出区。
PMOS管300部分包括：位于衬底100上的第二N阱302；位于第二N阱302上的漏极引出区304以及第二源极引出区306；位于第二N阱302表面且位于漏极引出区304和第二源极引出区306之间的第二栅氧化层308；位于第二栅氧化层308表面的第二多晶硅栅310。其中，第二漏极引出区304通过金属电极20引出作为PMOS管300的漏极，同时也作为PLDMOS管10的漏极D。第二多晶硅栅310通过金属电极20引出作为PMOS管300的栅极，同时也作为PLDMOS管10的栅极G。第二源极引出区306包括第二P型引出区和第二N型引出区，并通过金属电极20连接后作为PMOS管300的源极。第二N阱302为PMOS管300的沟道区域，并通过PMOS管300的栅极来控制整个PLDMOS管10的关断和开启。在本实施例中，第二N阱302的掺杂浓度高于第一N阱204的掺杂浓度且与第一N阱204相互接触，以提高沟道的导电性能。第二N阱302的掺杂浓度为1×1012㎝-3～1×1013㎝-3。第二N阱302的阱深增加，会使得PMOS管10的栅极与源极引出区、漏极引出区的重叠面积增大，从而导致寄生电容增大，影响整个PLDMOS管10的性能。因此，第二N阱302的阱深不宜设置过深。在本实施例中，第二N阱302的阱深小于第一N阱204的阱深，以减小寄生电容。在其他的实施例中，第二N阱302的阱深也可以等于或者大于第一N阱204的阱深。在本实施例中，第二N阱302的阱深为4微米～6微米。漏极引出区304为P+引出区，而第二源极引出区306中的第二P型引出区为P+引出区，第二N型引出区则为N+引出区。场氧化层208从第一N阱204表面延伸至第二N阱302表面。
图3为图2所示实施例中的高压P型横向双扩散金属氧化物半导体场效应管的等效结构图。为保证NLDMOS管200保持常开，将NLDMOS管200的栅极设为高电平。从图3中的连接关系可以看出，NLDMOS_G的开关特性与PMOS一致（同开同关），从而保证器件只有PMOS管300的栅极G为控制端。PMOS_D为PLDMOS管10的漏极，在器件工作时为超高电压；NLDMOS_S为PLDMOS管10的源极。具体地，当高压PLDMOS管10的栅极G为高电位时，器件关断，器件通过较长的第一N阱204作为漂移区进行耐压；当高压PLDMOS管10的栅极为低电位时，器件导通，器件电流通过第二N阱302后流向第一N阱204区域形成电流通路。
上述高压PLDMOS管10通过在NLDMOS管200的漏极设置有PMOS管300，能够保证器件在导通时拥有PMOS管200的性能，在关断时通过NLDMOS管200进行耐压，从而实现高压PLDMOS管10的耐压性能。并且，PMOS管300的制备与NLDMOS管200的制备同步进行，不会增加额外的工艺步骤。上述高压PLDMOS管10无需在其内部设置低掺杂P型漂移区来实现耐压，因此无需在集成过程中增加光刻层次和注入次数，制备工艺简单且成本较低。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，包括：
    衬底；
    N型横向双扩散金属氧化物半导体场效应管，形成于所述衬底上；以及
    P型金属氧化物半导体场效应，形成于所述N型横向双扩散金属氧化物半导体场效应管的漏极；
    其中，所述P型金属氧化物半导体场效应管的栅极作为所述高压P型横向双扩散金属氧化物半导体场效应管的栅极；所述P型金属氧化物半导体场效应管的漏极作为所述高压P型横向双扩散金属氧化物半导体场效应管的漏极；所述N型横向双扩散金属氧化物半导体场效应管的源极作为所述高压P型横向双扩散金属氧化物半导体场效应管的源极。
  2. 根据权利要求1所述的高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，所述衬底为P型衬底。
  3. 根据权利要求2所述的高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，所述衬底的电阻率在50Ω•cm～95Ω•cm。
  4. 根据权利要求1所述的高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，所述N型横向双扩散金属氧化物半导体场效应管包括：位于所述衬底上的P阱、第一N阱；位于所述P阱上的第一源极引出区，所述第一源极引出区通过金属电极出作为所述N型横向双扩散金属氧化物半导体场效应管的源极；位于所述第一N阱上的场氧化层；从所述P阱表面延伸至所述第一N阱表面的第一栅氧化层；位于所述第一栅氧化层和所述场氧化层的表面的第一多晶硅栅，所述第一多晶硅栅通过金属电极引出后作为所述N型横向双扩散金属氧化物半导体场效应管的栅极。
  5. 根据权利要求4所述的高压P型横向双扩撒金属氧化物半导体场效应管，其特征在于，所述P阱的掺杂浓度为1×1012㎝-3～1×1013㎝-3。
  6. 根据权利要求4所述的高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，所述N型横向双扩散金属氧化物半导体场效应管的栅极为高电平。
  7. 根据权利要求4所述的高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，所述第一源极引出区包括第一P型引出区和第一N型引出区；所述第一P型引出区和所述第一N型引出区通过金属电极进行连接。
  8. 根据权利要求4所述的高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，所述P阱的掺杂浓度高于所述第一N阱的掺杂浓度。
  9. 根据权利要求4所述的高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，所述P型金属氧化物半导体场效应管包括：位于所述衬底上的第二N阱，所述第二N阱与所述第一N阱相互接触；位于所述第二N阱上的漏极引出区以及第二源极引出区；所述漏极引出区通过金属电极引出作为所述P型金属氧化物半导体场效应管的漏极；所述第二源极引出区通过金属电极引出后作为所述P型金属氧化物半导体场效应管的源极；在所述第二N阱的表面且位于所述第二源极引出区和所述漏极引出区之间形成的第二栅氧化层；在所述第二栅氧化层上形成的第二多晶硅栅；所述第二多晶硅栅通过金属电极引出作为所述P型金属氧化物半导体场效应管的栅极。
  10. 根据权利要求9所述的高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，所述第二源极引出区包括第二P型引出区和第二N型引出区，所述第二P型引出区和所述第二N型引出区通过金属电极连接。
  11. 根据权利要求9所述的高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，所述场氧化层从所述第一N阱的表面延伸至所述第二N阱的表面。
  12. 根据权利要求9所述的高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，所述第二N阱的掺杂浓度高于所述第一N阱的掺杂浓度。
  13. 根据权利要求9所述的高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，所述第二N阱的掺杂浓度为1×1012㎝-3～1×1013㎝-3。
  14. 根据权利要求9所述的高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，所述第二N阱的阱深小于或等于所述第一N阱的阱深。
  15. 根据权利要求9所述的高压P型横向双扩散金属氧化物半导体场效应管，其特征在于，所述第二N阱的阱深为4微米～6微米。
PCT/CN2015/089807 2015-01-05 2015-09-16 高压p型横向双扩散金属氧化物半导体场效应管 WO2016110128A1 (zh)

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