WO2016106925A1 - 与非门锁存的驱动电路以及与非门锁存的移位寄存器 - Google Patents

与非门锁存的驱动电路以及与非门锁存的移位寄存器 Download PDF

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Publication number
WO2016106925A1
WO2016106925A1 PCT/CN2015/071710 CN2015071710W WO2016106925A1 WO 2016106925 A1 WO2016106925 A1 WO 2016106925A1 CN 2015071710 W CN2015071710 W CN 2015071710W WO 2016106925 A1 WO2016106925 A1 WO 2016106925A1
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WIPO (PCT)
Prior art keywords
nand gate
circuit
inverter
input end
clock
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Ceased
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PCT/CN2015/071710
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English (en)
French (fr)
Inventor
郝思坤
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to KR1020177021419A priority Critical patent/KR102057818B1/ko
Priority to DE112015005383.2T priority patent/DE112015005383B4/de
Priority to JP2017534661A priority patent/JP6434155B2/ja
Priority to GB1706902.2A priority patent/GB2546924B/en
Priority to RU2017125770A priority patent/RU2676019C1/ru
Priority to US14/433,661 priority patent/US9721513B2/en
Publication of WO2016106925A1 publication Critical patent/WO2016106925A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a NAND gate latch driving circuit and a NAND gate latch shift register.
  • GOA Gate Driver On The Array circuit
  • the GOA circuit has two basic functions: the first is to input the gate drive pulse, drive the gate line in the panel, and open the TFT in the display area (Thin Film Transistor, thin film field effect transistor), the pixel is charged by the gate line; the second is shift register, when the output of the nth gate drive pulse is completed, n+1 gate drive pulses can be performed by clock control Output, and pass it on.
  • the GOA circuit includes a pull-up circuit and a pull-up control (Pull-up control) Circuit), pull-down circuit, pull-down control Circuit) and the rising circuit responsible for the potential rise (Boost) Circuit).
  • the pull-up circuit is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control circuit is responsible for controlling the opening of the pull-up circuit, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down circuit is responsible for quickly pulling the scan signal low to low after the output of the scan signal, that is, the potential of the gate of the thin film transistor is pulled low to a low potential;
  • the pull-down hold circuit is responsible for the signal of the scan signal and the pull-up circuit (commonly called For Q point) Staying in the off state (ie, the set negative potential), there are usually two pull-down holding circuits that alternate.
  • the rising circuit is responsible for the secondary rise of the Q point potential, thus ensuring the normal output of the G(N) of the pull-up circuit.
  • LTPS Low Temperature Poly-silicon, low-temperature polysilicon process
  • CMOS Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor
  • the LTPS process has the advantages of low power consumption, high electron mobility, and wide noise margin. Therefore, it is gradually used by panel manufacturers, so it is necessary to develop a GOA circuit corresponding to the CMOS LTPS process.
  • Embodiments of the present invention provide a NAND gate latched driving circuit and a NAND gate latched shift register for use in a CMOS process with low power consumption and wide noise margin.
  • the invention provides a NAND gate latching driving circuit, comprising a plurality of cascaded NAND gate latching shift register circuits, each shift register circuit comprising a clock control transmission circuit and a NAND gate latch a circuit, wherein the clock control transmission circuit is triggered by the first clock pulse of the clock signal to transmit the driving pulse of the previous stage to the NAND gate latch circuit, and is latched by the NAND gate latch circuit, and the NAND gate latch The circuit is further triggered by a second clock pulse subsequent to the first clock signal to output a driving pulse; the clock control transmission circuit and the NAND gate latch circuit are respectively triggered by a rising edge; wherein the NAND gate latch circuit includes at least a first a phase detector, a first NAND gate, a second NAND gate, and a third NAND gate, wherein the input end of the first inverter is connected to the output end of the clock control transmission circuit, and the first input end of the first NAND gate is connected The output end of the first inverter, the second input end of the first N
  • the clock control transmission circuit inverts the driving pulse in the process of transmitting the driving pulse.
  • the NAND gate latch circuit further includes a multi-stage inverter circuit connected to the output terminal of the third NAND gate.
  • the multi-stage inverter circuit includes a plurality of second inverters arranged in series.
  • the number of second inverters is three.
  • the clock signals of the adjacent shift register circuits are mutually inverted.
  • the invention also provides a NAND gate latching driving circuit, comprising a plurality of cascaded NAND gate latching shift register circuits, each shift register circuit comprising a clock control transmission circuit and a NAND gate lock a memory circuit, wherein the clock control transmission circuit is triggered by the first clock pulse of the clock signal to transmit the driving pulse of the previous stage to the NAND gate latch circuit, and is latched by the NAND gate latch circuit, and the NAND gate lock
  • the memory circuit is further triggered by a second clock pulse subsequent to the first clock signal to output a drive pulse.
  • the clock control transmission circuit and the NAND gate latch circuit are respectively triggered by rising edges.
  • the NAND gate latch circuit includes at least a first inverter, a first NAND gate, a second NAND gate, and a third NAND gate, wherein an input end of the first inverter is connected to an output of the clock control transmission circuit.
  • the first input end of the first NAND gate is connected to the output end of the first inverter
  • the second input end of the first NAND gate is connected to the output end of the second NAND gate
  • the first end of the second NAND gate The input end is connected to the input end of the first inverter
  • the second input end of the second NAND gate is connected to the output end of the first NAND gate
  • the output end of the second NAND gate is further connected to the first part of the third non-gate
  • the second input of the third NAND gate receives the clock signal.
  • the clock control transmission circuit inverts the driving pulse in the process of transmitting the driving pulse.
  • the NAND gate latch circuit further includes a multi-stage inverter circuit connected to the output terminal of the third NAND gate.
  • the multi-stage inverter circuit includes a plurality of second inverters arranged in series.
  • the number of second inverters is three.
  • the clock signals of the adjacent shift register circuits are mutually inverted.
  • the invention also provides a NAND gate latching shift register, comprising a clock control transmission circuit and an NAND gate latch circuit, the NAND gate latch circuit comprising at least a first inverter, a first NAND gate, a second NAND gate and a third NAND gate, wherein an input end of the first inverter is connected to an output end of the clock control transmission circuit, and a first input end of the first NAND gate is connected to an output end of the first inverter, a second input end of the first NAND gate is connected to the output end of the second NAND gate, a first input end of the second NAND gate is connected between the input end of the first inverter, and a second second NAND gate The input end is connected to the output end of the first NAND gate, and the output end of the second NAND gate is further connected to the first input end of the third NAND gate.
  • the NAND gate latch circuit further includes a multi-stage inverter circuit connected to the output terminal of the third NAND gate.
  • the beneficial effect of the present invention is that the NAND latched driving circuit of the present invention is triggered by the first clock pulse of the clock signal through the clock control transmission circuit to transmit the driving pulse of the previous stage to the NAND gate lock.
  • the circuit is latched by the NAND gate latch circuit, and the NAND gate latch circuit is further triggered by the second clock pulse subsequent to the first clock signal to output a drive pulse, which can be applied to a CMOS process and has low power consumption.
  • the noise margin is wide.
  • FIG. 1 is a schematic structural diagram of a NAND gate latch driving circuit according to an embodiment of the present invention
  • Figure 2 is a circuit diagram of the shift register of Figure 1;
  • Figure 3 is a circuit diagram of a shift register of a second embodiment of the present invention.
  • FIG. 4 is a theoretical timing diagram of a NAND gate latch driving circuit according to an embodiment of the present invention.
  • Fig. 5 is a timing chart showing the simulation of the NAND gate latch driving circuit of the embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a NAND gate latch driving circuit according to an embodiment of the present invention.
  • the driving circuit 1 disclosed in this embodiment includes a plurality of NAND gate latch shift register circuits 10 arranged in cascade, each shift register circuit 10 including a clock control transmission circuit 11 and NAND
  • the NAND latch circuit 12 is further triggered by a second clock pulse subsequent to the first clock signal to output a drive pulse.
  • the clock control transmission circuit 11 inverts the drive pulse during the transmission of the drive pulse.
  • the clock control transmission circuit 11 and the NAND gate latch circuit 12 are respectively triggered by rising edges.
  • the embodiment of the present invention controls the signal transmission of the upper and lower stages through the clock control transmission circuit 11, and the signal is latched by the NAND gate latch circuit 12, which can be applied to the CMOS process, and has low power consumption and wide noise tolerance.
  • the NAND latch circuit 12 includes at least a first inverter 121, a first NAND gate 122, a second NAND gate 123, and a third NOT gate 124.
  • the input end of the first inverter 121 is connected to the output end of the clock control transmission circuit 11, and the first input end of the first NAND gate 122 is connected to the output end of the first inverter 123, the first NAND gate 122
  • the second input end is connected to the output end of the second NAND gate 123, the first input end of the second NAND gate 123 is connected to the input end of the first inverter 122, and the second input end of the second NAND gate 123 is connected.
  • the output of the second NAND gate 123 is further connected to the first input of the third NAND gate 124, and the second input of the third NAND gate 124 receives the clock signal CK.
  • the NAND latch circuit 12 further includes a multi-stage inverter circuit connected to the output terminal of the NAND gate to boost the driving capability of the drive circuit 1.
  • the multi-stage inverter circuit includes a plurality of second inverters 124 arranged in series. Preferably, the number of second inverters 124 is three.
  • the specific operation principle of the shift register circuit 10 is as follows: When the first clock pulse of the clock signal CK is a rising edge, the clock control transmission circuit 11 triggers the transmission of the drive pulse Gn-1 of the previous stage to the first inverter 121. In the transmission process, the drive pulse Gn-1 is inverted. The first NAND gate 122 and the second NAND gate 123 are transmitted through the first inverter 121, and the driving pulse Gn- of the previous stage is passed to the first NAND gate 122 and the second NAND gate 123 which are cross-connected. 1 is latched.
  • the NAND latch circuit 12 When the second clock pulse of the clock signal CK is a rising edge, that is, when the next clock pulse of the clock signal CK is a rising edge, the NAND latch circuit 12 is triggered to latch the first NAND gate 122 in the cross-connect and The drive pulse Gn-1 of the previous stage of the second NAND gate 123 is transmitted to the second inverter 124, and is transmitted to the gate Gn of the subsequent stage through the second inverter 124.
  • the clock control transmission circuit 11 further includes a clock signal XCK, and the clock signal XCK is opposite in phase to the clock signal CK.
  • the shift register circuit 20 includes a clock control transfer circuit 21 and an NAND gate latch circuit 22.
  • the NAND latch circuit 22 includes at least a first inverter 221, a first NAND gate 222, a second NAND gate 223, and a third NAND gate 224, wherein the input of the first inverter 221 is connected to a clock control.
  • the output end of the transmission circuit 21, the first input end of the first NAND gate 222 is connected to the output end of the first inverter 223, and the second input end of the first NAND gate 222 is connected to the output end of the second NAND gate 223.
  • the first input end of the second NAND gate 223 is connected to the input end of the first inverter 222, and the second input end of the second NAND gate 223 is connected to the output end of the first NAND gate 222.
  • the second NAND gate The output of 223 is further coupled to a first input of third NOT gate 224, and the second input of third NAND gate 224 receives a clock signal XCK.
  • the NAND latch circuit 22 further includes a multi-stage inverter circuit connected to the output terminal of the third NAND gate 224 to boost the driving capability of the drive circuit 1.
  • the multi-stage inverter circuit includes a plurality of second inverters 224 arranged in series. Preferably, the number of second inverters 224 is three.
  • the specific operation principle of the shift register circuit 20 is as follows: When the first clock pulse of the clock signal XCK is a rising edge, the clock control transfer circuit 21 triggers the transfer of the drive pulse Gn of the subsequent stage to the first inverter 221. In the transmission process, the driving pulse Gn of the subsequent stage is inverted. The first NAND gate 222 and the second NAND gate 223 are transmitted through the first inverter 221, and the driving pulse Gn of the subsequent stage is transmitted to the first NAND gate 222 and the second NAND gate 223 which are cross-connected. Latch.
  • the NAND gate latch circuit 22 When the second clock pulse of the clock signal XCK is a rising edge, that is, when the next clock pulse of the clock signal XCK is a rising edge, the NAND gate latch circuit 22 is triggered to latch the first NAND gate 222 that is cross-connected and The drive pulse Gn of the subsequent stage of the second NAND gate 223 is transmitted to the second inverter 224, and is transmitted to the drive pulse Gn+1 of the third stage through the second inverter 224.
  • the clock control transmission circuit 21 further includes a clock signal CK, and the clock signal CK is opposite in phase to the clock signal XCK.
  • the shift register circuit 10 is adjacent to the shift register circuit 20.
  • the NAND gate latched shift register circuit provided in the cascode latched drive circuit 1 may be divided into odd-numbered stages and even-numbered stages, and the shift register circuit 10 may be used as an odd number.
  • the stage shift register uses the shift register circuit 20 as an even-numbered shift register. It is also possible to use the shift register circuit 20 as an odd-numbered shift register and the shift register circuit 10 as an even-numbered shift register.
  • FIG. 4 is a theoretical timing diagram of a NAND gate latch driving circuit according to an embodiment of the present invention.
  • the shift register circuit 10 functions as an odd-numbered shift register
  • the shift register circuit 20 functions as an even-numbered shift register.
  • the clock signal CK and the clock signal XCK are opposite in phase.
  • the driving pulse Gn-1 of the previous stage is transmitted to the gate of the subsequent stage, that is, the driving pulse Gn-1 of the previous stage is switched from the high level to the low level, and the latter stage is The drive pulse Gn is turned from a low level to a high level to drive the corresponding gate.
  • the driving pulse Gn of the subsequent stage is transmitted to the gate of the third stage, that is, the driving pulse Gn of the subsequent stage is switched from the high level to the low level, and the driving pulse Gn of the third stage is driven.
  • Fig. 5 is a timing chart showing the simulation of the driving circuit of the embodiment of the present invention. Referring to Figure 5, the ordinate is voltage and the abscissa is time. As can be seen from the figure, the analog timing of the NAND gate latched driving circuit is the same as the theoretical timing in FIG.
  • the present invention also provides a NAND gate latched shift register.
  • the NAND gate latch shift register circuit 10 includes a clock control transfer circuit 11 and an NAND gate latch circuit 12, and a NAND gate lock.
  • the memory circuit 12 includes at least a first inverter 121, a first NAND gate 122, a second NAND gate 123, and a third NAND gate 124, wherein an input end of the first inverter 121 is connected to the clock control transmission circuit 11.
  • the first input end of the first NAND gate 122 is connected to the output end of the first inverter 123, and the second input end of the first NAND gate 122 is connected to the output end of the second NAND gate 123, the second The first input end of the NOT gate 123 is connected between the input ends of the first inverter 122, the second input end of the second NAND gate 123 is connected to the output end of the first NAND gate 122, and the second NAND gate 123 is The output terminal is further connected to the first input terminal of the third NOT gate 124, and the second input terminal of the third NAND gate 124 receives the clock signal CK.
  • the NAND latch circuit 12 further includes a multi-stage inverter circuit connected to the output terminal of the third NAND gate 124 to improve the driving capability.
  • the multi-stage inverter circuit includes a plurality of second inverters 124 arranged in series.
  • the number of second inverters 124 is three.
  • the specific operation principle of the shift register circuit 10 is as follows: When the first clock pulse of the clock signal CK is a rising edge, the clock control transmission circuit 11 triggers the transmission of the drive pulse Gn-1 of the previous stage to the first inverter 121. In the transmission process, the drive pulse Gn-1 is inverted. The first NAND gate 122 and the second NAND gate 123 are transmitted through the first inverter 121, and the driving pulse Gn- of the previous stage is passed to the first NAND gate 122 and the second NAND gate 123 which are cross-connected. 1 is latched.
  • the NAND latch circuit 12 When the second clock pulse of the clock signal CK is a rising edge, that is, when the next clock pulse of the clock signal CK is a rising edge, the NAND latch circuit 12 is triggered to latch the first NAND gate 122 in the cross-connect and The drive pulse Gn-1 of the previous stage of the second NAND gate 123 is transmitted to the second inverter 124, and is transmitted to the gate Gn of the subsequent stage through the second inverter 124.
  • the clock control transmission circuit 11 further includes a clock signal XCK, and the clock signal XCK is opposite in phase to the clock signal CK.
  • the driving circuit of the NAND gate latch may be cascaded through a plurality of shift registers 10, the signal transmission of the upper and lower stages is controlled by the clock control transmission circuit 11, and the signal is latched by the NAND gate latch circuit 12. It can be applied to CMOS processes with low power consumption and wide noise margin.
  • the driving pulse disclosed in the present invention is preferably a gate driving pulse.
  • the NAND gate latch driving circuit of the present invention is triggered by the first clock pulse of the clock signal through the clock control transmission circuit to transmit the driving pulse of the previous stage to the NAND gate latch circuit, and
  • the non-gate latch circuit is latched, and the NAND gate latch circuit is further triggered by the second clock pulse subsequent to the first clock signal to output a drive pulse, which can be applied to a CMOS process, and has low power consumption and wide noise margin.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

一种与非门锁存的驱动电路以及与非门锁存的移位寄存器。该与非门锁存的驱动电路包括多个级联设置的移位寄存电路（10），每一所述移位寄存电路包括时钟控制传输电路（11）以及与非门锁存电路（12），其中所述时钟控制传输电路（11）由所述时钟信号的第一时钟脉冲进行触发将前一级的驱动脉冲传输至所述与非门锁存电路（12），并由所述与非门锁存电路（12）进行锁存，所述与非门锁存电路（12）进一步由所述第一时钟信号后续的第二时钟脉冲进行触发进而输出所述驱动脉冲。与非门锁存的驱动电路能够适用于CMOS制程，功耗低、噪声容限宽。

Description

与非门锁存的驱动电路以及与非门锁存的移位寄存器
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种与非门锁存的驱动电路以及与非门锁存的移位寄存器。
【背景技术】
GOA（Gate Driver On Array）电路是利用现有的液晶显示器的Array制程将栅极扫描驱动电路制作在Array基板上，以实现逐行扫描的驱动方式。其具有降低生产成本和窄边框设计的优点，为多种显示器所使用。GOA电路要具有两项基本功能：第一是输入栅极驱动脉冲，驱动面板内的栅极线，打开显示区内的TFT（Thin Film Transistor，薄膜场效应晶体管），由栅极线对像素进行充电；第二是移位寄存，当第n个栅极驱动脉冲输出完成后，可以通过时钟控制进行n+1个栅极驱动脉冲的输出，并依此传递下去。
GOA电路包括上拉电路（Pull-up circuit）、上拉控制电路（Pull-up control circuit）、下拉电路（Pull-down circuit）、下拉控制电路（Pull-down control circuit）以及负责电位抬升的上升电路（Boost circuit）。具体地，上拉电路主要负责将输入的时钟讯号（Clock）输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制电路负责控制上拉电路的打开，一般是由上级GOA电路传递来的信号作用。下拉电路负责在输出扫描信号后，快速将扫描信号拉低为低电位，即薄膜晶体管的栅极的电位拉低为低电位；下拉保持电路则负责将扫描信号和上拉电路的信号（通常称为Q点） 保持在关闭状态（即设定的负电位），通常有两个下拉保持电路交替作用。上升电路则负责Q点电位的二次抬升，这样确保上拉电路的G(N)正常输出。
不同的GOA电路可以使用不同的制程。LTPS（Low Temperature Poly-silicon，低温多晶硅）制程具有高电子迁移率和技术成熟的优点，目前被中小尺寸显示器广泛使用。CMOS（Complementary Metal Oxide Semiconductor，互补金属氧化物半导体） LTPS制程具有低功耗、电子迁移率高、噪声容限宽等优点, 因此逐渐为面板厂商使用，如此需要开发与CMOS LTPS制程对应的GOA电路。
【发明内容】
本发明实施例提供了一种与非门锁存的驱动电路以及与非门锁存的移位寄存器，以适用于CMOS制程，功耗低、噪声容限宽。
本发明提供一种与非门锁存的驱动电路，其包括多个级联设置的与非门锁存的移位寄存电路，每一移位寄存电路包括时钟控制传输电路以及与非门锁存电路，其中时钟控制传输电路由时钟信号的第一时钟脉冲进行触发将前一级的驱动脉冲传输至与非门锁存电路，并由与非门锁存电路进行锁存，与非门锁存电路进一步由第一时钟信号后续的第二时钟脉冲进行触发进而输出驱动脉冲；时钟控制传输电路和与非门锁存电路分别为上升沿触发；其中，与非门锁存电路至少包括第一反相器、第一与非门、第二与非门以及第三与非门，其中第一反相器的输入端连接时钟控制传输电路的输出端，第一与非门的第一输入端连接第一反相器的输出端，第一与非门的第二输入端连接第二与非门的输出端，第二与非门的第一输入端连接第一反相器的输入端，第二与非门的第二输入端连接第一与非门的输出端，第二与非门的输出端进一步连接与第三非门的第一输入端，第三与非门的第二输入端接收时钟信号。
其中，时钟控制传输电路在传输驱动脉冲的过程中对驱动脉冲进行反相。
其中，与非门锁存电路进一步包括与第三与非门的输出端连接的多级反相电路。
其中，多级反相电路包括串联设置的多个第二反相器。
其中，第二反相器的数量为三个。
其中，相邻的移位寄存电路的时钟信号互为反相。
本发明还提供一种与非门锁存的驱动电路，其包括多个级联设置的与非门锁存的移位寄存电路，每一移位寄存电路包括时钟控制传输电路以及与非门锁存电路，其中时钟控制传输电路由时钟信号的第一时钟脉冲进行触发将前一级的驱动脉冲传输至与非门锁存电路，并由与非门锁存电路进行锁存，与非门锁存电路进一步由第一时钟信号后续的第二时钟脉冲进行触发进而输出驱动脉冲。
其中，时钟控制传输电路和与非门锁存电路分别为上升沿触发。
其中，与非门锁存电路至少包括第一反相器、第一与非门、第二与非门以及第三与非门，其中第一反相器的输入端连接时钟控制传输电路的输出端，第一与非门的第一输入端连接第一反相器的输出端，第一与非门的第二输入端连接第二与非门的输出端，第二与非门的第一输入端连接第一反相器的输入端，第二与非门的第二输入端连接第一与非门的输出端，第二与非门的输出端进一步连接与第三非门的第一输入端，第三与非门的第二输入端接收时钟信号。
其中，时钟控制传输电路在传输驱动脉冲的过程中对驱动脉冲进行反相。
其中，与非门锁存电路进一步包括与第三与非门的输出端连接的多级反相电路。
其中，多级反相电路包括串联设置的多个第二反相器。
其中，第二反相器的数量为三个。
其中，相邻的移位寄存电路的时钟信号互为反相。
本发明还提供一种与非门锁存的移位寄存器，其包括时钟控制传输电路以及与非门锁存电路，与非门锁存电路至少包括第一反相器、第一与非门、第二与非门以及第三与非门，其中第一反相器的输入端连接时钟控制传输电路的输出端，第一与非门的第一输入端连接第一反相器的输出端，第一与非门的第二输入端连接第二与非门的输出端，第二与非门的第一输入端连接第一反相器的输入端之间，第二与非门的第二输入端连接第一与非门的输出端，第二与非门的输出端进一步连接第三与非门的第一输入端。
其中，与非门锁存电路进一步包括与第三与非门的输出端连接的多级反相电路。
通过上述方案，本发明的有益效果是：本发明的与非门锁存的驱动电路通过时钟控制传输电路由时钟信号的第一时钟脉冲进行触发将前一级的驱动脉冲传输至与非门锁存电路，并由与非门锁存电路进行锁存，与非门锁存电路进一步由第一时钟信号后续的第二时钟脉冲进行触发进而输出驱动脉冲，能够适用于CMOS制程，功耗低、噪声容限宽。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明实施例的与非门锁存的驱动电路的结构示意图；
图2是图1中的移位寄存器的电路图；
图3是本发明第二实施例的移位寄存器的电路图；
图4是本发明实施例的与非门锁存的驱动电路的理论时序图；
图5是本发明实施例的与非门锁存的驱动电路的模拟时序图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1所示，图1是本发明实施例的与非门锁存的驱动电路的结构示意图。如图1所示，本实施例所揭示的驱动电路1包括多个级联设置的与非门锁存的移位寄存电路10，每一移位寄存电路10包括时钟控制传输电路11以及与非门锁存电路12，其中时钟控制传输电路11由时钟信号的第一时钟脉冲进行触发将前一级的驱动脉冲传输至与非门锁存电路12，并由与非门锁存电路12进行锁存，与非门锁存电路12进一步由第一时钟信号后续的第二时钟脉冲进行触发进而输出驱动脉冲。其中时钟控制传输电路11在传输驱动脉冲的过程中对驱动脉冲进行反相。并且时钟控制传输电路11和与非门锁存电路12分别为上升沿触发。本发明实施例通过时钟控制传输电路11控制上下级信号传递，通过与非门锁存电路12锁存信号，能够适用于CMOS制程，功耗低、噪声容限宽。
在更具体的实施例中，如图2所示，与非门锁存电路12至少包括第一反相器121、第一与非门122、第二与非门123以及与第三非门124，其中第一反相器121的输入端连接时钟控制传输电路11的输出端，第一与非门122的第一输入端连接第一反相器123的输出端，第一与非门122的第二输入端连接第二与非门123的输出端，第二与非门123的第一输入端连接第一反相器122的输入端，第二与非门123的第二输入端连接第一与非门122的输出端，第二与非门123的输出端进一步连接第三与非门124的第一输入端，第三与非门124的第二输入端接收时钟信号CK。与非门锁存电路12进一步包括与与非门的输出端连接的多级反相电路以提升驱动电路1的驱动能力。其中，多级反相电路包括串联设置的多个第二反相器124。优选地，第二反相器124的数量为三个。
移位寄存电路10具体的工作原理如下：时钟信号CK的第一时钟脉冲为上升沿时，时钟控制传输电路11触发将前一级的驱动脉冲Gn-1传输至第一反相器121。其中在传输过程中，对驱动脉冲Gn-1进行反相。再经过第一反相器121传输第一与非门122以及第二与非门123，通过至交叉连接的第一与非门122以及第二与非门123对前一级的驱动脉冲Gn-1进行锁存。时钟信号CK的第二时钟脉冲为上升沿，即时钟信号CK的下一个时钟脉冲为上升沿时，对与非门锁存电路12进行触发，使锁存在交叉连接的第一与非门122以及第二与非门123的前一级的驱动脉冲Gn-1传输至第二反相器124，通过第二反相器124传输至后一级的栅极Gn。其中，时钟控制传输电路11还包括时钟信号XCK，时钟信号XCK与时钟信号CK相位相反。
在本发明实施例中，相邻的移位寄存电路的时钟信号互为反相。参见图3，移位寄存电路20包括时钟控制传输电路21以及与非门锁存电路22。与非门锁存电路22至少包括第一反相器221、第一与非门222、第二与非门223以及第三与非门224，其中第一反相器221的输入端连接时钟控制传输电路21的输出端，第一与非门222的第一输入端连接第一反相器223的输出端，第一与非门222的第二输入端连接第二与非门223的输出端，第二与非门223的第一输入端连接第一反相器222的输入端，第二与非门223的第二输入端连接第一与非门222的输出端，第二与非门223的输出端进一步连接与第三非门224的第一输入端，第三与非门224的第二输入端接收时钟信号XCK。与非门锁存电路22进一步包括与第三与非门224的输出端连接的多级反相电路以提升驱动电路1的驱动能力。其中，多级反相电路包括串联设置的多个第二反相器224。优选地，第二反相器224的数量为三个。
移位寄存电路20具体的工作原理如下：时钟信号XCK的第一时钟脉冲为上升沿时，时钟控制传输电路21触发将后一级的驱动脉冲Gn传输至第一反相器221。其中在传输过程中，对后一级的驱动脉冲Gn进行反相。再经过第一反相器221传输第一与非门222以及第二与非门223，通过至交叉连接的第一与非门222以及第二与非门223对后一级的驱动脉冲Gn进行锁存。时钟信号XCK的第二时钟脉冲为上升沿，即时钟信号XCK的下一个时钟脉冲为上升沿时，对与非门锁存电路22进行触发，使锁存在交叉连接的第一与非门222以及第二与非门223的后一级的驱动脉冲Gn传输至第二反相器224，通过第二反相器224传输至第三级的驱动脉冲Gn+1。其中，时钟控制传输电路21还包括时钟信号CK，时钟信号CK与时钟信号XCK相位相反。
在本发明实施例中，移位寄存电路10与移位寄存电路20是相邻的。在实际应用中，可以将与非门锁存的驱动电路1中的多个级联设置的与非门锁存的移位寄存电路分成奇数级和偶数级，可以将移位寄存电路10作为奇数级移位寄存器，将移位寄存电路20作为偶数级移位寄存器。也可以将移位寄存电路20作为奇数级移位寄存器，将移位寄存电路10作为偶数级移位寄存器。参见图4，图4是本发明实施例的与非门锁存的驱动电路的理论时序图。其中移位寄存电路10作为奇数级移位寄存器，移位寄存电路20作为偶数级移位寄存器。从图中可以看出，时钟信号CK和时钟信号XCK相位相反。时钟信号CK为上升沿时，前一级的驱动脉冲Gn-1传输至后一级的栅极，即前一级的驱动脉冲Gn-1由高电平转为低电平，后一级的驱动脉冲Gn由低电平转为高电平，驱动对应的栅极。时钟信号XCK为上升沿时，而后一级的驱动脉冲Gn传输至第三级的栅极，即后一级的驱动脉冲Gn由高电平转为低电平，而第三级的驱动脉冲Gn+1则低电平转为高电平，驱动对应的栅极。图5是本发明实施例的驱动电路的模拟时序图。参见图5，其中纵坐标为电压，横坐标为时间。从图中可以看出，与非门锁存的驱动电路的模拟时序与图4中的理论时序相同。
本发明还提供一种与非门锁存的移位寄存器，参见图2，与非门锁存的移位寄存电路10包括时钟控制传输电路11以及与非门锁存电路12，与非门锁存电路12至少包括第一反相器121、第一与非门122、第二与非门123以及第三与非门124，其中第一反相器121的输入端连接时钟控制传输电路11的输出端，第一与非门122的第一输入端连接第一反相器123的输出端，第一与非门122的第二输入端连接第二与非门123的输出端，第二与非门123的第一输入端连接第一反相器122的输入端之间，第二与非门123的第二输入端连接第一与非门122的输出端，第二与非门123的输出端进一步连接与第三非门124的第一输入端，第三与非门124的第二输入端接收时钟信号CK。与非门锁存电路12进一步包括与第三与非门124的输出端连接的多级反相电路以提升驱动能力。其中，多级反相电路包括串联设置的多个第二反相器124。优选地，第二反相器124的数量为三个。
移位寄存电路10具体的工作原理如下：时钟信号CK的第一时钟脉冲为上升沿时，时钟控制传输电路11触发将前一级的驱动脉冲Gn-1传输至第一反相器121。其中在传输过程中，对驱动脉冲Gn-1进行反相。再经过第一反相器121传输第一与非门122以及第二与非门123，通过至交叉连接的第一与非门122以及第二与非门123对前一级的驱动脉冲Gn-1进行锁存。时钟信号CK的第二时钟脉冲为上升沿，即时钟信号CK的下一个时钟脉冲为上升沿时，对与非门锁存电路12进行触发，使锁存在交叉连接的第一与非门122以及第二与非门123的前一级的驱动脉冲Gn-1传输至第二反相器124，通过第二反相器124传输至后一级的栅极Gn。其中，时钟控制传输电路11还包括时钟信号XCK，时钟信号XCK与时钟信号CK相位相反。在本发明实施例中，可以通过多个移位寄存器10级联组成与非门锁存的驱动电路，通过时钟控制传输电路11控制上下级信号传递，通过与非门锁存电路12锁存信号，能够适用于CMOS制程，功耗低、噪声容限宽。
值得注意的是，本发明所揭示的驱动脉冲优选为栅极驱动脉冲。
综上所述，本发明的与非门锁存的驱动电路通过时钟控制传输电路由时钟信号的第一时钟脉冲进行触发将前一级的驱动脉冲传输至与非门锁存电路，并由与非门锁存电路进行锁存，与非门锁存电路进一步由第一时钟信号后续的第二时钟脉冲进行触发进而输出驱动脉冲，能够适用于CMOS制程，功耗低、噪声容限宽。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (16)

  1. 一种与非门锁存的驱动电路，其中，所述驱动电路包括多个级联设置的与非门锁存的移位寄存电路，每一所述移位寄存电路包括时钟控制传输电路以及与非门锁存电路，其中所述时钟控制传输电路由所述时钟信号的第一时钟脉冲进行触发将前一级的驱动脉冲传输至所述与非门锁存电路，并由所述与非门锁存电路进行锁存，所述与非门锁存电路进一步由所述第一时钟信号后续的第二时钟脉冲进行触发进而输出所述驱动脉冲；所述时钟控制传输电路和所述与非门锁存电路分别为上升沿触发；
    其中，所述与非门锁存电路至少包括第一反相器、第一与非门、第二与非门以及第三与非门，其中所述第一反相器的输入端连接所述时钟控制传输电路的输出端，所述第一与非门的第一输入端连接所述第一反相器的输出端，所述第一与非门的第二输入端连接所述第二与非门的输出端，所述第二与非门的第一输入端连接所述第一反相器的输入端，所述第二与非门的第二输入端连接所述第一与非门的输出端，所述第二与非门的输出端进一步连接所述第三与非门的第一输入端，所述第三与非门的第二输入端接收所述时钟信号。
  2. 根据权利要求1所述的驱动电路，其中，所述时钟控制传输电路在传输所述驱动脉冲的过程中对所述驱动脉冲进行反相。
  3. 根据权利要求1所述的驱动电路，其中，所述与非门锁存电路进一步包括与所述第三与非门的输出端连接的多级反相电路。
  4. 根据权利要求1所述的驱动电路，其中，所述多级反相电路包括串联设置的多个第二反相器。
  5. 根据权利要求4所述的驱动电路，其中，所述第二反相器的数量为三个。
  6. 根据权利要求1所述的驱动电路，其中，相邻的所述移位寄存电路的所述时钟信号互为反相。
  7. 一种与非门锁存的驱动电路，其中，所述驱动电路包括多个级联设置的与非门锁存的移位寄存电路，每一所述移位寄存电路包括时钟控制传输电路以及与非门锁存电路，其中所述时钟控制传输电路由所述时钟信号的第一时钟脉冲进行触发将前一级的驱动脉冲传输至所述与非门锁存电路，并由所述与非门锁存电路进行锁存，所述与非门锁存电路进一步由所述第一时钟信号后续的第二时钟脉冲进行触发进而输出所述驱动脉冲。
  8. 根据权利要求7所述的驱动电路，其中，所述时钟控制传输电路和所述与非门锁存电路分别为上升沿触发。
  9. 根据权利要求7所述的驱动电路，其中，所述与非门锁存电路至少包括第一反相器、第一与非门、第二与非门以及第三与非门，其中所述第一反相器的输入端连接所述时钟控制传输电路的输出端，所述第一与非门的第一输入端连接所述第一反相器的输出端，所述第一与非门的第二输入端连接所述第二与非门的输出端，所述第二与非门的第一输入端连接所述第一反相器的输入端，所述第二与非门的第二输入端连接所述第一与非门的输出端，所述第二与非门的输出端进一步连接所述第三与非门的第一输入端，所述第三与非门的第二输入端接收所述时钟信号。
  10. 根据权利要求9所述的驱动电路，其中，所述时钟控制传输电路在传输所述驱动脉冲的过程中对所述驱动脉冲进行反相。
  11. 根据权利要求9所述的驱动电路，其中，所述与非门锁存电路进一步包括与所述第三与非门的输出端连接的多级反相电路。
  12. 根据权利要求9所述的驱动电路，其中，所述多级反相电路包括串联设置的多个第二反相器。
  13. 根据权利要求12所述的驱动电路，其中，所述第二反相器的数量为三个。
  14. 根据权利要求7所述的驱动电路，其中，相邻的所述移位寄存电路的所述时钟信号互为反相。
  15. 一种与非门锁存的移位寄存器，其中，所述移位寄存电路包括时钟控制传输电路以及与非门锁存电路，所述与非门锁存电路至少包括第一反相器、第一与非门、第二与非门以及第三与非门，其中所述第一反相器的输入端连接所述时钟控制传输电路的输出端，所述第一与非门的第一输入端连接所述第一反相器的输出端，所述第一与非门的第二输入端连接所述第二与非门的输出端，所述第二与非门的第一输入端连接所述第一反相器的输入端，所述第二与非门的第二输入端连接所述第一与非门的输出端，所述第二与非门的输出端进一步连接所述第三与非门的第一输入端。
  16. 根据权利要求15所述的移位寄存器，其中，所述与非门锁存电路进一步包括与所述第三与非门的输出端连接的多级反相电路。
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