WO2019061604A1 - 扫描驱动电路及显示装置 - Google Patents

扫描驱动电路及显示装置 Download PDF

Info

Publication number
WO2019061604A1
WO2019061604A1 PCT/CN2017/107175 CN2017107175W WO2019061604A1 WO 2019061604 A1 WO2019061604 A1 WO 2019061604A1 CN 2017107175 W CN2017107175 W CN 2017107175W WO 2019061604 A1 WO2019061604 A1 WO 2019061604A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
signal
scan driving
scan
circuit
Prior art date
Application number
PCT/CN2017/107175
Other languages
English (en)
French (fr)
Inventor
赵莽
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/735,924 priority Critical patent/US10650767B2/en
Publication of WO2019061604A1 publication Critical patent/WO2019061604A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a scan driving circuit and a display device.
  • GOA Gate Driver On Array
  • the scan driving circuit of the conventional display device has only one of forward scanning or reverse scanning, which limits the flexibility of the driving of the display device, and is disadvantageous for reducing the power consumption of the driving even if the existing display device has Forward scan and reverse scan drive, but the circuit design is complex, which is not conducive to reducing power consumption and narrow bezel design.
  • the technical problem to be solved by the present invention is to provide a scan driving circuit and a display device capable of performing forward scanning and reverse scanning driving modes, improving the flexibility of driving of the display device, reducing driving power consumption and facilitating narrow frame design. .
  • the present invention adopts a technical solution to provide a scan driving circuit including a plurality of cascaded scan driving units, wherein the plurality of cascaded scan driving units include a first-stage scan driving unit and a plurality of intermediate The first-level scan driving unit, each of the intermediate-level scan driving units, and the last-stage scan driving unit each include:
  • An input circuit configured to receive a forward scan control voltage or a reverse scan control voltage, and selectively receive an upper scan drive signal or a lower scan drive signal according to the forward scan control voltage or the reverse scan control voltage Generating a pull-up control signal according to the received forward scan control voltage and the upper scan drive signal, or generating a pull-down control signal according to the received reverse scan control voltage and the lower scan drive signal;
  • a latch circuit connected to the input circuit, for pulling up the pull-up control signal point according to the pull-up control signal and pulling down the pull-up control signal point according to the pull-down control signal;
  • a processing circuit connected to the latch circuit, for receiving a clock signal and generating a scan driving signal of the current stage according to the clock signal and the signal of the pull-up control signal point;
  • a buffer circuit connected to the processing circuit for driving an output of the scan driving signal of the current stage
  • a reset circuit connected to the latch circuit for receiving a reset signal to clear the pull-up control signal point.
  • one technical solution adopted by the present invention is to provide a display device, the display device comprising a scan driving circuit, the scan driving circuit comprising a plurality of cascaded scan driving units, the plurality of cascaded
  • the scan driving unit includes a first-stage scan driving unit, a plurality of intermediate-level scan driving units, and a last-stage scan driving unit, and the first-level scan driving unit, each intermediate-level scan driving unit, and the last-level scan driving unit are included :
  • An input circuit configured to receive a forward scan control voltage or a reverse scan control voltage, and selectively receive an upper scan drive signal or a lower scan drive signal according to the forward scan control voltage or the reverse scan control voltage Generating a pull-up control signal according to the received forward scan control voltage and the upper scan drive signal, or generating a pull-down control signal according to the received reverse scan control voltage and the lower scan drive signal;
  • a latch circuit connected to the input circuit, for pulling up the pull-up control signal point according to the pull-up control signal and pulling down the pull-up control signal point according to the pull-down control signal;
  • a processing circuit connected to the latch circuit, for receiving a clock signal and generating a scan driving signal of the current stage according to the clock signal and the signal of the pull-up control signal point;
  • a buffer circuit connected to the processing circuit for driving an output of the scan driving signal of the current stage
  • a reset circuit connected to the latch circuit for receiving a reset signal to clear the pull-up control signal point.
  • the scan driving circuit and the display device of the present invention output a pull-up control signal and a pull-down control signal through the input circuit to realize forward scanning and reverse scanning driving.
  • the pull-up control signal point is pulled up or pulled down by the latch circuit, and the scan driving signal of the current stage is generated by the processing circuit and the buffer circuit, and the reset circuit is used to
  • the scan driving circuit is cleared to improve the flexibility of the display device driving, and the driving power consumption is reduced and the narrow bezel design is facilitated.
  • FIG. 1 is a circuit diagram of a first embodiment of a scan driving circuit of the present invention
  • FIG. 2 is a circuit diagram of a second embodiment of the scan driving circuit of the present invention.
  • FIG. 3 is a schematic diagram showing the operation timing of the forward scanning of the scan driving circuit of the present invention.
  • Figure 5 is a schematic view showing a driving frame of the scan driving circuit of the present invention.
  • FIG. 6 is a timing chart showing simulation waveforms of the scan driving circuit of the present invention.
  • Fig. 7 is a schematic structural view of a display device of the present invention.
  • FIG. 1 is a circuit diagram of a first embodiment of a scan driving circuit of the present invention.
  • the scan driving circuit includes a plurality of cascaded scan driving units 1.
  • the plurality of cascaded scan driving units 1 include a first level scan driving unit, a plurality of intermediate level scanning driving units, and a last stage scanning driving unit.
  • the first-stage scan driving unit, each intermediate-level scan driving unit and the last-stage scan driving unit each include an input circuit 10 for receiving a forward scan control voltage U2D or a reverse scan control voltage D2U, and according to the forward scan
  • the control voltage U2D or the reverse scan control voltage D2U selectively receives the upper scan drive signal Gate(n-1) or the lower scan drive signal Gate(n+1) to receive the forward scan control voltage according to the received U2D and the upper-level scan driving signal Gate(n-1) generate a pull-up control signal H(n), or according to the received reverse scan control voltage D2U and the lower-level scan driving signal Gate(n+1) Generating a pull-down control signal L(n) to enable the scan driving circuit to implement a driving mode of forward scanning and reverse scanning, wherein, in the forward scanning, the upper scanning drive of the first-stage scanning driving unit The signal is the trigger signal STV, the lower-level scan driving signal of the last-stage scan driving unit is the trigger signal STV; and the reverse-scanning
  • a latch circuit 20 connected to the input circuit 10 for pulling up the pull-up control signal point Q(n) according to the pull-up control signal H(n) and according to the pull-down control signal L(n) The pull-up control signal point Q(n) is pulled down;
  • the processing circuit 30 is connected to the latch circuit 20 for receiving the clock signal CK and generating the current-level scan driving signal Gate(n) according to the clock signal CK and the signal of the pull-up control signal point Q(n);
  • a buffer circuit 40 connected to the processing circuit 30, for driving the output of the current-level scan driving signal Gate(n);
  • the reset circuit 50 is connected to the latch circuit 40 for receiving a reset signal Reset to clear the pull-up control signal point Q(n).
  • the input circuit 10 includes first to fourth transmission gates 11-14, first control terminals of the first and third transmission gates 11, 13 and the second and fourth transmission gates 12, 14
  • the second control terminal is connected to the reverse scan control voltage D2U, the second control end of the first and third transmission gates 11, 13 and the first control of the second and fourth transmission gates 12, 14
  • the terminal is connected to the forward scanning control voltage U2D, and the input ends of the first and fourth transmission gates 11, 14 are connected to the upper scanning driving signal Gate(n-1), the first transmission gate 11
  • the output end is connected to the output end of the second transmission gate 12 and the latch circuit 20, and the input end of the second transmission gate 12 is connected to the input end of the third transmission gate 13 and receives the lower-level scan driving signal Gate (n+1), an output end of the third transmission gate 13 is connected to an output terminal of the fourth transmission gate 14 and the latch circuit 20.
  • the latch circuit 20 includes a first NOR gate X1 and a second NOR gate X2, and a first input end of the first NOR gate X1 is connected to an output end of the first transmission gate 11 a second input end of the first NOR gate X1 is connected to an output end of the second NOR gate X2 and the processing circuit 30, and an output end of the first NOR gate X1 is connected to the second NOR gate A first input of X2, a second input of the second NOR gate X2 is coupled to an output of the fourth transfer gate 14.
  • the processing circuit 30 includes a NAND gate Y1, the first input end of the NAND gate Y1 receives the clock signal CK, and the second input end of the NAND gate Y1 is connected to the second or non-gate
  • the output of the gate X2 is connected to the buffer circuit 40 at the output of the NAND gate Y1.
  • the buffer circuit 40 includes first to third inverters U1-U3, and an input end of the first inverter U1 is connected to an output terminal of the NAND gate Y1, and the second inverter An input end of the U2 is connected to an output end of the first inverter U1, and an input end of the third inverter U3 is connected to an output end of the second inverter U2, the third inverter U3 The output terminal outputs the current-level scan driving signal Gate(n).
  • the reset circuit 50 includes a controllable switch T1, and the control end of the controllable switch T1 receives the reset signal Reset, and the first end of the controllable switch T1 is connected to the second NOR gate X2. At the output end, the second end of the controllable switch T1 is connected to the off voltage terminal VGL.
  • controllable switch T1 is an N-type thin film transistor, and the control end, the first end, and the second end of the controllable switch T1 respectively correspond to a gate and a source of the N-type thin film transistor and Drain.
  • controllable switch T1 can also be other types of switches as long as the object of the present invention can be achieved.
  • FIG. 2 is a circuit diagram of a second embodiment of the scan driving circuit of the present invention.
  • the second embodiment of the scan driving circuit is different from the first embodiment in that the reset circuit 50 includes a controllable switch T1, and the control end of the controllable switch T1 receives the reset signal Reset.
  • the first end of the controllable switch T1 is connected to the open voltage terminal VGH, and the second end of the controllable switch T1 is connected to the output end of the first NOR gate X1.
  • controllable switch T1 is a P-type thin film transistor, and the control end, the first end and the second end of the controllable switch T1 respectively correspond to the gate and the source of the P-type thin film transistor and Drain.
  • controllable switch T1 can also be other types of switches as long as the object of the present invention can be achieved.
  • the working principle of the scan driving circuit for forward scanning (ie, scanning from the first stage to the last stage) is described as follows: (wherein the upper scanning drive of the first stage scanning driving unit is driven The signal is the trigger signal STV, the lower-level scan driving signal of the first-stage scan driving unit is Gate(n+1), and the upper-level scan driving signal of the intermediate-level scan driving unit is Gate(n-1), the intermediate-level scanning The lower-level scan driving signal of the driving unit is Gate(n+1), and the upper-level scan driving signal of the last-stage scan driving unit is Gate(n-1), and the lower-level scan driving signal of the last-stage scan driving unit is a trigger signal. STV)
  • the forward scan control voltage U2D is at a high level
  • the reverse scan control voltage D2U is at a low level, at which time the upper scan drive signal Gate(n-1) is supplied to the input
  • the circuit 10 is configured to generate a pull-up control signal H(n) for pulling up the pull-up control signal point Q(n) by the pull-up control signal H(n)
  • the lower-level scan driving signal Gate (n+1) is supplied to the input circuit 10 to generate a pull-down control signal L(n)
  • the pull-up control signal point Q(n) is pulled down and cleared by the pull-down control signal L(n)
  • a high level pulse of the reset signal Reset provides a reset signal for the pull-up control signal point Q(n)
  • the low level pulse of the reset signal Reset provides a reset signal for the pull up control signal point Q(n).
  • the current-level scan driving signal Gate(2) outputs a high-level pulse signal, and at the same time, the current-level scan driving signal Gate(2) is used as the upper-level scan driving signal of the next-stage scan driving unit.
  • the pull-up control signal point Q(2) After the high-level pulse signal of the lower-level scan driving signal Gate(3) is generated, the pull-up control signal point Q(2) is pulled down to a low-level signal, and the current-level scan driving signal Gate(2) Stable output low level signal.
  • the zero-to-low level signal, the current-level scan driving signal Gate (1920) stably outputs a low-level signal.
  • the working principle of the scan driving circuit for reverse scanning (ie, scanning from the last stage to the first stage) is described as follows: (wherein, the upper level scan driving unit of the last stage scan driving unit is driven The signal is the trigger signal STV, the lower-level scan driving signal of the last-stage scan driving unit is Gate(n-1), and the upper-level scan driving signal of the intermediate-stage scan driving unit is Gate(n+1), the intermediate-level scanning
  • the lower-level scan driving signal of the driving unit is Gate(n-1)
  • the upper-level scan driving signal of the first-stage scan driving unit is Gate(n+1)
  • the lower-level scan driving signal of the first-stage scan driving unit is a trigger signal.
  • the forward scan control voltage U2D is at a low level, and the reverse scan control voltage D2U is at a high level, at which time the upper scan drive signal Gate(n+1) is supplied to the input
  • the circuit 10 is configured to generate a pull-up control signal H(n) for pulling up the pull-up control signal point Q(n) by the pull-up control signal H(n), the lower-level scan driving signal Gate (n-1) is supplied to the input circuit to generate a pull-down control signal L(n), and the pull-up control signal point Q(n) is pulled down and cleared by the pull-down control signal L(n).
  • a high level pulse of the reset signal Reset provides a reset signal for the pull up control signal point Q(n)
  • the low level pulse of the reset signal Reset provides a reset signal for the pull-up control signal point Q(n).
  • the single-side scan driving circuit requires a trigger signal STV trace for the input of the first-stage or last-stage scan driving unit; the single-side scan driving circuit requires a positive The scan control voltage U2D trace and a reverse scan control voltage D2U are routed for the forward/backward scan control of the scan drive circuit; the single-sided scan drive circuit requires two clock signals CK traces (one of them) The clock signal trace CK3 is used to provide a clock signal for the odd-numbered scan driving unit, and the other clock signal trace CK1 is used to provide a clock signal for the even-numbered scan driving unit) for the generation of the scan driving signal; the single-side scan driving circuit A reset signal Reset is required for the reset processing of each stage of the scan driving unit; the single-sided scan driving circuit requires a turn-on voltage terminal VGH trace and a turn-off voltage terminal VGL trace for the scan drive circuit Power drive. It can be seen from the signal waveform of Fig. 6 that the scan driving circuit can
  • FIG. 7 is a schematic structural view of a display device of the present invention.
  • the display device includes the above-mentioned scan driving circuit, and other components and functions of the display device are the same as those of the existing display device, and details are not described herein again.
  • the scan driving circuit and the display device output a pull-up control signal and a pull-down control signal through the input circuit to implement forward and reverse scan control, and pull up or pull down the pull-up control signal point through the latch circuit Clearing, generating, by the processing circuit and the buffer circuit, a scan driving signal of the current stage, and clearing the scan driving circuit by the reset circuit, thereby improving flexibility of driving of the display device and reducing driving Power consumption.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)

Abstract

一种扫描驱动电路及显示装置。扫描驱动电路包括若干级联的扫描驱动单元（1），其包括输入电路（10）产生上拉控制信号（H(n)）及下拉控制信号（L(n)）；锁存电路（20）对上拉控制信号点（Q(n)）进行上拉及下拉；处理电路（30）产生本级扫描驱动信号（Gate(n)）；缓存电路（40）驱动本级扫描驱动信号（Gate(n)）的输出；复位电路（50）对上拉控制信号点（Q(n)）进行清零，以此提高显示装置驱动的灵活性，而且降低了驱动功耗且利于窄边框设计。

Description

扫描驱动电路及显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种扫描驱动电路及显示装置。
【背景技术】
GOA(Gate Driver On Array，阵列基板行驱动) 是利用薄膜晶体管液晶显示器阵列制程将栅极行扫描驱动信号电路制作在阵列基板上，实现对显示装置逐行扫描的驱动方式的一项技术。随着低温多晶硅（LTPS）半导体薄膜晶体管的发展，而且由于LTPS半导体本身超高载流子迁移率的特性，相应的显示装置周边集成电路也成为业界关注的焦点。然而，现有显示装置的扫描驱动电路只有正向扫描或反向扫描中的一种驱动方式，这限制了显示装置驱动的灵活性，而且不利于降低驱动的功耗，即使现有显示装置有正向扫描及反向扫描驱动方式，但是电路设计复杂，不利于降低功耗及窄边框设计。
【发明内容】
本发明主要解决的技术问题是提供一种扫描驱动电路及显示装置，能够进行正向扫描及反向扫描驱动方式，提高了显示装置驱动的灵活性，而且降低了驱动功耗且利于窄边框设计。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种扫描驱动电路，包括若干级联的扫描驱动单元，所述若干级联的扫描驱动单元包括第一级扫描驱动单元、若干中间级扫描驱动单元及最后一级扫描驱动单元，所述第一级扫描驱动单元、每一中间级扫描驱动单元及最后一级扫描驱动单元均包括：
输入电路，用于接收正向扫描控制电压或反向扫描控制电压，并根据所述正向扫描控制电压或所述反向扫描控制电压选择性的接收上级扫描驱动信号或下级扫描驱动信号，以根据接收到的所述正向扫描控制电压及所述上级扫描驱动信号产生上拉控制信号，或者根据接收到的所述反向扫描控制电压及所述下级扫描驱动信号产生下拉控制信号；
锁存电路，连接所述输入电路，用于根据所述上拉控制信号对上拉控制信号点进行上拉及根据所述下拉控制信号对所述上拉控制信号点进行下拉；
处理电路，连接所述锁存电路，用于接收时钟信号并根据所述时钟信号及所述上拉控制信号点的信号产生本级扫描驱动信号；
缓存电路，连接所述处理电路，用于驱动所述本级扫描驱动信号的输出；及
复位电路，连接所述锁存电路，用于接收复位信号以对所述上拉控制信号点进行清零。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种显示装置，所述显示装置包括扫描驱动电路，所述扫描驱动电路包括若干级联的扫描驱动单元，所述若干级联的扫描驱动单元包括第一级扫描驱动单元、若干中间级扫描驱动单元及最后一级扫描驱动单元，所述第一级扫描驱动单元、每一中间级扫描驱动单元及最后一级扫描驱动单元均包括：
输入电路，用于接收正向扫描控制电压或反向扫描控制电压，并根据所述正向扫描控制电压或所述反向扫描控制电压选择性的接收上级扫描驱动信号或下级扫描驱动信号，以根据接收到的所述正向扫描控制电压及所述上级扫描驱动信号产生上拉控制信号，或者根据接收到的所述反向扫描控制电压及所述下级扫描驱动信号产生下拉控制信号；
锁存电路，连接所述输入电路，用于根据所述上拉控制信号对上拉控制信号点进行上拉及根据所述下拉控制信号对所述上拉控制信号点进行下拉；
处理电路，连接所述锁存电路，用于接收时钟信号并根据所述时钟信号及所述上拉控制信号点的信号产生本级扫描驱动信号；
缓存电路，连接所述处理电路，用于驱动所述本级扫描驱动信号的输出；及
复位电路，连接所述锁存电路，用于接收复位信号以对所述上拉控制信号点进行清零。
本发明的有益效果是：区别于现有技术的情况，本发明的所述扫描驱动电路及显示装置通过所述输入电路输出上拉控制信号及下拉控制信号以实现正向扫描及反向扫描驱动方式，通过所述锁存电路对所述上拉控制信号点进行上拉充电或者下拉清零，通过所述处理电路及所述缓存电路产生本级扫描驱动信号，并通过所述复位电路对所述扫描驱动电路进行清零，以此提高显示装置驱动的灵活性，而且降低了驱动功耗且利于窄边框设计。
【附图说明】
图1是本发明扫描驱动电路的第一实施例的电路示意图；
图2是本发明扫描驱动电路的第二实施例的电路示意图；
图3是本发明扫描驱动电路正向扫描的工作时序示意图；
图4是本发明扫描驱动电路反向扫描的工作时序示意图；
图5是本发明扫描驱动电路的驱动框架示意图；
图6是本发明的扫描驱动电路的仿真波形时序示意图；
图7是本发明显示装置的结构示意图。
【具体实施方式】
请参阅图1，是本发明扫描驱动电路的第一实施例的电路示意图。所述扫描驱动电路包括若干级联的扫描驱动单元1，所述若干级联的扫描驱动单元1包括第一级扫描驱动单元、若干中间级扫描驱动单元及最后一级扫描驱动单元，所述第一级扫描驱动单元、每一中间级扫描驱动单元及最后一级扫描驱动单元均包括输入电路10，用于接收正向扫描控制电压U2D或反向扫描控制电压D2U，并根据所述正向扫描控制电压U2D或所述反向扫描控制电压D2U选择性的接收上级扫描驱动信号Gate(n-1)或下级扫描驱动信号Gate(n+1)，以根据接收到的所述正向扫描控制电压U2D及所述上级扫描驱动信号Gate(n-1)产生上拉控制信号H(n)，或者根据接收到的所述反向扫描控制电压D2U及所述下级扫描驱动信号Gate(n+1)产生下拉控制信号L(n)，以使得所述扫描驱动电路实现正向扫描及反向扫描的驱动方式，其中，正向扫描时，所述第一级扫描驱动单元的上级扫描驱动信号为触发信号STV，所述最后一级扫描驱动单元的下级扫描驱动信号为所述触发信号STV；反向扫描时，所述最后一级扫描驱动单元的上级扫描驱动信号为所述触发信号STV，所述第一级扫描驱动单元的下级扫描驱动信号为所述触发信号STV；
锁存电路20，连接所述输入电路10，用于根据所述上拉控制信号H(n)对上拉控制信号点Q(n)进行上拉及根据所述下拉控制信号L(n)对所述上拉控制信号点Q(n)进行下拉；
处理电路30，连接所述锁存电路20，用于接收时钟信号CK并根据所述时钟信号CK及所述上拉控制信号点Q(n)的信号产生本级扫描驱动信号Gate(n)；
缓存电路40，连接所述处理电路30，用于驱动所述本级扫描驱动信号Gate(n)的输出；及
复位电路50，连接所述锁存电路40，用于接收复位信号Reset以对所述上拉控制信号点Q(n)进行清零。
具体地，所述输入电路10包括第一至第四传输门11-14，所述第一及第三传输门11、13的第一控制端及所述第二及第四传输门12、14的第二控制端均连接所述反向扫描控制电压D2U，所述第一及第三传输门11、13的第二控制端及所述第二及第四传输门12、14的第一控制端均连接所述正向扫描控制电压U2D，所述第一及第四传输门11、14的输入端均连接所述上级扫描驱动信号Gate(n-1)，所述第一传输门11的输出端连接所述第二传输门12的输出端及所述锁存电路20，所述第二传输门12的输入端连接所述第三传输门13的输入端并接收所述下级扫描驱动信号Gate(n+1)，所述第三传输门13的输出端连接所述第四传输门14的输出端及所述锁存电路20。
具体地，所述锁存电路20包括第一或非门X1及第二或非门X2，所述第一或非门X1的第一输入端连接所述第一传输门11的输出端，所述第一或非门X1的第二输入端连接所述第二或非门X2的输出端及所述处理电路30，所述第一或非门X1的输出端连接所述第二或非门X2的第一输入端，所述第二或非门X2的第二输入端连接所述第四传输门14的输出端。
具体地，所述处理电路30包括与非门Y1，所述与非门Y1的第一输入端接收所述时钟信号CK，所述与非门Y1的第二输入端连接所述第二或非门X2的输出端，所述与非门Y1的输出端连接所述缓存电路40。
具体地，所述缓存电路40包括第一至第三反相器U1-U3，所述第一反相器U1的输入端连接所述与非门Y1的输出端，所述第二反相器U2的输入端连接所述第一反相器U1的输出端，所述第三反相器U3的输入端连接所述第二反相器U2的输出端，所述第三反相器U3的输出端输出所述本级扫描驱动信号Gate(n)。
具体地，所述复位电路50包括可控开关T1，所述可控开关T1的控制端接收所述复位信号Reset，所述可控开关T1的第一端连接所述第二或非门X2的输出端，所述可控开关T1的第二端连接关闭电压端VGL。
在本实施例中，所述可控开关T1为N型薄膜晶体管，所述可控开关T1的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、源极及漏极。在其他实施例中，所述可控开关T1也可为其他类型的开关，只要能实现本发明的目的即可。
请参阅图2，是本发明扫描驱动电路的第二实施例的电路示意图。所述扫描驱动电路的第二实施例与上述第一实施例的区别之处在于：所述复位电路50包括可控开关T1，所述可控开关T1的控制端接收所述复位信号Reset，所述可控开关T1的第一端连接开启电压端VGH，所述可控开关T1的第二端连接所述第一或非门X1的输出端。
在本实施例中，所述可控开关T1为P型薄膜晶体管，所述可控开关T1的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、源极及漏极。在其他实施例中，所述可控开关T1也可为其他类型的开关，只要能实现本发明的目的即可。
请参阅图3、图5及图6，所述扫描驱动电路正向扫描（即从第一级扫描至最后一级）的工作原理描述如下：（其中，第一级扫描驱动单元的上级扫描驱动信号为触发信号STV，所述第一级扫描驱动单元的下级扫描驱动信号为Gate(n+1)，中间级扫描驱动单元的上级扫描驱动信号为Gate(n-1)，所述中间级扫描驱动单元的下级扫描驱动信号为Gate(n+1)，最后一级扫描驱动单元的上级扫描驱动信号为Gate(n-1)，所述最后一级扫描驱动单元的下级扫描驱动信号为触发信号STV）
正向扫描时，所述正向扫描控制电压U2D为高电平，所述反向扫描控制电压D2U为低电平，此时所述上级扫描驱动信号Gate(n-1)提供给所述输入电路10以使其产生上拉控制信号H(n)，通过所述上拉控制信号H(n)对所述上拉控制信号点Q(n)进行上拉充电，所述下级扫描驱动信号Gate(n+1)提供给所述输入电路10以使其产生下拉控制信号L(n)，通过所述下拉控制信号L(n)对所述上拉控制信号点Q(n)进行下拉清零，在所述扫描驱动电路的第一实施例的电路中，所述复位信号Reset的高电平脉冲为所述上拉控制信号点Q(n)提供复位信号，在所述扫描驱动电路的第二实施例的电路中，所述复位信号Reset的低电平脉冲为所述上拉控制信号点Q(n)提供复位信号。当第一级扫描驱动单元（即n=1）的上级扫描驱动信号即触发信号STV的高电平脉冲来临时，所述上拉控制信号点Q(1)被充电至高电平，在所述下级扫描驱动信号Gate（2）的高电平脉冲信号产生之前，所述上拉控制信号点Q(1)一直维持高电平信号，当时钟信号CK3的高电平脉冲信号来临时，所述本级扫描驱动信号Gate（1）输出高电平脉冲信号，同时，所述本级扫描驱动信号Gate（1）作为下一级扫描驱动单元的上级扫描驱动信号，当所述下级扫描驱动信号Gate（2）的高电平脉冲信号产生后，所述上拉控制信号点Q(1)被下拉清零至低电平信号，所述本级扫描驱动信号Gate（1）稳定输出低电平信号。
当中间级扫描驱动单元如第二级扫描驱动单元（即n=2）的上级扫描驱动信号Gate（1）的高电平脉冲来临时，所述上拉控制信号点Q（2）被充电至高电平，在所述下级扫描驱动信号Gate（3）的高电平脉冲信号产生之前，所述上拉控制信号点Q（2）一直维持高电平信号，当时钟信号CK1的高电平脉冲信号来临时，所述本级扫描驱动信号Gate（2）输出高电平脉冲信号，同时，所述本级扫描驱动信号Gate（2）作为下一级扫描驱动单元的上级扫描驱动信号，当所述下级扫描驱动信号Gate（3）的高电平脉冲信号产生后，所述上拉控制信号点Q（2）被下拉清零至低电平信号，所述本级扫描驱动信号Gate（2）稳定输出低电平信号。
当最后一级扫描驱动单元（即n=1920）的上级扫描驱动信号Gate（1919）的高电平脉冲来临时，所述上拉控制信号点Q（1920）被充电至高电平，在所述下级扫描驱动信号即触发信号STV的高电平脉冲信号产生之前，所述上拉控制信号点Q（1920）一直维持高电平信号，当时钟信号CK1的高电平脉冲信号来临时，所述本级扫描驱动信号Gate（1920）输出高电平脉冲信号，当所述下级扫描驱动信号即触发信号STV的高电平脉冲信号产生后，所述上拉控制信号点Q（1920）被下拉清零至低电平信号，所述本级扫描驱动信号Gate（1920）稳定输出低电平信号。
请参阅图4、图5及图6，所述扫描驱动电路反向扫描（即从最后一级扫描至第一级）的工作原理描述如下：（其中，最后一级扫描驱动单元的上级扫描驱动信号为触发信号STV，所述最后一级扫描驱动单元的下级扫描驱动信号为Gate(n-1)，中间级扫描驱动单元的上级扫描驱动信号为Gate(n+1)，所述中间级扫描驱动单元的下级扫描驱动信号为Gate(n-1)，第一级扫描驱动单元的上级扫描驱动信号为Gate(n+1)，所述第一级扫描驱动单元的下级扫描驱动信号为触发信号STV）
反向扫描时，所述正向扫描控制电压U2D为低电平，所述反向扫描控制电压D2U为高电平，此时所述上级扫描驱动信号Gate(n+1)提供给所述输入电路10以使其产生上拉控制信号H(n)，通过所述上拉控制信号H(n)对所述上拉控制信号点Q(n)进行上拉充电，所述下级扫描驱动信号Gate(n-1)提供给所述输入电路以使其产生下拉控制信号L(n)，通过所述下拉控制信号L(n)对所述上拉控制信号点Q(n)进行下拉清零。在所述扫描驱动电路的第一实施例中，所述复位信号Reset的高电平脉冲为所述上拉控制信号点Q(n)提供复位信号，在所述扫描驱动电路的第二实施例的电路中，所述复位信号Reset的低电平脉冲为所述上拉控制信号点Q(n)提供复位信号。当最后一级扫描驱动单元（即n=1920）的上级扫描驱动信号即触发信号STV的高电平脉冲来临时，所述上拉控制信号点Q（1920）被充电至高电平，在下级扫描驱动信号Gate（1919）的高电平脉冲信号产生之前，所述上拉控制信号点Q（1920）一直维持高电平信号，当时钟信号CK3的高电平脉冲信号来临时，所述本级扫描驱动信号Gate(1920)输出高电平脉冲信号，同时，本级扫描驱动信号Gate(1920)作为倒数第二级扫描驱动单元（即n=1919）的上级扫描驱动信号，当倒数第二级扫描驱动信号Gate(1919)的高电平脉冲信号产生后，所述上拉控制信号点Q(1920)被下拉清零至低电平信号，所述本级扫描驱动信号Gate(1920)稳定输出低电平信号。
当中间级扫描驱动单元如倒数第二级扫描驱动单元（即n=1919）的上级扫描驱动信号Gate（1920）的高电平脉冲来临时，所述上拉控制信号点Q（1919）被充电至高电平，在下级扫描驱动信号Gate（1918）的高电平脉冲信号产生之前，所述上拉控制信号点Q（1919）一直维持高电平信号，当时钟信号CK3的高电平脉冲信号来临时，所述本级扫描驱动信号Gate(1919)输出高电平脉冲信号，同时，本级扫描驱动信号Gate(1919)作为倒数第三级扫描驱动单元（即n=1918）的上级扫描驱动信号，当倒数第三级扫描驱动信号Gate(1918)的高电平脉冲信号产生后，所述上拉控制信号点Q(1919)被下拉清零至低电平信号，所述本级扫描驱动信号Gate(1919)稳定输出低电平信号。
当第一级扫描驱动单元（即n=1）的上级扫描驱动信号Gate（2）的高电平脉冲来临时，所述上拉控制信号点Q（1）被充电至高电平，在下级扫描驱动信号即触发信号STV的高电平脉冲信号产生之前，所述上拉控制信号点Q（1）一直维持高电平信号，当时钟信号CK3的高电平脉冲信号来临时，所述本级扫描驱动信号Gate(1)输出高电平脉冲信号，当下级扫描驱动信号即所述触发信号STV的高电平脉冲信号产生后，所述上拉控制信号点Q(1)被下拉清零至低电平信号，所述本级扫描驱动信号Gate(1)稳定输出低电平信号。
请参阅图5及图6，可以看出其中单边扫描驱动电路需要一根触发信号STV走线，用于第一级或者最后一级扫描驱动单元的输入；单边扫描驱动电路需要一根正向扫描控制电压U2D走线和一根反向扫描控制电压D2U走线，用于所述扫描驱动电路的正反向扫描的控制；单边扫描驱动电路需要两根时钟信号CK走线（其中一条时钟信号走线CK3用于为奇数级扫描驱动单元提供时钟信号，另一条时钟信号走线CK1用于为偶数级扫描驱动单元提供时钟信号），用于扫描驱动信号的产生；单边扫描驱动电路需要一根复位信号Reset走线，用于每一级扫描驱动单元的复位处理；单边扫描驱动电路需要一条开启电压端VGH走线和一条关闭电压端VGL走线，用于所述扫描驱动电路的电源驱动。通过图6的信号波形可以看出所述扫描驱动电路能够很好的进行工作。
请参阅图7，是本发明显示装置的结构示意图。所述显示装置包括上述扫描驱动电路，所述显示装置的其他元件及功能与现有显示装置相同，在此不再赘述。
所述扫描驱动电路及显示装置通过所述输入电路输出上拉控制信号及下拉控制信号以实现正反向扫描控制，通过所述锁存电路对所述上拉控制信号点进行上拉充电或者下拉清零，通过所述处理电路及所述缓存电路产生本级扫描驱动信号，并通过所述复位电路对所述扫描驱动电路进行清零，以此提高显示装置驱动的灵活性，而且降低了驱动功耗。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种扫描驱动电路，其中，所述扫描驱动电路包括若干级联的扫描驱动单元，所述若干级联的扫描驱动单元包括第一级扫描驱动单元、若干中间级扫描驱动单元及最后一级扫描驱动单元，所述第一级扫描驱动单元、每一中间级扫描驱动单元及最后一级扫描驱动单元均包括：
    输入电路，用于接收正向扫描控制电压或反向扫描控制电压，并根据所述正向扫描控制电压或所述反向扫描控制电压选择性的接收上级扫描驱动信号或下级扫描驱动信号，以根据接收到的所述正向扫描控制电压及所述上级扫描驱动信号产生上拉控制信号，或者根据接收到的所述反向扫描控制电压及所述下级扫描驱动信号产生下拉控制信号；
    锁存电路，连接所述输入电路，用于根据所述上拉控制信号对上拉控制信号点进行上拉及根据所述下拉控制信号对所述上拉控制信号点进行下拉；
    处理电路，连接所述锁存电路，用于接收时钟信号并根据所述时钟信号及所述上拉控制信号点的信号产生本级扫描驱动信号；
    缓存电路，连接所述处理电路，用于驱动所述本级扫描驱动信号的输出；及
    复位电路，连接所述锁存电路，用于接收复位信号以对所述上拉控制信号点进行清零。
  2. 根据权利要求1所述的扫描驱动电路，其中，所述输入电路包括第一至第四传输门，所述第一及第三传输门的第一控制端及所述第二及第四传输门的第二控制端均连接所述反向扫描控制电压，所述第一及第三传输门的第二控制端及所述第二及第四传输门的第一控制端均连接所述正向扫描控制电压，所述第一及第四传输门的输入端均连接所述上级扫描驱动信号，所述第一传输门的输出端连接所述第二传输门的输出端及所述锁存电路，所述第二传输门的输入端连接所述第三传输门的输入端并接收所述下级扫描驱动信号，所述第三传输门的输出端连接所述第四传输门的输出端及所述锁存电路。
  3. 根据权利要求2所述的扫描驱动电路，其中，所述锁存电路包括第一或非门及第二或非门，所述第一或非门的第一输入端连接所述第一传输门的输出端，所述第一或非门的第二输入端连接所述第二或非门的输出端及所述处理电路，所述第一或非门的输出端连接所述第二或非门的第一输入端，所述第二或非门的第二输入端连接所述第四传输门的输出端。
  4. 根据权利要求3所述的扫描驱动电路，其中，所述处理电路包括与非门，所述与非门的第一输入端接收所述时钟信号，所述与非门的第二输入端连接所述第二或非门的输出端，所述与非门的输出端连接所述缓存电路。
  5. 根据权利要求4所述的扫描驱动电路，其中，所述缓存电路包括第一至第三反相器，所述第一反相器的输入端连接所述与非门的输出端，所述第二反相器的输入端连接所述第一反相器的输出端，所述第三反相器的输入端连接所述第二反相器的输出端，所述第三反相器的输出端输出所述本级扫描驱动信号。
  6. 根据权利要求3所述的扫描驱动电路，其中，所述复位电路包括可控开关，所述可控开关的控制端接收所述复位信号，所述可控开关的第一端连接所述第二或非门的输出端，所述可控开关的第二端连接关闭电压端。
  7. 根据权利要求6所述的扫描驱动电路，其中，所述可控开关为N型薄膜晶体管，所述可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、源极及漏极。
  8. 根据权利要求3所述的扫描驱动电路，其中，所述复位电路包括可控开关，所述可控开关的控制端接收所述复位信号，所述可控开关的第一端连接开启电压端，所述可控开关的第二端连接所述第一或非门的输出端。
  9. 根据权利要求8所述的扫描驱动电路，其中，所述可控开关为P型薄膜晶体管，所述可控开关的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、源极及漏极。
  10. 一种显示装置，其中，所述显示装置包括扫描驱动电路，所述扫描驱动电路包括若干级联的扫描驱动单元，所述若干级联的扫描驱动单元包括第一级扫描驱动单元、若干中间级扫描驱动单元及最后一级扫描驱动单元，所述第一级扫描驱动单元、每一中间级扫描驱动单元及最后一级扫描驱动单元均包括：
    输入电路，用于接收正向扫描控制电压或反向扫描控制电压，并根据所述正向扫描控制电压或所述反向扫描控制电压选择性的接收上级扫描驱动信号或下级扫描驱动信号，以根据接收到的所述正向扫描控制电压及所述上级扫描驱动信号产生上拉控制信号，或者根据接收到的所述反向扫描控制电压及所述下级扫描驱动信号产生下拉控制信号；
    锁存电路，连接所述输入电路，用于根据所述上拉控制信号对上拉控制信号点进行上拉及根据所述下拉控制信号对所述上拉控制信号点进行下拉；
    处理电路，连接所述锁存电路，用于接收时钟信号并根据所述时钟信号及所述上拉控制信号点的信号产生本级扫描驱动信号；
    缓存电路，连接所述处理电路，用于驱动所述本级扫描驱动信号的输出；及
    复位电路，连接所述锁存电路，用于接收复位信号以对所述上拉控制信号点进行清零。
  11. 根据权利要求10所述的显示装置，其中，所述输入电路包括第一至第四传输门，所述第一及第三传输门的第一控制端及所述第二及第四传输门的第二控制端均连接所述反向扫描控制电压，所述第一及第三传输门的第二控制端及所述第二及第四传输门的第一控制端均连接所述正向扫描控制电压，所述第一及第四传输门的输入端均连接所述上级扫描驱动信号，所述第一传输门的输出端连接所述第二传输门的输出端及所述锁存电路，所述第二传输门的输入端连接所述第三传输门的输入端并接收所述下级扫描驱动信号，所述第三传输门的输出端连接所述第四传输门的输出端及所述锁存电路。
  12. 根据权利要求11所述的显示装置，其中，所述锁存电路包括第一或非门及第二或非门，所述第一或非门的第一输入端连接所述第一传输门的输出端，所述第一或非门的第二输入端连接所述第二或非门的输出端及所述处理电路，所述第一或非门的输出端连接所述第二或非门的第一输入端，所述第二或非门的第二输入端连接所述第四传输门的输出端。
  13. 根据权利要求12所述的显示装置，其中，所述处理电路包括与非门，所述与非门的第一输入端接收所述时钟信号，所述与非门的第二输入端连接所述第二或非门的输出端，所述与非门的输出端连接所述缓存电路。
  14. 根据权利要求13所述的显示装置，其中，所述缓存电路包括第一至第三反相器，所述第一反相器的输入端连接所述与非门的输出端，所述第二反相器的输入端连接所述第一反相器的输出端，所述第三反相器的输入端连接所述第二反相器的输出端，所述第三反相器的输出端输出所述本级扫描驱动信号。
  15. 根据权利要求12所述的显示装置，其中，所述复位电路包括可控开关，所述可控开关的控制端接收所述复位信号，所述可控开关的第一端连接所述第二或非门的输出端，所述可控开关的第二端连接关闭电压端。
  16. 根据权利要求15所述的显示装置，其中，所述可控开关为N型薄膜晶体管，所述可控开关的控制端、第一端及第二端分别对应所述N型薄膜晶体管的栅极、源极及漏极。
  17. 根据权利要求12所述的显示装置，其中，所述复位电路包括可控开关，所述可控开关的控制端接收所述复位信号，所述可控开关的第一端连接开启电压端，所述可控开关的第二端连接所述第一或非门的输出端。
  18. 根据权利要求17所述的显示装置，其中，所述可控开关为P型薄膜晶体管，所述可控开关的控制端、第一端及第二端分别对应所述P型薄膜晶体管的栅极、源极及漏极。
PCT/CN2017/107175 2017-09-27 2017-10-21 扫描驱动电路及显示装置 WO2019061604A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/735,924 US10650767B2 (en) 2017-09-27 2017-10-21 Scan-driving circuit and a display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710896670.X 2017-09-27
CN201710896670.XA CN107424582B (zh) 2017-09-27 2017-09-27 扫描驱动电路及显示装置

Publications (1)

Publication Number Publication Date
WO2019061604A1 true WO2019061604A1 (zh) 2019-04-04

Family

ID=60435947

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/107175 WO2019061604A1 (zh) 2017-09-27 2017-10-21 扫描驱动电路及显示装置

Country Status (3)

Country Link
US (1) US10650767B2 (zh)
CN (1) CN107424582B (zh)
WO (1) WO2019061604A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108735163B (zh) 2018-05-30 2020-11-17 京东方科技集团股份有限公司 用于阵列基板行驱动单元的或逻辑运算电路
CN112382226B (zh) * 2020-11-27 2022-04-26 Tcl华星光电技术有限公司 数据驱动芯片以及显示装置
WO2022188018A1 (zh) * 2021-03-09 2022-09-15 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动器以及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130127807A1 (en) * 2011-11-18 2013-05-23 Yong-Jae Kim Scan driver and driving method thereof
CN104505014A (zh) * 2014-12-31 2015-04-08 厦门天马微电子有限公司 一种驱动电路、阵列基板和触控显示装置及其驱动方法
CN105355179A (zh) * 2015-12-03 2016-02-24 武汉华星光电技术有限公司 一种扫描驱动电路及其显示装置
CN105427821A (zh) * 2015-12-25 2016-03-23 武汉华星光电技术有限公司 适用于In Cell型触控显示面板的GOA电路
CN105702223A (zh) * 2016-04-21 2016-06-22 武汉华星光电技术有限公司 减小时钟信号负载的cmos goa电路
CN106157898A (zh) * 2016-06-28 2016-11-23 厦门天马微电子有限公司 一种扫描电路、栅极驱动电路及显示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103236272B (zh) * 2013-03-29 2016-03-16 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动装置与显示装置
TWI512703B (zh) * 2014-03-06 2015-12-11 Au Optronics Corp 移位暫存電路及移位暫存器
CN104269132B (zh) * 2014-10-29 2016-08-03 京东方科技集团股份有限公司 一种移位寄存单元、显示面板和显示装置
CN104361875B (zh) * 2014-12-02 2017-01-18 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN104575429A (zh) * 2015-01-30 2015-04-29 合肥京东方光电科技有限公司 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
CN104700806B (zh) * 2015-03-26 2017-01-25 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置
CN104732940B (zh) * 2015-03-30 2017-03-15 深圳市华星光电技术有限公司 Cmos栅极驱动电路
CN104966480B (zh) * 2015-07-21 2017-08-25 京东方科技集团股份有限公司 阵列基板行驱动电路单元、驱动电路和显示面板
US9824658B2 (en) * 2015-09-22 2017-11-21 Shenzhen China Star Optoelectronics Technology Co., Ltd GOA circuit and liquid crystal display device
CN105244003B (zh) * 2015-11-12 2018-01-09 深圳市华星光电技术有限公司 栅极驱动电路以及移位寄存电路
CN106057131B (zh) * 2016-05-27 2018-11-23 武汉华星光电技术有限公司 扫描驱动电路及具有该电路的平面显示装置
US20170358266A1 (en) * 2016-06-13 2017-12-14 Wuhan China Star Optoelectronics Technology Co., Ltd. Goa circuit and liquid crystal display
CN106297629B (zh) * 2016-08-22 2018-06-15 武汉华星光电技术有限公司 扫描驱动电路及具有该电路的平面显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130127807A1 (en) * 2011-11-18 2013-05-23 Yong-Jae Kim Scan driver and driving method thereof
CN104505014A (zh) * 2014-12-31 2015-04-08 厦门天马微电子有限公司 一种驱动电路、阵列基板和触控显示装置及其驱动方法
CN105355179A (zh) * 2015-12-03 2016-02-24 武汉华星光电技术有限公司 一种扫描驱动电路及其显示装置
CN105427821A (zh) * 2015-12-25 2016-03-23 武汉华星光电技术有限公司 适用于In Cell型触控显示面板的GOA电路
CN105702223A (zh) * 2016-04-21 2016-06-22 武汉华星光电技术有限公司 减小时钟信号负载的cmos goa电路
CN106157898A (zh) * 2016-06-28 2016-11-23 厦门天马微电子有限公司 一种扫描电路、栅极驱动电路及显示装置

Also Published As

Publication number Publication date
US10650767B2 (en) 2020-05-12
CN107424582B (zh) 2019-08-30
CN107424582A (zh) 2017-12-01
US20190385554A1 (en) 2019-12-19

Similar Documents

Publication Publication Date Title
WO2018035995A1 (zh) 扫描驱动电路
WO2017049661A1 (zh) 扫描驱动电路及具有该电路的液晶显示装置
WO2016165162A1 (zh) 一种goa电路及液晶显示器
WO2011095099A1 (zh) 栅极驱动电路单元、栅极驱动电路及显示装置
WO2018120330A1 (zh) 栅极驱动电路以及液晶显示装置
WO2018218718A1 (zh) 双向移位寄存器单元、双向移位寄存器及显示面板
WO2018094807A1 (zh) Goa驱动电路及液晶显示装置
WO2016037381A1 (zh) 基于igzo制程的栅极驱动电路
WO2016095267A1 (zh) 移位寄存器、级传栅极驱动电路及显示面板
WO2016106803A1 (zh) 用于液晶显示装置的goa电路
WO2018018724A1 (zh) 扫描驱动电路及具有该电路的平面显示装置
WO2018023859A1 (zh) 扫描驱动电路及具有该电路的平面显示装置
JPH1185111A (ja) 液晶表示素子
WO2018072303A1 (zh) Goa驱动电路及液晶显示装置
WO2018223519A1 (zh) Goa驱动电路及液晶显示器
WO2019010810A1 (zh) 一种goa电路及液晶显示器
WO2017049660A1 (zh) 扫描驱动电路及具有该电路的液晶显示装置
WO2016106925A1 (zh) 与非门锁存的驱动电路以及与非门锁存的移位寄存器
WO2018120286A1 (zh) 一种驱动电路及显示面板
WO2022007147A1 (zh) Goa电路以及显示面板
WO2019061604A1 (zh) 扫描驱动电路及显示装置
KR20070002412A (ko) 액정표시장치의 아날로그 샘플링 장치
WO2018045625A1 (zh) 平面显示装置及其扫描驱动电路
WO2019010816A1 (zh) 一种goa电路及液晶显示器
WO2017197684A1 (zh) 基于ltps半导体薄膜晶体管的goa电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17927744

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17927744

Country of ref document: EP

Kind code of ref document: A1