WO2016106815A1 - 显示装置及其栅极驱动电路 - Google Patents

显示装置及其栅极驱动电路 Download PDF

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WO2016106815A1
WO2016106815A1 PCT/CN2015/070440 CN2015070440W WO2016106815A1 WO 2016106815 A1 WO2016106815 A1 WO 2016106815A1 CN 2015070440 W CN2015070440 W CN 2015070440W WO 2016106815 A1 WO2016106815 A1 WO 2016106815A1
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transistor
gate
level
drain
circuit
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PCT/CN2015/070440
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English (en)
French (fr)
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郝思坤
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深圳市华星光电技术有限公司
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Priority to US14/433,662 priority Critical patent/US20160189658A1/en
Publication of WO2016106815A1 publication Critical patent/WO2016106815A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a display device and a gate driving circuit thereof.
  • the GOA (Gate Driver On Array) circuit is a driving method in which a gate scanning driving circuit is fabricated on an Array substrate by using an Array process of a conventional liquid crystal display to realize progressive scanning. It has the advantages of reduced production costs and a narrow bezel design for use with a variety of displays.
  • the GOA circuit has two basic functions: the first is to input the gate drive signal, drive the gate line in the panel, open the TFT (Thin Film Transistor) in the display area, and perform pixel-by-gate on the gate line. Charging; the second is shift register, after the output of the nth gate drive signal is completed, the output of n+1 gate drive signals can be output by clock control, and then transmitted.
  • the GOA circuit includes a pull-up circuit, a pull-up control circuit, a pull-down circuit, a pull-down control circuit, and an increase in potential rise.
  • Boost circuit Specifically, the pull-up circuit is mainly responsible for outputting an input clock signal (Clock) to the gate of the thin film transistor as a driving signal of the liquid crystal display.
  • the pull-up control circuit is responsible for controlling the opening of the pull-up circuit, which is generally a signal transmitted by the upper-level GOA circuit.
  • the pull-down circuit is responsible for quickly pulling the scan signal low to low after the output of the scan signal, that is, the potential of the gate of the thin film transistor is pulled low to a low potential;
  • the pull-down hold circuit is responsible for the signal of the scan signal and the pull-up circuit (commonly called For Q point) to remain in the off state (ie set negative potential), there are usually two pull-down holding circuits alternated.
  • the rising circuit is responsible for the secondary rise of the Q point potential, thus ensuring the normal output of the G(N) of the pull-up circuit.
  • the LTPS Low Temperature Poly-silicon
  • CMOS Complementary Metal Oxide Semiconductor
  • CMOS Complementary Metal Oxide Semiconductor
  • Embodiments of the present invention provide a display device and a gate driving circuit thereof, which are suitable for a CMOS process and increase circuit stability.
  • the present invention provides a gate driving circuit including a plurality of shift register circuits, the plurality of shift register circuits being cascaded in series, each shift register circuit comprising: a first pull-up circuit including first a transistor, a gate and a source of the first transistor are connected to a gate drive signal of the previous stage; a second pull-up circuit includes a second transistor, and a gate of the second transistor is connected to a drain of the first transistor, the source The pole is connected to the first clock signal, the drain is connected to the gate drive signal output end; the first capacitor is connected between the drain and the gate of the second transistor; and the first pull-down circuit includes a third transistor, a source of the third transistor is coupled to the output of the gate drive signal, and a drain is coupled to the first level; a second pull-down circuit includes a fourth transistor, the source of the fourth transistor being coupled to the drain of the first transistor, The drain is connected to the first level; the pull-down control circuit is coupled to the gate driving signal of the previous stage, the gate driving signal of
  • the shift register circuit further includes a second capacitor, one end of the second capacitor is connected to the first level, and the other end of the second capacitor is connected to the gate of the third transistor and the gate of the fourth transistor.
  • the pull-down control circuit includes: a fifth transistor, a gate of the fifth transistor is connected to a gate driving signal of the previous stage, a source is connected to the first level, a gate of the drain and the third transistor, and a fourth transistor a gate connection; a sixth transistor, a gate of the sixth transistor is connected to a gate driving signal of the previous stage, a source is connected to the first level; and a seventh transistor, a gate of the seventh transistor and a sixth transistor a drain connection, a source connected to the second level, a drain connected to the drain of the fifth transistor, a third capacitor connected between the source and the gate of the seventh transistor, and an eighth transistor The gate of the eight transistor is connected to the gate drive signal of the latter stage, the source is connected to the drain of the sixth transistor, and the drain is connected to the second level.
  • the first level is a high level and the second level is a low level.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all P-type MOS transistors.
  • the present invention also provides a display device comprising a liquid crystal display panel and a gate driving circuit, the gate driving circuit being connected to the liquid crystal display panel for providing a scanning driving signal for the liquid crystal display panel, the gate driving circuit comprising a plurality of shifts a register circuit, the plurality of shift register circuits are cascaded in series, each shift register circuit includes: a first pull-up circuit including a first transistor, a gate and a source of the first transistor and a previous stage a gate drive signal is connected; a second pull-up circuit includes a second transistor, a gate of the second transistor is connected to a drain of the first transistor, a source is connected to the first clock signal, and a drain and a gate drive signal are output
  • the first capacitor is connected between the drain and the gate of the second transistor;
  • the first pull-down circuit includes a third transistor, and the source of the third transistor is connected to the output of the gate driving signal, and the drain
  • the pole is connected to the first level;
  • the second pull-down circuit includes
  • the shift register circuit further includes a second capacitor, one end of the second capacitor is connected to the first level, and the other end of the second capacitor is connected to the gate of the third transistor and the gate of the fourth transistor.
  • the pull-down control circuit includes: a fifth transistor, a gate of the fifth transistor is connected to a gate driving signal of the previous stage, a source is connected to the first level, a gate of the drain and the third transistor, and a fourth transistor a gate connection; a sixth transistor, a gate of the sixth transistor is connected to a gate driving signal of the previous stage, a source is connected to the first level; and a seventh transistor, a gate of the seventh transistor and a sixth transistor a drain connection, a source connected to the second level, a drain connected to the drain of the fifth transistor, a third capacitor connected between the source and the gate of the seventh transistor, and an eighth transistor The gate of the eight transistor is connected to the gate drive signal of the latter stage, the source is connected to the drain of the sixth transistor, and the drain is connected to the second level.
  • the first level is a high level and the second level is a low level.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are all P-type MOS transistors.
  • the beneficial effect of the present invention is that the pull-down control circuit of the present invention is coupled to the gate driving signal of the previous stage, the gate driving signal of the subsequent stage, the gate of the third transistor, and the gate of the fourth transistor. a pole, a first level, and a second level, the pull-down control circuit controls the third transistor and the fourth transistor according to the gate driving signal of the previous stage and the gate driving signal of the subsequent stage, is suitable for the CMOS process, and adds the circuit stability.
  • FIG. 1 is a schematic structural view of a gate driving circuit according to an embodiment of the present invention.
  • Figure 2 is a circuit diagram of the shift register circuit shown in Figure 1;
  • FIG. 3 is an analog timing diagram of the gate driving circuit shown in FIG. 1;
  • FIG. 4 is a schematic structural view of a display device according to an embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
  • the gate driving circuit 10 disclosed in this embodiment includes a plurality of shift register circuits 11, and a plurality of shift register circuits 11 are cascaded in series.
  • the shift register circuit 11 includes a first pull-up circuit 111, a second pull-up circuit 112, a first pull-down circuit 113, a second pull-down circuit 114, a pull-down control circuit 115, and a first capacitor C1.
  • the first pull-up circuit 111 includes a first transistor T1, the gate and the source of the first transistor T1 are connected to the gate drive signal G(n-1) of the previous stage; and the second pull-up circuit 112 includes the second The transistor T2, the gate of the second transistor T2 is connected to the drain of the first transistor T1, the source of the second transistor T2 is connected to the first clock signal CK, and the drain of the second transistor T2 is connected to the gate driving signal output G.
  • the first capacitor C1 is connected between the gate and the drain of the second transistor T2;
  • the first pull-down circuit 113 includes a third transistor T3, the source of the third transistor T3 is connected to the gate driving signal output terminal G(n), the drain of the third transistor T3 is connected to the first level Vgh, and the second pull-down circuit 114 includes the fourth transistor T4, the fourth The source of the transistor T4 is connected to the drain of the first transistor T1, the drain of the fourth transistor T4 is connected to the first level Vgh; one end of the second capacitor C2 is connected to the first level Vgh, and the second capacitor C2 is One end is connected to the gate of the third transistor T3 and the gate of the fourth transistor T4; the pull-down control circuit 115 is coupled to the gate driving signal G(n-1) of the previous stage and the gate driving signal G of the subsequent stage.
  • the gate of the third transistor T3, the gate of the fourth transistor T4, the first level Vgh, and the second level Vgl, and the pull-down control circuit 115 according to the gate drive signal G(n) of the previous stage -1) and the gate drive signal G(n+1) of the subsequent stage controls the operation of the third transistor T3 and the fourth transistor T4, that is, controls the third transistor T3 and the fourth transistor T4 to be turned on or off.
  • the pull-down control circuit 115 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.
  • the gate of the fifth transistor T5 is connected to the gate driving signal G(n-1) of the previous stage, the source of the fifth transistor T5 is connected to the first level Vgh, and the drain of the fifth transistor T5 is connected to the third transistor.
  • the gate of T3 is connected to the gate of the fourth transistor T4; the gate of the sixth transistor T6 is connected to the gate drive signal G(n-1) of the previous stage, and the source of the sixth transistor T6 is at the first level Vgh is connected; the gate of the seventh transistor T7 is connected to the drain of the sixth transistor T6, the source of the seventh transistor T7 is connected to the second level Vgl, the drain of the seventh transistor T7 and the drain of the fifth transistor T5 Connected, the third capacitor C3 is connected between the source and the gate of the seventh transistor T7; the gate of the eighth transistor T8 is connected to the gate drive signal G(n+1) of the subsequent stage, and the eighth transistor T8 is connected The source is connected to the drain of the sixth transistor T6, and the drain of the eighth transistor T8 is connected to the second level Vgl.
  • the first level Vgh is preferably a high level
  • the second level Vgl is preferably a low level.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all P-type MOS transistors, in other embodiments Those skilled in the art can also set the above transistors as other field effect transistors, such as N-type MOS tubes.
  • the gate driving signal G(n-1) of the previous stage is at a low level, the first transistor T1 is turned on, the first clock signal CK is at a high level, and the gate of the second transistor T2 is low.
  • Level, the second transistor T2 is turned on; the fifth transistor T5 and the sixth transistor T6 are both turned on, the gate of the seventh transistor T7 and the eighth transistor T
  • the source of 8 is high level, then the seventh transistor T7 is turned off, the gate driving signal G(n+1) of the latter stage is high level, the eighth transistor T8 is turned off; the gate of the third transistor T3 is turned off
  • the gates of the poles and the fourth transistor T4 are both at a high level, and the third transistor T3 and the fourth transistor T4 are both turned off; therefore, the signal output from the gate driving signal output terminal G(n) and the first clock signal CK
  • the signal output from the gate drive signal output terminal G(n) is at a high level.
  • the gate drive signal G(n-1) of the previous stage changes from a low level to a high level, the first transistor T1 is turned off, and the first clock signal CK is changed from a high level to a low level.
  • the second transistor T2 is turned on; the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are both turned off, the gate driving signal G(n+1) of the subsequent stage is high level, and the eighth transistor T8 Disconnected, the third transistor T3 and the fourth transistor T4 are both turned off; therefore, the signal outputted by the gate driving signal output terminal G(n) is the same as the first clock signal CK, that is, the gate driving signal output terminal G(n) The output signal changes from high to low.
  • the gate drive signal G(n-1) of the previous stage is at a high level
  • the first transistor T1 is turned off
  • the first clock signal CK is at a low level
  • the second transistor T2 is turned on
  • the five transistors T5, the sixth transistor T6 and the seventh transistor T7 are both turned off
  • the gate drive signal G(n+1) of the latter stage is at a high level
  • the eighth transistor T8 is turned off
  • the third transistor T3 and the fourth transistor are turned off.
  • the transistor T4 is turned off; therefore, the signal output from the gate drive signal output terminal G(n) is the same as the first clock signal CK, that is, the signal output from the gate drive signal output terminal G(n) is at a low level.
  • the gate driving signal G(n-1) of the previous stage is at a high level
  • the first transistor T1 is turned off
  • the first clock signal CK is changed from a low level to a high level
  • the second transistor T2 is turned off.
  • the fifth transistor T5 and the sixth transistor T6 are turned off
  • the gate driving signal G(n+1) of the subsequent stage is changed from a high level to a low level
  • the eighth transistor T8 is turned on
  • the seventh transistor is turned on.
  • T7 is turned on, the gate of the third transistor T3 and the gate of the fourth transistor T4 are both low, and the third transistor T3 and the fourth transistor T4 are turned on, and the gate driving signal output terminal G(n) outputs The signal continues to be high.
  • the pull-down control circuit 115 is coupled to the gate drive signal G(n-1) of the previous stage, the gate drive signal (n+1) of the subsequent stage, the gate of the third transistor T3, and the fourth The gate of the transistor T4, the first level Vgh, and the second level Vgl, the pull-down control circuit 115 according to the gate drive signal G(n-1) of the previous stage and the gate drive signal of the subsequent stage (n+1)
  • the third transistor T3 and the fourth transistor T4 are controlled to be suitable for a CMOS process, and circuit stability is increased to reduce the number of clock signals.
  • the present invention further provides a display device.
  • the display device 20 disclosed in the embodiment includes a liquid crystal display panel 21 and a gate driving circuit 22, and the gate driving circuit 22 is connected to the liquid crystal display panel 21, and the gate is The driving circuit 22 is configured to provide a scanning driving signal for the liquid crystal display panel 21.
  • the gate driving circuit 22 is the gate driving circuit 10 disclosed in the above embodiment, and details are not described herein again.
  • the pull-down control circuit of the present invention is coupled to the gate driving signal of the previous stage, the gate driving signal of the subsequent stage, the gate of the third transistor, the gate of the fourth transistor, and the first level. And a second level, the pull-down control circuit controls the third transistor and the fourth transistor according to the gate driving signal of the previous stage and the gate driving signal of the subsequent stage, is suitable for the CMOS process, and increases circuit stability.

Abstract

一种显示装置（20）及其栅极驱动电路（10,22）。该栅极驱动电路（10,22）包括多个移位寄存电路（11），多个移位寄存电路（11）以串联方式进行级联，每一移位寄存电路（11）包括：第一上拉电路（111）；第二上拉电路（112）；第一电容（C1）；第一下拉电路（113），其包括第三晶体管（T3）；第二下拉电路（114），其包括第四晶体管（T4）；下拉控制电路（115），其耦接于前一级的栅极驱动信号（G（n-1））、后一级的栅极驱动信号（G（n+1））、第三晶体管（T3）的栅极、第四晶体管（T4）的栅极、第一电平（Vgh）以及第二电平（Vgl），下拉控制电路（115）根据前一级的栅极驱动信号（G（n-1））和后一级的栅极驱动信号（G（n+1））控制第三晶体管（T3）和第四晶体管（T4）。通过以上方式，能够适用于CMOS制程，并且增加电路稳定性。

Description

显示装置及其栅极驱动电路 【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种显示装置及其栅极驱动电路。
【背景技术】
GOA(Gate Driver On Array)电路是利用现有的液晶显示器的Array制程将栅极扫描驱动电路制作在Array基板上，以实现逐行扫描的驱动方式。其具有降低生产成本和窄边框设计的优点，为多种显示器所使用。GOA电路要具有两项基本功能：第一是输入栅极驱动信号，驱动面板内的栅极线，打开显示区内的TFT(Thin Film Transistor，薄膜场效应晶体管)，由栅极线对像素进行充电；第二是移位寄存，当第n个栅极驱动信号输出完成后，可以通过时钟控制进行n+1个栅极驱动信号的输出，并依此传递下去。
GOA电路包括上拉电路(Pull-up circuit)、上拉控制电路(Pull-up control circuit)、下拉电路(Pull-down circuit)、下拉控制电路(Pull-down control circuit)以及负责电位抬升的上升电路(Boost circuit)。具体地，上拉电路主要负责将输入的时钟讯号(Clock)输出至薄膜晶体管的栅极，作为液晶显示器的驱动信号。上拉控制电路负责控制上拉电路的打开，一般是由上级GOA电路传递来的信号作用。下拉电路负责在输出扫描信号后，快速将扫描信号拉低为低电位，即薄膜晶体管的栅极的电位拉低为低电位；下拉保持电路则负责将扫描信号和上拉电路的信号(通常称为Q点)保持在关闭状态(即设定的负电位)，通常有两个下拉保持电路交替作用。上升电路则负责Q点电位的二次抬升，这样确保上拉电路的G(N)正常输出。
不同的GOA电路可以使用不同的制程。LTPS(LoW Temperature Poly-silicon，低温多晶硅)制程具有高电子迁移率和技术成熟的优点，目前被中小尺寸显示器广泛使用。CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)LTPS制程具有低功耗、电子迁移率高、噪声容限宽等优点，因此逐渐为面板厂商使用，如此需要开发与CMOS LTPS制程对应的GOA电路。
【发明内容】
本发明实施例提供了一种显示装置及其栅极驱动电路，以适用于CMOS制程，并且增加电路稳定性。
本发明提供一种栅极驱动电路，其包括多个移位寄存电路，多个移位寄存电路以串联方式进行级联，每一移位寄存电路包括：第一上拉电路，其包括第一晶体管，第一晶体管的栅极和源极与前一级的栅极驱动信号连接；第二上拉电路，其包括第二晶体管，第二晶体管的栅极与第一晶体管的漏极连接，源极与第一时钟信号连接，漏极与栅极驱动信号输出端连接；第一电容，其连接在第二晶体管的漏极和栅极之间；第一下拉电路，其包括第三晶体管，第三晶体管的源极与栅极驱动信号输出端连接，漏极与第一电平连接；第二下拉电路，其包括第四晶体管，第四晶体管的源极与第一晶体管的漏极连接，漏极与第一电平连接；下拉控制电路，其耦接于前一级的栅极驱动信号、后一级的栅极驱动信号、第三晶体管的栅极、第四晶体管的栅极、第一电平以及第二电平，下拉控制电路根据前一级的栅极驱动信号和后一级的栅极驱动信号控制第三晶体管和第四晶体管。
其中，移位寄存电路还包括第二电容，第二电容的一端与第一电平连接，第二电容的另二端与第三晶体管的栅极和第四晶体管的栅极连接。
其中，下拉控制电路包括：第五晶体管，第五晶体管的栅极与前一级的栅极驱动信号连接，源极与第一电平连接，漏极与第三晶体管的栅极和第四晶体管的栅极连接；第六晶体管，第六晶体管的栅极与前一级的栅极驱动信号连接，源极与第一电平连接；第七晶体管，第七晶体管的栅极与第六晶体管的漏极连接，源极与第二电平连接，漏极与第五晶体管的漏极连接；第三电容，第三电容连接在第七晶体管的源极和栅极之间；第八晶体管，第八晶体管的栅极与后一级的栅极驱动信号连接，源极与第六晶体管的漏极连接，漏极与第二电平连接。
其中，第一电平为高电平，第二电平为低电平。
其中，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管以及第八晶体管均为P型MOS管。
本发明还提供一种显示装置，其包括液晶显示面板和栅极驱动电路，栅极驱动电路与液晶显示面板连接，用于为液晶显示面板提供扫描驱动信号，栅极驱动电路包括多个移位寄存电路，多个移位寄存电路以串联方式进行级联，每一移位寄存电路包括：第一上拉电路，其包括第一晶体管，第一晶体管的栅极和源极与前一级的栅极驱动信号连接；第二上拉电路，其包括第二晶体管，第二晶体管的栅极与第一晶体管的漏极连接，源极与第一时钟信号连接，漏极与栅极驱动信号输出端连接；第一电容，其连接在第二晶体管的漏极和栅极之间；第一下拉电路，其包括第三晶体管，第三晶体管的源极与栅极驱动信号输出端连接，漏极与第一电平连接；第二下拉电路，其包括第四晶体管，第四晶体管的源极与第一晶体管的漏极连接，漏极与第一电平连接；下拉控制电路，其耦接于前一级的栅极驱动信号、后一级的栅极驱动信号、第三晶体管的栅极、第四晶体管的栅极、第一电平以及第二电平，下拉控制电路根据前一级的栅极驱动信号和后一级的栅极驱动信号控制第三晶体管和第四晶体管。
其中，移位寄存电路还包括第二电容，第二电容的一端与第一电平连接，第二电容的另二端与第三晶体管的栅极和第四晶体管的栅极连接。
其中，下拉控制电路包括：第五晶体管，第五晶体管的栅极与前一级的栅极驱动信号连接，源极与第一电平连接，漏极与第三晶体管的栅极和第四晶体管的栅极连接；第六晶体管，第六晶体管的栅极与前一级的栅极驱动信号连接，源极与第一电平连接；第七晶体管，第七晶体管的栅极与第六晶体管的漏极连接，源极与第二电平连接，漏极与第五晶体管的漏极连接；第三电容，第三电容连接在第七晶体管的源极和栅极之间；第八晶体管，第八晶体管的栅极与后一级的栅极驱动信号连接，源极与第六晶体管的漏极连接，漏极与第二电平连接。
其中，第一电平为高电平，第二电平为低电平。
其中，第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管以及第八晶体管均为P型MOS管。
通过上述方案，本发明的有益效果是：本发明的下拉控制电路耦接于前一级的栅极驱动信号、后一级的栅极驱动信号、第三晶体管的栅极、第四晶体管的栅 极、第一电平以及第二电平，下拉控制电路根据前一级的栅极驱动信号和后一级的栅极驱动信号控制第三晶体管和第四晶体管，适用于CMOS制程，并且增加电路稳定性。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明一实施例的栅极驱动电路的结构示意图；
图2是图1所示的移位寄存电路的电路图；
图3是图1所示的栅极驱动电路的模拟时序图；
图4是本发明一实施例的显示装置的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1所示，图1是本发明一实施例的栅极驱动电路的结构示意图。如图1所示，本实施例所揭示的栅极驱动电路10包括多个移位寄存电路11，多个移位寄存电路11以串联方式进行级联。
如图2所示，移位寄存电路11包括第一上拉电路111、第二上拉电路112、第一下拉电路113、第二下拉电路114、下拉控制电路115、第一电容C1、第二电容C2以及第三电容C3。
其中，第一上拉电路111包括第一晶体管T1，第一晶体管T1的栅极和源极与前一级的栅极驱动信号G(n-1)连接；第二上拉电路112包括第二晶体管T2，第二晶体管T2的栅极与第一晶体管T1的漏极连接，第二晶体管T2的源极与第一时钟信号CK连接，第二晶体管T2的漏极与栅极驱动信号输出端G(n)连接，第一电容C1连接在第二晶体管T2的栅极和漏极之间；第一下拉电路113包括第三晶体管 T3，第三晶体管T3的源极和栅极驱动信号输出端G(n)连接，第三晶体管T3的漏极与第一电平Vgh连接；第二下拉电路114包括第四晶体管T4，第四晶体管T4的源极与第一晶体管T1的漏极连接，第四晶体管T4的漏极与第一电平Vgh连接；第二电容C2的一端与第一电平Vgh连接，第二电容C2的另一端与第三晶体管T3的栅极和第四晶体管T4的栅极连接；下拉控制电路115耦接于前一级的栅极驱动信号G(n-1)、后一级的栅极驱动信号G(n+1)、第三晶体管T3的栅极、第四晶体管T4的栅极、第一电平Vgh以及第二电平Vgl，下拉控制电路115根据前一级的栅极驱动信号G(n-1)和后一级的栅极驱动信号G(n+1)控制第三晶体管T3和第四晶体管T4工作，即控制第三晶体管T3和第四晶体管T4导通或断开。
其中，下拉控制电路115包括：第五晶体管T5、第六晶体管T6、第七晶体管T7以及第八晶体管T8。第五晶体管T5的栅极与前一级的栅极驱动信号G(n-1)连接，第五晶体管T5的源极与第一电平Vgh连接，第五晶体管T5的漏极与第三晶体管T3的栅极和第四晶体管T4的栅极连接；第六晶体管T6的栅极与前一级的栅极驱动信号G(n-1)连接，第六晶体管T6的源极与第一电平Vgh连接；第七晶体管T7的栅极与第六晶体管T6的漏极连接，第七晶体管T7的源极与第二电平Vgl连接，第七晶体管T7的漏极与第五晶体管T5的漏极连接，第三电容C3连接在第七晶体管T7的源极和栅极之间；第八晶体管T8的栅极与后一级的栅极驱动信号G(n+1)连接，第八晶体管T8的源极与第六晶体管T6的漏极连接，第八晶体管T8的漏极与第二电平Vgl连接。
在本实施例中，第一电平Vgh优选为高电平，第二电平Vgl优选为低电平。第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7以及第八晶体管T8均为P型MOS管，在其他实施例中，本领域的技术人员还可以将上述晶体管设置为其他场效应管，例如N型MOS管。
以下结合图3所示的时序图详细描述栅极驱动电路10的工作原理。
在第一时刻t1，前一级的栅极驱动信号G(n-1)为低电平，第一晶体管T1导通，第一时钟信号CK为高电平，第二晶体管T2的栅极为低电平，第二晶体管T2导通；第五晶体管T5和第六晶体管T6均导通，第七晶体管T7的栅极和第八晶体管T 8的源极均为高电平，则第七晶体管T7断开，后一级的栅极驱动信号G(n+1)为高电平，第八晶体管T8断开；第三晶体管T3的栅极和第四晶体管T4的栅极均为高电平，则第三晶体管T3和第四晶体管T4均断开；因此，栅极驱动信号输出端G(n)输出的信号与第一时钟信号CK相同，即栅极驱动信号输出端G(n)输出的信号为高电平。
在第二时刻t2，前一级的栅极驱动信号G(n-1)由低电平变为高电平，第一晶体管T1断开，第一时钟信号CK由高电平变为低电平，第二晶体管T2导通；第五晶体管T5、第六晶体管T6和第七晶体管T7均断开，后一级的栅极驱动信号G(n+1)为高电平，第八晶体管T8断开，第三晶体管T3和第四晶体管T4均断开；因此，栅极驱动信号输出端G(n)输出的信号与第一时钟信号CK相同，即栅极驱动信号输出端G(n)输出的信号由高电平变为低电平。
在第三时刻t3，前一级的栅极驱动信号G(n-1)为高电平，第一晶体管T1断开，第一时钟信号CK为低电平，第二晶体管T2导通；第五晶体管T5、第六晶体管T6和第七晶体管T7均断开，后一级的栅极驱动信号G(n+1)为高电平，第八晶体管T8断开，第三晶体管T3和第四晶体管T4均断开；因此，栅极驱动信号输出端G(n)输出的信号与第一时钟信号CK相同，即栅极驱动信号输出端G(n)输出的信号为低电平。
在第四时刻t4，前一级的栅极驱动信号G(n-1)为高电平，第一晶体管T1断开，第一时钟信号CK由低电平变高电平，第二晶体管T2导通；第五晶体管T5和第六晶体管T6断开，后一级的栅极驱动信号G(n+1)为由高电平变为低电平，第八晶体管T8导通，第七晶体管T7导通，第三晶体管T3的栅极和第四晶体管T4的栅极均为低电平，则第三晶体管T3和第四晶体管T4导通，则栅极驱动信号输出端G(n)输出的信号持续为高电平。
本实施例通过下拉控制电路115耦接于前一级的栅极驱动信号G(n-1)、后一级的栅极驱动信号(n+1)、第三晶体管T3的栅极、第四晶体管T4的栅极、第一电平Vgh以及第二电平Vgl，下拉控制电路115根据前一级的栅极驱动信号G(n-1)和后一级的栅极驱动信号(n+1)控制第三晶体管T3和第四晶体管T4，适用于CMOS制程，并且增加电路稳定性，减少时钟信号数目。
本发明还提供一种显示装置，如图4所示，本实施例所揭示显示装置20包括液晶显示面板21和栅极驱动电路22，栅极驱动电路22与液晶显示面板21连接，并且栅极驱动电路22用于为液晶显示面板21提供扫描驱动信号，该栅极驱动电路22为上述实施例所揭示的栅极驱动电路10，在此不再赘述。
综上所述，本发明的下拉控制电路耦接于前一级的栅极驱动信号、后一级的栅极驱动信号、第三晶体管的栅极、第四晶体管的栅极、第一电平以及第二电平，下拉控制电路根据前一级的栅极驱动信号和后一级的栅极驱动信号控制第三晶体管和第四晶体管，适用于CMOS制程，并且增加电路稳定性。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

  1. 一种栅极驱动电路，其中，所述栅极驱动电路包括多个移位寄存电路，所述多个移位寄存电路以串联方式进行级联，每一所述移位寄存电路包括：
    第一上拉电路，其包括第一晶体管，所述第一晶体管的栅极和源极与前一级的栅极驱动信号连接；
    第二上拉电路，其包括第二晶体管，所述第二晶体管的栅极与所述第一晶体管的漏极连接，源极与第一时钟信号连接，漏极与栅极驱动信号输出端连接；
    第一电容，其连接在所述第二晶体管的漏极和栅极之间；
    第一下拉电路，其包括第三晶体管，所述第三晶体管的源极与所述栅极驱动信号输出端连接，漏极与第一电平连接；
    第二下拉电路，其包括第四晶体管，所述第四晶体管的源极与所述第一晶体管的漏极连接，漏极与所述第一电平连接；
    下拉控制电路，其耦接于所述前一级的栅极驱动信号、后一级的栅极驱动信号、所述第三晶体管的栅极、所述第四晶体管的栅极、所述第一电平以及第二电平，所述下拉控制电路根据所述前一级的栅极驱动信号和所述后一级的栅极驱动信号控制所述第三晶体管和所述第四晶体管。
  2. 根据权利要求1所述的栅极驱动电路，其中，所述移位寄存电路还包括第二电容，所述第二电容的一端与所述第一电平连接，所述第二电容的另二端与所述第三晶体管的栅极和所述第四晶体管的栅极连接。
  3. 根据权利要求2所述的栅极驱动电路，其中，所述下拉控制电路包括：
    第五晶体管，所述第五晶体管的栅极与所述前一级的栅极驱动信号连接，源极与所述第一电平连接，漏极与所述第三晶体管的栅极和所述第四晶体管的栅极连接；
    第六晶体管，所述第六晶体管的栅极与所述前一级的栅极驱动信号连接，源极与所述第一电平连接；
    第七晶体管，所述第七晶体管的栅极与所述第六晶体管的漏极连接，源极与所述第二电平连接，漏极与所述第五晶体管的漏极连接；
    第三电容，所述第三电容连接在所述第七晶体管的源极和栅极之间；
    第八晶体管，所述第八晶体管的栅极与所述后一级的栅极驱动信号连接，源极与所述第六晶体管的漏极连接，漏极与所述第二电平连接。
  4. 根据权利要求3所述的栅极驱动电路，其中，所述第一电平为高电平，所述第二电平为低电平。
  5. 根据权利要求4所述的栅极驱动电路，其中，所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管以及第八晶体管均为P型MOS管。
  6. 一种显示装置，其中，所述显示装置包括液晶显示面板和栅极驱动电路，所述栅极驱动电路与所述液晶显示面板连接，用于为所述液晶显示面板提供扫描驱动信号，所述栅极驱动电路包括多个移位寄存电路，所述多个移位寄存电路以串联方式进行级联，每一所述移位寄存电路包括：
    第一上拉电路，其包括第一晶体管，所述第一晶体管的栅极和源极与前一级的栅极驱动信号连接；
    第二上拉电路，其包括第二晶体管，所述第二晶体管的栅极与所述第一晶体管的漏极连接，源极与第一时钟信号连接，漏极与栅极驱动信号输出端连接；
    第一电容，其连接在所述第二晶体管的漏极和栅极之间；
    第一下拉电路，其包括第三晶体管，所述第三晶体管的源极与所述栅极驱动信号输出端连接，漏极与第一电平连接；
    第二下拉电路，其包括第四晶体管，所述第四晶体管的源极与所述第一晶体管的漏极连接，漏极与所述第一电平连接；
    下拉控制电路，其耦接于所述前一级的栅极驱动信号、后一级的栅极驱动信号、所述第三晶体管的栅极、所述第四晶体管的栅极、所述第一电平以及第二电平，所述下拉控制电路根据所述前一级的栅极驱动信号和所述后一级的栅极驱动信号控制所述第三晶体管和所述第四晶体管。
  7. 根据权利要求6所述的显示装置，其中，所述移位寄存电路还包括第二电容，所述第二电容的一端与所述第一电平连接，所述第二电容的另二端与所述第三晶体管的栅极和所述第四晶体管的栅极连接。
  8. 根据权利要求7所述的显示装置，其中，所述下拉控制电路包括：第五晶体管，所述第五晶体管的栅极与所述前一级的栅极驱动信号连接，源极与所述第一电平连接，漏极与所述第三晶体管的栅极和所述第四晶体管的栅极连接；
    第六晶体管，所述第六晶体管的栅极与所述前一级的栅极驱动信号连接，源极与所述第一电平连接；
    第七晶体管，所述第七晶体管的栅极与所述第六晶体管的漏极连接，源极与所述第二电平连接，漏极与所述第五晶体管的漏极连接；
    第三电容，所述第三电容连接在所述第七晶体管的源极和栅极之间；
    第八晶体管，所述第八晶体管的栅极与所述后一级的栅极驱动信号连接，源极与所述第六晶体管的漏极连接，漏极与所述第二电平连接。
  9. 根据权利要求8所述的显示装置，其中，所述第一电平为高电平，所述第二电平为低电平。
  10. 根据权利要求9所述的显示装置，其中，所述第一晶体管、第二晶 体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管以及第八晶体管均为P型MOS管。
PCT/CN2015/070440 2014-12-30 2015-01-09 显示装置及其栅极驱动电路 WO2016106815A1 (zh)

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