WO2016106842A1 - 薄膜晶体管阵列基板、液晶面板以及液晶显示器 - Google Patents
薄膜晶体管阵列基板、液晶面板以及液晶显示器 Download PDFInfo
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- WO2016106842A1 WO2016106842A1 PCT/CN2015/070606 CN2015070606W WO2016106842A1 WO 2016106842 A1 WO2016106842 A1 WO 2016106842A1 CN 2015070606 W CN2015070606 W CN 2015070606W WO 2016106842 A1 WO2016106842 A1 WO 2016106842A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133514—Colour filters
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/441—Interconnections, e.g. scanning lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W42/00—Arrangements for protection of devices
- H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
- G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
Definitions
- the present invention relates to the field of liquid crystal display technologies, and in particular, to a thin film transistor array substrate, a liquid crystal panel, and a liquid crystal display.
- Liquid crystal display which is a flat and ultra-thin display device, is an important part of liquid crystal display.
- a conventional liquid crystal panel includes at least an array substrate 1 and a color filter substrate 2 disposed opposite to each other, and a liquid crystal layer 3 between the array substrate 1 and the filter substrate 2.
- the array substrate 1 includes a first substrate 11, scan lines 12 and data lines 13 on the first substrate 11, and a pixel region 14 defined by the intersection of the scan lines 12 and the data lines 13.
- the pixel region 14 includes a thin film transistor 14a and a pixel electrode 14b located above the thin film transistor 14a.
- the gate electrode 141 of the thin film transistor 14a is electrically connected to the scanning line 12, one of the source/drain electrodes 142 is electrically connected to the data line 13, and the other source/drain 143 is electrically connected to the pixel electrode 14b.
- the filter substrate 2 includes a second substrate 21 and an array of color resist units 22 disposed on the second substrate 21, and the black matrix 23 is disposed between the color resist units 22 to be spaced apart from each other.
- the black matrix 22 on the filter substrate 2 corresponds to the scanning line 12 and the data line 13 on the array substrate 1 and the area of the thin film transistor 14a to prevent light leakage between adjacent pixel regions 14, affecting display quality. Since there is a gap between the array substrate 1 and the filter substrate 2, the black matrix 22 needs to cover a large area to prevent light leakage, which reduces the aperture ratio of the display.
- the present invention provides a thin film transistor array substrate, which is thin
- a metal metal light shielding layer is disposed above the film transistor array, which can replace the conventional black matrix disposed on the filter substrate, and functions as a light shielding layer, and the metal light shielding layer can block light from being irradiated onto the active layer of the thin film transistor, thereby improving The display quality of the display device.
- a thin film transistor array substrate includes a first substrate, scan lines and data lines on the first substrate, and pixel regions defined by intersections of scan lines and data lines;
- the pixel region includes a thin film transistor and a pixel electrode over the thin film transistor;
- the thin film transistor includes: a gate on the first substrate, the gate is electrically connected to the scan line; and is located on the gate An active layer; a source and a drain electrically connected to the active layer, one end of the source/drain being electrically connected to the data line, and the other end being electrically connected to the pixel electrode;
- a metal light shielding layer is disposed between the thin film transistor and the pixel electrode, and the metal light shielding layer includes a first light shielding region, a second light shielding region, and a third light shielding region, which are separated from each other, wherein the first light shielding region is located Between the source/drain and the pixel electrode, the pixel electrode is electrically connected to the source/drain through the first light shielding region; the second light shielding region is located above the active layer The third light shielding area is located above the scan line and the data line.
- the thin film transistor is provided with a first insulating medium layer, the metal light shielding layer is located on the first insulating medium layer, and the first insulating medium layer is provided with a first via hole, the first light shielding layer a region is connected to the source/drain through the first via; a second insulating dielectric layer is disposed on the metal light shielding layer, the pixel electrode is located on the second insulating dielectric layer, and the second A second via hole is disposed in the insulating dielectric layer, and the pixel electrode is connected to the first light shielding region through the second via hole.
- the metal light shielding layer is a single layer or a plurality of layers of ferrous metal materials.
- the metal material is molybdenum.
- the gate is provided with a gate insulating layer, and the source/drain and the active layer are located on the gate insulating layer.
- the present invention also provides a liquid crystal panel comprising an array substrate and a filter substrate disposed opposite to each other and a liquid crystal layer between the array substrate and the filter substrate, wherein the array substrate is a thin film transistor array substrate as described above,
- the filter substrate includes a second substrate and a color resistive unit array disposed on the second substrate.
- the filter substrate is further provided with a common electrode layer between the liquid crystal layers.
- the color resistive unit array includes a red color resist, a green color resist, and a blue color resist.
- a liquid crystal display including a liquid crystal panel and a backlight module.
- the liquid crystal panel is disposed opposite to the backlight module, and the backlight module provides a display light source to the liquid crystal panel, so that The liquid crystal panel displays an image, wherein the liquid crystal panel is a liquid crystal panel as described above.
- the thin film transistor array substrate provided in the embodiment of the present invention functions as a light shielding by disposing a metal metal light shielding layer over the thin film transistor array instead of the conventional black matrix disposed on the filter substrate.
- the metal light shielding layer is disposed on the array substrate, the area that needs to be shielded can be better aligned and closer to the area that needs to be blocked, so a smaller area is required (the black matrix is disposed on the filter substrate compared to the prior art).
- the upper area can cover the area that needs to be occluded, and the pixel area can obtain a higher aperture ratio.
- the metal light shielding layer can block light from being irradiated onto the active layer of the thin film transistor, thereby improving the display quality of the display device.
- FIG. 1 is a schematic structural view of a conventional liquid crystal panel.
- FIG. 2 is a structural diagram of an array substrate in the liquid crystal panel of FIG. 1.
- FIG. 3 is a structural diagram of a filter substrate in the liquid crystal panel of FIG. 1.
- FIG. 4 is a schematic structural view of a liquid crystal panel according to an embodiment of the present invention.
- FIG. 5 is a cross-sectional view showing the structure of an array substrate according to an embodiment of the present invention.
- FIG. 6 is a top plan view showing the structure of an array substrate according to an embodiment of the present invention.
- FIG. 7 is a structural diagram of a filter substrate provided by an embodiment of the present invention.
- FIG. 8 is a structural diagram of a liquid crystal display according to an embodiment of the present invention.
- the object of the present invention is to improve the leakage of light when a black matrix for shading is disposed on a filter substrate in a conventional liquid crystal panel because a black matrix needs to cover a large area.
- the problem of reducing the aperture ratio of the display provides a thin film transistor array substrate and a liquid crystal panel including the array substrate, by placing a metal metal light shielding layer over the thin film transistor array instead of the conventional black color disposed on the filter substrate Matrix to make the pixels of the LCD panel The area can achieve a higher aperture ratio.
- the metal light shielding layer can block light from being irradiated onto the active layer of the thin film transistor, thereby improving the display quality of the display device.
- the liquid crystal panel provided in this embodiment includes an array substrate 10 and a filter substrate 20 disposed opposite to each other, and a liquid crystal layer 30 between the array substrate 10 and the filter substrate 20 .
- a common electrode layer 40 is further disposed between the filter substrate 20 and the liquid crystal layer 30.
- the array substrate 10 is a thin film transistor array substrate, and the array substrate 10 includes a first substrate 101, scan lines 102 and data lines 103 on the first substrate 101, and scan lines 102 and The data line 103 crosses the defined pixel area 104.
- the pixel region 104 includes a thin film transistor 104a and a pixel electrode 104b located above the thin film transistor 104a.
- the thin film transistor 104a is disposed near the intersection of the scanning line 102 and the data line 103.
- the thin film transistor 104a includes a gate 1041 on the first substrate 101, the gate 1041 is electrically connected to the scan line 102, and an active layer on the gate 1041. 1042; a source/drain 1043, 1044 electrically connected to the active layer 1042, one end of the source/drain 1043, 1044 is electrically connected to the data line 103, and the other end is connected to the pixel electrode 104b Electrical connection.
- a gate insulating layer 108 is disposed on the gate electrode 1041, and the source/drain electrodes 1043, 1044 and the active layer 1042 are located on the gate insulating layer 108.
- a metal light shielding layer 105 is disposed between the thin film transistor 104a and the pixel electrode 104b, and the metal light shielding layer 105 includes a first light shielding region 1051 and a second isolation from each other.
- the first light-shielding region 1051 is located between the source/drain electrodes 1043, 1044 and the pixel electrode 104b, and the pixel electrode 104b is electrically connected to the first light-shielding region 1051 through the first light-shielding region 1051.
- the source/drain 1043, 1044; the second light-shielding region 1052 is located above the active layer 1042; the third light-shielding region 1053 is located above the scan line 102 and the data line 103. Specifically, as shown in FIG.
- the thin film transistor 104a is provided with a first insulating dielectric layer 106, the metal light shielding layer 105 is located on the first insulating dielectric layer 106, and the first insulating dielectric layer 106 a first via 1061 is disposed, the first light blocking region 1051 is connected to the source/drain 1043, 1044 through the first via 1061; and the second insulating medium is disposed on the metal light shielding layer 105 Layer 107, the pixel electrode 104b is located in the second On the insulating dielectric layer 107, a second via 1071 is disposed in the second insulating dielectric layer 107, and the pixel electrode 104b is connected to the first light blocking region 1051 through the second via 1071.
- the metal light shielding layer 105 is prepared on the first insulating dielectric layer 106 by a PVD process, and then the metal light shielding layer 105 is divided into first light shielding regions separated by a photolithography process. 1051.
- the metal light shielding layer 105 is a single layer or a plurality of layers of ferrous metal material.
- a preferred metallic material is molybdenum.
- the metal light shielding layer 105 covers the scanning line 102 and the data line 103 and the non-display area such as the thin film transistor 104a, and functions as a light blocking.
- the filter substrate 20 in the liquid crystal panel includes a second substrate 201 and an array of color resist units 202 disposed on the second substrate 201.
- the color resist unit 201 array includes a red color resist 202R and a green color.
- the metal light shielding layer 105 is disposed on the array substrate 10, it is possible to better align the area that needs to be blocked and is closer to the area that needs to be blocked, so a smaller area is required (compared to the black matrix in the prior art)
- the area on the filter substrate can cover the area that needs to be blocked, and thus the pixel area 104 can obtain a higher aperture ratio.
- the second light-shielding region 1052 is located on the active layer 1042, which can block light from being irradiated onto the active layer 1042 of the thin film transistor 104a, reducing the generation of photo-generated carriers, so that the working state of the thin film transistor 104a is more stable, and the display device is improved. Display quality.
- a second insulating dielectric layer 107 is disposed between the pixel electrode 104b and the metal light shielding layer 105, and the pixel electrode 104b is electrically connected to the third light shielding region 1053 through the second via hole 1071, and the pixel electrode 104b and the first light shielding region
- the insulating layer 1051 is insulated from the second light blocking region 1052, so that a larger area of the pixel electrode 104b can be designed.
- the pixel electrode 104b can extend above the third light blocking region 1053 (on the scan line 102 and the data line 103). Above), the area of the pixel area is increased, and the aperture ratio is further increased.
- the embodiment also provides a liquid crystal display.
- the liquid crystal display includes a liquid crystal panel 100 and a backlight module 200 .
- the liquid crystal panel 100 is opposite to the backlight module 200 .
- the display 200 provides a display light source to the liquid crystal panel 100 to cause the liquid crystal panel 100 to display an image.
- the liquid crystal panel 100 uses the liquid crystal panel provided in the foregoing embodiment.
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Abstract
本发明公开了一种薄膜晶体管阵列基板,包括第一基板、位于第一基板上的扫描线和数据线以及由扫描线和数据线交叉限定的像素区域;像素区域包括薄膜晶体管和位于薄膜晶体管上方的像素电极;其中,所述薄膜晶体管与所述像素电极之间设置有一金属遮光层,所述金属遮光层包括相互隔离的第一遮光区、第二遮光区和第三遮光区,所述第一遮光区位于所述源极/漏极与所述像素电极之间,所述像素电极通过所述第一遮光区电连接到所述源极/漏极;所述第二遮光区位于所述有源层上方;所述第三遮光区位于所述扫描线和数据线上方。本发明还公开了一种液晶面板,该液晶面板包括如上的薄膜晶体管阵列基板。本发明还公开了包含前述液晶面板的液晶显示器。
Description
本发明涉及液晶显示技术领域,尤其涉及一种薄膜晶体管阵列基板、液晶面板以及液晶显示器。
液晶显示器(Liquid Crystal Display,LCD),为平面超薄的显示设备,液晶面板是液晶显示器的重要组成部分。
参阅图1-3,常用的液晶面板至少包括相对设置的阵列基板(array substrate)1和滤光基板(color filter substrate)2以及位于阵列基板1和滤光基板2之间的液晶层3。其中,阵列基板1包括第一基板11、位于第一基板11上的扫描线12和数据线13以及由扫描线12和数据线13交叉限定的像素区域14。其中,像素区域14包括薄膜晶体管14a和位于薄膜晶体管14a上方的像素电极14b。薄膜晶体管14a的栅极141与扫描线12电连接、其中的一个源极/漏极142与数据线13电连接,另一个源极/漏极143与像素电极14b电连接。滤光基板2包括第二基板21以及设置于第二基板21上的色阻单元22阵列,色阻单元22之间设置有黑色矩阵23相互间隔。
滤光基板2上的黑色矩阵22对应于阵列基板1上的扫描线12和数据线13以及薄膜晶体管14a的区域,以防止相邻的像素区域14之间漏光,影响显示质量。由于阵列基板1和滤光基板2之间具有间距,因此黑色矩阵22需要覆盖较大面积的区域才能防止漏光,降低了显示器的开口率。
另外,如图1中现有的阵列基板1中,薄膜晶体管14a的有源层144上方没有遮挡物,光线可以照射到该有源层144上,形成光生载流子,降低了显示器的性能。
发明内容
鉴于现有技术存在的不足,本发明提供了一种薄膜晶体管阵列基板,在薄
膜晶体管阵列上方设置一金属金属遮光层,其可以代替传统的设置于滤光基板上的黑色矩阵,起到遮光的作用,并且该金属遮光层可以阻挡光线照射到薄膜晶体管的有源层,提高了显示设备的显示品质。
为了实现上述目的,本发明采用了如下的技术方案:
一种薄膜晶体管阵列基板,包括第一基板、位于所述第一基板上的扫描线和数据线以及由扫描线和数据线交叉限定的像素区域;
所述像素区域包括薄膜晶体管和位于薄膜晶体管上方的像素电极;该薄膜晶体管包括:位于所述第一基板上的栅极,所述栅极与所述扫描线电连接;位于所述栅极上的有源层;与所述有源层电连接的源极和漏极,所述源极/漏极的一端与所述数据线电连接,另一端与所述像素电极电连接;
其中,所述薄膜晶体管与所述像素电极之间设置有一金属遮光层,所述金属遮光层包括相互隔离的第一遮光区、第二遮光区和第三遮光区,所述第一遮光区位于所述源极/漏极与所述像素电极之间,所述像素电极通过所述第一遮光区电连接到所述源极/漏极;所述第二遮光区位于所述有源层上方;所述第三遮光区位于所述扫描线和数据线上方。
其中,所述薄膜晶体管上设置有第一绝缘介质层,所述金属遮光层位于所述第一绝缘介质层上,所述第一绝缘介质层中设置有第一过孔,所述第一遮光区通过所述第一过孔连接到所述源极/漏极;所述金属遮光层上设置有第二绝缘介质层,所述像素电极位于所述第二绝缘介质层上,所述第二绝缘介质层中设置有第二过孔,所述像素电极通过所述第二过孔连接到所述第一遮光区。
其中,所述金属遮光层为单层或多层黑色金属材料层。
其中,所述金属材料为钼。
其中,所述栅极上设置有栅极绝缘层,所述源极/漏极以及有源层位于所述栅极绝缘层上。
本发明还提供了一种液晶面板,包括相对设置的阵列基板和滤光基板以及位于阵列基板和滤光基板之间的液晶层,其中,所述阵列基板为如上所述的薄膜晶体管阵列基板,所述滤光基板包括第二基板以及设置于该第二基板上的色阻单元阵列。
其中,所述滤光基板于所述液晶层之间还设置有公共电极层。
其中,所述色阻单元阵列包括红色色阻、绿色色阻和蓝色色阻。
本发明的另一方面是提供一种液晶显示器,包括液晶面板及背光模组,所述液晶面板与所述背光模组相对设置,所述背光模组提供显示光源给所述液晶面板,以使所述液晶面板显示影像,其中,所述液晶面板为如上所述的液晶面板。
相比于现有技术,本发明实施例中提供的薄膜晶体管阵列基板,通过在薄膜晶体管阵列上方设置一金属金属遮光层,代替传统的设置于滤光基板上的黑色矩阵,起到遮光的作用。由于该金属遮光层设置于阵列基板上,可以更好对准需要遮挡的区域且距离需要遮挡的区域更近,因此需要较小的面积(相比于现有技术中黑色矩阵设置于滤光基板上)就可以覆盖需要遮挡的区域,进而像素区域可以获得更高的开口率。另外,该金属遮光层可以阻挡光线照射到薄膜晶体管的有源层,提高了显示设备的显示品质。
图1是现有的一种液晶面板的结构示意图。
图2是如图1的液晶面板中的阵列基板的结构图示。
图3是如图1的液晶面板中的滤光基板的结构图示。
图4是本发明实施例提供的液晶面板的结构示意图。
图5是本发明实施例提供的阵列基板的结构剖面图。
图6是本发明实施例提供的阵列基板的结构俯视图。
图7是本发明实施例提供的滤光基板的结构图示。
图8是本发明实施例提供的液晶显示器的结构图示。
如前所述,本发明的目的是为了改善传统的液晶面板中,用于遮光的黑色矩阵设置于滤光基板上时,由于液晶盒的间距使得黑色矩阵需要覆盖较大面积的区域才能防止漏光,降低显示器的开口率的问题,提供了一种薄膜晶体管阵列基板以及包含该阵列基板的液晶面板,通过在薄膜晶体管阵列上方设置一金属金属遮光层,代替传统的设置于滤光基板上的黑色矩阵,使液晶面板的像素
区域可以获得更高的开口率。另外,该金属遮光层可以阻挡光线照射到薄膜晶体管的有源层,提高了显示设备的显示品质。
下面将结合附图以及具体实施例,对本发明实施例中的技术方案进行详细地描述,显然,所描述的实施例仅仅是本发明一部分实例,而不是全部实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护范围。
如图4所示,本实施例提供的液晶面板包括相对设置的阵列基板10和滤光基板20以及位于阵列基板10和滤光基板20之间的液晶层30。滤光基板20与所述液晶层30之间还设置有公共电极层40。
其中,参阅图5和图6,阵列基板10为薄膜晶体管阵列基板,该阵列基板10包括第一基板101、位于所述第一基板101上的扫描线102和数据线103以及由扫描线102和数据线103交叉限定的像素区域104。所述像素区域104包括薄膜晶体管104a和位于薄膜晶体管104a上方的像素电极104b。
具体地,薄膜晶体管104a设置于扫描线102和数据线103交叉点附近。如图5所示的,薄膜晶体管104a包括:位于所述第一基板101上的栅极1041,所述栅极1041与所述扫描线102电连接;位于所述栅极1041上的有源层1042;与所述有源层1042电连接的源极/漏极1043、1044,所述源极/漏极1043、1044的一端与所述数据线103电连接,另一端与所述像素电极104b电连接。进一步地,所述栅极1041上设置有栅极绝缘层108,所述源极/漏极1043、1044以及有源层1042位于所述栅极绝缘层108上。
其中,本实施例提供的阵列基板10中,所述薄膜晶体管104a与所述像素电极104b之间设置有一金属遮光层105,所述金属遮光层105包括相互隔离的第一遮光区1051、第二遮光区1052和第三遮光区1053。如图6所示的,所述第一遮光区1051位于所述源极/漏极1043、1044与所述像素电极104b之间,所述像素电极104b通过所述第一遮光区1051电连接到所述源极/漏极1043、1044;所述第二遮光区1052位于所述有源层1042上方;所述第三遮光区1053位于所述扫描线102和数据线103上方。具体地,如图5所示的,所述薄膜晶体管104a上设置有第一绝缘介质层106,所述金属遮光层105位于所述第一绝缘介质层106上,所述第一绝缘介质层106中设置有第一过孔1061,所述第一遮光区1051通过所述第一过孔1061连接到所述源极/漏极1043、1044;所述金属遮光层105上设置有第二绝缘介质层107,所述像素电极104b位于所述第二
绝缘介质层107上,所述第二绝缘介质层107中设置有第二过孔1071,所述像素电极104b通过所述第二过孔1071连接到所述第一遮光区1051。
其中,在制备完成第一绝缘介质层106之后,通过PVD工艺在第一绝缘介质层106上制备得到金属遮光层105,然后通过光刻工艺将金属遮光层105划分为相互隔离的第一遮光区1051、第二遮光区1052和第三遮光区1053。金属遮光层105为单层或多层黑色金属材料层。优选的金属材料为钼。
金属遮光层105覆盖于扫描线102和数据线103以及薄膜晶体管104a等非显示区域的上方,可以起到遮光的作用。相应的该液晶面板中的滤光基板20上可以取消黑色矩阵的工艺。如图7所示,该液晶面板中的滤光基板20包括第二基板201以及设置于该第二基板201上的色阻单元202阵列,所述色阻单元201阵列包括红色色阻202R、绿色色阻202G和蓝色色阻202B。由于该金属遮光层105设置于阵列基板10上,可以更好地对准需要遮挡的区域且距离需要遮挡的区域更近,因此需要较小的面积(相比于现有技术中黑色矩阵设置于滤光基板上)就可以覆盖需要遮挡的区域,进而像素区域104可以获得更高的开口率。
另外,第二遮光区1052位于有源层1042上,可以阻挡光线照射到薄膜晶体管104a的有源层1042,减少光生载流子的产生,使得薄膜晶体管104a的工作状态更加稳定,提高了显示设备的显示品质。
进一步地,像素电极104b与金属遮光层105之间设置有第二绝缘介质层107,像素电极104b通过第二过孔1071仅与第三遮光区1053互相导通,像素电极104b与第一遮光区1051和第二遮光区1052之间绝缘,因此可以设计更大面积的像素电极104b,如图6所示的,像素电极104b可以延伸到第三遮光区1053上方(位于扫描线102和数据线103的上方),增加了像素区域的面积,进一步提高了开口率。
本实施例还提供了一种液晶显示器,如图8所示,该液晶显示器包括液晶面板100及背光模组200,所述液晶面板100与所述背光模组200相对设置,所述背光模组200提供显示光源给所述液晶面板100,以使所述液晶面板100显示影像。其中,所述液晶面板100采用本实施例前述提供的液晶面板。
以上所述仅是本申请的具体实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本申请原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本申请的保护范围。
Claims (19)
- 一种薄膜晶体管阵列基板,其中,包括第一基板、位于所述第一基板上的扫描线和数据线以及由扫描线和数据线交叉限定的像素区域;所述像素区域包括薄膜晶体管和位于薄膜晶体管上方的像素电极;该薄膜晶体管包括:位于所述第一基板上的栅极,所述栅极与所述扫描线电连接;位于所述栅极上的有源层;与所述有源层电连接的源极/漏极,所述源极/漏极的一端与所述数据线电连接,另一端与所述像素电极电连接;其中,所述薄膜晶体管与所述像素电极之间设置有一金属遮光层,所述金属遮光层包括相互隔离的第一遮光区、第二遮光区和第三遮光区,所述第一遮光区位于所述源极/漏极与所述像素电极之间,所述像素电极通过所述第一遮光区电连接到所述源极/漏极;所述第二遮光区位于所述有源层上方;所述第三遮光区位于所述扫描线和数据线上方。
- 根据权利要求1所述的薄膜晶体管阵列基板,其中,所述薄膜晶体管上设置有第一绝缘介质层,所述金属遮光层位于所述第一绝缘介质层上,所述第一绝缘介质层中设置有第一过孔,所述第一遮光区通过所述第一过孔连接到所述源极/漏极;所述金属遮光层上设置有第二绝缘介质层,所述像素电极位于所述第二绝缘介质层上,所述第二绝缘介质层中设置有第二过孔,所述像素电极通过所述第二过孔连接到所述第一遮光区。
- 根据权利要求2所述的薄膜晶体管阵列基板,其中,所述金属遮光层为单层或多层黑色金属材料层。
- 根据权利要求3所述的薄膜晶体管阵列基板,其中,所述金属材料为钼。
- 根据权利要求2所述的薄膜晶体管阵列基板,其中,所述栅极上设置有栅极绝缘层,所述源极/漏极以及有源层位于所述栅极绝缘层上。
- 一种液晶面板,包括相对设置的阵列基板和滤光基板以及位于阵列基板和滤光基板之间的液晶层,其中,所述阵列基板为薄膜晶体管阵列基板,该薄膜晶体管阵列基板包括第一基板、位于所述第一基板上的扫描线和数据线以及由扫描线和数据线交叉限定的像素区域;所述像素区域包括薄膜晶体管和位于薄膜晶体管上方的像素电极;该薄膜晶体管包括:位于所述第一基板上的栅极,所述栅极与所述扫描线电连接;位于所述栅极上的有源层;与所述有源层电连接的源极/漏极,所述源极/漏极的一端与所述数据线电连接,另一端与所述像素电极电连接;其中,所述薄膜晶体管与所述像素电极之间设置有一金属遮光层,所述金属遮光层包括相互隔离的第一遮光区、第二遮光区和第三遮光区,所述第一遮光区位于所述源极/漏极与所述像素电极之间,所述像素电极通过所述第一遮光区电连接到所述源极/漏极;所述第二遮光区位于所述有源层上方;所述第三遮光区位于所述扫描线和数据线上方;所述滤光基板包括第二基板以及设置于该第二基板上的色阻单元阵列。
- 根据权利要求6所述的液晶面板,其中,所述薄膜晶体管上设置有第一绝缘介质层,所述金属遮光层位于所述第一绝缘介质层上,所述第一绝缘介质层中设置有第一过孔,所述第一遮光区通过所述第一过孔连接到所述源极/漏极;所述金属遮光层上设置有第二绝缘介质层,所述像素电极位于所述第二绝缘介质层上,所述第二绝缘介质层中设置有第二过孔,所述像素电极通过所述第二过孔连接到所述第一遮光区。
- 根据权利要求7所述的液晶面板,其中,所述金属遮光层为单层或多层黑色金属材料层。
- 根据权利要求8所述的液晶面板,其中,所述金属材料为钼。
- 根据权利要求7所述的液晶面板,其中,所述栅极上设置有栅极绝缘层,所述源极/漏极以及有源层位于所述栅极绝缘层上。
- 根据权利要求6所述的液晶面板,其中,所述滤光基板与所述液晶层之间还设置有公共电极层。
- 根据权利要求6所述的液晶面板,其中,所述色阻单元阵列包括红色色阻、绿色色阻和蓝色色阻。
- 一种液晶显示器,包括液晶面板及背光模组,所述液晶面板与所述背光模组相对设置,所述背光模组提供显示光源给所述液晶面板,以使所述液晶面板显示影像,其中,所述液晶面板包括相对设置的阵列基板和滤光基板以及位于阵列基板和滤光基板之间的液晶层,其中,所述阵列基板为薄膜晶体管阵列基板,该薄膜晶体管阵列基板包括第一基板、位于所述第一基板上的扫描线和数据线以及由扫描线和数据线交叉限定的像素区域;所述像素区域包括薄膜晶体管和位于薄膜晶体管上方的像素电极;该薄膜晶体管包括:位于所述第一基板上的栅极,所述栅极与所述扫描线电连接;位于所述栅极上的有源层;与所述有源层电连接的源极/漏极,所述源极/漏极的一端与所述数据线电连接,另一端与所述像素电极电连接;其中,所述薄膜晶体管与所述像素电极之间设置有一金属遮光层,所述金属遮光层包括相互隔离的第一遮光区、第二遮光区和第三遮光区,所述第一遮光区位于所述源极/漏极与所述像素电极之间,所述像素电极通过所述第一遮光区电连接到所述源极/漏极;所述第二遮光区位于所述有源层上方;所述第三遮光区位于所述扫描线和数据线上方;所述滤光基板包括第二基板以及设置于该第二基板上的色阻单元阵列。
- 根据权利要求13所述的液晶显示器,其中,所述薄膜晶体管上设置有第一绝缘介质层,所述金属遮光层位于所述第一绝缘介质层上,所述第一绝缘介质层中设置有第一过孔,所述第一遮光区通过所述第一过孔连接到所述源极/漏极;所述金属遮光层上设置有第二绝缘介质层,所述像素电极位于所述第二绝缘介质层上,所述第二绝缘介质层中设置有第二过孔,所述像素电极通过所述第二过孔连接到所述第一遮光区。
- 根据权利要求14所述的液晶显示器,其中,所述金属遮光层为单层或多层黑色金属材料层。
- 根据权利要求15所述的液晶显示器,其中,所述金属材料为钼。
- 根据权利要求14所述的液晶显示器,其中,所述栅极上设置有栅极绝缘层,所述源极/漏极以及有源层位于所述栅极绝缘层上。
- 根据权利要求13所述的液晶显示器,其中,所述滤光基板与所述液晶层之间还设置有公共电极层。
- 根据权利要求13所述的液晶显示器,其中,所述色阻单元阵列包括红色色阻、绿色色阻和蓝色色阻。
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| US14/425,043 US20160342048A1 (en) | 2014-12-31 | 2015-01-13 | Thin film transistor array substrate, liquid crystal panel and liquid crystal display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114911103A (zh) * | 2022-04-22 | 2022-08-16 | 广州华星光电半导体显示技术有限公司 | 阵列基板及液晶面板 |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104977764A (zh) * | 2015-06-18 | 2015-10-14 | 深圳市华星光电技术有限公司 | 一种阵列基板及其制作方法、液晶显示器 |
| CN105097831B (zh) | 2015-06-23 | 2019-03-29 | 京东方科技集团股份有限公司 | 低温多晶硅背板及其制造方法和发光器件 |
| CN105404048A (zh) * | 2015-12-17 | 2016-03-16 | 武汉华星光电技术有限公司 | 液晶显示装置 |
| KR102514320B1 (ko) * | 2015-12-24 | 2023-03-27 | 삼성디스플레이 주식회사 | 표시 장치 |
| KR20170115133A (ko) * | 2016-04-04 | 2017-10-17 | 삼성디스플레이 주식회사 | 액정 표시 장치 |
| US11018164B2 (en) * | 2017-01-19 | 2021-05-25 | Sharp Kabushiki Kaisha | Thin-film transistor substrate, display panel, and display device |
| CN106855670A (zh) * | 2017-02-28 | 2017-06-16 | 厦门天马微电子有限公司 | 阵列基板、显示面板和显示装置 |
| CN107093618B (zh) | 2017-05-04 | 2019-12-17 | 京东方科技集团股份有限公司 | 像素电路结构及使用其的显示器件 |
| US10345638B2 (en) * | 2017-08-01 | 2019-07-09 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Display panel and display device |
| CN108020971A (zh) | 2017-12-22 | 2018-05-11 | 武汉华星光电技术有限公司 | 阵列基板、液晶面板以及液晶显示装置 |
| CN110275333B (zh) * | 2018-03-14 | 2022-11-25 | 群创光电股份有限公司 | 显示设备以及其制造方法 |
| WO2020073308A1 (en) * | 2018-10-12 | 2020-04-16 | Boe Technology Group Co., Ltd. | Substrate for electronic device, display apparatus, method of fabricating substrate for electronic device |
| CN109407388A (zh) | 2018-11-14 | 2019-03-01 | 惠科股份有限公司 | 一种显示面板的制程方法、显示面板及显示装置 |
| CN110082975A (zh) * | 2019-04-12 | 2019-08-02 | 深圳市华星光电半导体显示技术有限公司 | 阵列基板以及显示面板 |
| CN110109306B (zh) * | 2019-04-25 | 2020-12-08 | 武汉华星光电技术有限公司 | 阵列基板及其制造方法、显示面板 |
| CN112859466B (zh) * | 2019-11-28 | 2025-04-22 | 京东方科技集团股份有限公司 | 显示基板和显示面板 |
| KR20210070462A (ko) | 2019-12-04 | 2021-06-15 | 삼성디스플레이 주식회사 | 표시장치 |
| CN111679496B (zh) * | 2020-06-11 | 2023-09-26 | Tcl华星光电技术有限公司 | 背光模组及其制作方法、显示终端 |
| CN214505500U (zh) * | 2020-09-15 | 2021-10-26 | 信利半导体有限公司 | 一种显示面板及显示装置 |
| CN113820883A (zh) * | 2021-09-29 | 2021-12-21 | Tcl华星光电技术有限公司 | 显示面板的像素单元及显示面板 |
| US11953795B2 (en) | 2021-09-29 | 2024-04-09 | Tcl China Star Optoelectronics Technology Co., Ltd. | Pixel unit of a display panel and display panel |
| CN115347001A (zh) * | 2022-08-03 | 2022-11-15 | 武汉华星光电半导体显示技术有限公司 | 阵列基板及显示面板 |
| CN115494672B (zh) * | 2022-09-28 | 2024-07-30 | 厦门天马微电子有限公司 | 显示模组及显示装置 |
| CN116560135A (zh) * | 2023-03-22 | 2023-08-08 | 滁州惠科光电科技有限公司 | 显示面板及显示装置 |
| CN116344555B (zh) * | 2023-03-31 | 2026-04-10 | 天马新型显示技术研究院(厦门)有限公司 | 显示面板、成型方法以及显示装置 |
| US12386227B2 (en) | 2023-04-25 | 2025-08-12 | Guangzhou China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and manufacturing method thereof, and electronic device |
| CN117457668A (zh) * | 2023-04-25 | 2024-01-26 | 广州华星光电半导体显示技术有限公司 | 显示面板及其制备方法 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1523408A (zh) * | 2003-02-21 | 2004-08-25 | 精工爱普生株式会社 | 电光面板及电子设备 |
| CN101067705A (zh) * | 2007-07-03 | 2007-11-07 | 友达光电股份有限公司 | 液晶显示器的像素结构及其制造方法 |
| US20090267075A1 (en) * | 2008-04-23 | 2009-10-29 | Industrial Technology Research Institute | Oganic thin film transistor and pixel structure and method for manufacturing the same and display panel |
| CN101587273A (zh) * | 2004-05-28 | 2009-11-25 | 夏普株式会社 | 有源矩阵基板和显示装置 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001109404A (ja) * | 1999-10-01 | 2001-04-20 | Sanyo Electric Co Ltd | El表示装置 |
| JP2003289072A (ja) * | 2002-03-28 | 2003-10-10 | Sharp Corp | 平坦化膜を有する基板及び表示装置用基板、並びにそれら基板の製造方法 |
| JP2004342923A (ja) * | 2003-05-16 | 2004-12-02 | Seiko Epson Corp | 液晶装置、アクティブマトリクス基板、表示装置、及び電子機器 |
| JP4055764B2 (ja) * | 2004-01-26 | 2008-03-05 | セイコーエプソン株式会社 | 電気光学装置及び電子機器 |
| JP4591451B2 (ja) * | 2007-01-10 | 2010-12-01 | ソニー株式会社 | 半導体装置および表示装置 |
| WO2011045953A1 (ja) * | 2009-10-15 | 2011-04-21 | シャープ株式会社 | 液晶表示パネルおよびその製造方法、液晶表示装置 |
-
2014
- 2014-12-31 CN CN201410856582.3A patent/CN104465675B/zh active Active
-
2015
- 2015-01-13 US US14/425,043 patent/US20160342048A1/en not_active Abandoned
- 2015-01-13 WO PCT/CN2015/070606 patent/WO2016106842A1/zh not_active Ceased
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1523408A (zh) * | 2003-02-21 | 2004-08-25 | 精工爱普生株式会社 | 电光面板及电子设备 |
| CN101587273A (zh) * | 2004-05-28 | 2009-11-25 | 夏普株式会社 | 有源矩阵基板和显示装置 |
| CN101067705A (zh) * | 2007-07-03 | 2007-11-07 | 友达光电股份有限公司 | 液晶显示器的像素结构及其制造方法 |
| US20090267075A1 (en) * | 2008-04-23 | 2009-10-29 | Industrial Technology Research Institute | Oganic thin film transistor and pixel structure and method for manufacturing the same and display panel |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114911103A (zh) * | 2022-04-22 | 2022-08-16 | 广州华星光电半导体显示技术有限公司 | 阵列基板及液晶面板 |
| CN114911103B (zh) * | 2022-04-22 | 2024-03-08 | 广州华星光电半导体显示技术有限公司 | 阵列基板及液晶面板 |
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