WO2016045247A1 - 脉冲信号合并电路、显示面板和显示装置 - Google Patents

脉冲信号合并电路、显示面板和显示装置 Download PDF

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Publication number
WO2016045247A1
WO2016045247A1 PCT/CN2015/070193 CN2015070193W WO2016045247A1 WO 2016045247 A1 WO2016045247 A1 WO 2016045247A1 CN 2015070193 W CN2015070193 W CN 2015070193W WO 2016045247 A1 WO2016045247 A1 WO 2016045247A1
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Prior art keywords
pulse signal
level
control transistor
output
gate
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PCT/CN2015/070193
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English (en)
French (fr)
Inventor
李全虎
宋琛
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京东方科技集团股份有限公司
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Priority to JP2017534865A priority Critical patent/JP6406740B2/ja
Priority to KR1020157023557A priority patent/KR101708801B1/ko
Priority to EP15747351.3A priority patent/EP3200177B1/en
Priority to US14/769,068 priority patent/US9536469B2/en
Publication of WO2016045247A1 publication Critical patent/WO2016045247A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0213—Addressing of scan or signal lines controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pulse signal combining circuit, a display panel, and a display device.
  • a multi-pulse gate drive signal composed of a plurality of time-divisionally effective single-pulse drive signals having different pulse widths is required due to the need for pixel compensation.
  • the use of a single unit circuit to generate a multi-pulse gate drive signal is difficult to achieve from the principle of a single pulse.
  • the pixel driving needs to add more TFT (thin film transistor), resulting in a complicated OLED pixel structure. The effective light-emitting area of the OLED is reduced.
  • the main purpose of the present disclosure is to provide a pulse signal combining circuit, a display panel and a display device, which can realize multi-pulse output by adding or a unit directly by using an existing single-pulse signal generating circuit, and realize multiple single-pulse signals. Lossless merge.
  • the present disclosure provides a pulse signal combining circuit for combining N input pulse signals into an output pulse signal, the N input pulse signals being sequentially valid in each display period, and N is greater than 1
  • An integer of the pulse signal combining circuit comprising the pulse signal combining circuit comprising N output control units and a pulse signal output terminal, wherein
  • the nth output control unit the first control end is connected to the nth input pulse signal, the second control end is connected to the n+1th input pulse signal, and the output end is connected to the pulse signal output end for use in each display period And controlling, after the first nth input pulse signal is first valid, and before the first n+1 input pulse signal is valid for the first time, controlling to output the nth input pulse signal to the pulse signal output end; n is a positive integer smaller than N ;
  • the Nth output control unit the first control end is connected to the Nth input pulse signal, the second control end is connected to the first input pulse signal, and the output end is connected to the pulse signal output end for being used in each display period After the N input pulse signal is first valid until a period before the first input pulse signal is first valid in the next display period, the control outputs the Nth input pulse signal to the pulse signal output terminal.
  • each of the output control units includes:
  • the gate is a second control end of the output control unit, the first pole is connected to the second pole of the first output control transistor, and the second pole is connected to the first level;
  • a third output control transistor the gate is connected to the second pole of the first output control transistor, the first pole is connected to the first control terminal, and the second pole is connected to the pulse signal output end;
  • the third output control transistor is turned off when the second output control transistor is turned on and the gate of the third output control transistor is turned on to the first level.
  • the N input pulse signals are all forward pulse signals
  • the first output control transistor, the second output control transistor, and the third control transistor are both n-type TFTs, a first level Low level
  • the N input pulse signals are all negative pulse signals
  • the first output control transistor, the second output control transistor, and the third control transistor are both p-type TFTs, and the first level is high. Level.
  • the pulse signal combining circuit of the present disclosure further includes:
  • the output invalidation control unit includes a gate potential control transistor, an invalid control transistor, and N active control transistors respectively inputting the N input pulse signals, where
  • the gate potential control transistor has a gate and a first pole connected to a second level
  • the invalid control transistor has a gate connected to the second pole of the gate potential control transistor, a first pole connected to the pulse signal output end, and a second pole connected to the first level;
  • the mth effective control transistor the gate is connected to the mth input pulse signal, the first pole and the invalid control
  • the gate of the transistor is connected, the second pole is connected to the third level, and m is a positive integer less than or equal to N;
  • the second level control causes the gate potential control transistor to be turned on
  • the mth effective control transistor When the mth input pulse signal is valid, the mth effective control transistor is turned on, so that the gate of the invalid control transistor is connected to the third level, so that the invalid control transistor is turned off;
  • the gate of the invalid control transistor is connected to the second level, so that the invalid control transistor is turned on, and the pulse signal output terminal is connected to the first level.
  • the N input pulse signals are all forward pulse signals
  • the gate potential control transistor, the invalid control transistor, and the N effective control transistors are all n-type TFTs, and the first power Flat is low, the second level is high, and the third level is low;
  • the N input pulse signals are all negative pulse signals
  • the gate potential control transistor, the invalid control transistor, and the N active control transistors are all p-type TFTs, and the first level is A high level, the second level is a low level, and the third level is a high level.
  • the third level is smaller than the first level; when the n-type TFT is an enhancement TFT, the third level is The first levels are the same.
  • the present disclosure also provides a display panel, including the pulse signal combining circuit described above;
  • the pulse signal combining circuit is configured to provide a gate driving signal to the display panel through a pulse signal output end.
  • the display panel is an OLED display panel.
  • the present disclosure also provides a display device including the above display panel.
  • the pulse signal combining circuit, the display panel and the display device of the present disclosure may have a plurality of single pulse signals (the single pulse signal may be a single pulse gate drive signal of a single pulse gate drive circuit) Combined with the output pulse signal, there is no special modification to the single-pulse signal generating circuit.
  • the existing single-pulse signal generating circuit multiple pulse output can be realized directly by adding or a unit, and multiple single pulses can be realized.
  • FIG. 1 is a structural block diagram of a pulse signal combining circuit according to an embodiment of the present disclosure
  • FIG. 2 is a circuit diagram of a pulse signal combining circuit according to another embodiment of the present disclosure.
  • FIG. 3 is a timing diagram of a forward first input pulse signal Input1, a forward second input pulse signal Input2, and a pulse signal output terminal OUT, which are used by the pulse signal combining circuit according to the embodiment of the present disclosure;
  • FIG. 4 is a timing diagram of a negative first input pulse signal Input1, a negative second input pulse signal Input2, and a pulse signal output terminal OUT signal used by the pulse signal combining circuit according to the embodiment of the present disclosure;
  • FIG. 5 is a circuit diagram of a pulse signal combining circuit according to still another embodiment of the present disclosure.
  • FIG. 6 is a circuit diagram of a pulse signal combining circuit according to still another embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • one of the poles is referred to as a source and the other pole is referred to as a drain.
  • the transistor may be an n-type transistor or a p-type transistor.
  • the pulse signal combining circuit is configured to combine N input pulse signals into an output pulse signal, wherein the N input pulse signals are sequentially valid in each display period, and N is an integer greater than 1.
  • the pulse signal combining circuit includes N output control units and a pulse signal output terminal, wherein
  • the nth output control unit the first control end is connected to the nth input pulse signal, the second control end is connected to the n+1th input pulse signal, and the output end is connected to the pulse signal output end; for each display period And controlling, after the first nth input pulse signal is first valid, and before the first n+1 input pulse signal is valid for the first time, controlling to output the nth input pulse signal to the pulse signal output end; n is a positive integer smaller than N ;
  • the Nth output control unit the first control terminal is connected to the Nth input pulse signal, and the second control terminal is connected Entering a first input pulse signal, the output end is connected to the pulse signal output end, and is used for each display period after the first N input pulse signal is first valid until the first input pulse signal is first valid in the next display period And controlling to output the Nth input pulse signal to the pulse signal output end.
  • the pulse signal combining circuit may combine a plurality of single pulse signals (the single pulse signal may be a single pulse gate driving signal of a single pulse gate driving circuit) as an output pulse signal, and There is no special modification in the pulse signal generating circuit, and the existing single-pulse signal generating circuit can realize multi-pulse output directly by adding or the unit, that is, the output control unit described in the embodiment of the present disclosure, and realize multi-pulse Lossless combination of single pulse signals.
  • the pulse signal combining circuit of the embodiment of the present disclosure When the pulse signal combining circuit of the embodiment of the present disclosure is applied to combine the single-pulse gate driving signals of the single-pulse gate driving circuit as a multi-pulse gate driving signal, there is no single-pulse gate driving circuit. Special modifications. Therefore, the multi-pulse output can be realized directly by adding or a unit by using the existing single-pulse gate driving circuit.
  • the frame size of the OLED display panel can be compressed, the cost of the gate driving chip can be reduced, the probability of poor bonding of the gate driving chip can be reduced, and the OLED display panel can be improved. Yield.
  • the pulse signal combining circuit includes N output control units (only the first output control unit, the second output control unit, the third output control unit, the nth output control unit, and the Nth output control unit are shown in FIG. 1) And pulse signal output terminal OUT;
  • the first output control unit has a first control terminal connected to the first input pulse signal Input1, a second control terminal connected to the second input pulse signal Input2, and an output terminal connected to the pulse signal output terminal OUT for In each display period, after the first input pulse signal Input1 is first valid and the second input pulse signal Input2 is first valid, the control outputs the first input pulse signal Input1 to the pulse signal output terminal OUT. ;
  • a second output control unit the first control end is connected to the second input pulse signal Input2, the second control end is connected to the third input pulse signal Input3, and the output end is connected to the pulse signal output end OUT, Controlling, during each display period, the second input pulse is output to the pulse signal output terminal OUT during a period of time after the second input pulse signal Input2 is first valid and the third input pulse signal Input3 is first valid.
  • the first control terminal is connected to the third input pulse signal Input3, the second control terminal is connected to the fourth input pulse signal Input4, and the output end is connected to the pulse signal output terminal OUT for use in each display cycle
  • the control outputs the third input pulse signal Input3 to the pulse signal output end;
  • the nth output control unit the first control end is connected to the nth input pulse signal Inputn, the second control end is connected to the n+1th input pulse signal Inputn+1, and the output end is connected with the pulse signal output end OUT for During each display period, after the nth input pulse signal Inputn is first valid and the n+1th input pulse signal Inputn+1 is first valid, the control outputs the nth input pulse to the pulse signal output end.
  • Signal Inputn; n is a positive integer less than N;
  • the Nth output control unit has a first control terminal connected to the Nth input pulse signal InputN, a second control terminal connected to the first input pulse signal Input1, and an output terminal connected to the pulse signal output terminal OUT for each display period
  • the Nth input pulse signal InputN is output to the pulse signal output terminal OUT after the first Nth input pulse signal InputN is first valid until the first input pulse signal Input1 is first valid in the next display period.
  • each of the output control units includes:
  • a second output control transistor the gate is connected to the second control end of the output control unit, the first pole is connected to the second pole of the first output control transistor, and the second pole is connected to the first level;
  • a third output control transistor the gate is connected to the second pole of the first output control transistor, the first pole is connected to the first control terminal, and the second pole is connected to the pulse signal output end;
  • the third output control transistor is turned off when the second output control transistor is turned on and the gate of the third output control transistor is turned on to the first level.
  • the N output control units have the same structure; when the N input pulse signals are all positive pulses, the transistors used in the pulse combined signals according to the embodiments of the present disclosure are all n-type. TFT;
  • the first output control unit includes:
  • the first output control transistor M1_1, the gate and the first pole are connected to the first control terminal of the first output control unit, the first control terminal of the first output control unit is connected to the first input pulse signal Input1;
  • a second output control transistor M2_1 the gate is connected to the second control end of the first output control unit, the first pole is connected to the second pole of the first output control transistor M1_1, and the second pole is connected to the low level VGL2;
  • the second control end of the first output control unit is connected to the second input pulse signal Input2;
  • a third output control transistor M3_1 the gate is connected to the second pole of the first output control transistor M1_1, the first pole is connected to the first control terminal, and the second pole is connected to the pulse signal output terminal OUT;
  • M1_1 When Input1 is pulled low to low level, M1_1 is turned off; but the potential of the gate of M3_1 is maintained at a high level, M3_1 is maintained to be turned on, and Input1, which is low level at this time, continues to be output to OUT through M3_1, and is output to The OUT signal is pulled low until Input2 is high, and M2_1 is turned on to pull the potential of the gate of M3_1 low to low level VGL2, and M3_1 is turned off. During the display period, the first output control unit stops operating.
  • M1_2, M2_2, and M3_2 form a second output control unit, the gate of M1_2 is connected to Input2, the gate of M2_2 is connected to Input3, the second pole of M3_2 is connected to OUT, and the second pole of M2_2 is low.
  • Level VGL2 the gate of M1_2 is connected to Input2
  • the gate of M2_2 is connected to Input3
  • the second pole of M3_2 is connected to OUT
  • the second pole of M2_2 is low.
  • M1_2 and M3_2 are turned on, and M2_2 is turned off, thereby pulling the signal output to OUT. High, at this time, the potential of the gate of M3_2 is high.
  • M1_2 When Input2 is pulled low to low level, M1_2 is turned off; however, the potential of the gate of M3_2 is maintained at a high level, M3_2 is maintained to be turned on, and Input2, which is low level at this time, continues to be output to OUT through M3_2, and is output to The OUT signal is pulled low until Input3 is high, and M2_2 is turned on to pull the potential of the gate of M3_2 low to low level VGL2, and M3_2 is turned off. During the display period, the second output control unit stops jobs.
  • M1_3, M2_3 and M3_3 constitute a second output control unit, the gate of M1_3 is connected to Input3, the gate of M2_3 is connected to Input4, the second pole of M3_3 is connected to OUT, and the second pole of M2_3 is connected low.
  • Level VGL2 the gate of M1_3 is connected to Input3
  • the gate of M2_3 is connected to Input4
  • the second pole of M3_3 is connected to OUT
  • the second pole of M2_3 is connected low.
  • M1_3 and M3_3 are turned on, and M2_3 is turned off, thereby pulling the signal output to OUT. High, at this time, the potential of the gate of M3_3 is high.
  • M1_3 When Input3 is pulled low to low level, M1_3 is turned off; but the potential of the gate of M3_3 is maintained at a high level, M3_3 is maintained to be turned on, and Input3 which is low level at this time is continuously output to OUT through M3_3, and output to The OUT signal is pulled low until Input4 is high, and M2_3 is turned on to pull the potential of the gate of M3_3 low to low level VGL2, and M3_3 is turned off.
  • the third output control unit stops working;
  • M1_N, M2_N and M3_N constitute an Nth output control unit, the gate of M1_N is connected to InputN, the gate of M2_N is connected to Input1, the second pole of M3_N is connected to OUT, and the second pole of M2_N is low.
  • Level VGL2 the gate of M1_N is connected to InputN
  • the gate of M2_N is connected to Input1
  • the second pole of M3_N is connected to OUT
  • the second pole of M2_N is low.
  • M1_N and M3_N are turned on, and M2_N is turned off, thereby pulling the signal output to OUT. High, at this time, the potential of the gate of M3_N is high.
  • M1_N When InputN is pulled low to low level, M1_N is turned off, but the potential of the gate of M3_N is maintained at a high level, M3_N remains on, and Input3, which is low at this time, continues to be output to OUT through M3_N, and is output to The OUT signal is pulled low until Input1 is high in the next display period, and M2_N is turned on to pull the potential of the gate of M3_N low to low level VGL2, and M3_N is turned off.
  • the Nth output control unit stops working.
  • FIG. 3 is a first input pulse signal Input1, a second input pulse signal Input2, and a pulse signal output used by the pulse signal combining circuit according to the embodiment of the present disclosure when N is 2 and both Input1 and Input2 are forward pulse signals. Timing diagram of the signal output from terminal OUT.
  • N input pulse signals are all negative pulse signals
  • all of the transistors in FIG. 2 are replaced with p-type TFTs. Due to the electrical parameters of the p-type TFT and the n-type TFT The parameters are not identical, so the TFT size needs to be modified, and the low-level VGL2 in Figure 2 is replaced with a high-level VGH to achieve lossless combination of the negative-direction pulse signals.
  • 4 is a first input pulse signal Input1, a second input pulse signal Input2, and a pulse signal used by the pulse signal combining circuit according to the embodiment of the present disclosure when N is 2 and both Input1 and Input2 are negative pulse signals. Timing diagram of the signal output from the output OUT.
  • the pulse signal combining circuit shown in FIG. 2 in actual operation, may cause the potential of the gate of the third control transistor to be maintained at a high level when the output pulse signal needs to be pulled down due to leakage of the TFT, and thus the present disclosure
  • the output invalid control unit is further used to pull down the output pulse signal.
  • the pulse signal combining circuit of the embodiment of the present disclosure further includes:
  • the output invalidation control unit may include a gate potential control transistor, an invalid control transistor, and N active control transistors respectively accessing the N input pulse signals, where
  • the gate potential control transistor has a gate and a first pole connected to a second level
  • the invalid control transistor has a gate connected to the second pole of the gate potential control transistor, a first pole connected to the pulse signal output end, and a second pole connected to the first level;
  • the mth effective control transistor the gate is connected to the mth input pulse signal, the first pole is connected to the gate of the invalid control transistor, the second pole is connected to the third level, and m is a positive integer less than or equal to N;
  • the second level control causes the gate potential control transistor to be turned on
  • the mth effective control transistor When the mth input pulse signal is valid, the mth effective control transistor is turned on, so that the gate of the invalid control transistor is connected to the third level, so that the invalid control transistor is turned off;
  • the gate of the invalid control transistor is connected to the second level, so that the invalid control transistor is turned on, and the pulse signal output terminal is connected to the first level.
  • the N input pulse signals are all forward pulse signals, and all the transistors in the pulse signal combining circuit shown in FIG. 5 adopt an n-type TFT;
  • FIG. 5 also adds an output invalidation control unit
  • the output invalid control unit includes:
  • the first effective control transistor is identified as M6_1
  • the second active control transistor is identified as M6_2
  • the third active control transistor is identified as M6_3
  • the Nth active control transistor is identified as M6_N )among them
  • the gate potential control transistor M7, the gate and the first pole are connected to a high level VGH;
  • the inactive control transistor M8, the gate is connected to the second pole of the gate potential control transistor M7, the first pole is connected to the pulse signal output terminal OUT, and the second pole is connected to the low level VGL2;
  • the first effective control transistor M6_1 the gate is connected to the first input pulse signal Input1, the first pole is connected to the gate of the invalid control transistor M8, and the second pole is connected to the low level VGL1;
  • the second effective control transistor M6_2 the gate is connected to the first two input pulse signal Input2, the first pole is connected to the gate of the invalid control transistor M8, and the second pole is connected to the low level VGL1;
  • the third effective control transistor M6_3, the gate is connected to the third input pulse signal Input3, the first pole is connected to the gate of the invalid control transistor M8, and the second pole is connected to the low level VGL1;
  • the Nth effective control transistor M6_N the gate is connected to the Nth input pulse signal InputN, the first pole is connected to the gate of the invalid control transistor M8, and the second pole is connected to the low level VGL1;
  • the gate of the invalid control transistor M8 is connected to the high level VGH, so that the invalid control transistor M8 is turned on, and the pulse signal output terminal OUT is connected to the low level VGL2.
  • the output pulse signal is pulled low, so that even if there is a gate leakage condition of M3_N, (that is, when the output of the VGL2 low-level signal cannot be realized by the normal input control unit), the output pulse signal can be guaranteed to be pulled low.
  • VGL1 is smaller than VGL2, for example, VGL1 is usually -10V, and VGL2 is usually -5V; when the pulse signal is described in the embodiment of the present disclosure
  • VGL1 and VGL2 can be the same, for example, VGL1 is -5V, and VGL2 is also -5V.
  • the N input pulse signals are all negative pulse signals
  • all of the transistors in FIG. 5 are replaced with p-type TFTs. Since the electrical parameters of the p-type TFT and the n-type TFT parameters are not completely the same, it is necessary to modify the TFT size, and the The low level VGL2 and the low level VGL1 are replaced with a high level VGH, and the high level VGH in FIG. 5 is replaced with a low level VGL1 to realize the lossless combination of the negative direction pulse signals.
  • An embodiment of the present disclosure further provides a display panel including the pulse signal combining circuit described above;
  • the pulse signal combining circuit is configured to provide a gate driving signal to the display panel through a pulse signal output end.
  • the display panel may be an OLED display panel.
  • Embodiments of the present disclosure also provide a display device including the above display panel.

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Abstract

一种脉冲信号合并电路、显示面板和显示装置。脉冲信号合并电路用于将在每一显示周期内依次有效的N个输入脉冲信号合并，N为大于1的整数。脉冲信号合并电路包括N个输出控制单元和脉冲信号输出端（OUT），其中，第n输出控制单元的第一控制端接入第n输入脉冲信号，第二控制端接入第n+1输入脉冲信号，输出端与该脉冲信号输出端（OUT）连接，用于在每一显示周期内，在该第n输入脉冲信号首次有效之后而该第n+1输入脉冲信号首次有效之前的时间段内，控制向该脉冲信号输出端（OUT）输出该第n输入脉冲信号；n为小于N的正整数。

Description

脉冲信号合并电路、显示面板和显示装置
相关申请的交叉引用
本申请主张在2014年9月23日在中国提交的中国专利申请号No.201410490231.5的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种脉冲信号合并电路、显示面板和显示装置。
背景技术
在OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板中，由于像素补偿的需要，需要由多个脉冲宽度不同的分时有效的单脉冲驱动信号合并而成的多脉冲栅极驱动信号。然而，在现有技术中，使用一个单元电路来产生多脉冲栅极驱动信号，从单脉冲的原理上很难实现。而在大尺寸的OLED显示面板中，如果仅能使用产生单脉冲栅极驱动信号的栅极驱动电路，则像素驱动需要增加更多TFT(thin film transistor，薄膜晶体管)，从而导致OLED像素结构复杂，OLED有效发光面积减小。
发明内容
本公开的主要目的在于提供一种脉冲信号合并电路、显示面板和显示装置，以利用现有的单脉冲信号产生电路即可以直接通过增加或单元而实现多脉冲输出，实现对多个单脉冲信号的无损合并。
为了达到上述目的，本公开提供了一种脉冲信号合并电路，用于将N个输入脉冲信号合并为输出脉冲信号，所述N个输入脉冲信号在每一显示周期内依次有效，N为大于1的整数，所述脉冲信号合并电路包括所述脉冲信号合并电路包括N个输出控制单元和脉冲信号输出端，其中，
第n输出控制单元，第一控制端接入第n输入脉冲信号，第二控制端接入第n+1输入脉冲信号，输出端与该脉冲信号输出端连接，用于在每一显示周期内，在该第n输入脉冲信号首次有效之后而该第n+1输入脉冲信号首次有效之前的时间段内，控制向该脉冲信号输出端输出该第n输入脉冲信号；n为小于N的正整数；
第N输出控制单元，第一控制端接入第N输入脉冲信号，第二控制端接入第一输入脉冲信号，输出端与该脉冲信号输出端连接，用于在每一显示周期内在该第N输入脉冲信号首次有效之后直至在下一显示周期内第一输入脉冲信号首次有效之前的时间段，控制向该脉冲信号输出端输出该第N输入脉冲信号。
可选地，每一所述输出控制单元分别包括：
第一输出控制晶体管，栅极和第一极为该输出控制单元的第一控制端；
第二输出控制晶体管，栅极为该输出控制单元的第二控制端，第一极与该第一输出控制晶体管的第二极连接，第二极接入第一电平；
以及，第三输出控制晶体管，栅极与该第一输出控制晶体管的第二极连接，第一极与该第一控制端连接，第二极与该脉冲信号输出端连接；
当所述第二输出控制晶体管导通而所述第三输出控制晶体管的栅极接入所述第一电平时，所述第三输出控制晶体管断开。
可选地，所述N个输入脉冲信号都为正向脉冲信号，所述第一输出控制晶体管、所述第二输出控制晶体管和所述第三控制晶体管都为n型TFT，第一电平为低电平；
或者，所述N个输入脉冲信号都为负向脉冲信号，所述第一输出控制晶体管、所述第二输出控制晶体管和所述第三控制晶体管都为p型TFT，第一电平为高电平。
可选地，本公开所述的脉冲信号合并电路还包括：
输出无效控制单元，分别接入所述N个输入脉冲信号，并与该脉冲信号输出端连接，用于当该N个输入脉冲信号都无效时，控制向该脉冲信号输出端输出无效的电平信号。
可选地，所述输出无效控制单元包括栅极电位控制晶体管、无效控制晶体管和分别接入所述N个输入脉冲信号的N个有效控制晶体管，其中，
所述栅极电位控制晶体管，栅极和第一极接入第二电平；
所述无效控制晶体管，栅极与该栅极电位控制晶体管的第二极连接，第一极与该脉冲信号输出端连接，第二极接入第一电平；
第m有效控制晶体管，栅极接入第m输入脉冲信号，第一极与该无效控 制晶体管的栅极连接，第二极接入第三电平，m为小于或等于N的正整数；
所述第二电平控制使得该栅极电位控制晶体管导通；
当该第m输入脉冲信号有效时，该第m有效控制晶体管导通，使得该无效控制晶体管的栅极接入该第三电平，从而该无效控制晶体管断开；
当该N个输入脉冲信号都无效时，该无效控制晶体管的栅极接入该第二电平，从而该无效控制晶体管导通，所述脉冲信号输出端接入第一电平。
可选地，所述N个输入脉冲信号都为正向脉冲信号，所述栅极电位控制晶体管、所述无效控制晶体管和所述N个有效控制晶体管都为n型TFT，所述第一电平为低电平，所述第二电平为高电平，所述第三电平为低电平；
或者，所述N个输入脉冲信号都为负向脉冲信号，所述栅极电位控制晶体管、所述无效控制晶体管和所述N个有效控制晶体管都为p型TFT，所述第一电平为高电平，所述第二电平为低电平，所述第三电平为高电平。
可选地，当所述n型TFT为耗尽型TFT时，所述第三电平小于所述第一电平；当所述n型TFT为增强型TFT时，所述第三电平与所述第一电平相同。
本公开还提供了一种显示面板，其中，包括上述的脉冲信号合并电路；
所述脉冲信号合并电路用于通过脉冲信号输出端为所述显示面板提供栅极驱动信号。
可选地，所述显示面板为OLED显示面板。
本公开还提供了一种显示装置，包括上述的显示面板。
与现有技术相比，本公开所述的脉冲信号合并电路、显示面板和显示装置，可以把多个单脉冲信号(该单脉冲信号可以为单脉冲栅极驱动电路的单脉冲栅极驱动信号)合并在一起作为输出脉冲信号，对单脉冲信号产生电路而言没有特殊的修改，利用现有的单脉冲信号产生电路即可以直接通过增加或单元而实现多脉冲输出，实现对多个单脉冲信号的无损合并；当本公开实施例所述的脉冲信号合并电路应用于将单脉冲栅极驱动电路的单脉冲栅极驱动信号合并在一起作为多脉冲栅极驱动信号时，对单脉冲栅极驱动电路而言没有特殊的修改，利用现有的单脉冲栅极驱动电路即可以直接通过增加或单元而实现多脉冲输出。
附图说明
图1是本公开实施例所述的脉冲信号合并电路的结构框图；
图2是本公开另一实施例所述的脉冲信号合并电路的电路图；
图3是本公开实施例所述的脉冲信号合并电路采用的正向的第一输入脉冲信号Input1、正向的第二输入脉冲信号Input2和脉冲信号输出端OUT输出的信号的时序图；
图4是本公开实施例所述的脉冲信号合并电路采用的负向的第一输入脉冲信号Input1、负向的第二输入脉冲信号Input2和脉冲信号输出端OUT输出的信号的时序图；
图5是本公开又一实施例所述的脉冲信号合并电路的电路图；
图6是本公开再一实施例所述的脉冲信号合并电路的电路图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。在具体实施时，所述晶体管可为n型晶体管也可以为p型晶体管。
本公开实施例所述的脉冲信号合并电路，用于将N个输入脉冲信号合并为输出脉冲信号，所述N个输入脉冲信号在每一显示周期内依次有效，N为大于1的整数，所述脉冲信号合并电路包括N个输出控制单元和脉冲信号输出端，其中，
第n输出控制单元，第一控制端接入第n输入脉冲信号，第二控制端接入第n+1输入脉冲信号，输出端与该脉冲信号输出端连接；用于在每一显示周期内，在该第n输入脉冲信号首次有效之后而该第n+1输入脉冲信号首次有效之前的时间段内，控制向该脉冲信号输出端输出该第n输入脉冲信号；n为小于N的正整数；
第N输出控制单元，第一控制端接入第N输入脉冲信号，第二控制端接 入第一输入脉冲信号，输出端与该脉冲信号输出端连接，用于在每一显示周期内在该第N输入脉冲信号首次有效之后直至在下一显示周期内第一输入脉冲信号首次有效之前的时间段，控制向该脉冲信号输出端输出该第N输入脉冲信号。
本公开实施例所述的脉冲信号合并电路，可以把多个单脉冲信号(该单脉冲信号可以为单脉冲栅极驱动电路的单脉冲栅极驱动信号)合并在一起作为输出脉冲信号，对单脉冲信号产生电路而言没有特殊的修改，利用现有的单脉冲信号产生电路即可以直接通过增加或单元，即，本公开实施例所述的输出控制单元，而实现多脉冲输出，实现对多个单脉冲信号的无损合并。
当本公开实施例所述的脉冲信号合并电路应用于将单脉冲栅极驱动电路的单脉冲栅极驱动信号合并在一起作为多脉冲栅极驱动信号时，对单脉冲栅极驱动电路而言没有特殊的修改。因此，利用现有的单脉冲栅极驱动电路即可以直接通过增加或单元而实现多脉冲输出。
当本公开实施例所述的脉冲信号合并电路应用于显示面板时，可以压缩OLED显示面板边框尺寸，降低栅极驱动芯片的成本，减小栅极驱动芯片绑定不良的机率，提高OLED显示面板良率。
图1所示为本公开一具体实施例所述的脉冲信号合并电路，用于将N个输入脉冲信号合并为输出脉冲信号，所述N个输入脉冲信号在每一显示周期内依次有效，N为大于1的整数。所述脉冲信号合并电路包括N个输出控制单元(在图1中仅示出第一输出控制单元、第二输出控制单元、第三输出控制单元、第n输出控制单元和第N输出控制单元)和脉冲信号输出端OUT；其中
在图1中，第一输出控制单元，第一控制端接入第一输入脉冲信号Input1，第二控制端接入第二输入脉冲信号Input2，输出端与脉冲信号输出端OUT连接，用于在在每一显示周期内，在该第一输入脉冲信号Input1首次有效之后而该第二输入脉冲信号Input2首次有效之前的时间段内，控制向该脉冲信号输出端OUT输出该第一输入脉冲信号Input1；
第二输出控制单元，第一控制端接入第二输入脉冲信号Input2，第二控制端接入第三输入脉冲信号Input3，输出端与脉冲信号输出端OUT连接，用 于在在每一显示周期内，在该第二输入脉冲信号Input2首次有效之后而该第三输入脉冲信号Input3首次有效之前的时间段内，控制向该脉冲信号输出端OUT输出该第二输入脉冲信号Input2；
第三输出控制单元，第一控制端接入第三输入脉冲信号Input3，第二控制端接入第四输入脉冲信号Input4，输出端与脉冲信号输出端OUT连接，用于在在每一显示周期内，在该第三输入脉冲信号Input3首次有效之后而该第四输入脉冲信号Input4首次有效之前的时间段内，控制向该脉冲信号输出端输出该第三输入脉冲信号Input3；
第n输出控制单元，第一控制端接入第n输入脉冲信号Inputn，第二控制端接入第n+1输入脉冲信号Inputn+1，输出端与该脉冲信号输出端OUT连接，用于在每一显示周期内，在该第n输入脉冲信号Inputn首次有效之后而该第n+1输入脉冲信号Inputn+1首次有效之前的时间段内，控制向该脉冲信号输出端输出该第n输入脉冲信号Inputn；n为小于N的正整数；
第N输出控制单元，第一控制端接入第N输入脉冲信号InputN，第二控制端接入第一输入脉冲信号Input1，输出端与该脉冲信号输出端OUT连接，用于在每一显示周期内在该第N输入脉冲信号InputN首次有效之后直至在下一显示周期内第一输入脉冲信号Input1首次有效之前的时间段，控制向该脉冲信号输出端OUT输出该第N输入脉冲信号InputN。
具体地，每一所述输出控制单元分别包括：
第一输出控制晶体管，栅极和第一极连接该输出控制单元的第一控制端；
第二输出控制晶体管，栅极连接该输出控制单元的第二控制端，第一极与该第一输出控制晶体管的第二极连接，第二极接入第一电平；
以及，第三输出控制晶体管，栅极与该第一输出控制晶体管的第二极连接，第一极与该第一控制端连接，第二极与该脉冲信号输出端连接；
当所述第二输出控制晶体管导通而所述第三输出控制晶体管的栅极接入所述第一电平时，所述第三输出控制晶体管断开。
具体的，如图2所示，所述N个输出控制单元的结构相同；当N个输入脉冲信号都为正向脉冲时，本公开实施例所述的脉冲合并信号采用的晶体管都为n型TFT；其中
第一输出控制单元包括：
第一输出控制晶体管M1_1，栅极和第一极连接该第一输出控制单元的第一控制端，该第一输出控制单元的第一控制端接入第一输入脉冲信号Input1；
第二输出控制晶体管M2_1，栅极连接该第一输出控制单元的第二控制端，第一极与该第一输出控制晶体管M1_1的第二极连接，第二极接入低电平VGL2；该第一输出控制单元的第二控制端接入第二输入脉冲信号Input2；
以及，第三输出控制晶体管M3_1，栅极与该第一输出控制晶体管M1_1的第二极连接，第一极与该第一控制端连接，第二极与该脉冲信号输出端OUT连接；
当所述第二输出控制晶体管M2_1导通而所述第三输出控制晶体管M3_1的栅极接入所述低电平VGL2时，所述第三输出控制晶体管M3_1断开。
在实际操作时，在每一显示周期内，当Input1为高电平(即Input1有效)，并且Input2为低电平(即Input2无效)时，M1_1和M3_1导通，M2_1断开，从而将输出至OUT的信号拉高，此时M3_1的栅极的电位为高电平。当Input1被拉低为低电平时，M1_1断开；但是M3_1的栅极的电位维持为高电平，M3_1维持导通，通过M3_1继续将此时为低电平的Input1输出至OUT，输出至OUT的信号被拉低，直至Input2为高电平，M2_1导通从而将M3_1的栅极的电位拉低为低电平VGL2，M3_1断开。在该显示周期内，第一输出控制单元停止工作。
在图2中，M1_2、M2_2和M3_2组成第二输出控制单元，M1_2的栅极接入Input2，M2_2的栅极接入Input3，M3_2的第二极与OUT连接，M2_2的第二极接入低电平VGL2。
在每一显示周期内，当Input2为高电平(即Input2有效)，并Input3为低电平(即Input3无效)时，M1_2和M3_2导通，M2_2断开，从而将输出至OUT的信号拉高，此时M3_2的栅极的电位为高电平。当Input2被拉低为低电平时，M1_2断开；但是M3_2的栅极的电位维持为高电平，M3_2维持导通，通过M3_2继续将此时为低电平的Input2输出至OUT，输出至OUT的信号被拉低，直至Input3为高电平，M2_2导通从而将M3_2的栅极的电位拉低为低电平VGL2，M3_2断开。在该显示周期内，第二输出控制单元停止 工作。
在图2中，M1_3、M2_3和M3_3组成第二输出控制单元，M1_3的栅极接入Input3，M2_3的栅极接入Input4，M3_3的第二极与OUT连接，M2_3的第二极接入低电平VGL2。
在每一显示周期内，当Input3为高电平(即Input3有效)，并Input4为低电平(即Input3无效)时，M1_3和M3_3导通，M2_3断开，从而将输出至OUT的信号拉高，此时M3_3的栅极的电位为高电平。当Input3被拉低为低电平时，M1_3断开；但是M3_3的栅极的电位维持为高电平，M3_3维持导通，通过M3_3继续将此时为低电平的Input3输出至OUT，输出至OUT的信号被拉低，直至Input4为高电平，M2_3导通从而将M3_3的栅极的电位拉低为低电平VGL2，M3_3断开。在该显示周期内，第三输出控制单元停止工作；
第四输出控制单元到第N-1输出控制单元的工作过程依次类推。
在图2中，M1_N、M2_N和M3_N组成第N输出控制单元，M1_N的栅极接入InputN，M2_N的栅极接入Input1，M3_N的第二极与OUT连接，M2_N的第二极接入低电平VGL2。
在每一显示周期内，当InputN为高电平(即InputN有效)，并Input1为低电平(即Input1无效)时，M1_N和M3_N导通，M2_N断开，从而将输出至OUT的信号拉高，此时M3_N的栅极的电位为高电平。当InputN被拉低为低电平时，M1_N断开，但是M3_N的栅极的电位维持为高电平，M3_N维持导通，通过M3_N继续将此时为低电平的Input3输出至OUT，输出至OUT的信号被拉低，直至下一个显示周期内Input1为高电平，M2_N导通从而将M3_N的栅极的电位拉低为低电平VGL2，M3_N断开。第N输出控制单元停止工作。
图3是当N为2，并且Input1和Input2都为正向脉冲信号时，本公开实施例所述的脉冲信号合并电路采用的第一输入脉冲信号Input1、第二输入脉冲信号Input2和脉冲信号输出端OUT输出的信号的时序图。
根据另外一种实施方式，当所述N个输入脉冲信号都为负向脉冲信号时，图2中的所有晶体管更换为p型TFT。由于p型TFT的电气参数和n型TFT 参数不完全相同，因此需要修改TFT尺寸，并且将图2中的低电平VGL2更换为高电平VGH才能实现负向脉冲信号无损合并。图4是当N为2时，并Input1和Input2都为负向脉冲信号时，本公开实施例所述的脉冲信号合并电路采用的第一输入脉冲信号Input1、第二输入脉冲信号Input2和脉冲信号输出端OUT输出的信号的时序图。
如图2所示的脉冲信号合并电路，在实际操作时，由于TFT的漏电有可能使得在需要拉低输出脉冲信号时第三控制晶体管的栅极的电位不能维持为高电平，因此本公开进一步采用输出无效控制单元来拉低输出脉冲信号。
可选地，本公开实施例所述的脉冲信号合并电路还包括：
输出无效控制单元，分别接入所述N个输入脉冲信号，并与该脉冲信号输出端连接，用于当该N个输入脉冲信号都无效时，控制向该脉冲信号输出端输出无效的电平信号。
具体地，所述输出无效控制单元可以包括栅极电位控制晶体管、无效控制晶体管和分别接入所述N个输入脉冲信号的N个有效控制晶体管，其中，
所述栅极电位控制晶体管，栅极和第一极接入第二电平；
所述无效控制晶体管，栅极与该栅极电位控制晶体管的第二极连接，第一极与该脉冲信号输出端连接，第二极接入第一电平；
第m有效控制晶体管，栅极接入第m输入脉冲信号，第一极与该无效控制晶体管的栅极连接，第二极接入第三电平，m为小于或等于N的正整数；
所述第二电平控制使得该栅极电位控制晶体管导通；
当该第m输入脉冲信号有效时，该第m有效控制晶体管导通，使得该无效控制晶体管的栅极接入该第三电平，从而该无效控制晶体管断开；
当该N个输入脉冲信号都无效时，该无效控制晶体管的栅极接入该第二电平，从而该无效控制晶体管导通，所述脉冲信号输出端接入第一电平。
根据一种具体实施方式，如图5所示，所述N个输入脉冲信号都为正向脉冲信号，图5所示的脉冲信号合并电路中的所有晶体管都采用n型TFT；
在图2的基础上，图5还增加了输出无效控制单元；
该输出无效控制单元包括：
栅极电位控制晶体管M7、无效控制晶体管M8和分别接入所述N个输 入脉冲信号的N个有效控制晶体管(在图5中，第一有效控制晶体管标识为M6_1，第二有效控制晶体管标识为M6_2，第三有效控制晶体管标识为M6_3，第N有效控制晶体管标识为M6_N)其中，
所述栅极电位控制晶体管M7，栅极和第一极接入高电平VGH；
所述无效控制晶体管M8，栅极与该栅极电位控制晶体管M7的第二极连接，第一极与该脉冲信号输出端OUT连接，第二极接入低电平VGL2；
第一有效控制晶体管M6_1，栅极接入第一输入脉冲信号Input1，第一极与该无效控制晶体管M8的栅极连接，第二极接入低电平VGL1；
第二有效控制晶体管M6_2，栅极接入第一二输入脉冲信号Input2，第一极与该无效控制晶体管M8的栅极连接，第二极接入低电平VGL1；
第三有效控制晶体管M6_3，栅极接入第三输入脉冲信号Input3，第一极与该无效控制晶体管M8的栅极连接，第二极接入低电平VGL1；
第N有效控制晶体管M6_N，栅极接入第N输入脉冲信号InputN，第一极与该无效控制晶体管M8的栅极连接，第二极接入低电平VGL1；
当任一输入脉冲信号为高电平时，该输入脉冲信号接入的有效控制晶体管导通，使得该无效控制晶体管的栅极接入该低电平VGL1，从而该无效控制晶体管M8断开；
当该N个输入脉冲信号都为低电平时，该无效控制晶体管M8的栅极接入高电平VGH，从而该无效控制晶体管M8导通，所述脉冲信号输出端OUT接入低电平VGL2，输出脉冲信号被拉低，这样即使存在M3_N的栅极漏电情况，(即依靠正常的输入控制单元无法实现VGL2低电平信号的输出时)输出脉冲信号也可以保证被拉低。
当本公开实施例所述的脉冲信号合并电路采用n沟道耗尽型TFT时，VGL1小于VGL2，例如，VGL1通常为-10V，VGL2通常为-5V；当本公开实施例所述的脉冲信号合并电路采用n沟道增强型TFT时，VGL1和VGL2可以相同，例如VGL1为-5V，VGL2也为-5V。
根据另外一种实施方式，如图6所示，当所述N个输入脉冲信号都为负向脉冲信号时，图5中的所有晶体管更换为p型TFT。由于p型TFT的电气参数和n型TFT参数不完全相同，因此需要修改TFT尺寸，并且将图5中的 低电平VGL2和低电平VGL1更换为高电平VGH，将图5中的高电平VGH更换为低电平VGL1，才能实现负向脉冲信号无损合并。本公开实施例还提供一种显示面板，包括上述的脉冲信号合并电路；
所述脉冲信号合并电路用于通过脉冲信号输出端为所述显示面板提供栅极驱动信号。
可选地，所述显示面板可以为OLED显示面板。
本公开实施例还提供一种显示装置，包括上述的显示面板。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (10)

  1. 一种脉冲信号合并电路，用于将N个输入脉冲信号合并为输出脉冲信号，所述N个输入脉冲信号在每一显示周期内依次有效，N为大于1的整数，其中，所述脉冲信号合并电路包括N个输出控制单元和脉冲信号输出端，其中，
    第n输出控制单元，第一控制端接入第n输入脉冲信号，第二控制端接入第n+1输入脉冲信号，输出端与该脉冲信号输出端连接，用于在每一显示周期内，在该第n输入脉冲信号首次有效之后而该第n+1输入脉冲信号首次有效之前的时间段内，控制向该脉冲信号输出端输出该第n输入脉冲信号；n为小于N的正整数；
    第N输出控制单元，第一控制端接入第N输入脉冲信号，第二控制端接入第一输入脉冲信号，输出端与该脉冲信号输出端连接，用于在每一显示周期内在该第N输入脉冲信号首次有效之后直至在下一显示周期内第一输入脉冲信号首次有效之前的时间段，控制向该脉冲信号输出端输出该第N输入脉冲信号。
  2. 如权利要求1所述的脉冲信号合并电路，其中，每一所述输出控制单元分别包括：
    第一输出控制晶体管，栅极和第一极连接该输出控制单元的第一控制端；
    第二输出控制晶体管，栅极连接该输出控制单元的第二控制端，第一极与该第一输出控制晶体管的第二极连接，第二极接入第一电平；以及
    第三输出控制晶体管，栅极与该第一输出控制晶体管的第二极连接，第一极与该第一控制端连接，第二极与该脉冲信号输出端连接；
    当所述第二输出控制晶体管导通而所述第三输出控制晶体管的栅极接入所述第一电平时，所述第三输出控制晶体管断开。
  3. 如权利要求2所述的脉冲信号合并电路，其中，
    所述N个输入脉冲信号都为正向脉冲信号，所述第一输出控制晶体管、所述第二输出控制晶体管和所述第三控制晶体管都为n型TFT，第一电平为低电平；
    或者，所述N个输入脉冲信号都为负向脉冲信号，所述第一输出控制晶体管、所述第二输出控制晶体管和所述第三控制晶体管都为p型TFT，第一电平为高电平。
  4. 如权利要求1至3中任一权利要求所述的脉冲信号合并电路，还包括：
    输出无效控制单元，分别接入所述N个输入脉冲信号，并与该脉冲信号输出端连接，用于当该N个输入脉冲信号都无效时，控制向该脉冲信号输出端输出无效的电平信号。
  5. 如权利要求4所述的脉冲信号合并电路，其中，所述输出无效控制单元包括栅极电位控制晶体管、无效控制晶体管和分别接入所述N个输入脉冲信号的N个有效控制晶体管，其中，
    所述栅极电位控制晶体管，栅极和第一极接入第二电平；
    所述无效控制晶体管，栅极与该栅极电位控制晶体管的第二极连接，第一极与该脉冲信号输出端连接，第二极接入第一电平；
    第m有效控制晶体管，栅极接入第m输入脉冲信号，第一极与该无效控制晶体管的栅极连接，第二极接入第三电平，m为小于或等于N的正整数；
    所述第二电平控制使得该栅极电位控制晶体管导通；
    当该第m输入脉冲信号有效时，该第m有效控制晶体管导通，使得该无效控制晶体管的栅极接入该第三电平，从而该无效控制晶体管断开；
    当该N个输入脉冲信号都无效时，该无效控制晶体管的栅极接入该第二电平，从而该无效控制晶体管导通，所述脉冲信号输出端接入第一电平。
  6. 如权利要求5所述的脉冲信号合并电路，其中，
    所述N个输入脉冲信号都为正向脉冲信号，所述栅极电位控制晶体管、所述无效控制晶体管和所述N个有效控制晶体管都为n型TFT，所述第一电平为低电平，所述第二电平为高电平，所述第三电平为低电平；
    或者，所述N个输入脉冲信号都为负向脉冲信号，所述栅极电位控制晶体管、所述无效控制晶体管和所述N个有效控制晶体管都为p型TFT，所述第一电平为高电平，所述第二电平为低电平，所述第三电平为高电平。
  7. 如权利要求6所述的脉冲信号合并电路，其中，
    当所述n型TFT为耗尽型TFT时，所述第三电平小于所述第一电平；
    当所述n型TFT为增强型TFT时，所述第三电平与所述第一电平相同。
  8. 一种显示面板，包括如权利要求1至7中任一权利要求所述的脉冲信号合并电路；
    所述脉冲信号合并电路用于通过脉冲信号输出端为所述显示面板提供栅极驱动信号。
  9. 如权利要求8所述的显示面板，其中，所述显示面板为OLED显示面板。
  10. 一种显示装置，包括如权利要求8或9所述的显示面板。
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US20160253962A1 (en) 2016-09-01
EP3200177B1 (en) 2019-06-05
CN104252843B (zh) 2016-08-24
EP3200177A4 (en) 2018-03-21
KR101708801B1 (ko) 2017-02-21
US9536469B2 (en) 2017-01-03
JP2017531214A (ja) 2017-10-19
JP6406740B2 (ja) 2018-10-17
CN104252843A (zh) 2014-12-31
KR20160048713A (ko) 2016-05-04

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