WO2016019602A1 - 高解析度amoled背板制造方法 - Google Patents

高解析度amoled背板制造方法 Download PDF

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WO2016019602A1
WO2016019602A1 PCT/CN2014/084870 CN2014084870W WO2016019602A1 WO 2016019602 A1 WO2016019602 A1 WO 2016019602A1 CN 2014084870 W CN2014084870 W CN 2014084870W WO 2016019602 A1 WO2016019602 A1 WO 2016019602A1
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layer
forming
low temperature
gate
temperature polysilicon
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French (fr)
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徐源竣
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to KR1020177004225A priority Critical patent/KR101850662B1/ko
Priority to US14/390,026 priority patent/US9356239B2/en
Priority to JP2017506729A priority patent/JP6405036B2/ja
Priority to GB1700512.5A priority patent/GB2542532B/en
Publication of WO2016019602A1 publication Critical patent/WO2016019602A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6719—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions having significant overlap between the lightly-doped drains and the gate electrodes, e.g. gate-overlapped LDD [GOLDD] TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/30—Doping active layers, e.g. electron transporting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • H10K71/233—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers by photolithographic etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes

Definitions

  • the present invention relates to the field of display, and in particular to a high resolution AMOLED backplane manufacturing method. Background technique
  • the Organic Light Emitting Diode (OLED) display device Compared with the current mainstream display technology Thin Film Transistor Liquid Crystal Display (TFT-LCD), the Organic Light Emitting Diode (OLED) display device has a wide viewing angle, high brightness, high contrast, and low power consumption. The advantages of being lighter and thinner are the focus of current flat panel display technology.
  • the driving methods of the organic light emitting display device are classified into a passive matrix type (PM, Passive Matrix) and an active matrix type (AM, Active Matrix). Compared with passive matrix drives, active matrix drives have the advantages of large display information, low power consumption, long device life, and high picture contrast.
  • PM Passive Matrix
  • AM Active Matrix
  • active matrix organic light emitting diode (AMOLED) display devices mainly use low temperature polysilicon thin film transistors (LTPS-TFT) to drive OLED light.
  • active matrix organic light emitting diode display devices mainly include a switching TFT (Switch TFT), a driving TFT (Driving TFT), a storage capacitor (Cst), and an organic light emitting diode (OLED).
  • a storage capacitor stores a data signal switched by a switching TFT, and drives a driving TFT in response to the stored data signal, thereby causing the OLED to emit light using an output current corresponding to the data signal.
  • FIG. 1 it is a schematic diagram of a low temperature polysilicon array (LTPS-Array) structure of a conventional AMOLED backplane.
  • the preparation process of the AMOLED backplane is as follows: a first buffer layer 101 and a second buffer layer 102 are deposited on the substrate 100, the first buffer layer 101 may be SiNx, and the second buffer layer 102 may be SiOx; An amorphous silicon (a-Si) layer is deposited on the second buffer layer 102, and then a high-temperature dehydrogenation process is performed to remove the hydrogen content in the a-Si layer, and the a-Si layer is converted into low-temperature polysilicon by a low-temperature polysilicon process (Poly a layer of -Si), and patterning the low temperature polysilicon layer to form a patterned low temperature polysilicon layer 110; performing a P+ ion doping process on the patterned low temperature polysilicon layer 110, implanting P+ ions; depositing a gate on the
  • the patterning of the polysilicon layer or other layers is generally achieved by a yellow light process, which may be: coating a polycrystalline layer with a photo-sensitive material, the layer being a so-called photoresist layer, and then passing the light through the light. A cover is irradiated onto the photoresist to expose the photoresist layer. Since the reticle has a pattern of polysilicon layer, part of the light will pass through the reticle and illuminate the photoresist layer, so that the exposure of the photoresist layer is selective, and at the same time, the pattern on the reticle is completely copied to On the photoresist.
  • a yellow light process which may be: coating a polycrystalline layer with a photo-sensitive material, the layer being a so-called photoresist layer, and then passing the light through the light. A cover is irradiated onto the photoresist to expose the photoresist layer. Since the reticle has a pattern of polysilicon layer, part of the light will pass through the
  • a portion of the photoresist is removed using a suitable developer such that the photoresist layer develops the desired pattern.
  • a portion of the polysilicon layer is removed by an etching process, and the etching process may be performed by wet etching, dry etching, or both.
  • all the remaining patterned photoresist layers are removed, thereby completing the patterning process of the polysilicon layer.
  • the words “switching TFT”, “driving TFT” and “storage capacitor” generally indicate the positions of the respective switching TFTs, driving TFTs, and storage capacitor structures in the figure.
  • the patterned low temperature polysilicon layer 110 formed by patterning the low temperature polysilicon layer generally includes a storage capacitor region 1, a TFT source/drain region and channel regions 2, 3, and a storage capacitor region 1 for correspondingly forming a storage capacitor, a TFT source/drain
  • the polar region and the channel region 2 are used to correspondingly form the source/drain and the channel of the switching TFT, and the TFT source/drain region and the channel region 3 are used to correspondingly form the source/drain and the channel of the driving TFT.
  • a buffer layer and an amorphous silicon layer are first deposited, and the amorphous silicon layer is changed into a low-temperature polysilicon layer by laser crystallization, and then patterned by a yellow/etching process, and the low-temperature polysilicon layer is doped.
  • the other layers are formed via a deposition/yellow/etching process, respectively.
  • P+ is doped before the gate 120 is formed.
  • the switching TFT and the driving TFT are formed as gate overlap TFTs.
  • the overlap length L is at least 1.25 microns. Since the width of the gate must be widened, the transmittance of the panel is affected, which is not conducive to improving the resolution of the panel. Summary of the invention
  • an object of the present invention is to provide a high-resolution AMOLED backplane manufacturing method, which increases panel resolution.
  • the present invention provides a high-resolution AMOLED backplane manufacturing method, including:
  • Step 10 forming a first buffer layer on the substrate
  • Step 20 forming a low temperature polysilicon layer on the first buffer layer
  • Step 30 patterning the low temperature polysilicon layer to form a patterned low temperature polysilicon layer including a storage capacitor region and a TFT source/drain region and a channel region;
  • Step 40 forming a gate insulating layer on the patterned low temperature polysilicon layer, and setting a suitable photoresist mask on the gate insulating layer corresponding to the TFT source/drain region and the storage capacitor region, and Patterning the low temperature polysilicon layer for the first P+ ion doping;
  • Step 50 forming a gate metal layer on the gate insulating layer, patterning the gate metal layer to form a gate, and using the gate as a hard mask to perform a second P+ ion doping on the patterned low temperature polysilicon layer ;
  • Step 60 forming a first insulating layer on the gate, forming a source/drain on the first insulating layer, the source/drain passing through the first time in the TFT source/drain region via the contact window P+ ion doping and partial contact of the second P+ ion doping.
  • the second P+ ion doping is greater than the depth of the first P+ ion doping implanted P+ ions to the patterned low temperature polysilicon layer.
  • the method further includes forming a second buffer layer between the first buffer layer and the low temperature polysilicon layer.
  • the method further includes forming a second insulating layer between the first insulating layer and the source/drain. Wherein, further comprising forming a flat layer on the source/drain.
  • the electrode layer is formed on the flat layer.
  • the method further includes forming an organic layer on the electrode layer.
  • the gate is metal molybdenum.
  • the present invention also provides a high-resolution AMOLED backplane manufacturing method, including: Step 10: forming a first buffer layer on a substrate;
  • Step 20 forming a low temperature polysilicon layer on the first buffer layer
  • Step 30 patterning the low temperature polysilicon layer to form a patterned low temperature polysilicon layer including a storage capacitor region and a TFT source/drain region and a channel region;
  • Step 40 forming a gate insulating layer on the patterned low temperature polysilicon layer, providing a photoresist mask on the gate insulating layer corresponding to the TFT source/drain region and the storage capacitor region, and patterning the low temperature polysilicon layer Performing the first P+ ion doping;
  • Step 50 forming a gate metal layer on the gate insulating layer, patterning the gate metal layer to form a gate, and using the gate as a hard mask to perform a second P+ ion doping on the patterned low temperature polysilicon layer ;
  • Step 60 forming a first insulating layer on the gate, forming a source/drain on the first insulating layer, the source/drain passing through the first time in the TFT source/drain region via the contact window Partial contact of P+ ion doping and second P+ ion doping;
  • the second P+ ion doping is greater than the depth of the first P+ ion doping implanted P+ ions to the patterned low temperature polysilicon layer;
  • the high-resolution AMOLED backplane manufacturing method further includes forming a first buffer a second buffer layer between the layer and the low temperature polysilicon layer;
  • the high-resolution AMOLED backplane manufacturing method further includes forming a second insulating layer between the first insulating layer and the source/drain;
  • the high-resolution AMOLED backplane manufacturing method further includes forming a flat layer on the source/drain;
  • the high-resolution AMOLED backplane manufacturing method further includes forming an electrode layer on the flat layer;
  • the high-resolution AMOLED backplane manufacturing method further includes forming an organic layer on the electrode layer;
  • the high-resolution AMOLED backplane manufacturing method further includes forming a spacer on the organic layer;
  • the gate is metal molybdenum.
  • the high-resolution AMOLED backplane manufacturing method of the present invention improves the design rule and increases the panel resolution by performing two P+ dopings; and reduces the contact resistance of the source/drain and the P+ doped region.
  • FIG. 1 is a schematic structural view of a low-temperature polysilicon array of a conventional AMOLED backplane
  • FIG. 2 is a schematic structural view of an AMOLED backplane manufactured by using a high-resolution AMOLED backplane manufacturing method according to a preferred embodiment of the present invention
  • FIG. 5 are schematic diagrams showing a doping process in a preferred embodiment of a high-resolution AMOLED backplane manufacturing method according to the present invention.
  • FIG. 6 is a flow chart of a preferred embodiment of a high resolution AMOLED backplane manufacturing method of the present invention. detailed description
  • FIG. 6 there is shown a flow chart of a preferred embodiment of a high resolution AMOLED backplane manufacturing method of the present invention.
  • the method mainly includes:
  • Step 10 forming a first buffer layer on the substrate
  • Step 20 forming a low temperature polysilicon layer on the first buffer layer
  • Step 30 Patterning the low temperature polysilicon layer to form a storage capacitor region and a TFT source/drain Patterned low temperature polysilicon layer of regions and channel regions;
  • Step 40 forming a gate insulating layer on the patterned low temperature polysilicon layer, and setting a suitable photoresist mask on the gate insulating layer corresponding to the TFT source/drain region and the storage capacitor region, and patterning the low temperature
  • the polysilicon layer is subjected to the first P+ ion doping
  • Step 50 forming a gate metal layer on the gate insulating layer, patterning the gate metal layer to form a gate, and using the gate as a hard mask to perform a second P+ ion doping on the patterned low temperature polysilicon layer ;
  • Step 60 forming a first insulating layer on the gate, forming a source/drain on the first insulating layer, the source/drain passing through the first time in the TFT source/drain region via the contact window P+ ion doping and partial contact of the second P+ ion doping.
  • the method can be used in combination with the existing AMOLED backplane manufacturing method, and the difference from the existing AMOLED backplane manufacturing method is that two P+ ion doping is adopted, so there is no need to be different in the yellow light process as shown in FIG.
  • FIG. 2 is a schematic structural diagram of an AMOLED backplane manufactured by using a high-resolution AMOLED backplane manufacturing method according to a preferred embodiment of the present invention
  • FIGS. 3 to 5 are high resolutions of the present invention.
  • AMOLED Back Sheet Manufacturing Method A schematic diagram of a doping process in a preferred embodiment. The preparation process of the AMOLED backplane of the preferred embodiment is as follows:
  • the first buffer layer 201 and the second buffer layer 202 are deposited on the substrate 200.
  • the substrate 200 is a transparent substrate, which may be a glass substrate or a plastic substrate, and the first buffer layer 201 may be SiNx.
  • the second buffer layer 202 may be SiOx; depositing an amorphous silicon (a-Si) layer on the second buffer layer 202, and then performing a high-temperature dehydrogenation process to remove the hydrogen content in the a-Si layer, by a low-temperature polysilicon process, for example Laser crystallization converts the a-Si layer into a low temperature polysilicon (Poly-Si) layer and patterns the low temperature polysilicon layer to form a patterned low temperature polysilicon layer 210.
  • a-Si amorphous silicon
  • Poly-Si low temperature polysilicon
  • the patterned low temperature polysilicon layer 210 generally includes a storage capacitor region 21, a TFT source/drain region and channel regions 22, 23, a storage capacitor region 21 for correspondingly forming a storage capacitor, and a TFT source/drain region and channel region 22 for Corresponding to the source/drain and the channel forming the switching TFT, the TFT source/drain region 23 is used to correspondingly form the source/drain and the channel of the driving TFT.
  • a gate insulating layer 211 is formed on the patterned low temperature polysilicon layer 210, and a suitable photoresist mask (PR) 212 is disposed on the gate insulating layer 211 corresponding to the TFT source/drain regions 22, 23 and the storage capacitor region 21. And performing the first P+ ion doping on the patterned low temperature polysilicon layer 210.
  • PR photoresist mask
  • the polysilicon corresponding to the storage capacitor is not covered by the photoresist mask, so that the polysilicon here is doped after the first doping, conductivity It can be improved to require conductive features similar to metal conductors.
  • FIG. 4 is a schematic diagram of a second doping process in accordance with a preferred embodiment of the present invention
  • FIG. 5 is a schematic diagram of a second doping result.
  • a P+ region is formed in the patterned low temperature polysilicon layer 210 by the first doping.
  • the photoresist mask 212 is removed, a gate metal layer is deposited over the gate insulating layer 211, exposed through the gate metal layer by a mask process, and then developed and etched to form a gate 220.
  • the pole 220 can be molybdenum.
  • the gate 220 is directly self-aligned as a hard mask, and the patterned low temperature polysilicon layer is subjected to a second P+ ion doping.
  • the depth of the first P+ ion doping and the second P+ ion doping implant P+ ions to the patterned low temperature polysilicon layer 210 may be different, and the second doping may be performed. , and the ion implanter emits a higher depth than the first time. Therefore, as shown in FIG. 5, both ends of the original patterned low-temperature polysilicon layer 210 have a P++ doped portion and a P+ doped portion, and the storage capacitor region is a P+ doped portion of a general concentration.
  • the heterogeneous concentration distribution of the P++ region is a superposition of Gaussian distributions of two different depths.
  • a first insulating layer 221 and a second insulating layer 222 may also be deposited on the gate electrode 220.
  • the first insulating layer 221 and the second insulating layer 222 may be SiOx and SiNx.
  • the source/drain 230 can be formed on the second insulating layer 222 by using a contact window to contact the ultra-high concentration P++ region to lower the contact resistance of the source/drain 230 and the P+ doped region.
  • the OLED process can be connected to the driving TFT in the later stage, which shows a smaller impedance when controlling the OLED to be bright and dark.
  • the source/drain 230 may be a stacked structure formed by sputtering of Ti/Al/Ti, which effectively reduces the resistance value, greatly improves the TFT response rate, and contributes to an improvement in resolution and display size of the flat display device.
  • a flat layer 240 can be formed on the source/drain electrodes 230.
  • An electrode layer 250 is formed on the flat layer 240.
  • An organic photoresist layer 260 is formed on the electrode layer 250, and a spacer 270 is formed on the organic photoresist layer 260.
  • the electrode layer 250 may be an ITO/Ag/ITO laminated structure, which effectively increases the reflectance and increases the brightness of the OLED display.
  • the high-resolution AMOLED backplane manufacturing method of the present invention improves the design rule and increases the panel resolution by performing two P+ dopings; and reduces the contact resistance of the source/drain electrodes and the P+ doped region.

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Abstract

一种高解析度AMOLED背板制造方法。该方法包括：步骤10、在基板（200）上形成第一缓冲层（201）；步骤20、在该第一缓冲层（201）上形成低温多晶硅层（210）；步骤30、图案化该低温多晶硅层（210）；步骤40、形成栅极绝缘层（211），在该栅极绝缘层（211）上对应TFT源/漏极区域（22，23）和储存电容区域（21）设置适当的光阻掩膜（212），并对图案化低温多晶硅层（210）进行第一次P+离子掺杂；步骤50、形成栅极（220），将栅极（220）作为硬掩膜对该图案化低温多晶硅层（210）进行第二次P+离子掺杂；步骤60、在栅极（220）上形成第一绝缘层（221），在该第一绝缘层（221）上形成源/漏极（230），源/漏极（230）经由接触窗与该TFT源/漏极区域（22，23）中同时经过该第一次P+离子掺杂和第二次P+离子掺杂的部分接触。该高解析度AMOLED背板制造方法改善设计规则，增加面板解析度；降低源/漏极和P+掺杂区域的接触电阻。

Description

高解析度 AMOLED背板制造方法
技术领域
本发明涉及显示领域， 尤其涉及一种高解析度 AMOLED 背板制造方 法。 背景技术
有机发光二极管 (Organic Light Emitting Diode, OLED)显示装置相比现 在的主流显示技术薄膜晶体管液晶显示装置（Thin Film Transistor Liquid Crystal Display, TFT-LCD), 具有广视角、 高亮度、 高对比度、 低能耗、 体 积更轻薄等优点， 是目前平板显示技术关注的焦点。 有机发光显示装置的 驱动方法分为被动矩阵式 (PM, Passive Matrix)和主动矩阵式 (AM, Active Matrix)两种。 而相比被动矩阵式驱动， 主动矩阵式驱动具有显示信息量大、 功耗低、 器件寿命长、 画面对比度高等优点。
目前主动矩阵式有机发光二极管 （AMOLED) 显示装置主要使用低温 多晶硅薄膜晶体管 （LTPS-TFT) 驱动 OLED发光。 一般而言主动矩阵式有 机发光二极管显示装置主要包括开关 TFT (Switch TFT) ,驱动 TFT (Driving TFT) , 存储电容 （Cst) 和有机发光二极管 （OLED)。 常规的 AMOLED显 示装置中， 存储电容器存储由开关 TFT进行切换的数据信号， 并响应于所 存储的数据信号对驱动 TFT进行驱动， 从而利用与数据信号相对应的输出 电流使 OLED发光。
如图 1 所示， 其为一种传统 AMOLED 背板的低温多晶硅阵列 (LTPS-Array) 结构示意图。 该 AMOLED 背板的制备过程如下： 在基板 100上沉积第一緩冲层 101 及第二緩冲层 102， 该第一緩冲层 101 可以为 SiNx, 第二緩冲层 102可以为 SiOx; 在第二緩冲层 102上沉积非晶硅 (a-Si) 层， 然后进行高温脱氢制程去除 a-Si层中的氢含量， 通过低温多晶硅工艺 将该 a-Si层转化为低温多晶硅 (Poly-Si)层， 并图案化该低温多晶硅层形成 图案化低温多晶硅层 110 ; 对该图案化低温多晶硅层 110进行 P+离子摻杂 制程， 注入 P+离子； 在该图案化低温多晶硅层 110上沉积栅极绝缘层 （GI) 111 ; 在栅极绝缘层 111上方沉积栅极金属层， 该栅极金属层用掩膜工艺进 行曝光， 再经显影、 刻蚀工艺， 制作栅极 120 ; 在栅极 120上沉积第一绝缘 层 121及第二绝缘层 122，利用接触窗制作源 /漏极 130，再制作平坦层（PL) 140， 电极层 150， 有机层 （Bank) 160， 以及间隔物 （PS) 170。 多晶硅层或其它层的图案化一般通过黄光制程实现， 其具体方式可为： 在多晶硅层上覆一层感光 （photo-sensitive) 材料， 该层即所谓的光阻层， 然后使得光线通过光罩照射于光阻上以将该光阻层曝光。 由于光罩上具有 多晶硅层的图案， 将使部分光线得以穿过光罩而照射于光阻层上， 使得光 阻层的曝光具有选择性， 同时借此将光罩上的图案完整的复印至光阻上。 然后， 利用合适的显影液剂 （developer) 除去部分光阻， 使得光阻层显现 所需要的图案。 接着， 通过蚀刻工艺将部分多晶硅层去除， 在此的蚀刻工 艺可选用湿式蚀刻、 干式蚀刻或两者配合使用。 最后， 将剩余的图案化的 光阻层全部去除， 进而完成多晶硅层的图案化制程。
图 1及本发明其它附图中， 文字"开关 TFT"、 "驱动 TFT"及"存储电容" 大体上表示了相应的开关 TFT、 驱动 TFT及存储电容结构在图中的位置。 低温多晶硅层经图案化所形成图案化低温多晶硅层 110 大体上包括存储电 容区域 1， TFT源 /漏极区域和通道区 2、 3， 储电容区域 1 用于对应形成存 储电容， TFT源 /漏极区域和通道区 2用于对应形成开关 TFT的源 /漏极和通 道， TFT源 /漏极区域和通道区 3用于对应形成驱动 TFT的源 /漏极和通道。 如图 1所示，现有技术中先沉积緩冲层及非晶硅层， 非晶硅层经由激光结晶 变为低温多晶硅层， 接着通过黄光 /蚀刻制程图案化， 低温多晶硅层会进行 摻杂制程， 其它层分别经由沉积 /黄光 /蚀刻制程形成。 因为要形成存储电容 所以 P+要在栅极 120 形成之前进行摻杂 （doping) , 为了避免黄光偏移 (shift) , 开关 TFT、 驱动 TFT会做成栅极重叠 TFT (gate overlap TFT) , 单边重叠长度 L至少为 1.25微米。 由于必须加宽栅极宽度的做法， 影响到 面板的透光率， 不利于提高面板的解析度。 发明内容
因此， 本发明的目的在于提供一种高解析度 AMOLED背板制造方法， 增加面板解析度。
为实现上述目的， 本发明提供一种高解析度 AMOLED背板制造方法， 包括：
步骤 10、 在基板上形成第一緩冲层；
步骤 20、 在该第一緩冲层上形成低温多晶硅层；
步骤 30、图案化该低温多晶硅层形成包括存储电容区域和 TFT源 /漏极 区域和通道区域的图案化低温多晶硅层；
步骤 40、 在该图案化低温多晶硅层上形成栅极绝缘层， 在该栅极绝缘 层上对应该 TFT源 /漏极区域和储存电容区域设置适当的光阻掩膜， 并对该 图案化低温多晶硅层进行第一次 P+离子摻杂；
步骤 50、 在该栅极绝缘层上形成栅极金属层， 图案化该栅极金属层形 成栅极， 将该栅极作为硬掩膜对该图案化低温多晶硅层进行第二次 P+离子 摻杂；
步骤 60、在该栅极上形成第一绝缘层，在该第一绝缘层上形成源 /漏极， 该源 /漏极经由接触窗与该 TFT源 /漏极区域中同时经过该第一次 P+离子摻 杂和第二次 P+离子摻杂的部分接触。
其中， 该第二次 P+离子摻杂比该第一次 P+离子摻杂植入 P+离子到该 图案化低温多晶硅层的深度大。
其中， 还包括形成位于该第一緩冲层与低温多晶硅层之间的第二緩冲 层。
其中， 还包括形成位于该第一绝缘层与源 /漏极之间的第二绝缘层。 其中， 还包括在该源 /漏极上形成平坦层。
其中， 还包括在该平坦层上形成电极层。
其中， 还包括在该电极层上形成有机层。
其中， 还包括在该有机层上形成间隔物。
其中， 所述栅极为金属钼。
本发明还提供一种高解析度 AMOLED背板制造方法， 包括： 步骤 10、 在基板上形成第一緩冲层；
步骤 20、 在该第一緩冲层上形成低温多晶硅层；
步骤 30、图案化该低温多晶硅层形成包括存储电容区域和 TFT源 /漏极 区域和通道区域的图案化低温多晶硅层；
步骤 40、 在该图案化低温多晶硅层上形成栅极绝缘层， 在该栅极绝缘 层上对应该 TFT源 /漏极区域和存储电容区域设置光阻掩膜， 并对该图案化 低温多晶硅层进行第一次 P+离子摻杂；
步骤 50、 在该栅极绝缘层上形成栅极金属层， 图案化该栅极金属层形 成栅极， 将该栅极作为硬掩膜对该图案化低温多晶硅层进行第二次 P+离子 摻杂；
步骤 60、在该栅极上形成第一绝缘层，在该第一绝缘层上形成源 /漏极， 该源 /漏极经由接触窗与该 TFT源 /漏极区域中同时经过该第一次 P+离子摻 杂和第二次 P+离子摻杂的部分接触；
其中， 该第二次 P+离子摻杂比该第一次 P+离子摻杂植入 P+离子到该 图案化低温多晶硅层的深度大；
所述的高解析度 AMOLED背板制造方法，还包括形成位于该第一緩冲 层与低温多晶硅层之间的第二緩冲层；
所述的高解析度 AMOLED背板制造方法，还包括形成位于该第一绝缘 层与源 /漏极之间的第二绝缘层；
所述的高解析度 AMOLED 背板制造方法， 还包括在该源 /漏极上形成 平坦层；
所述的高解析度 AMOLED背板制造方法，还包括在该平坦层上形成电 极层；
所述的高解析度 AMOLED背板制造方法，还包括在该电极层上形成有 机层；
所述的高解析度 AMOLED背板制造方法，还包括在该有机层上形成间 隔物；
其中， 所述栅极为金属钼。
综上所述， 本发明高解析度 AMOLED背板制造方法通过进行两次 P+ 摻杂， 改善设计规则， 增加面板解析度； 降低源 /漏极和 P+摻杂区域的接触 电阻。 附图说明
下面结合附图， 通过对本发明的具体实施方式详细描述， 将使本发明 的技术方案及其他有益效果显而易见。
附图中，
图 1为一种传统 AMOLED背板的低温多晶硅阵列结构示意图； 图 2为应用本发明高解析度 AMOLED背板制造方法一较佳实施例所制 造的 AMOLED背板的结构示意图；
图 3至图 5为本发明高解析度 AMOLED背板制造方法一较佳实施例中 摻杂过程示意图；
图 6 为本发明高解析度 AMOLED 背板制造方法一较佳实施例的流程 图。 具体实施方式
参见图 6， 其为本发明高解析度 AMOLED背板制造方法一较佳实施例 的流程图。 该方法主要包括：
步骤 10、 在基板上形成第一緩冲层；
步骤 20、 在该第一緩冲层上形成低温多晶硅层；
步骤 30、图案化该低温多晶硅层形成包括存储电容区域和 TFT源 /漏极 区域和通道区域的图案化低温多晶硅层；
步骤 40、 在该图案化低温多晶硅层上形成栅极绝缘层， 在该栅极绝缘 层上对应该 TFT源 /漏极区域和储存电容区域设置适当的光阻掩膜， 并对该 图案化低温多晶硅层进行第一次 P+离子摻杂；
步骤 50、 在该栅极绝缘层上形成栅极金属层， 图案化该栅极金属层形 成栅极， 将该栅极作为硬掩膜对该图案化低温多晶硅层进行第二次 P+离子 摻杂；
步骤 60、在该栅极上形成第一绝缘层，在该第一绝缘层上形成源 /漏极， 该源 /漏极经由接触窗与该 TFT源 /漏极区域中同时经过该第一次 P+离子摻 杂和第二次 P+离子摻杂的部分接触。
该方法可以结合现有 AMOLED 背板制造方法来使用， 其区别于现有 AMOLED 背板制造方法的地方在于采用了两次 P+离子摻杂， 因此无需如 图 1 所示因顾虑黄光制程中不同层別的位移误差， 而必须加宽栅极宽度的 做法。 进而， 提升了透光率， 通过改善设计规则 （design rule) , 增加面板 解析度。
参见图 2及图 3至图 5， 图 2为应用本发明高解析度 AMOLED背板制 造方法一较佳实施例所制造的 AMOLED 背板的结构示意图， 图 3 至图 5 为本发明高解析度 AMOLED 背板制造方法一较佳实施例中摻杂过程示意 图。 该较佳实施例的 AMOLED背板的制备过程如下：
在基板 200上沉积第一緩冲层 201及第二緩冲层 202， 在本实施例中， 基板 200为透明基板， 其可为玻璃基板或塑胶基板， 第一緩冲层 201 可以 为 SiNx， 第二緩冲层 202可以为 SiOx; 在第二緩冲层 202上沉积非晶硅 (a - Si)层， 然后进行高温脱氢制程去除 a-Si 层中的氢含量， 通过低温多晶硅 工艺例如激光结晶将该 a-Si层转化为低温多晶硅 (Poly-Si)层， 并图案化该 低温多晶硅层形成图案化低温多晶硅层 210。
如图 3 所示， 其为本发明一较佳实施例中第一次摻杂过程示意图。 图 案化低温多晶硅层 210大体上包括存储电容区域 21， TFT源 /漏极区域和通 道区域 22、 23， 储电容区域 21 用于对应形成存储电容， TFT源 /漏极区域 和通道区域 22用于对应形成开关 TFT的源 /漏极和通道， TFT源 /漏极区域 23 用于对应形成驱动 TFT 的源 /漏极和通道。 在图案化低温多晶硅层 210 上形成栅极绝缘层 211，在该栅极绝缘层 211上对应该 TFT源 /漏极区域 22, 23和存储电容区域 21设置适当的光阻掩膜 （PR) 212， 并对图案化低温多 晶硅层 210进行第一次 P+离子摻杂。 第一次摻杂时， 对应于存储电容处的 多晶硅未采用光阻掩膜遮盖， 使得此处的多晶硅经第一次摻杂后， 导电性 能提高， 要求其具有类似金属导体的导电特征。
如图 4及 5所示， 图 4为本发明一较佳实施例中第二次摻杂过程示意 图， 图 5 为第二次摻杂结果示意图。 如图 4所示， 经第一次摻杂， 在图案 化低温多晶硅层 210 中形成 P+区域。 然后， 除去光阻掩膜 212， 在栅极绝 缘层 211 上方沉积栅极金属层， 通过该栅极金属层用掩膜工艺进行曝光， 再经显影、 刻蚀工艺， 制作栅极 220， 该栅极 220可以为钼。 将该栅极 220 作为硬掩膜 （hard mask) , 直接自我对准 （self-align) , 对该图案化低温多 晶硅层进行第二次 P+离子摻杂。 通过控制离子注入机的能量参数等， 可以 使该第一次 P+离子摻杂和第二次 P+离子摻杂植入 P+离子到该图案化低温 多晶硅层 210 的深度不同， 经第二次摻杂， 且离子注入机发射深度较第一 次程度高。 从而， 如图 5所示， 原图案化低温多晶硅层 210的两端分别具 有 P++摻杂部与 P+摻杂部， 存储电容区域则是一般浓度的 P+摻杂部。 P++ 区域的杂^浓度分布是两个不同深度的高斯分布的叠加。
还可以在栅极 220上沉积第一绝缘层 221及第二绝缘层 222，该第一绝 缘层 221及第二绝缘层 222可以为 SiOx及 SiNx。然后， 可以利用接触窗在 第二绝缘层 222上制作源 /漏极 230， 与超高浓度 P++区域接触， 降低源 /漏 极 230和 P+摻杂区域的接触 （contact) 电阻。 进而可以在后期 OLED制程 与驱动 TFT 导通连接， 在控制 OLED 亮暗时体现出更小阻抗。 该源 /漏极 230可以为 Ti/Al/Ti通过溅射形成的层叠结构， 有效降低电阻阻值， 极大提 高 TFT响应速率， 利于平面显示装置解析度提高和显示尺寸的扩大。
然后， 可以在源 /漏极 230上制作平坦层 240。 在平坦层 240上形成电 极层 250。 在电极层 250上形成有机光阻层 260， 在有机光阻层 260上形成 间隔物 270。 该电极层 250可以为 ITO/Ag/ITO层叠结构， 有效提高反射率, 增加 OLED显示器的亮度。 综上所述， 本发明高解析度 AMOLED背板制 造方法通过进行两次 P+摻杂， 改善设计规则， 增加面板解析度； 降低源 /漏 极和 P+摻杂区域的接触电阻。
以上所述， 对于本领域的普通技术人员来说， 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形， 而所有这些改变和变形 都应属于本发明后附的权利要求的保护范围。

Claims

权 利 要 求
1、 一种高解析度 AMOLED背板制造方法， 包括：
步骤 10、 在基板上形成第一緩冲层；
步骤 20、 在该第一緩冲层上形成低温多晶硅层；
步骤 30、图案化该低温多晶硅层形成包括存储电容区域和 TFT源 /漏极 区域和通道区域的图案化低温多晶硅层；
步骤 40、 在该图案化低温多晶硅层上形成栅极绝缘层， 在该栅极绝缘 层上对应该 TFT源 /漏极区域和存储电容区域设置光阻掩膜， 并对该图案化 低温多晶硅层进行第一次 P+离子摻杂；
步骤 50、 在该栅极绝缘层上形成栅极金属层， 图案化该栅极金属层形 成栅极， 将该栅极作为硬掩膜对该图案化低温多晶硅层进行第二次 P+离子 摻杂；
步骤 60、在该栅极上形成第一绝缘层，在该第一绝缘层上形成源 /漏极， 该源 /漏极经由接触窗与该 TFT源 /漏极区域中同时经过该第一次 P+离子摻 杂和第二次 P+离子摻杂的部分接触。
2、 如权利要求 1所述的高解析度 AMOLED背板制造方法， 其中， 该 第二次 P+离子摻杂比该第一次 P+离子摻杂植入 P+离子到该图案化低温多 晶硅层的深度大。
3、 如权利要求 1所述的高解析度 AMOLED背板制造方法， 还包括形 成位于该第一緩冲层与低温多晶硅层之间的第二緩冲层。
4、 如权利要求 1所述的高解析度 AMOLED背板制造方法， 还包括形 成位于该第一绝缘层与源 /漏极之间的第二绝缘层。
5、 如权利要求 1所述的高解析度 AMOLED背板制造方法， 还包括在 该源 /漏极上形成平坦层。
6、 如权利要求 5所述的高解析度 AMOLED背板制造方法， 还包括在 该平坦层上形成电极层。
7、 如权利要求 6所述的高解析度 AMOLED背板制造方法， 还包括在 该电极层上形成有机层。
8、 如权利要求 7所述的高解析度 AMOLED背板制造方法， 还包括在 该有机层上形成间隔物。
9、 如权利要求 1所述的高解析度 AMOLED背板制造方法， 其中， 所 述栅极为金属钼。
10、 一种高解析度 AMOLED背板制造方法， 包括：
步骤 10、 在基板上形成第一緩冲层；
步骤 20、 在该第一緩冲层上形成低温多晶硅层；
步骤 30、图案化该低温多晶硅层形成包括存储电容区域和 TFT源 /漏极 区域和通道区域的图案化低温多晶硅层；
步骤 40、 在该图案化低温多晶硅层上形成栅极绝缘层， 在该栅极绝缘 层上对应该 TFT源 /漏极区域和存储电容区域设置光阻掩膜， 并对该图案化 低温多晶硅层进行第一次 P+离子摻杂；
步骤 50、 在该栅极绝缘层上形成栅极金属层， 图案化该栅极金属层形 成栅极， 将该栅极作为硬掩膜对该图案化低温多晶硅层进行第二次 P+离子 摻杂；
步骤 60、在该栅极上形成第一绝缘层，在该第一绝缘层上形成源 /漏极， 该源 /漏极经由接触窗与该 TFT源 /漏极区域中同时经过该第一次 P+离子摻 杂和第二次 P+离子摻杂的部分接触；
其中， 该第二次 P+离子摻杂比该第一次 P+离子摻杂植入 P+离子到该 图案化低温多晶硅层的深度大；
所述的高解析度 AMOLED背板制造方法，还包括形成位于该第一緩冲 层与低温多晶硅层之间的第二緩冲层；
所述的高解析度 AMOLED背板制造方法，还包括形成位于该第一绝缘 层与源 /漏极之间的第二绝缘层；
所述的高解析度 AMOLED 背板制造方法， 还包括在该源 /漏极上形成 平坦层；
所述的高解析度 AMOLED背板制造方法，还包括在该平坦层上形成电 极层；
所述的高解析度 AMOLED背板制造方法，还包括在该电极层上形成有 机层；
所述的高解析度 AMOLED背板制造方法，还包括在该有机层上形成间 隔物；
其中， 所述栅极为金属钼。
PCT/CN2014/084870 2014-08-07 2014-08-21 高解析度amoled背板制造方法 Ceased WO2016019602A1 (zh)

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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104362125B (zh) * 2014-09-25 2017-10-13 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104465702B (zh) * 2014-11-03 2019-12-10 深圳市华星光电技术有限公司 Amoled背板的制作方法
CN104538429B (zh) * 2014-12-26 2019-07-02 深圳市华星光电技术有限公司 Amoled背板的制作方法及其结构
CN104810382A (zh) 2015-05-07 2015-07-29 深圳市华星光电技术有限公司 Amoled背板的制作方法及其结构
CN104952884B (zh) * 2015-05-13 2019-11-26 深圳市华星光电技术有限公司 Amoled背板结构及其制作方法
KR20170050729A (ko) * 2015-10-30 2017-05-11 엘지디스플레이 주식회사 유기 발광 표시 장치
CN105374882A (zh) * 2015-12-21 2016-03-02 武汉华星光电技术有限公司 一种低温多晶硅薄膜晶体管及其制备方法
CN106601778B (zh) 2016-12-29 2019-12-24 深圳市华星光电技术有限公司 Oled背板及其制作方法
WO2018179132A1 (ja) * 2017-03-29 2018-10-04 シャープ株式会社 表示デバイスの製造方法、表示デバイス、表示デバイスの製造装置、成膜装置
CN109300914A (zh) * 2018-09-27 2019-02-01 武汉华星光电半导体显示技术有限公司 阵列基板及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080206938A1 (en) * 2005-09-30 2008-08-28 Au Optronics Corp. Low temperature polysilicon thin film transistor display and method of fabricating the same
CN101593730A (zh) * 2008-05-29 2009-12-02 统宝光电股份有限公司 影像显示系统及其制造方法
CN101877310A (zh) * 2009-12-03 2010-11-03 四川虹视显示技术有限公司 Oled用tft基板的金属诱导结晶化方法
CN102522410A (zh) * 2011-12-22 2012-06-27 深圳莱宝高科技股份有限公司 一种薄膜晶体管阵列基板及其制作方法
CN103050410A (zh) * 2012-10-30 2013-04-17 昆山工研院新型平板显示技术中心有限公司 低温多晶硅薄膜晶体管的制造方法、低温多晶硅薄膜晶体管
CN103123910A (zh) * 2012-10-31 2013-05-29 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3197667B2 (ja) * 1993-03-24 2001-08-13 三洋電機株式会社 アキュムレーション型多結晶シリコン薄膜トランジスタ
US6127211A (en) * 1997-10-02 2000-10-03 Matsushita Electric Industrial Co., Ltd. Method of manufacturing transistor
TW495854B (en) * 2000-03-06 2002-07-21 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
TWI224806B (en) * 2000-05-12 2004-12-01 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
JP2002359252A (ja) * 2000-09-29 2002-12-13 Toshiba Corp 平面表示装置及びその製造方法
JP2002185008A (ja) * 2000-12-19 2002-06-28 Hitachi Ltd 薄膜トランジスタ
US7379136B2 (en) * 2003-12-29 2008-05-27 Lg.Philips Lcd Co., Ltd. Transflective type liquid crystal display device and method for fabricating the same
KR100579188B1 (ko) * 2004-02-12 2006-05-11 삼성에스디아이 주식회사 엘디디 구조를 갖는 박막트랜지스터
CN100447964C (zh) * 2004-11-26 2008-12-31 中华映管股份有限公司 薄膜晶体管的制作方法
JP5089077B2 (ja) * 2005-04-28 2012-12-05 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7507998B2 (en) 2006-09-29 2009-03-24 Tpo Displays Corp. System for displaying images and method for fabricating the same
KR100848341B1 (ko) * 2007-06-13 2008-07-25 삼성에스디아이 주식회사 박막트랜지스터, 그의 제조방법, 및 이를 포함하는유기전계발광표시장치
JP5708910B2 (ja) * 2010-03-30 2015-04-30 ソニー株式会社 薄膜トランジスタおよびその製造方法、並びに表示装置
KR101856221B1 (ko) * 2011-09-20 2018-05-09 엘지디스플레이 주식회사 박막 트랜지스터의 제조 방법 및 유기발광 표시장치의 제조 방법
CN103137557B (zh) * 2013-02-05 2015-02-18 深圳市华星光电技术有限公司 阵列基板、显示装置及阵列基板的制造方法
CN103137497A (zh) * 2013-02-26 2013-06-05 深圳市华星光电技术有限公司 低温多晶硅晶体管的制作方法
CN103151388B (zh) * 2013-03-05 2015-11-11 京东方科技集团股份有限公司 一种多晶硅薄膜晶体管及其制备方法、阵列基板
CN104240633B (zh) * 2013-06-07 2018-01-09 上海和辉光电有限公司 薄膜晶体管和有源矩阵有机发光二极管组件及其制造方法
CN103456765B (zh) * 2013-09-10 2015-09-16 深圳市华星光电技术有限公司 有源式有机电致发光器件背板及其制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080206938A1 (en) * 2005-09-30 2008-08-28 Au Optronics Corp. Low temperature polysilicon thin film transistor display and method of fabricating the same
CN101593730A (zh) * 2008-05-29 2009-12-02 统宝光电股份有限公司 影像显示系统及其制造方法
CN101877310A (zh) * 2009-12-03 2010-11-03 四川虹视显示技术有限公司 Oled用tft基板的金属诱导结晶化方法
CN102522410A (zh) * 2011-12-22 2012-06-27 深圳莱宝高科技股份有限公司 一种薄膜晶体管阵列基板及其制作方法
CN103050410A (zh) * 2012-10-30 2013-04-17 昆山工研院新型平板显示技术中心有限公司 低温多晶硅薄膜晶体管的制造方法、低温多晶硅薄膜晶体管
CN103123910A (zh) * 2012-10-31 2013-05-29 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置

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