CN104143533A - 高解析度amoled背板制造方法 - Google Patents

高解析度amoled背板制造方法 Download PDF

Info

Publication number
CN104143533A
CN104143533A CN201410387118.4A CN201410387118A CN104143533A CN 104143533 A CN104143533 A CN 104143533A CN 201410387118 A CN201410387118 A CN 201410387118A CN 104143533 A CN104143533 A CN 104143533A
Authority
CN
China
Prior art keywords
layer
polycrystalline silicon
temperature polycrystalline
silicon layer
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410387118.4A
Other languages
English (en)
Other versions
CN104143533B (zh
Inventor
徐源竣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201410387118.4A priority Critical patent/CN104143533B/zh
Priority to GB1700512.5A priority patent/GB2542532B/en
Priority to KR1020177004225A priority patent/KR101850662B1/ko
Priority to US14/390,026 priority patent/US9356239B2/en
Priority to PCT/CN2014/084870 priority patent/WO2016019602A1/zh
Priority to JP2017506729A priority patent/JP6405036B2/ja
Publication of CN104143533A publication Critical patent/CN104143533A/zh
Application granted granted Critical
Publication of CN104143533B publication Critical patent/CN104143533B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/124Insulating layers formed between TFT elements and OLED elements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/30Doping active layers, e.g. electron transporting layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78627Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00Organic light-emitting devices
    • H10K50/80Constructional details
    • H10K50/805Electrodes
    • H10K50/81Anodes
    • H10K50/818Reflective anodes, e.g. ITO combined with thick metallic layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/1201Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/121Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/131Interconnections, e.g. wiring lines or terminals
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • H10K71/233Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers by photolithographic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明涉及一种高解析度AMOLED背板制造方法。该方法包括:步骤10、在基板上形成第一缓冲层;步骤20、在该第一缓冲层上形成低温多晶硅层;步骤30、图案化该低温多晶硅层;步骤40、形成栅极绝缘层,在该栅极绝缘层上对应该TFT源/漏极区域和储存电容区域设置适当的光阻掩膜,并对图案化低温多晶硅层进行第一次P+离子掺杂;步骤50、形成栅极,将栅极作为硬掩膜对该图案化低温多晶硅层进行第二次P+离子掺杂;步骤60、在栅极上形成第一绝缘层,在该第一绝缘层上形成源/漏极,源/漏极经由接触窗与该TFT源/漏极区域中同时经过该第一次P+离子掺杂和第二次P+离子掺杂的部分接触。本发明高解析度AMOLED背板制造方法改善设计规则,增加面板解析度;降低源/漏极和P+掺杂区域的接触电阻。

Description

高解析度AMOLED背板制造方法
技术领域
本发明涉及显示领域,尤其涉及一种高解析度AMOLED背板制造方法。
背景技术
有机发光二极管(Organic Light Emitting Diode,OLED)显示装置相比现在的主流显示技术薄膜晶体管液晶显示装置(Thin Film Transistor Liquid CrystalDisplay,TFT-LCD),具有广视角、高亮度、高对比度、低能耗、体积更轻薄等优点,是目前平板显示技术关注的焦点。有机发光显示装置的驱动方法分为被动矩阵式(PM,Passive Matrix)和主动矩阵式(AM,Active Matrix)两种。而相比被动矩阵式驱动,主动矩阵式驱动具有显示信息量大、功耗低、器件寿命长、画面对比度高等优点。
目前主动矩阵式有机发光二极管(AMOLED)显示装置主要使用低温多晶硅薄膜晶体管(LTPS-TFT)驱动OLED发光。一般而言主动矩阵式有机发光二极管显示装置主要包括开关TFT(Switch TFT)、驱动TFT(DrivingTFT)、存储电容(Cst)和有机发光二极管(OLED)。常规的AMOLED显示装置中,存储电容器存储由开关TFT进行切换的数据信号,并响应于所存储的数据信号对驱动TFT进行驱动,从而利用与数据信号相对应的输出电流使OLED发光。
如图1所示,其为一种传统AMOLED背板的低温多晶硅阵列(LTPS-Array)结构示意图。该AMOLED背板的制备过程如下:在基板100上沉积第一缓冲层101及第二缓冲层102,该第一缓冲层101可以为SiNx,第二缓冲层102可以为SiOx;在第二缓冲层102上沉积非晶硅(a-Si)层,然后进行高温脱氢制程去除a-Si层中的氢含量,通过低温多晶硅工艺将该a-Si层转化为低温多晶硅(Poly-Si)层,并图案化该低温多晶硅层形成图案化低温多晶硅层110;对该图案化低温多晶硅层110进行P+离子掺杂制程,注入P+离子;在该图案化低温多晶硅层110上沉积栅极绝缘层(GI)111;在栅极绝缘层111上方沉积栅极金属层,该栅极金属层用掩膜工艺进行曝光,再经显影、刻蚀工艺,制作栅极120;在栅极120上沉积第一绝缘层121及第二绝缘层122,利用接触窗制作源/漏极130,再制作平坦层(PL)140,电极层150,有机层(Bank)160,以及间隔物(PS)170。
多晶硅层或其它层的图案化一般通过黄光制程实现,其具体方式可为:在多晶硅层上覆一层感光(photo-sensitive)材料,该层即所谓的光阻层,然后使得光线通过光罩照射于光阻上以将该光阻层曝光。由于光罩上具有多晶硅层的图案,将使部分光线得以穿过光罩而照射于光阻层上,使得光阻层的曝光具有选择性,同时借此将光罩上的图案完整的复印至光阻上。然后,利用合适的显影液剂(developer)除去部分光阻,使得光阻层显现所需要的图案。接着,通过蚀刻工艺将部分多晶硅层去除,在此的蚀刻工艺可选用湿式蚀刻、干式蚀刻或两者配合使用。最后,将剩余的图案化的光阻层全部去除,进而完成多晶硅层的图案化制程。
图1及本发明其它附图中,文字“开关TFT”、“驱动TFT”及“存储电容”大体上表示了相应的开关TFT、驱动TFT及存储电容结构在图中的位置。低温多晶硅层经图案化所形成图案化低温多晶硅层110大体上包括存储电容区域1,TFT源/漏极区域和通道区2、3,储电容区域1用于对应形成存储电容,TFT源/漏极区域和通道区2用于对应形成开关TFT的源/漏极和通道,TFT源/漏极区域和通道区3用于对应形成驱动TFT的源/漏极和通道。如图1所示,现有技术中先沉积缓冲层及非晶硅层,非晶硅层经由激光结晶变为低温多晶硅层,接着通过黄光/蚀刻制程图案化,低温多晶硅层会进行掺杂制程,其它层分别经由沉积/黄光/蚀刻制程形成。因为要形成存储电容所以P+要在栅极120形成之前进行掺杂(doping),为了避免黄光偏移(shift),开关TFT、驱动TFT会做成栅极重叠TFT(gate overlap TFT),单边重叠长度L至少为1.25微米。由于必须加宽栅极宽度的做法,影响到面板的透光率,不利于提高面板的解析度。
发明内容
因此,本发明的目的在于提供一种高解析度AMOLED背板制造方法,增加面板解析度。
为实现上述目的,本发明提供一种高解析度AMOLED背板制造方法,包括:
步骤10、在基板上形成第一缓冲层;
步骤20、在该第一缓冲层上形成低温多晶硅层;
步骤30、图案化该低温多晶硅层形成包括存储电容区域和TFT源/漏极区域和通道区域的图案化低温多晶硅层;
步骤40、在该图案化低温多晶硅层上形成栅极绝缘层,在该栅极绝缘层上对应该TFT源/漏极区域和储存电容区域设置适当的光阻掩膜,并对该图案化低温多晶硅层进行第一次P+离子掺杂;
步骤50、在该栅极绝缘层上形成栅极金属层,图案化该栅极金属层形成栅极,将该栅极作为硬掩膜对该图案化低温多晶硅层进行第二次P+离子掺杂;
步骤60、在该栅极上形成第一绝缘层,在该第一绝缘层上形成源/漏极,该源/漏极经由接触窗与该TFT源/漏极区域中同时经过该第一次P+离子掺杂和第二次P+离子掺杂的部分接触。
其中,该第二次P+离子掺杂比该第一次P+离子掺杂植入P+离子到该图案化低温多晶硅层的深度大。
其中,还包括形成位于该第一缓冲层与低温多晶硅层之间的第二缓冲层。
其中,还包括形成位于该第一绝缘层与源/漏极之间的第二绝缘层。
其中,还包括在该源/漏极上形成平坦层。
其中,还包括在该平坦层上形成电极层。
其中,还包括在该电极层上形成有机层。
其中,还包括在该有机层上形成间隔物。
其中,所述栅极为金属钼。
综上所述,本发明高解析度AMOLED背板制造方法通过进行两次P+掺杂,改善设计规则,增加面板解析度;降低源/漏极和P+掺杂区域的接触电阻。
附图说明
下面结合附图,通过对本发明的具体实施方式详细描述,将使本发明的技术方案及其他有益效果显而易见。
附图中,
图1为一种传统AMOLED背板的低温多晶硅阵列结构示意图;
图2为应用本发明高解析度AMOLED背板制造方法一较佳实施例所制造的AMOLED背板的结构示意图;
图3至图5为本发明高解析度AMOLED背板制造方法一较佳实施例中掺杂过程示意图;
图6为本发明高解析度AMOLED背板制造方法一较佳实施例的流程图。
具体实施方式
参见图6,其为本发明高解析度AMOLED背板制造方法一较佳实施例的流程图。该方法主要包括:
步骤10、在基板上形成第一缓冲层;
步骤20、在该第一缓冲层上形成低温多晶硅层;
步骤30、图案化该低温多晶硅层形成包括存储电容区域和TFT源/漏极区域和通道区域的图案化低温多晶硅层;
步骤40、在该图案化低温多晶硅层上形成栅极绝缘层,在该栅极绝缘层上对应该TFT源/漏极区域和储存电容区域设置适当的光阻掩膜,并对该图案化低温多晶硅层进行第一次P+离子掺杂;
步骤50、在该栅极绝缘层上形成栅极金属层,图案化该栅极金属层形成栅极,将该栅极作为硬掩膜对该图案化低温多晶硅层进行第二次P+离子掺杂;
步骤60、在该栅极上形成第一绝缘层,在该第一绝缘层上形成源/漏极,该源/漏极经由接触窗与该TFT源/漏极区域中同时经过该第一次P+离子掺杂和第二次P+离子掺杂的部分接触。
该方法可以结合现有AMOLED背板制造方法来使用,其区别于现有AMOLED背板制造方法的地方在于采用了两次P+离子掺杂,因此无需如图1所示因顾虑黄光制程中不同层別的位移误差,而必须加宽栅极宽度的做法。进而,提升了透光率,通过改善设计规则(design rule),增加面板解析度。
参见图2及图3至图5,图2为应用本发明高解析度AMOLED背板制造方法一较佳实施例所制造的AMOLED背板的结构示意图,图3至图5为本发明高解析度AMOLED背板制造方法一较佳实施例中掺杂过程示意图。该较佳实施例的AMOLED背板的制备过程如下:
在基板200上沉积第一缓冲层201及第二缓冲层202,在本实施例中,基板200为透明基板,其可为玻璃基板或塑胶基板,第一缓冲层201可以为SiNx,第二缓冲层202可以为SiOx;在第二缓冲层202上沉积非晶硅(a-Si)层,然后进行高温脱氢制程去除a-Si层中的氢含量,通过低温多晶硅工艺例如激光结晶将该a-Si层转化为低温多晶硅(Poly-Si)层,并图案化该低温多晶硅层形成图案化低温多晶硅层210。
如图3所示,其为本发明一较佳实施例中第一次掺杂过程示意图。图案化低温多晶硅层210大体上包括存储电容区域21,TFT源/漏极区域和通道区域22、23,储电容区域21用于对应形成存储电容,TFT源/漏极区域和通道区域22用于对应形成开关TFT的源/漏极和通道,TFT源/漏极区域23用于对应形成驱动TFT的源/漏极和通道。在图案化低温多晶硅层210上形成栅极绝缘层211,在该栅极绝缘层211上对应该TFT源/漏极区域22,23和存储电容区域21设置适当的光阻掩膜(PR)212,并对图案化低温多晶硅层210进行第一次P+离子掺杂。第一次掺杂时,对应于存储电容处的多晶硅未采用光阻掩膜遮盖,使得此处的多晶硅经第一次掺杂后,导电性能提高,要求其具有类似金属导体的导电特征。
如图4及5所示,图4为本发明一较佳实施例中第二次掺杂过程示意图,图5为第二次掺杂结果示意图。如图4所示,经第一次掺杂,在图案化低温多晶硅层210中形成P+区域。然后,除去光阻掩膜212,在栅极绝缘层211上方沉积栅极金属层,通过该栅极金属层用掩膜工艺进行曝光,再经显影、刻蚀工艺,制作栅极220,该栅极220可以为钼。将该栅极220作为硬掩膜(hard mask),直接自我对准(self-align),对该图案化低温多晶硅层进行第二次P+离子掺杂。通过控制离子注入机的能量参数等,可以使该第一次P+离子掺杂和第二次P+离子掺杂植入P+离子到该图案化低温多晶硅层210的深度不同,经第二次掺杂,且离子注入机发射深度较第一次程度高。从而,如图5所示,原图案化低温多晶硅层210的两端分别具有P++掺杂部与P+掺杂部,存储电容区域则是一般浓度的P+掺杂部。P++区域的杂质浓度分布是两个不同深度的高斯分布的叠加。
还可以在栅极220上沉积第一绝缘层221及第二绝缘层222,该第一绝缘层221及第二绝缘层222可以为SiOx及SiNx。然后,可以利用接触窗在第二绝缘层222上制作源/漏极230,与超高浓度P++区域接触,降低源/漏极230和P+掺杂区域的接触(contact)电阻。进而可以在后期OLED制程与驱动TFT导通连接,在控制OLED亮暗时体现出更小阻抗。该源/漏极230可以为Ti/Al/Ti通过溅射形成的层叠结构,有效降低电阻阻值,极大提高TFT响应速率,利于平面显示装置解析度提高和显示尺寸的扩大。
然后,可以在源/漏极230上制作平坦层240。在平坦层240上形成电极层250。在电极层250上形成有机光阻层260,在有机光阻层260上形成间隔物270。该电极层250可以为ITO/Ag/ITO层叠结构,有效提高反射率,增加OLED显示器的亮度。综上所述,本发明高解析度AMOLED背板制造方法通过进行两次P+掺杂,改善设计规则,增加面板解析度;降低源/漏极和P+掺杂区域的接触电阻。
以上所述,对于本领域的普通技术人员来说,可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形,而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (9)

1.一种高解析度AMOLED背板制造方法,其特征在于,包括:
步骤10、在基板上形成第一缓冲层;
步骤20、在该第一缓冲层上形成低温多晶硅层;
步骤30、图案化该低温多晶硅层形成包括存储电容区域和TFT源/漏极区域和通道区域的图案化低温多晶硅层;
步骤40、在该图案化低温多晶硅层上形成栅极绝缘层,在该栅极绝缘层上对应该TFT源/漏极区域和存储电容区域设置光阻掩膜,并对该图案化低温多晶硅层进行第一次P+离子掺杂;
步骤50、在该栅极绝缘层上形成栅极金属层,图案化该栅极金属层形成栅极,将该栅极作为硬掩膜对该图案化低温多晶硅层进行第二次P+离子掺杂;
步骤60、在该栅极上形成第一绝缘层,在该第一绝缘层上形成源/漏极,该源/漏极经由接触窗与该TFT源/漏极区域中同时经过该第一次P+离子掺杂和第二次P+离子掺杂的部分接触。
2.如权利要求1所述的高解析度AMOLED背板制造方法,其特征在于,该第二次P+离子掺杂比该第一次P+离子掺杂植入P+离子到该图案化低温多晶硅层的深度大。
3.如权利要求1所述的高解析度AMOLED背板制造方法,其特征在于,还包括形成位于该第一缓冲层与低温多晶硅层之间的第二缓冲层。
4.如权利要求1所述的高解析度AMOLED背板制造方法,其特征在于,还包括形成位于该第一绝缘层与源/漏极之间的第二绝缘层。
5.如权利要求1所述的高解析度AMOLED背板制造方法,其特征在于,还包括在该源/漏极上形成平坦层。
6.如权利要求5所述的高解析度AMOLED背板制造方法,其特征在于,还包括在该平坦层上形成电极层。
7.如权利要求6所述的高解析度AMOLED背板制造方法,其特征在于,还包括在该电极层上形成有机层。
8.如权利要求7所述的高解析度AMOLED背板制造方法,其特征在于,还包括在该有机层上形成间隔物。
9.如权利要求1所述的高解析度AMOLED背板制造方法,其特征在于,所述栅极为金属钼。
CN201410387118.4A 2014-08-07 2014-08-07 高解析度amoled背板制造方法 Active CN104143533B (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CN201410387118.4A CN104143533B (zh) 2014-08-07 2014-08-07 高解析度amoled背板制造方法
GB1700512.5A GB2542532B (en) 2014-08-07 2014-08-21 Method for manufacturing high resolution AMOLED backplane
KR1020177004225A KR101850662B1 (ko) 2014-08-07 2014-08-21 고해상도 amoled 백플레인의 제조방법
US14/390,026 US9356239B2 (en) 2014-08-07 2014-08-21 Method for manufacturing high resolution AMOLED backplane
PCT/CN2014/084870 WO2016019602A1 (zh) 2014-08-07 2014-08-21 高解析度amoled背板制造方法
JP2017506729A JP6405036B2 (ja) 2014-08-07 2014-08-21 高解像度を有するamoledバックプレートの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410387118.4A CN104143533B (zh) 2014-08-07 2014-08-07 高解析度amoled背板制造方法

Publications (2)

Publication Number Publication Date
CN104143533A true CN104143533A (zh) 2014-11-12
CN104143533B CN104143533B (zh) 2017-06-27

Family

ID=51852677

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410387118.4A Active CN104143533B (zh) 2014-08-07 2014-08-07 高解析度amoled背板制造方法

Country Status (6)

Country Link
US (1) US9356239B2 (zh)
JP (1) JP6405036B2 (zh)
KR (1) KR101850662B1 (zh)
CN (1) CN104143533B (zh)
GB (1) GB2542532B (zh)
WO (1) WO2016019602A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104538429A (zh) * 2014-12-26 2015-04-22 深圳市华星光电技术有限公司 Amoled背板的制作方法及其结构
CN106601778A (zh) * 2016-12-29 2017-04-26 深圳市华星光电技术有限公司 Oled背板及其制作方法
US10038043B2 (en) 2015-05-07 2018-07-31 Shenzhen China Star Optoelectronics Technology Co., Ltd. Method for manufacturing AMOLED backplane and structure thereof
CN109300914A (zh) * 2018-09-27 2019-02-01 武汉华星光电半导体显示技术有限公司 阵列基板及其制作方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104362125B (zh) * 2014-09-25 2017-10-13 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN104465702B (zh) * 2014-11-03 2019-12-10 深圳市华星光电技术有限公司 Amoled背板的制作方法
CN104952884B (zh) * 2015-05-13 2019-11-26 深圳市华星光电技术有限公司 Amoled背板结构及其制作方法
KR20170050729A (ko) * 2015-10-30 2017-05-11 엘지디스플레이 주식회사 유기 발광 표시 장치
CN105374882A (zh) * 2015-12-21 2016-03-02 武汉华星光电技术有限公司 一种低温多晶硅薄膜晶体管及其制备方法
US10672854B2 (en) * 2017-03-29 2020-06-02 Sharp Kabushiki Kaisha Display device

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1213849A (zh) * 1997-10-02 1999-04-14 松下电器产业株式会社 晶体管的制造方法
CN1637548A (zh) * 2003-12-29 2005-07-13 Lg.菲利浦Lcd株式会社 透射反射型液晶显示器件及其制造方法
CN1655366A (zh) * 2004-02-12 2005-08-17 三星Sdi株式会社 具有轻掺杂漏极结构的薄膜晶体管
CN1779929A (zh) * 2004-11-26 2006-05-31 中华映管股份有限公司 薄膜晶体管的制作方法
US20080206938A1 (en) * 2005-09-30 2008-08-28 Au Optronics Corp. Low temperature polysilicon thin film transistor display and method of fabricating the same
CN101325220A (zh) * 2007-06-13 2008-12-17 三星Sdi株式会社 薄膜晶体管及其制造方法及包括该薄膜晶体管的显示装置
EP2270849A2 (en) * 2000-03-06 2011-01-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device and Manufacturing Method Thereof
CN102208452A (zh) * 2010-03-30 2011-10-05 索尼公司 薄膜晶体管及其制造方法、以及显示装置
CN102522410A (zh) * 2011-12-22 2012-06-27 深圳莱宝高科技股份有限公司 一种薄膜晶体管阵列基板及其制作方法
CN103021820A (zh) * 2011-09-20 2013-04-03 乐金显示有限公司 制造薄膜晶体管的方法和制造有机发光显示设备的方法
CN103137497A (zh) * 2013-02-26 2013-06-05 深圳市华星光电技术有限公司 低温多晶硅晶体管的制作方法
CN103151388A (zh) * 2013-03-05 2013-06-12 京东方科技集团股份有限公司 一种多晶硅薄膜晶体管及其制备方法、阵列基板
CN103456765A (zh) * 2013-09-10 2013-12-18 深圳市华星光电技术有限公司 有源式有机电致发光器件背板及其制作方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3197667B2 (ja) * 1993-03-24 2001-08-13 三洋電機株式会社 アキュムレーション型多結晶シリコン薄膜トランジスタ
TWI224806B (en) * 2000-05-12 2004-12-01 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
JP2002359252A (ja) * 2000-09-29 2002-12-13 Toshiba Corp 平面表示装置及びその製造方法
JP2002185008A (ja) * 2000-12-19 2002-06-28 Hitachi Ltd 薄膜トランジスタ
JP5089077B2 (ja) * 2005-04-28 2012-12-05 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7507998B2 (en) * 2006-09-29 2009-03-24 Tpo Displays Corp. System for displaying images and method for fabricating the same
CN101593730A (zh) * 2008-05-29 2009-12-02 统宝光电股份有限公司 影像显示系统及其制造方法
CN101877310A (zh) * 2009-12-03 2010-11-03 四川虹视显示技术有限公司 Oled用tft基板的金属诱导结晶化方法
CN103050410B (zh) * 2012-10-30 2015-09-16 昆山工研院新型平板显示技术中心有限公司 低温多晶硅薄膜晶体管的制造方法、低温多晶硅薄膜晶体管
CN103123910B (zh) * 2012-10-31 2016-03-23 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
CN103137557B (zh) * 2013-02-05 2015-02-18 深圳市华星光电技术有限公司 阵列基板、显示装置及阵列基板的制造方法
CN104240633B (zh) * 2013-06-07 2018-01-09 上海和辉光电有限公司 薄膜晶体管和有源矩阵有机发光二极管组件及其制造方法

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1213849A (zh) * 1997-10-02 1999-04-14 松下电器产业株式会社 晶体管的制造方法
EP2270849A2 (en) * 2000-03-06 2011-01-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device and Manufacturing Method Thereof
CN1637548A (zh) * 2003-12-29 2005-07-13 Lg.菲利浦Lcd株式会社 透射反射型液晶显示器件及其制造方法
CN1655366A (zh) * 2004-02-12 2005-08-17 三星Sdi株式会社 具有轻掺杂漏极结构的薄膜晶体管
CN1779929A (zh) * 2004-11-26 2006-05-31 中华映管股份有限公司 薄膜晶体管的制作方法
US20080206938A1 (en) * 2005-09-30 2008-08-28 Au Optronics Corp. Low temperature polysilicon thin film transistor display and method of fabricating the same
CN101325220A (zh) * 2007-06-13 2008-12-17 三星Sdi株式会社 薄膜晶体管及其制造方法及包括该薄膜晶体管的显示装置
CN102208452A (zh) * 2010-03-30 2011-10-05 索尼公司 薄膜晶体管及其制造方法、以及显示装置
CN103021820A (zh) * 2011-09-20 2013-04-03 乐金显示有限公司 制造薄膜晶体管的方法和制造有机发光显示设备的方法
CN102522410A (zh) * 2011-12-22 2012-06-27 深圳莱宝高科技股份有限公司 一种薄膜晶体管阵列基板及其制作方法
CN103137497A (zh) * 2013-02-26 2013-06-05 深圳市华星光电技术有限公司 低温多晶硅晶体管的制作方法
CN103151388A (zh) * 2013-03-05 2013-06-12 京东方科技集团股份有限公司 一种多晶硅薄膜晶体管及其制备方法、阵列基板
CN103456765A (zh) * 2013-09-10 2013-12-18 深圳市华星光电技术有限公司 有源式有机电致发光器件背板及其制作方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104538429A (zh) * 2014-12-26 2015-04-22 深圳市华星光电技术有限公司 Amoled背板的制作方法及其结构
WO2016101392A1 (zh) * 2014-12-26 2016-06-30 深圳市华星光电技术有限公司 Amoled背板的制作方法及其结构
CN104538429B (zh) * 2014-12-26 2019-07-02 深圳市华星光电技术有限公司 Amoled背板的制作方法及其结构
US10038043B2 (en) 2015-05-07 2018-07-31 Shenzhen China Star Optoelectronics Technology Co., Ltd. Method for manufacturing AMOLED backplane and structure thereof
CN106601778A (zh) * 2016-12-29 2017-04-26 深圳市华星光电技术有限公司 Oled背板及其制作方法
US10361256B2 (en) 2016-12-29 2019-07-23 Shenzhen China Star Optoelectronics Technology Co., Ltd. OLED back plate
CN106601778B (zh) * 2016-12-29 2019-12-24 深圳市华星光电技术有限公司 Oled背板及其制作方法
CN109300914A (zh) * 2018-09-27 2019-02-01 武汉华星光电半导体显示技术有限公司 阵列基板及其制作方法

Also Published As

Publication number Publication date
GB201700512D0 (en) 2017-03-01
JP2017524258A (ja) 2017-08-24
CN104143533B (zh) 2017-06-27
GB2542532A (en) 2017-03-22
KR101850662B1 (ko) 2018-04-19
KR20170034903A (ko) 2017-03-29
GB2542532B (en) 2019-12-11
US20160043351A1 (en) 2016-02-11
WO2016019602A1 (zh) 2016-02-11
JP6405036B2 (ja) 2018-10-17
US9356239B2 (en) 2016-05-31

Similar Documents

Publication Publication Date Title
CN104143533A (zh) 高解析度amoled背板制造方法
CN106981520B (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
US9368637B2 (en) Thin film transistor and manufacturing method thereof, array substrate and display device
US9627461B2 (en) Array substrate, its manufacturing method and display device
JP6460582B2 (ja) Amoledバックパネルの製造方法
CN104064688B (zh) 具有存储电容的tft基板的制作方法及该tft基板
US20160005799A1 (en) Thin film transistor, tft array substrate, manufacturing method thereof and display device
CN103383945B (zh) 一种阵列基板、显示装置及阵列基板的制造方法
CN103077957B (zh) 主动矩阵式有机发光二极管显示装置及其制作方法
CN105702623B (zh) Tft阵列基板的制作方法
US9006059B2 (en) CMOS transistor and method for fabricating the same
CN105390451A (zh) 低温多晶硅tft基板的制作方法
US10120256B2 (en) Preparation method for thin film transistor, preparation method for array substrate, array substrate, and display apparatus
TW201519416A (zh) 薄膜電晶體驅動背板及其製造方法
CN106024633A (zh) 薄膜晶体管及阵列基板的制备方法、阵列基板及显示装置
CN103123910A (zh) 阵列基板及其制造方法、显示装置
CN107799466B (zh) Tft基板及其制作方法
WO2013139128A1 (zh) 顶栅型n-tft、阵列基板及其制备方法和显示装置
CN107316874B (zh) 阵列基板及其制作方法、显示装置
US9142653B2 (en) Method for manufacturing thin-film transistor array substrate
CN108447822A (zh) Ltps tft基板的制作方法
CN105390443A (zh) Tft基板的制作方法
US10403761B2 (en) Array substrate and manufacturing method thereof, and display device
US20210408063A1 (en) Array substrate and method of manufacturing same
US10134765B2 (en) Oxide semiconductor TFT array substrate and method for manufacturing the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant