WO2016012479A1 - Träger für ein elektrisches bauelement - Google Patents
Träger für ein elektrisches bauelement Download PDFInfo
- Publication number
- WO2016012479A1 WO2016012479A1 PCT/EP2015/066715 EP2015066715W WO2016012479A1 WO 2016012479 A1 WO2016012479 A1 WO 2016012479A1 EP 2015066715 W EP2015066715 W EP 2015066715W WO 2016012479 A1 WO2016012479 A1 WO 2016012479A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- contact surface
- solder
- lotstoppstruktur
- component
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0235—Method for mounting laser chips
- H01S5/02355—Fixing laser chips on mounts
- H01S5/0237—Fixing laser chips on mounts by soldering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
- H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/69—Insulating materials thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0235—Method for mounting laser chips
- H01S5/02375—Positioning of the laser chips
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/036—Manufacture or treatment of packages
- H10H20/0364—Manufacture or treatment of packages of interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
- H10W72/07331—Connecting techniques
- H10W72/07336—Soldering or alloying
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
Definitions
- the invention relates to a support for an electrical component according to patent claim 1 and to a method for producing a support according to patent claim 9.
- Carrier for electrical components in particular for
- a carrier may have one or more contact surfaces through which an electrical component with the
- Carrier is electrically and mechanically connected.
- the object of the invention is to provide a carrier and a method for producing a carrier, wherein the carrier enables an improved solder connection between the component and the contact surface of the carrier.
- the object of the invention is achieved by the carrier according to
- Component and the carrier is made possible. This is achieved by using a contact surface
- solder stop structure extends only over a part of the entire length of the contact surface, so that a free connection region of the contact surface remains.
- the first surface area are connected to each other via the connection area.
- the first surface area has the solder pad.
- Solder material can be essentially limited to the first surface area. This makes it difficult to flow the solder material into non-advantageous regions of the contact surface. In addition, a better distribution of solder can be achieved.
- the solder stop structure is applied in the form of a layer on the contact surface. This allows the contact surface to be formed in a simple geometry by a simple process.
- the Lotstopp Cook itself is applied by means of another process in the form of a separate layer. Thus, the material for the Lotstopp réelle can be freely selected in many areas.
- the solder stop structure is formed by an uncovered part of the surface of the substrate. This embodiment has the advantage that there is no further process for depositing the solder stop structure
- Formation of the contact surface can be used, with the contact surface in the desired geometry below
- the solder stop structure is formed by a silicon layer or a silicon nitride layer or a silicon oxide layer. If necessary, these materials can be deposited easily and inexpensively, or the surface of the substrate can be provided with these materials. This provides a simple and inexpensive carrier.
- first and second surface areas are over a connection area connected with each other. This creates an electrical and mechanical connection between the surface areas
- connection area may be provided for receiving excess solder material of the solder pad.
- the solder stop structure is arranged parallel to a side surface of the component. This can ensure that solder material does not flow laterally beyond the area of the component during the melting process. Thus, the second area is free of
- connection region is associated with a mounted component on a side surface of the device, wherein solder material in the
- soldering process can be checked by means of a visual inspection, for example with the aid of a camera.
- Lotstopp Design prevents too much soldering material from the first surface area in the second
- an electrical component an optoelectronic component, in particular a semiconductor laser or a light emitting diode can be used.
- a power semiconductor can be used as the electrical component.
- 1 is a schematic plan view of a carrier
- FIG. 2 shows a cross section through the carrier of FIG. 1, "
- FIG. 3 shows a cross section through a further embodiment of a carrier
- Fig. 5 shows another embodiment of a carrier
- Fig. 1 shows a schematic plan view of a carrier with a substrate 1, wherein on the substrate 1 a
- the contact surface 2 is applied.
- the contact surface 2 consists of an electrically conductive material, for example a metal.
- a solder pad 3 is arranged on the contact surface 2.
- the solder pad 3 consists of a solid solder material that has been printed on the contact surface 2, for example.
- a Lotstopp Design 4 is provided which the
- connection surface 2 in a first surface area 5 and a second surface area 6 divided.
- the first and the second surface area 5, 6 are connected to one another via a connection area 7.
- the solder stop structure 4 does not extend over the entire length of the contact surface 2.
- a free connection region 7 remains, over which the first and the second
- FIG. 2 shows a cross-section A-A through the carrier of FIG. 1. It can be seen that in this embodiment the solder stop structure 4 is formed by a surface 8 of the substrate 1.
- the surface 8 can, for example
- the contact surface 2 when depositing the metallic contact surface 2, the contact surface 2 was patterned in the manner e.g. with photolithography, Metallevampfung, lift-off, etc., that a strip of the surface 8 in the form of
- Lot stop structure 4 was not covered with the contact surface 2. Thus, in this embodiment, no additional process introduced. The necessary
- the surface 8 may be formed, for example, by the material of the substrate, e.g. consists of silicon, are shown.
- the substrate 1 with a separate
- Surface layer are provided, which has the desired non-wetting properties of liquid solder material.
- silicon nitride, silicon oxide or silicon can be used for this purpose.
- Fig. 3 shows another embodiment in which the
- the layer 9 is trained.
- the layer 9 is applied to the contact surface 2.
- the layer 9 can be made of any material that is heavy or non-wettable by liquid solder.
- Silicon nitride or silicon oxide exist.
- solder stop structure 4 shows a further embodiment of a carrier, in which the solder stop structure 4 consists of two sections, which are guided transversely over the contact surface 2.
- the two solder stop structure 4 consists of two sections, which are guided transversely over the contact surface 2.
- Sections 4 are arranged in an axis and at a fixed distance 10 from each other.
- Fig. 5 shows a schematic representation of a
- solder stop structures 4 of FIGS. 4 and 5 may vary depending on the selected one
- FIG. 6 shows, in a schematic plan view, a carrier on which an electrical component 11, for example a semiconductor chip, an optoelectronic component, a
- Substrates 1 is electrically and mechanically connected.
- solder stop structure 4 Due to the solder stop structure 4, a lateral flow of the solder material into the second surface region 6 is avoided. Only in the connecting region 7 is a lateral flow of solder material 12 given. In the illustrated
- the Lotstopp Design 4 along a side surface 13 of the device 11 is aligned.
- solder material 12 laterally over the device 11 outstanding solder material 12 can be used to use an optical
- Lotstopp Scheme 4 also be performed along the entire side length of the device 11. This offers the advantage that no solder material flows laterally from the first surface region 5 into the second surface region 6. However, this embodiment has the disadvantage that an optical check of the soldering process is not possible.
- further electrical circuits 14 may be integrated into the substrate 1.
- the further electrical circuits 14 can be integrated into the substrate 1.
- a component 11 can also be applied to the
- Embodiments of Figures 2 to 5 may be mounted.
- the described carrier enables an improved
- the solder stop structure 4 and the solder pad 3 may be on an upper side and / or on an underside of a carrier
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017501252A JP6490788B2 (ja) | 2014-07-24 | 2015-07-22 | キャリアおよびキャリアを製造する方法 |
| DE112015003405.6T DE112015003405B4 (de) | 2014-07-24 | 2015-07-22 | Träger für ein elektrisches Bauelement und Verfahren zur Herstellung eines Trägers |
| US15/327,297 US10008440B2 (en) | 2014-07-24 | 2015-07-22 | Carrier for an electrical component |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102014110473.0 | 2014-07-24 | ||
| DE102014110473.0A DE102014110473A1 (de) | 2014-07-24 | 2014-07-24 | Träger für ein elektrisches Bauelement |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2016012479A1 true WO2016012479A1 (de) | 2016-01-28 |
Family
ID=53718011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/EP2015/066715 Ceased WO2016012479A1 (de) | 2014-07-24 | 2015-07-22 | Träger für ein elektrisches bauelement |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US10008440B2 (de) |
| JP (1) | JP6490788B2 (de) |
| DE (2) | DE102014110473A1 (de) |
| WO (1) | WO2016012479A1 (de) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7347047B2 (ja) * | 2019-09-12 | 2023-09-20 | 富士電機株式会社 | 半導体装置 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6362435B1 (en) * | 1999-12-20 | 2002-03-26 | Delphi Technologies, Inc. | Multi-layer conductor pad for reducing solder voiding |
| US7655957B2 (en) | 2006-04-27 | 2010-02-02 | Cree, Inc. | Submounts for semiconductor light emitting device packages and semiconductor light emitting device packages including the same |
| US20140001637A1 (en) * | 2012-06-29 | 2014-01-02 | Kyocera Slc Technologies Corporation | Wiring board |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2044494B2 (de) * | 1970-09-08 | 1972-01-13 | Siemens AG, 1000 Berlin u 8000 München | Anschlussflaechen zum anloeten von halbleiterbausteinen in flip chip technik |
| JPS5459080A (en) * | 1977-10-19 | 1979-05-12 | Nec Corp | Semiconductor device |
| US4835345A (en) * | 1987-09-18 | 1989-05-30 | Compaq Computer Corporation | Printed wiring board having robber pads for excess solder |
| KR940023325A (ko) * | 1993-03-11 | 1994-10-22 | 토모마쯔 켕고 | 땜납층을 프리코팅해서 사용되는 회로기판 및 땜납층이 프리코팅된 회로기판 |
| JP3871820B2 (ja) * | 1998-10-23 | 2007-01-24 | ローム株式会社 | 半導体発光素子 |
| JP2000286289A (ja) * | 1999-03-31 | 2000-10-13 | Fujitsu Ten Ltd | 金属貼付基板および半導体装置 |
| JP2002314143A (ja) * | 2001-04-09 | 2002-10-25 | Toshiba Corp | 発光装置 |
| KR101065076B1 (ko) * | 2005-05-07 | 2011-09-15 | 삼성전자주식회사 | 발광소자 패키지용 서브마운트 |
| JP4306772B2 (ja) * | 2006-10-05 | 2009-08-05 | 日亜化学工業株式会社 | 発光装置 |
| EP2302676A1 (de) * | 2009-09-29 | 2011-03-30 | ABB Technology AG | Hochleistungshalbleiterbauelement |
| CN102859671A (zh) * | 2010-12-03 | 2013-01-02 | 富士电机株式会社 | 半导体器件以及半导体器件的制造方法 |
| EP2741341B1 (de) * | 2011-08-01 | 2022-11-23 | Shikoku Instrumentation Co., Ltd. | Halbleiterbauelement und verfahren zu seiner herstellung |
| CN103137825B (zh) * | 2011-11-30 | 2016-06-01 | 光宝电子(广州)有限公司 | 发光二极管基板结构、发光二极管单元及其光源模块 |
| DE102012109161B4 (de) | 2012-09-27 | 2021-10-28 | Pictiva Displays International Limited | Organisches, optoelektronisches Bauelement, Verfahren zum Herstellen eines organischen, optoelektronischen Bauelementes und Verfahren zum stoffschlüssigen, elektrischen Kontaktieren |
-
2014
- 2014-07-24 DE DE102014110473.0A patent/DE102014110473A1/de not_active Withdrawn
-
2015
- 2015-07-22 WO PCT/EP2015/066715 patent/WO2016012479A1/de not_active Ceased
- 2015-07-22 DE DE112015003405.6T patent/DE112015003405B4/de active Active
- 2015-07-22 US US15/327,297 patent/US10008440B2/en active Active
- 2015-07-22 JP JP2017501252A patent/JP6490788B2/ja active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6362435B1 (en) * | 1999-12-20 | 2002-03-26 | Delphi Technologies, Inc. | Multi-layer conductor pad for reducing solder voiding |
| US7655957B2 (en) | 2006-04-27 | 2010-02-02 | Cree, Inc. | Submounts for semiconductor light emitting device packages and semiconductor light emitting device packages including the same |
| US20140001637A1 (en) * | 2012-06-29 | 2014-01-02 | Kyocera Slc Technologies Corporation | Wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP6490788B2 (ja) | 2019-03-27 |
| JP2017522731A (ja) | 2017-08-10 |
| US20170179016A1 (en) | 2017-06-22 |
| DE112015003405A5 (de) | 2017-04-20 |
| DE112015003405B4 (de) | 2024-03-28 |
| US10008440B2 (en) | 2018-06-26 |
| DE102014110473A1 (de) | 2016-01-28 |
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