WO2016011685A1 - 共平面型氧化物半导体tft基板的制作方法 - Google Patents

共平面型氧化物半导体tft基板的制作方法 Download PDF

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WO2016011685A1
WO2016011685A1 PCT/CN2014/084445 CN2014084445W WO2016011685A1 WO 2016011685 A1 WO2016011685 A1 WO 2016011685A1 CN 2014084445 W CN2014084445 W CN 2014084445W WO 2016011685 A1 WO2016011685 A1 WO 2016011685A1
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Prior art keywords
layer
photoresist layer
gate insulating
oxide semiconductor
insulating layer
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French (fr)
Inventor
吕晓文
曾志远
苏智昱
胡宇彤
李文辉
石龙强
张合静
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to JP2017502846A priority Critical patent/JP2017523611A/ja
Priority to GB1700581.0A priority patent/GB2542094B/en
Priority to US14/382,303 priority patent/US20160027904A1/en
Priority to KR1020177003562A priority patent/KR20170028429A/ko
Publication of WO2016011685A1 publication Critical patent/WO2016011685A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/875—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being semiconductor metal oxide, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3434—Deposited materials, e.g. layers characterised by the chemical composition being oxide semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a coplanar oxide semiconductor TFT substrate. Background technique
  • the flat display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the existing flat display devices mainly include a liquid crystal display (LCD) and an organic electroluminescence display device (OLED/organic electroluminescence display device), since they have self-luminescence, no backlight, High contrast, thin thickness, wide angle, fast response, flexible panel, wide temperature range, simple construction and simple process are considered to be the emerging application technologies for next-generation flat panel displays.
  • oxide semiconductors In the production of large-size OLED panels, oxide semiconductors have higher electron mobility, and compared with low-temperature polysilicon (LTPS), oxide semiconductors have simple process, high compatibility with amorphous silicon processes, and high generations. The production line is compatible and has been widely used.
  • LTPS low-temperature polysilicon
  • a common structure of an oxide semiconductor thin film transistor (TFT) substrate is a structure having an etch barrier layer (ESL), but the structure itself has some problems, such as etching uniformity is difficult to control, It is necessary to add a mask and a photolithography process, the gate overlaps the source/drain, the storage capacitance is large, and it is difficult to achieve high resolution.
  • ESL etch barrier layer
  • FIGS. 1 to 5 A method for fabricating a conventional coplanar oxide semiconductor TFT substrate is as shown in FIGS. 1 to 5, and includes the following steps:
  • Step 1 depositing a first metal layer on the substrate 100, and patterning the first metal layer by a photolithography process to form a gate electrode 200;
  • Step 2 depositing a gate insulating layer 300 on the substrate 100 and the gate 200, and patterning the same by a photolithography process;
  • Step 3 depositing a second metal layer on the gate insulating layer 300, and patterning the second metal layer by a photolithography process to form a source/drain 400;
  • Step 4 depositing on the source/drain 400 and patterning by photolithography to form an oxide semiconductor layer 500;
  • Step 5 Depositing on the oxide semiconductor layer 500 and the source/drain 400 and patterning by photolithography to form a protective layer 600.
  • the method for fabricating the coplanar oxide semiconductor TFT substrate has certain drawbacks, and is mainly embodied in the gate electrode 200, the gate insulating layer 300, the source/drain 400, and the oxide semiconductor layer 500.
  • Each layer structure such as the protective layer 6 00 needs to pass through a photolithography process, and each photolithography process includes a process such as film formation, yellow light, etching, and stripping, wherein the yellow light process includes a photoresist, Exposure, development, and each ray process requires a mask, resulting in longer process flow, lower production efficiency; more reticle required, higher production costs; and more processes, cumulative yield problems It is also more prominent. Summary of the invention
  • An object of the present invention is to provide a method for fabricating a coplanar oxide semiconductor TFT substrate, which can reduce the yellow light process, shorten the process flow and product production cycle, improve production efficiency and product yield, and enhance product competitiveness. And reduce the number of masks required and reduce production costs.
  • the present invention provides a method of fabricating a coplanar oxide semiconductor TFT substrate, comprising the steps of:
  • Step 1 providing a substrate
  • Step 2 depositing and patterning a first metal layer on the substrate to form a gate
  • Step 3 depositing a gate insulating layer on the gate and the substrate, so that the gate insulating layer completely covers the gate and the substrate;
  • Step 4 forming a photoresist layer with a certain thickness on the gate insulating layer; Step 5, performing sub-area exposure and development on the photoresist layer;
  • Step 6 removing the gate insulating layer under the via hole by etching to form a via hole in the gate insulating layer to expose the gate under the via hole;
  • Step 7 Removing the photoresist layer under the plurality of recessed portions of the photoresist layer to expose the gate insulating layer under the plurality of recesses;
  • Step 8 depositing a second metal layer on the gate insulating layer and the remaining photoresist layer, the second metal layer filling the communication hole and connecting with the gate;
  • Step 9 removing the remaining photoresist layer and the second metal layer deposited thereon to form a source/drain electrode
  • Step 10 Deposit and pattern an oxide semiconductor layer on the source/drain and gate insulating layers; Step 11. Deposit and pattern a protective layer on the oxide semiconductor layer and the source/drain.
  • the patterning is achieved by.
  • the photoresist layer is subjected to sub-region exposure using a halftone process.
  • the depth H of the depressed portion of the photoresist layer in the step 5 is larger than the thickness of the source/drain to be formed.
  • the gate insulating layer under the via hole is removed by dry etching.
  • an oxygen ashing process is used to remove the photoresist layer under the plurality of depressed portions of the photoresist layer.
  • step 8 physical vapor deposition is used to deposit a second metal layer on the gate insulating layer and the remaining photoresist layer.
  • the remaining photoresist layer and a portion of the second metal layer deposited thereon are removed using a lift-off liquid to form a source/drain.
  • the material of the oxide semiconductor layer in the step 10 is IGZO.
  • the photoresist layer is subjected to partial exposure and development by a halftone process, and the remaining photoresist layer is removed by a lift-off process and deposited thereon.
  • the upper second metal layer realizes forming a gate insulating layer and a source/drain with only one photomask and one yellow light process.
  • the method for fabricating the coplanar oxide semiconductor TFT substrate of the present invention reduces the yellow light process, shortens the process flow and product production cycle, and improves the production efficiency. With product yield, it enhances the competitiveness of the product, reduces the number of masks required, and reduces production costs.
  • FIG. 1 is a schematic view showing a first step of a method for fabricating a conventional coplanar oxide semiconductor TFT substrate
  • FIG. 2 is a schematic view showing the second step of the method for fabricating a conventional coplanar oxide semiconductor TFT substrate
  • FIG. 3 is a schematic view showing a step 3 of a method for fabricating a conventional coplanar oxide semiconductor TFT substrate
  • FIG. 4 is a schematic view showing a step 4 of a conventional method for fabricating a coplanar oxide semiconductor TFT substrate
  • FIG. 5 is a schematic view showing a step 5 of a method for fabricating a conventional coplanar oxide semiconductor TFT substrate
  • FIG. 6 is a flow chart of a method for fabricating a coplanar oxide semiconductor TFT substrate according to the present invention
  • FIG. 7 is a schematic view showing a step 2 of a method for fabricating a coplanar oxide semiconductor TFT substrate according to the present invention
  • 8 is a schematic diagram of step 3 of a method for fabricating a coplanar oxide semiconductor TFT substrate of the present invention
  • FIG. 9 is a schematic view showing a step 4 of a method for fabricating a coplanar oxide semiconductor TFT substrate of the present invention.
  • FIG. 10 is a schematic view showing a step 5 of a method for fabricating a coplanar oxide semiconductor TFT substrate of the present invention
  • Figure 11 is a schematic view showing the step 6 of the method for fabricating a coplanar oxide semiconductor TFT substrate of the present invention.
  • FIG. 12 is a schematic view showing a step 7 of a method for fabricating a coplanar oxide semiconductor TFT substrate of the present invention
  • Figure 13 is a schematic view showing the step 8 of the method for fabricating a coplanar oxide semiconductor TFT substrate of the present invention.
  • Figure 14 is a schematic view showing the step 9 of the method for fabricating a coplanar oxide semiconductor TFT substrate of the present invention.
  • FIG. 15 is a schematic view showing a step 10 of a method for fabricating a coplanar oxide semiconductor TFT substrate according to the present invention.
  • FIG. 6 is a flowchart of a method for fabricating a coplanar oxide semiconductor TFT substrate according to the present invention. The method includes the following steps:
  • Step 1 Provide a substrate 1.
  • the substrate 1 is a transparent substrate, and preferably, the substrate 1 is a glass substrate.
  • Step 2 depositing and patterning the first metal layer on the substrate 1 to form a gate
  • the patterning is achieved by.
  • Step 3 Referring to FIG. 8, a gate insulating layer 3 is deposited on the gate 2 and the substrate 1, so that the gate insulating layer 3 completely covers the gate 2 and the substrate 1.
  • Step 4 a photoresist layer 4 having a certain thickness is formed on the gate insulating layer 3. Specifically, the photoresist layer 4 is formed by coating a photoresist. It is to be noted that the thickness of the photoresist layer 4 is sufficiently thick to ensure that the source/drain 51 formed in the subsequent step 9 has a suitable thickness. Step 5. Referring to FIG. 10, the photoresist layer 4 is subjected to sub-area exposure and development.
  • a half-tone process is used to fully expose the region of the photoresist layer 4 corresponding to the via hole 31 in the gate insulating layer 3, and the via hole 41 is formed after development; the photoresist layer 4 is formed.
  • the area corresponding to the source/drain 51 is half-exposed, and a plurality of recesses 42 are formed after development; the remaining areas of the photoresist layer 4 are not exposed, the initial thickness of the photoresist layer 4 is retained, and the photoresist layer is The depth H of the depressed portion 42 of 4 is larger than the thickness of the source/drain 51 to be formed.
  • step 5 only a mask and a yellow light process are used to define a pattern corresponding to the gate insulating layer 3 and the source/drain 51, respectively.
  • Step 6 referring to FIG. 11, removing the gate insulating layer 3 under the via hole 41 by dry etching, forming a via hole 31 in the gate insulating layer 3 to expose the gate electrode 2 under the via hole 31, thereby Patterning of the gate insulating layer 3 is completed.
  • Step 7 referring to FIG. 12, the photoresist layer 4 under the plurality of recessed portions 42 of the photoresist layer 4 is removed by an oxygen ashing process (0 2 Ashmg) to expose the gate insulating under the plurality of recessed portions 42.
  • This step 7 removes the photoresist layer 4 under the plurality of recesses 42 of the photoresist layer 4, and the source/drain 51 formed in the subsequent step 9 is located on the exposed gate insulating layer 3. While removing the photoresist layer 4 under the plurality of recessed portions 42 of the photoresist layer 4, the remaining portion of the photoresist layer 4 is thick. The degree is also removed, and the thickness of the remaining photoresist layer 4' is correspondingly reduced.
  • Step 8 Referring to FIG. 13, a second metal layer 5 is deposited on the gate insulating layer 3 and the remaining photoresist layer 4' by a physical vapor deposition (PVD) method, and the second metal layer 5 fills the via hole 31 and The gate 2 is connected.
  • PVD physical vapor deposition
  • Step 9 Referring to FIG. 14, the remaining photoresist layer 4' and the second metal layer 5 deposited thereon are removed, and the patterning of the second metal layer 5 is completed to form the source/drain 51.
  • the remaining photoresist layer 4' and the second metal layer 5 deposited thereon are removed by lift-off using a stripper. It is worth mentioning that, because the stripping solution dissolves the photoresist but does not dissolve the metal, the stripping solution contains metal impurities, and the filter screen is used to filter out the metal in the stripping liquid, so that the stripping liquid can be recycled.
  • Step 10 Referring to FIG. 15, the oxide semiconductor layer 6 is deposited and patterned on the source/drain 51 and the gate insulating layer 3.
  • the material of the oxide semiconductor layer 6 is indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • Step 11 a protective layer 7 is deposited and patterned on the oxide semiconductor layer 6 and the source/drain electrodes 51 to complete the fabrication of the coplanar oxide semiconductor TFT substrate.
  • the patterning is achieved by.
  • the photoresist layer is subjected to partial exposure and development by a halftone process, and the remaining photoresist layer and the second metal layer deposited thereon are removed by a lift-off process.
  • the gate insulating layer and the source/drain are formed by using only one photomask and one yellow light process.
  • the method for fabricating the coplanar oxide semiconductor TFT substrate of the present invention reduces the yellow light process, shortens the process flow and product production cycle, and improves the production efficiency. With product yield, it enhances the competitiveness of the product, reduces the number of masks required, and reduces production costs.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种共平面型氧化物半导体TFT基板的制作方法，包括：步骤1、提供基板(1)；步骤2、形成栅极(2)；步骤3、沉积栅极绝缘层(3)；步骤4、在栅极绝缘层(3)上形成光阻层(4)；步骤5、对光阻层(4)进行分区域曝光、显影，形成通孔(41)、数个凹陷部(42)；步骤6、去除通孔(41)下方的栅极绝缘层(3)；步骤7、去除光阻层(4)的数个凹陷部(42)下方的光阻层(4)；步骤8、在栅极绝缘层(3)与剩余的光阻层(4')上沉积第二金属层(5)；步骤9、去除剩余的光阻层(4')及沉积于其上的第二金属层(5)，形成源/漏极(51)；步骤10、沉积并图案化氧化物半导体层(6)；步骤11、沉积并图案化保护层(7)。

Description

共平面型氧化物半导体 TFT基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种共平面型氧化物半导体 TFT 基板的制作方法。 背景技术
平面显示器件具有机身薄、 省电、 无辐射等众多优点，得到了广泛的 应用。现有的平面显示器件主要包括液晶显示器件 ( Liquid Crystal Display , LCD )及有机电致发光显示器件 ( Organic Light Emitting Display , OLED \ 有机电致发光显示器件由于同时具备自发光，不需背光源、 对比度高、 厚度薄、 枧角广、 反应速度快、 可用于挠曲性面板、 使用温度范围广、 构 造及制程较简单等优异特性，被认为是下一代平面显示器的新兴应用技术。
在 OLED大尺寸面板生产中，氧化物半导体由于具有较高的电子迁移 率，而且相比低温多晶硅（ LTPS ) ,氧化物半导体制程简单，与非晶硅制程 相容性较高，且与高世代生产线兼容而得到了广泛的应用。
目前，氧化物半导体薄膜晶体管 ( TFT )基板的常用结构为具有蚀刻阻 挡层（ ESL )的结构，但该结构本身存在一些问题，如蚀刻均一性难以控制， 需要多加一道光罩及光刻制程，栅极与源 /漏极交叠，存储电容较大，难以 达到高分辨率等。
相比于具有蚀刻阻挡层的结构，共平面型（ Coplanar )氧化物半导体 TFT基板结构更为合理，更具有量产前途。 现有的共平面型氧化物半导体 TFT基板的制作方法如图 1至图 5所示，包括如下步骤：
步骤 1、在基板 100上沉积第一金属层，并通过光刻制程使第一金属层 图案化，形成栅极 200；
步骤 2、 在基板 100及栅极 200上沉积栅极绝缘层 300 ,并通过光刻制 程使其图案化；
步骤 3、在栅极绝缘层 300上沉积第二金属层，并通过光刻制程使第二 金属层图案化，形成源 /漏极 400；
步骤 4、 在源 /漏极 400上沉积并通过光刻制程图案化，形成氧化物半 导体层 500；
步骤 5、 在氧化物半导体层 500及源 /漏极 400上沉积并通过光刻制程 图案化，形成保护层 600。
该共平面型氧化物半导体 TFT基板的制作方法存在一定的弊端，主要 表现在所述栅极 200、栅极绝缘层 300、源 /漏极 400、氧化物半导体层 500、 保护层 600等每一层结构的形成均需要通过一道光刻制程，而每一道光刻 制程包括成膜、 黄光、 蚀刻、 剥离等制程工序，其中黄光制程又包括涂光 刻胶、 曝光、 显影，且每一道黄光制程需要一光罩，造成工序流程较长， 生产效率较低；所需的光罩数量较多，生产成本较高；而工序越多，累积 的良率问题也越凸显。 发明内容
本发明的目的在于提供一种共平面型氧化物半导体 TFT基板的制作方 法，通过该方法能够减少黄光制程，缩短工序流程与产品生产周期、 提高 生产效率与产品良率，提升产品的竞争力，并减少所需的光罩数量，降低 生产成本。
为实现上述目的，本发明提供一种共平面型氧化物半导体 TFT基板的 制作方法，包括如下步骤：
步骤 1、 提供一基板；
步骤 2、 在基板上沉积并图案化第一金属层，形成栅极；
步骤 3、在栅极与基板上沉积栅极绝缘层，使该栅极绝缘层完全覆盖栅 极与基板；
步骤 4、 在栅极绝缘层上形成一定厚度的光阻层； 步骤 5、 对光阻层进行分区域曝光、 显影；
对光阻层对应欲形成于栅极绝缘层内的连通孔的区域进行全曝光，显 影后形成通孔；对光阻层对应欲形成源 /漏极的区域进行半曝光，显影后形 成数个凹陷部；对光阻层的其余区域不进行曝光；
步骤 6、通过蚀刻去除所述通孔下方的栅极绝缘层，形成栅极绝缘层内 的连通孔，以露出连通孔下方的栅极；
步骤 7、去除光阻层的数个凹陷部下方的光阻层，以露出所述数个凹陷 部下方的栅极绝缘层；
步骤 8、在栅极绝缘层与剩余的光阻层上沉积第二金属层，该第二金属 层填充连通孔并与栅极进行连接；
步骤 9、 去除剩余的光阻层及沉积于其上的第二金属层，以形成源 /漏 极；
步骤 10、 在源 /漏极与栅极绝缘层上沉积并图案化氧化物半导体层； 步骤 11、 在氧化物半导体层与源 /漏极上沉积并图案化保护层。
所述图案化通过 实现。
所述步骤 5中采用半色调工艺对光阻层进行分区域曝光。
所述步骤 5中光阻层的凹陷部的深度 H大于欲形成的源 /漏极的厚度。 所述步骤 6中采用干法蚀刻去除所述通孔下方的栅极绝缘层。
所述步骤 7 中采用氧气灰化工艺去除光阻层的数个凹陷部下方的光阻 层。
所述步骤 8中采用物理气相沉积法在栅极绝缘层与剩余的光阻层上沉 积第二金属层。
所述步骤 9中使用剥离液剥离去除剩余的光阻层及沉积于其上的部分 第二金属层，以形成源 /漏极。
所述步骤 10中的氧化物半导体层的材料为 IGZO。
本发明的有益效果：本发明的共平面型氧化物半导体 TFT基板的制作 方法，通过采用半色调工艺对光阻层进行分区域曝光、 显影，采用剥离工 艺去除剩余的光阻层及沉积于其上的第二金属层，实现了仅用一道光罩、 一道黄光制程形成栅极绝缘层与源 /漏极。 相比现有的共平面型氧化物半导 体 TFT基板的制作方法，本发明的共平面型氧化物半导体 TFT基板的制作 方法减少了黄光制程，缩短了工序流程与产品生产周期、 提高了生产效率 与产品良率，提升了产品的竞争力，并减少了所需的光罩数量，降低了生 产成本。 附图说明 为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本 发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发 明加以限制。
附图中，
图 1为现有的共平面型氧化物半导体 TFT基板的制作方法步骤 1的示 意图；
图 2为现有的共平面型氧化物半导体 TFT基板的制作方法步骤 2的示 意图；
图 3为现有的共平面型氧化物半导体 TFT基板的制作方法步骤 3的示 意图；
图 4为现有的共平面型氧化物半导体 TFT基板的制作方法步骤 4的示 意图；
图 5为现有的共平面型氧化物半导体 TFT基板的制作方法步骤 5的示 意图；
图 6为本发明共平面型氧化物半导体 TFT基板的制作方法的流程图； 图 7为本发明共平面型氧化物半导体 TFT基板的制作方法的步骤 2的 示意图； 图 8为本发明共平面型氧化物半导体 TFT基板的制作方法的步骤 3的 示意图；
图 9为本发明共平面型氧化物半导体 TFT基板的制作方法的步骤 4的 示意图；
图 10为本发明共平面型氧化物半导体 TFT基板的制作方法的步骤 5 的示意图；
图 11为本发明共平面型氧化物半导体 TFT基板的制作方法的步骤 6的 示意图；
图 12为本发明共平面型氧化物半导体 TFT基板的制作方法的步骤 7 的示意图；
图 13为本发明共平面型氧化物半导体 TFT基板的制作方法的步骤 8 的示意图；
图 14为本发明共平面型氧化物半导体 TFT基板的制作方法的步骤 9 的示意图；
图 15为本发明共平面型氧化物半导体 TFT基板的制作方法的步骤 10 的示意图；
图 16为本发明共平面型氧化物半导体 TFT基板的制作方法的步骤 11 的示意图 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 6 ,为本发明共平面型氧化物半导体 TFT基板的制作方法的 流程图，该方法包括如下步骤：
步骤 1、 提供一基板 1。
具体的，所述基板 1为透明基板，优选的，所述基板 1为玻璃基板。 步骤 2、 请参阅图 7 ,在基板 1上沉积并图案化第一金属层，形成栅极
2。
具体的，所述图案化通过 实现。
步骤 3、 请参阅图 8 ,在栅极 2与基板 1上沉积栅极绝缘层 3 ,使该栅 极绝缘层 3完全覆盖栅极 2与基板 1。
步骤 4、 请参阅图 9 ,在栅极绝缘层 3上形成一定厚度的光阻层 4。 具体的，所述光阻层 4通过涂覆光刻胶形成。 需要特别说明的是，为 保证在后续步骤 9中形成的源 \漏极 51具有合适的厚度，所述光阻层 4的厚 度要足够厚。 步骤 5、 请参阅图 10 ,对光阻层 4进行分区域曝光、 显影。
具体的，采用半色调 ( Half -tone )工艺对光阻层 4对应谷妍成于栅极 绝缘层 3内的连通孔 31的区域进行全曝光，显影后形成通孔 41；对光阻层 4对应欲形成源 /漏极 51的区域进行半曝光，显影后形成数个凹陷部 42；对 光阻层 4的其余区域不进行曝光，保留光阻层 4的初始厚度，且所述光阻 层 4的凹陷部 42的深度 H大于欲形成的源 /漏极 51的厚度。
该步骤 5仅使用一道光罩、 一道黄光制程即定义出了栅极绝缘层 3与 源 /漏极 51分别所需对应的图案。
步骤 6、 请参阅图 11 ,通过干法蚀刻去除所述通孔 41下方的栅极绝缘 层 3 ,形成栅极绝缘层 3内的连通孔 31 ,以露出连通孔 31下方的栅极 2 , 从而完成栅极绝缘层 3的图案化。
步骤 7、 请参阅图 12 ,采用氧气灰化工艺（ 02 Ashmg )去除光阻层 4 的数个凹陷部 42下方的光阻层 4 ,以露出所述数个凹陷部 42下方的栅极绝 缘层 3。
该步骤 7去除了光阻层 4的数个凹陷部 42下方的光阻层 4 ,后续步骤 9中形成的源 /漏极 51即位于所露出的栅极绝缘层 3上。在去除光阻层 4的 数个凹陷部 42下方的光阻层 4的同时，所述光阻层 4的其余区域的部分厚 度也被去除，剩余的光阻层 4'的厚度相应减小。
步骤 8、 请参阅图 13 ,采用物理气相沉积 ( PVD )法在栅极绝缘层 3 与剩余的光阻层 4'上沉积第二金属层 5 ,该第二金属层 5填充连通孔 31并 与栅极 2进行连接。
步骤 9、 请参阅图 14 ,去除剩余的光阻层 4'及沉积于其上的第二金属 层 5 ,完成第二金属层 5的图案化，以形成源 /漏极 51。
具体的，在该步骤 9中，使用剥离液剥离去除剩余的光阻层 4'及沉积 于其上的第二金属层 5。值得一提的是，由于剥离液溶解光阻但并不溶解金 属，造成剥离液中含有金属杂质，使用滤网过滤掉剥离液中的金属，使得 剥离液能够循环使用。
步骤 10、 请参阅图 15 ,在源 /漏极 51与栅极绝缘层 3上沉积并图案化 氧化物半导体层 6。
具体的，所述氧化物半导体层 6的材料为铟镓锌氧化物 ( IGZO )。 所述图案化通过 实现。
步骤 11、 请参阅图 16 ,在氧化物半导体层 6与源 /漏极 51上沉积并图 案化保护层 7 ,完成共平面型氧化物半导体 TFT基板的制作。
具体的，所述图案化通过 实现。 本发明的共平面型氧化物半导体 TFT基板的制作方法，通过采用半色 调工艺对光阻层进行分区域曝光、 显影，采用剥离工艺去除剩余的光阻层 及沉积于其上的第二金属层，实现了仅用一道光罩、 一道黄光制程形成栅 极绝缘层与源 /漏极。相比现有的共平面型氧化物半导体 TFT基板的制作方 法 ,本发明的共平面型氧化物半导体 TFT基板的制作方法减少了黄光制程 , 缩短了工序流程与产品生产周期、 提高了生产效率与产品良率，提升了产 品的竞争力，并减少了所需的光罩数量，降低了生产成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形 都应属于本发明后附的权利要求的保护范围。

Claims

杈 利 要 求
1、 一种共平面型氧化物半导体 TFT基板的制作方法，包括如下步骤： 步骤 1、 提供一基板；
步骤 2、 在基板上沉积并图案化第一金属层，形成栅极；
步骤 3、在栅极与基板上沉积栅极绝缘层，使该栅极绝缘层完全覆盖栅 极与基板；
步骤 4、 在栅极绝缘层上形成一定厚度的光阻层；
步骤 5、 对光阻层进行分区域曝光、 显影；
对光阻层对应欲形成于栅极绝缘层内的连通孔的区域进行全曝光，显 影后形成通孔；对光阻层对应欲形成源 /漏极的区域进行半曝光，显影后形 成数个凹陷部；对光阻层的其余区域不进行曝光；
步骤 6、通过蚀刻去除所述通孔下方的栅极绝缘层，形成栅极绝缘层内 的连通孔，以露出连通孔下方的栅极；
步骤 7、去除光阻层的数个凹陷部下方的光阻层，以露出所述数个凹陷 部下方的栅极绝缘层；
步骤 8、在栅极绝缘层与剩余的光阻层上沉积第二金属层，该第二金属 层填充连通孔并与栅极进行连接； 步骤 9、 去除剩余的光阻层及沉积于其上的第二金属层，以形成源\漏 极；
步骤 10、 在源 /漏极与栅极绝缘层上沉积并图案化氧化物半导体层； 步骤 11、 在氧化物半导体层与源\漏极上沉积并图案化保护层。
2、 如权利要求 1所述的共平面型氧化物半导体 TFT基板的制作方法， 其中，所述图案化通过 实现。
3、 如权利要求 1所述的共平面型氧化物半导体 TFT基板的制作方法， 其中，所述步骤 5中采用半色调工艺对光阻层进行分区域曝光。
4、 如权利要求 1所述的共平面型氧化物半导体 TFT基板的制作方法， 其中 ,所述步骤 5中光阻层的凹陷部的深度 H大于欲形成的源\漏极的厚度。
5、 如权利要求 1所述的共平面型氧化物半导体 TFT基板的制作方法， 其中，所述步骤 6中采用干法蚀刻去除所述通孔下方的栅极绝缘层。
6、 如权利要求 1所述的共平面型氧化物半导体 TFT基板的制作方法， 其中，所述步骤 7中采用氧气灰化工艺去除光阻层的数个凹陷部下方的光 阻层。
7、 如权利要求 1所述的共平面型氧化物半导体 TFT基板的制作方法， 其中，所述步骤 8中采用物理气相沉积法在栅极绝缘层与剩余的光阻层上 沉禾 二金属层。
8、 如权利要求 1所述的共平面型氧化物半导体 TFT基板的制作方法， 其中，所述步骤 9中使用剥离液剥离去除剩余的光阻层及沉积于其上的部 分第二金属层，以形成源籠。
9、 如权利要求 1所述的共平面型氧化物半导体 TFT基板的制作方法， 其中，所述步骤 10中的氧化物半导体层的材料为 IGZO。
10、一种共平面型氧化物半导体 TFT基板的制作方法，包括如下步骤： 步骤 1、 提供一基板；
步骤 2、 在基板上沉积并图案化第一金属层，形成栅极；
步骤 3、在栅极与基板上沉积栅极绝缘层，使该栅极绝缘层完全覆盖栅 极与基板；
步骤 4、 在栅极绝缘层上形成一定厚度的光阻层；
步骤 5、 对光阻层进行分区域曝光、 显影；
对光阻层对应欲形成于栅极绝缘层内的连通孔的区域进行全曝光，显 影后形成通孔；对光阻层对应欲形成源 /漏极的区域进行半曝光，显影后形 成数个凹陷部；对光阻层的其余区域不进行曝光；
步骤 6、通过蚀刻去除所述通孔下方的栅极绝缘层，形成栅极绝缘层内 的连通孔，以露出连通孔下方的栅极；
步骤 7、去除光阻层的数个凹陷部下方的光阻层，以露出所述数个凹陷 部下方的栅极绝缘层；
步骤 8、在栅极绝缘层与剩余的光阻层上沉积第二金属层，该第二金属 层填充连通孔并与栅极进行连接；
步骤 9、 去除剩余的光阻层及沉积于其上的第二金属层，以形成源\漏 极；
步骤 10、 在源 /漏极与栅极绝缘层上沉积并图案化氧化物半导体层； 步骤 11、 在氧化物半导体层与源\漏极上沉积并图案化保护层； 其中，所述图案化通过 实现；
其中，所述步骤 5中采用半色调工艺对光阻层进行分区域曝光； 其中，所述步骤 5中光阻层的凹陷部的深度 Η大于欲形成的源\漏极的 厚度；
其中，所述步骤 ό中采用干法蚀刻去除所述通孔下方的栅极绝缘层； 其中，所述步骤 7 中采用氧气灰化工艺去除光阻层的数个凹陷部下方 的光阻层；
其中，所述步骤 8中采用物理气相沉积法在栅极绝缘层与剩余的光阻 层上沉积 二金属层；
其中，所述步骤 9中使用剥离液剥离去除剩余的光阻层及沉积于其上 的部分第二金属层，以形成源\漏极；
其中，所述步骤 10中的氧化物半导体层的材料为 IGZO。
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