WO2015192394A1 - 一种显示面板及其制作方法 - Google Patents

一种显示面板及其制作方法 Download PDF

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Publication number
WO2015192394A1
WO2015192394A1 PCT/CN2014/081097 CN2014081097W WO2015192394A1 WO 2015192394 A1 WO2015192394 A1 WO 2015192394A1 CN 2014081097 W CN2014081097 W CN 2014081097W WO 2015192394 A1 WO2015192394 A1 WO 2015192394A1
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WO
WIPO (PCT)
Prior art keywords
metal layer
silicon nitride
substrate
soldering
display panel
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PCT/CN2014/081097
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English (en)
French (fr)
Inventor
黄世帅
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/391,058 priority Critical patent/US9312251B2/en
Publication of WO2015192394A1 publication Critical patent/WO2015192394A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods

Definitions

  • the invention belongs to the technical field of displays, and in particular relates to a display panel and a manufacturing method thereof.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display
  • COF substrate chip on film
  • soldering lead 2 is provided on the COF substrate 1, and a protective layer 3 is applied on the soldering lead 2. Copper is often used as a material for soldering leads because of its good electrical and thermal conductivity and good flexibility. Solder leads with uncoated protective layer 3 are left on the COF substrate for soldering to the terminal traces of the liquid crystal panel.
  • a layer of tuffy resin glue is applied on the thin film transistor side of the liquid crystal panel to prevent the liquid crystal panel terminal trace from being corroded by H2O, chloride ions and the like.
  • tuffy resin coating is not applied on the back side of the COF, as shown in Figure 2. Therefore, some of the solder leads on the COF are exposed to the air, although the copper is more resistant to corrosion and will not It is corroded by water vapor, but an electrochemical reaction occurs in the presence of ions and is corroded.
  • the electrochemical reaction is as follows:
  • the object of the present invention is to provide a display panel and a manufacturing method thereof, which are intended to solve the problem that a part of the soldering lead on the COF after the welding of the COF substrate existing in the prior art is exposed to the air and there is an ion in the air. Electrochemical reactions occur underneath, and the solder leads are corroded, which affects the transmission of signals.
  • the present invention is achieved by a display panel comprising an array substrate and a COF substrate, wherein the COF substrate is provided with a plurality of soldering leads;
  • the array substrate includes:
  • a first metal layer disposed on the surface of the substrate
  • soldering region is a region where the terminal trace is connected to the soldering lead
  • the plurality of terminal traces are respectively press-fitted in one-to-one correspondence with the plurality of soldering leads on the COF substrate; and the vias are disposed on the soldering region between each adjacent terminal traces.
  • the via is used to expose the metal layer.
  • soldering region between adjacent terminal traces is provided with a via hole for exposing the first metal layer.
  • soldering region between adjacent terminal traces is provided with a via hole for exposing the second metal layer.
  • the material of the first silicon nitride layer is G-silicon nitride, and the material of the second silicon nitride layer is D-silicon nitride.
  • the material used for the first metal layer and the second metal layer is aluminum.
  • the material used for the first metal layer and the second metal layer is copper.
  • Another object of the present invention is to provide a method for fabricating a display panel, the display panel comprising an array substrate and a flip chip COF substrate, wherein the COF substrate is provided with a plurality of soldering leads, and the display panel is fabricated Includes the following steps:
  • soldering region is a region where the terminal trace is connected to the soldering lead
  • the plurality of terminal traces are respectively press-fitted in one-to-one correspondence with the plurality of solder leads on the COF substrate.
  • the step of sequentially forming a metal layer and a silicon nitride layer on the substrate includes:
  • the step of arranging a plurality of terminal traces on the surface of the silicon nitride layer of the soldering region of the substrate includes:
  • a plurality of terminal traces are arranged at intervals on the surface of the second silicon nitride layer of the soldering region of the substrate.
  • Performing via etching on the soldering region between adjacent terminal traces to form via holes, and the steps of exposing the metal layer to the via holes include:
  • Performing via etching on the soldering region between adjacent terminal traces to form via holes, and the steps of exposing the metal layer to the via holes include:
  • Via etching is performed on the second silicon nitride layer between adjacent terminal traces to form via holes, the via holes exposing the second metal layer.
  • the via holes are provided on the soldering region between each adjacent terminal trace.
  • Another object of the present invention is to provide a display panel including an array substrate and a COF substrate, wherein the COF substrate is provided with a plurality of soldering leads;
  • the array substrate includes:
  • a silicon nitride layer disposed on a surface of the metal layer
  • soldering region is a region where the terminal trace is connected to the soldering lead
  • the plurality of terminal traces are respectively press-fitted in a one-to-one correspondence with the plurality of soldering leads on the COF substrate; and the through-holes are disposed on the soldering region between the adjacent terminal traces. Vias are used to expose the metal layer.
  • the metal layer includes a first metal layer and a second metal layer, the silicon nitride layer including a first silicon nitride layer and a second silicon nitride layer;
  • the first metal layer is disposed on a surface of the substrate
  • the first silicon nitride layer is disposed on the first metal layer
  • the second metal layer is disposed on the first silicon nitride layer
  • the second silicon nitride layer is disposed on the second metal layer
  • the plurality of terminal traces are arranged at intervals on the surface of the second silicon nitride layer of the soldering region.
  • a via hole is provided on the soldering region between adjacent terminal traces for exposing the first metal layer.
  • a via hole is provided on the soldering region between adjacent terminal traces for exposing the second metal layer.
  • the via holes are provided on the soldering region between each adjacent terminal trace.
  • a via hole is formed by performing via etching on a soldering region between adjacent terminal traces on an array substrate, the via hole exposing a metal layer on the array substrate such that when on the array substrate
  • the exposed soldering lead is located at the edge of the via area, even if there is air around the exposed soldering lead, but the metal layer can share the soldering lead due to the exposed metal layer in the via area.
  • the risk of corrosion which can delay the time and speed at which the soldering leads are corroded.
  • the invention effectively reduces the risk of corrosion and breakage of the soldering leads on the COF substrate, increases the use time of the product, and prolongs the life of the product.
  • FIG. 1 is a schematic structural view of a COF substrate provided by the prior art
  • FIG. 2 is a schematic view showing a structure in which a part of a soldering lead on a COF provided by the prior art is exposed to the air;
  • FIG. 3 is a schematic flowchart of an implementation process of a method for manufacturing a display panel according to an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural view of all silicon nitride layers and a second metal layer after being etched according to an embodiment of the present invention
  • FIG. 6 is a schematic structural view of a second silicon nitride layer after being etched according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of a via hole disposed between adjacent terminal traces according to an embodiment of the present invention.
  • a via hole is formed by performing via etching on a soldering region between adjacent terminal traces on the array substrate, the via hole exposing a metal layer on the array substrate, so that the array substrate
  • the exposed soldering lead is located at the edge of the via area, even if there is air around the exposed soldering lead, but the metal layer can be shared because the metal layer is exposed in the via area.
  • the risk of corrosion of the solder leads can delay the time and speed at which the solder leads are corroded.
  • the display panel includes an array substrate and a flip chip COF substrate, and the COF substrate is provided with a plurality of solder leads.
  • FIG. 3 is a schematic flowchart of a method for fabricating a display panel according to an embodiment of the present invention.
  • the method for fabricating the display panel includes the following steps:
  • step S101 a substrate is provided, and a metal layer and a silicon nitride layer are sequentially formed on the substrate;
  • step S101 includes:
  • a second silicon nitride layer is formed on the second metal layer.
  • first metal layer the second metal layer
  • first silicon nitride layer the first silicon nitride layer
  • second silicon nitride layer all require the steps of painting, exposing, developing and etching through the photoresist, because it is The technical means are commonly used in the field, and therefore will not be described here.
  • the material for forming the first silicon nitride layer is G-silicon nitride
  • the material for forming the second silicon nitride layer is D-silicon nitride.
  • the material used to form the first metal layer and the second metal layer may be other metal materials such as aluminum or copper.
  • step S102 a plurality of terminal traces are arranged at intervals on the surface of the silicon nitride layer of the soldering region of the substrate, and the soldering region is a region where the terminal trace is connected to the soldering lead;
  • the step S102 when there are two layers of silicon nitride layers, the step S102 includes:
  • a plurality of terminal traces are arranged at intervals on a surface of the second silicon nitride layer of the soldering region of the substrate, and the soldering region is a region where the terminal trace is connected to the soldering lead.
  • step S103 the soldering region between adjacent terminal traces is subjected to via etching to form via holes, the via holes exposing the metal layer;
  • step S103 includes:
  • the exposed solder leads are located in the via holes.
  • the air first reacts electrochemically with the aluminum metal layer, thereby delaying the corrosion of the solder wire of the copper material on the GOF substrate and slowing the corrosion of the solder wire of the copper material.
  • the exposed solder leads are located in the via holes. At the edge of the area, even if there is air around the exposed soldering lead, since the copper metal layer is exposed in the via area, the copper metal layer can also consume part of water vapor and ions, thus sharing the soldering of the copper material on the GOF substrate. The risk of corrosion of the leads.
  • step S103 includes:
  • Via etching is performed on the second silicon nitride layer between adjacent terminal traces to form via holes, the via holes exposing the second metal layer.
  • the exposed second metal layer is made of aluminum metal
  • the terminal traces on the array substrate are connected to the solder leads on the COF substrate
  • the exposed solder leads are located in the via holes.
  • the air first reacts electrochemically with the aluminum metal layer, thereby delaying the corrosion of the solder wire of the copper material on the GOF substrate and slowing the corrosion of the solder wire of the copper material.
  • the exposed solder leads are located in the via holes. At the edge of the area, even if there is air around the exposed soldering lead, since the copper metal layer is exposed in the via area, the copper metal layer can also consume part of water vapor and ions, thus sharing the soldering of the copper material on the GOF substrate. The risk of corrosion of the leads.
  • the vias are provided on the soldering area between each adjacent terminal trace.
  • step S104 the plurality of terminal traces are respectively press-fitted in one-to-one correspondence with the plurality of soldering leads on the COF substrate.
  • FIG. 4 is a schematic structural diagram of a display panel according to Embodiment 1 of the present invention. For the convenience of description, only parts related to the embodiment of the present invention are shown.
  • the display panel includes an array substrate and a COF substrate, and the COF substrate is provided with a plurality of soldering leads.
  • the array substrate includes a substrate 10, a metal layer 20, a silicon nitride layer 30, and a plurality of terminal traces 40.
  • the metal layer 20 is disposed on the surface of the substrate 10; the silicon nitride layer 30 is disposed on the surface of the metal layer 20; and the plurality of terminal traces 40 are arranged at intervals on the surface of the silicon nitride layer 30 of the soldering region.
  • the soldering region is a region where the terminal trace 40 is connected to the soldering lead.
  • the plurality of terminal traces 40 are respectively press-fitted in one-to-one correspondence with the plurality of soldering leads on the COF substrate; and the vias 50 are disposed on the soldering region between the adjacent terminal traces 40.
  • the via 50 is used to expose the metal layer 20.
  • FIG. 5 and FIG. 6 are schematic diagrams showing the structure of a display panel according to Embodiment 2 of the present invention. For the convenience of description, only parts related to the embodiment of the present invention are shown.
  • the display panel includes an array substrate and a COF substrate, and the COF substrate is provided with a plurality of soldering leads.
  • the array substrate includes a substrate 100, a first metal layer 200, a first silicon nitride layer 300, a second metal layer 400, a second silicon nitride layer 500, and a plurality of terminal traces 600.
  • the first metal layer 200 is disposed on the surface of the substrate 100; the first silicon nitride layer 300 is disposed on the first metal layer 200; and the second metal layer 400 is disposed on the first nitrogen layer
  • the second silicon nitride layer 500 is disposed on the second metal layer 400; the plurality of terminal traces 600 are spaced apart from the second silicon nitride disposed in the soldering region On the surface of layer 500.
  • the soldering region is a region where the terminal trace 600 is connected to the soldering lead.
  • the plurality of terminal traces 600 are respectively press-fitted in a one-to-one correspondence with the plurality of soldering leads on the COF substrate; and the vias 700 are disposed on the soldering region between the adjacent terminal traces 600.
  • the via 700 is used to expose the first metal layer 200 or the second metal layer 400.
  • the first silicon nitride layer 300 is made of G-silicon nitride
  • the second silicon nitride layer 500 is made of D-silicon nitride.
  • the material used for the first metal layer 200 and the second metal layer 400 may be other metal materials such as aluminum or copper.
  • the second silicon nitride layer 500, the second metal layer 400, and the first silicon nitride layer 300 between the adjacent terminal traces 600 are sequentially etched by via etching.
  • the hole 700, then the via 700 will expose the first metal layer 200 after etching, as shown in FIG.
  • the exposed first metal layer 200 is made of aluminum metal
  • the terminal traces 600 on the array substrate are connected to the solder leads on the COF substrate
  • the exposed solder leads are located.
  • the edge of the via 700 area even if there is air around the exposed soldering lead, since the aluminum metal layer is exposed in the via 700 area, since the aluminum easily loses electrons, the electron generating electricity is preferentially lost in the atmosphere with water vapor and ions.
  • the chemical reaction so the air first reacts electrochemically with the aluminum metal layer, thereby delaying the corrosion of the solder wire of the copper material on the GOF substrate and slowing down the corrosion of the solder wire of the copper material.
  • the exposed first metal layer 200 is made of copper metal
  • the terminal traces 600 on the array substrate are connected to the solder leads on the COF substrate
  • the exposed solder leads are located.
  • the copper metal layer can also consume part of the water vapor and ions, thus sharing the GOF substrate. The risk of corrosion of the soldered leads of the copper material.
  • the via 700 is formed by performing via etching on the second silicon nitride layer 500 between the adjacent terminal traces 600, and the via 700 is exposed after etching.
  • the second metal layer 400 is described. As shown in Figure 6.
  • the exposed second metal layer 400 when the exposed second metal layer 400 is made of aluminum metal, and when the terminal traces 600 on the array substrate are connected to the solder leads on the COF substrate, the exposed solder leads are located.
  • the edge of the via 700 area even if there is air around the exposed soldering lead, since the aluminum metal layer is exposed in the via 700 area, since the aluminum easily loses electrons, the electron generating electricity is preferentially lost in the atmosphere with water vapor and ions.
  • the chemical reaction so the air first reacts electrochemically with the aluminum metal layer, thereby delaying the corrosion of the solder wire of the copper material on the GOF substrate and slowing down the corrosion of the solder wire of the copper material.
  • the exposed second metal layer 400 when the exposed second metal layer 400 is made of copper metal, and when the terminal traces 600 on the array substrate are connected to the solder leads on the COF substrate, the exposed solder leads are located. At the edge of the via 700 area, even if there is air around the exposed soldering lead, since the copper metal layer is exposed in the via 700 area, the copper metal layer can also consume part of the water vapor and ions, thus sharing the GOF substrate. The risk of corrosion of the soldered leads of the copper material.
  • the vias 700 are provided on the soldering regions between each adjacent terminal traces 600. As shown in FIG. 7, a schematic structural view of a via 700 is provided between adjacent terminal traces 600 on the array substrate.
  • a via hole is formed by performing via etching on a soldering region between adjacent terminal traces on the array substrate, the via hole exposing a metal layer on the array substrate, such that when on the array substrate When the terminal trace is connected to the soldering lead on the COF substrate, the exposed soldering lead is located at the edge of the via area, even if there is air around the exposed soldering lead, but the metal layer can share the soldering lead due to the exposed metal layer in the via area. The risk of corrosion, which can delay the time and speed at which the soldering leads are corroded.
  • the exposed metal layer is made of aluminum metal
  • the terminal traces on the array substrate are connected to the solder leads on the COF substrate
  • the exposed solder leads are located at the edge of the via region, even if the solder is bare.
  • There is air around the lead wire but since the aluminum metal layer is exposed in the via hole area, since aluminum easily loses electrons, in the atmosphere with water vapor and ions, the electrons are preferentially lost, and the air reacts first with aluminum.
  • the layer undergoes an electrochemical reaction, thereby delaying the corrosion of the solder wire of the copper material on the GOF substrate and slowing down the corrosion of the solder wire of the copper material.
  • the exposed metal layer is made of copper metal
  • the terminal traces on the array substrate are connected to the solder leads on the COF substrate
  • the exposed solder leads are located at the edge of the via region, even if bare.
  • the copper metal layer can also consume part of the water vapor and ions, thus sharing the risk of corrosion of the solder wire of the copper material on the GOF substrate.
  • the embodiment of the invention effectively reduces the risk of corrosion and fracture of the soldering leads on the COF substrate, thereby increasing the use time of the product and prolonging the life of the product.

Abstract

一种显示面板及其制作方法，该显示面板包括：阵列基板及COF基板，COF基板上设置有多条焊接引线；阵列基板包括：金属层（20）设置于基板（10）表面上；氮化硅层（30）设置于金属层（20）表面上；多条端子走线（40）间隔排列设置于焊接区域的氮化硅层（30）表面上，在相邻端子走线（40）之间的焊接区域上设置有过孔（50），过孔（50）裸露出金属层（20）。该显示面板有效降低了COF基板上的焊接引线被腐蚀断裂的风险。

Description

一种显示面板及其制作方法 技术领域
本发明属于显示器技术领域，尤其涉及一种显示面板及其制作方法。
 背景技术
TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器）面板在正常显示时，需要使用COF基板（chip on film，覆晶薄膜）连接PCB板（Printed Circuit Board，印刷电路板）和液晶面板，从而可以使得PCB板上的信号能够导通到面板中。
如图1所示，在COF基板1上设置焊接引线2，在焊接引线2上涂布保护层3。由于铜具有良好的导电导热性能以及有良好的柔韧性，因此铜常作为制作焊接引线的材料。在COF基板上会留出未涂布保护层3的焊接引线用于焊接到液晶面板的端子走线。
在模组阶段，COF完成焊接后会在液晶面板的薄膜晶体管侧涂布一层tuffy树脂胶，用于防止液晶面板端子走线被H2O、氯离子等腐蚀。然而，由于制程限制一般不会在COF背面做tuffy树脂胶涂布的动作，如图2所示，因此COF上的焊接引线会有一部分裸露在空气中，虽然铜抗腐蚀性较强，不会被水蒸气腐蚀，但是在有离子存在的环境下会发生电化学反应，会被腐蚀掉。特别是在氯离子存在的状态下，由于氯离子有很强的穿透性和容易水解成酸的特性，因此大大加快了下述的电化学反应，形成点蚀和坑蚀，严重情况下会使得裸露的铜断裂，影响信号的传输。电化学反应如下所示：
Figure TP140379PCT-appb-I000001
 技术问题
本发明的目的在于提供一种显示面板及其制作方法，旨在解决现有技术中存在的COF基板完成焊接后COF上的焊接引线会有一部分裸露在空气中，当空气中有离子存在的环境下会发生电化学反应，焊接引线会被腐蚀掉，从而影响信号的传输的问题。
 技术解决方案
本发明是这样实现的，一种显示面板，包括一阵列基板以及一COF基板，所述COF基板上设置有多条焊接引线；其中
所述阵列基板包括：
一基板；
一第一金属层，设置于所述基板表面上；
一第一氮化硅层，设置于所述第一金属层上；
一第二金属层，设置于所述第一氮化硅层上；
一第二氮化硅层，设置于所述第二金属层上；以及
多条端子走线，间隔排列设置于焊接区域的所述第二氮化硅层表面上，所述焊接区域为所述端子走线与所述焊接引线进行连接的区域；
其中所述多条端子走线分别与COF基板上的所述多条焊接引线一一对应压合连接；在每相邻的所述端子走线之间的所述焊接区域上均设置有过孔，所述过孔用于裸露出所述金属层。
其中在相邻所述端子走线之间的所述焊接区域上设置有过孔，所述过孔用于裸露出所述第一金属层。
其中在相邻所述端子走线之间的所述焊接区域上设置有过孔，所述过孔用于裸露出所述第二金属层。
其中所述第一氮化硅层采用的材料为G-氮化硅，所述第二氮化硅层采用的材料为D-氮化硅。
其中所述第一金属层和所述第二金属层采用的材料是铝。
其中所述第一金属层和所述第二金属层采用的材料是铜。
本发明的另一目的在于提供一种显示面板的制作方法，所述显示面板包括一阵列基板以及一覆晶薄膜COF基板，所述COF基板上设置多条焊接引线，所述显示面板的制作方法包括以下步骤：
提供一基板，在所述基板上依次形成金属层和氮化硅层；
在所述基板的焊接区域的所述氮化硅层表面上间隔排列设置多条端子走线，所述焊接区域为所述端子走线与所述焊接引线进行连接的区域；
对相邻所述端子走线之间的所述焊接区域进行过孔蚀刻形成过孔，所述过孔裸露出所述金属层；以及
将所述多条端子走线分别与所述COF基板上的所述多条焊接引线一一对应压合连接。
所述在所述基板上依次形成金属层和氮化硅层的步骤包括：
在所述基板上形成第一金属层；
在所述第一金属层上形成第一氮化硅层；
在所述第一氮化硅层上形成第二金属层；
在所述第二金属层上形成第二氮化硅层；
所述在所述基板的焊接区域的所述氮化硅层表面上间隔排列设置多条端子走线的步骤包括：
在所述基板的焊接区域的所述第二氮化硅层表面上间隔排列设置多条端子走线。
对相邻所述端子走线之间的所述焊接区域进行过孔蚀刻形成过孔，所述过孔裸露出所述金属层的步骤包括：
对相邻所述端子走线之间的第二氮化硅层、第二金属层及第一氮化硅层依次进行过孔蚀刻形成过孔，所述过孔裸露出所述第一金属层。
对相邻所述端子走线之间的所述焊接区域进行过孔蚀刻形成过孔，所述过孔裸露出所述金属层的步骤包括：
对相邻所述端子走线之间的第二氮化硅层进行过孔蚀刻形成过孔，所述过孔裸露出所述第二金属层。
在每相邻的所述端子走线之间的所述焊接区域上均设置所述过孔。
本发明的另一目的在于提供一种显示面板，包括一阵列基板以及一COF基板，所述COF基板上设置有多条焊接引线；
所述阵列基板包括：
一基板；
金属层，设置于所述基板表面上；
氮化硅层，设置于所述金属层表面上；以及
多条端子走线，间隔排列设置于焊接区域的所述氮化硅层表面上，所述焊接区域为所述端子走线与所述焊接引线进行连接的区域；
其中所述多条端子走线分别与COF基板上的所述多条焊接引线一一对应压合连接；在相邻所述端子走线之间的所述焊接区域上设置有过孔，所述过孔用于裸露出所述金属层。
所述金属层包括第一金属层和第二金属层，所述氮化硅层包括第一氮化硅层和第二氮化硅层；
所述第一金属层设置于所述基板表面上；
所述第一氮化硅层设置于所述第一金属层上；
所述第二金属层设置于所述第一氮化硅层上；
所述第二氮化硅层设置于所述第二金属层上；
所述多条端子走线间隔排列设置于所述焊接区域的所述第二氮化硅层表面上。
在相邻所述端子走线之间的所述焊接区域上设置有过孔，所述过孔用于裸露出所述第一金属层。
在相邻所述端子走线之间的所述焊接区域上设置有过孔，所述过孔用于裸露出所述第二金属层。
在每相邻的所述端子走线之间的所述焊接区域上均设置所述过孔。
 有益效果
在本发明中，通过对阵列基板上的相邻端子走线之间的焊接区域进行过孔蚀刻形成过孔，所述过孔裸露出所述阵列基板上的金属层，使得当阵列基板上的端子走线与COF基板上的焊接引线连接时，裸露的焊接引线由于位于过孔区域边缘，即使裸露的焊接引线周边存在空气，但由于过孔区域裸露出金属层，该金属层能够分担焊接引线被腐蚀的风险，从而能够延缓焊接引线被腐蚀的时间和速度。本发明有效降低了COF基板上的焊接引线被腐蚀断裂的风险，增加了产品的使用时间，以及延长了产品的寿命。
 附图说明
图1是现有技术提供的COF基板的结构示意图；
图2是现有技术提供的COF上焊接引线会有一部分裸露在空气中的结构示意图；
图3是本发明实施例提供的显示面板的制作方法的实现流程示意图；
图4是本发明实施例提供的显示面板的结构示意图；
图5是本发明实施例提供的全部氮化硅层及第二金属层被蚀刻后的结构示意图；
图6是本发明实施例提供的第二氮化硅层被蚀刻后的结构示意图；
图7是本发明实施例提供的相邻端子走线之间设置有过孔的结构示意图。
 本发明的最佳实施方式
为了使本发明的目的、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本发明实施例中，通过对阵列基板上的相邻端子走线之间的焊接区域进行过孔蚀刻形成过孔，所述过孔裸露出所述阵列基板上的金属层，使得当阵列基板上的端子走线与COF基板上的焊接引线连接时，裸露的焊接引线由于位于过孔区域边缘，即使裸露的焊接引线周边存在空气，但由于过孔区域裸露出金属层，该金属层能够分担焊接引线被腐蚀的风险，从而能够延缓焊接引线被腐蚀的时间和速度。解决了现有技术中存在的COF基板完成焊接后COF上的焊接引线会有一部分裸露在空气中，当空气中有离子存在的环境下会发生电化学反应，焊接引线会被腐蚀掉，从而影响信号的传输的问题。
在本发明实施例中，为了便于说明，仅示出了与本发明实施例相关的部分。显示面板包括一阵列基板以及一覆晶薄膜COF基板，所述COF基板上设置多条焊接引线。
请参阅图3，为本发明实施例提供的显示面板的制作方法的实现流程示意图，所述显示面板的制作方法包括以下步骤：
在步骤S101中，提供一基板，在所述基板上依次形成金属层和氮化硅层；
在本发明实施例中，步骤S101包括：
在所述基板上形成第一金属层；
在所述第一金属层上形成第一氮化硅层；
在所述第一氮化硅层上形成第二金属层；
在所述第二金属层上形成第二氮化硅层。
然而，可以理解的是，形成第一金属层，第二金属层，第一氮化硅层和第二氮化硅层均需要通过光阻的涂抹，曝光，显影和蚀刻等步骤，由于是本领域常用技术手段，因此，在此不再赘述。
优选地，形成所述第一氮化硅层采用的材料为G-氮化硅，形成所述第二氮化硅层采用的材料为D-氮化硅。形成第一金属层和第二金属层采用的材料可以是铝或铜等其他金属材料。然而，可以理解的是，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
在步骤S102中，在所述基板的焊接区域的所述氮化硅层表面上间隔排列设置多条端子走线，所述焊接区域为所述端子走线与所述焊接引线进行连接的区域；
Figure TP140379PCT-appb-I000002
在本发明实施例中，当存在二层氮化硅层时，所述步骤S102包括：
在所述基板的焊接区域的所述第二氮化硅层表面上间隔排列设置多条端子走线，所述焊接区域为所述端子走线与所述焊接引线进行连接的区域。
在步骤S103中，对相邻所述端子走线之间的所述焊接区域进行过孔蚀刻形成过孔，所述过孔裸露出所述金属层；
作为本发明实施例一，步骤S103包括：
对相邻所述端子走线之间的第二氮化硅层、第二金属层及第一氮化硅层依次进行过孔蚀刻形成过孔，所述过孔裸露出所述第一金属层。
在本发明实施例中，当裸露出的第一金属层采用的材料为铝金属时，且当阵列基板上的端子走线与COF基板上的焊接引线连接时，裸露的焊接引线由于位于过孔区域边缘，即使裸露的焊接引线周边存在空气，但由于过孔区域裸露出的是铝制金属层，由于铝容易失去电子，在有水气和离子的氛围中优先失去电子发生电化学反应，因此空气会先与铝制金属层发生电化学反应，从而延缓了GOF基板上的铜材料的焊接引线被腐蚀的时间，以及减缓了铜材料的焊接引线被腐蚀的速度。
在本发明实施例中，当裸露出的第一金属层采用的材料为铜金属时，且当阵列基板上的端子走线与COF基板上的焊接引线连接时，裸露的焊接引线由于位于过孔区域边缘，即使裸露的焊接引线周边存在空气，但由于过孔区域裸露出的是铜制金属层，铜制金属层也可以消耗部分水气和离子，因此分担了GOF基板上的铜材料的焊接引线被腐蚀的风险。
Figure TP140379PCT-appb-I000002
作为本发明实施例二，步骤S103包括：
对相邻所述端子走线之间的第二氮化硅层进行过孔蚀刻形成过孔，所述过孔裸露出所述第二金属层。
在本发明实施例中，当裸露出的第二金属层采用的材料为铝金属时，且当阵列基板上的端子走线与COF基板上的焊接引线连接时，裸露的焊接引线由于位于过孔区域边缘，即使裸露的焊接引线周边存在空气，但由于过孔区域裸露出的是铝制金属层，由于铝容易失去电子，在有水气和离子的氛围中优先失去电子发生电化学反应，因此空气会先与铝制金属层发生电化学反应，从而延缓了GOF基板上的铜材料的焊接引线被腐蚀的时间，以及减缓了铜材料的焊接引线被腐蚀的速度。
在本发明实施例中，当裸露出的第二金属层采用的材料为铜金属时，且当阵列基板上的端子走线与COF基板上的焊接引线连接时，裸露的焊接引线由于位于过孔区域边缘，即使裸露的焊接引线周边存在空气，但由于过孔区域裸露出的是铜制金属层，铜制金属层也可以消耗部分水气和离子，因此分担了GOF基板上的铜材料的焊接引线被腐蚀的风险。
Figure TP140379PCT-appb-I000002
优选地，为了更好地防止焊接引线被腐蚀断裂的风险，在每相邻的所述端子走线之间的所述焊接区域上均设置所述过孔。
在步骤S104中，将所述多条端子走线分别与所述COF基板上的所述多条焊接引线一一对应压合连接。
请参阅图4，为本发明实施例一提供的显示面板的结构示意图。为了便于说明，仅示出了与本发明实施例相关的部分。所述显示面板包括一阵列基板以及一COF基板，所述COF基板上设置有多条焊接引线。
Figure TP140379PCT-appb-I000002
所述阵列基板包括：一基板10、金属层20、氮化硅层30、以及多条端子走线40。
其中，金属层20设置于所述基板10表面上；氮化硅层30设置于所述金属层20表面上；多条端子走线40间隔排列设置于焊接区域的所述氮化硅层30表面上，所述焊接区域为所述端子走线40与所述焊接引线进行连接的区域。
其中所述多条端子走线40分别与COF基板上的所述多条焊接引线一一对应压合连接；在相邻所述端子走线40之间的所述焊接区域上设置有过孔50，所述过孔50用于裸露出所述金属层20。
请参阅图5及图6，为本发明实施例二提供的显示面板的结构示意图。为了便于说明，仅示出了与本发明实施例相关的部分。所述显示面板包括一阵列基板以及一COF基板，所述COF基板上设置有多条焊接引线。
Figure TP140379PCT-appb-I000002
所述阵列基板包括：一基板100、第一金属层200、第一氮化硅层300、第二金属层400、第二氮化硅层500以及多条端子走线600。
所述第一金属层200设置于所述基板100表面上；所述第一氮化硅层300设置于所述第一金属层200上；所述第二金属层400设置于所述第一氮化硅层300上；所述第二氮化硅层500设置于所述第二金属层400上；所述多条端子走线600间隔排列设置于所述焊接区域的所述第二氮化硅层500表面上。所述焊接区域为所述端子走线600与所述焊接引线进行连接的区域。
其中所述多条端子走线600分别与COF基板上的所述多条焊接引线一一对应压合连接；在相邻所述端子走线600之间的所述焊接区域上设置有过孔700，所述过孔700用于裸露出第一金属层200或第二金属层400。
Figure TP140379PCT-appb-I000002
优选地，所述第一氮化硅层300采用的材料为G-氮化硅，所述第二氮化硅层500采用的材料为D-氮化硅。第一金属层200和第二金属层400采用的材料可以是铝或铜等其他金属材料。然而，可以理解的是，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
作为本发明实施例一，通过对相邻所述端子走线600之间的第二氮化硅层500、第二金属层400及第一氮化硅层300依次进行过孔蚀刻便会形成过孔700，那么蚀刻后所述过孔700会裸露出所述第一金属层200，如图5所示。
Figure TP140379PCT-appb-I000002
在本发明实施例中，当裸露出的第一金属层200采用的材料为铝金属时，且当阵列基板上的端子走线600与COF基板上的焊接引线连接时，裸露的焊接引线由于位于过孔700区域边缘，即使裸露的焊接引线周边存在空气，但由于过孔700区域裸露出的是铝制金属层，由于铝容易失去电子，在有水气和离子的氛围中优先失去电子发生电化学反应，因此空气会先与铝制金属层发生电化学反应，从而延缓了GOF基板上的铜材料的焊接引线被腐蚀的时间，以及减缓了铜材料的焊接引线被腐蚀的速度。
在本发明实施例中，当裸露出的第一金属层200采用的材料为铜金属时，且当阵列基板上的端子走线600与COF基板上的焊接引线连接时，裸露的焊接引线由于位于过孔700区域边缘，即使裸露的焊接引线周边存在空气，但由于过孔700区域裸露出的是铜制金属层，铜制金属层也可以消耗部分水气和离子，因此分担了GOF基板上的铜材料的焊接引线被腐蚀的风险。
作为本发明实施例二，通过对相邻所述端子走线600之间的第二氮化硅层500进行过孔蚀刻便会形成过孔700，那么蚀刻后所述过孔700会裸露出所述第二金属层400。如图6所示。
在本发明实施例中，当裸露出的第二金属层400采用的材料为铝金属时，且当阵列基板上的端子走线600与COF基板上的焊接引线连接时，裸露的焊接引线由于位于过孔700区域边缘，即使裸露的焊接引线周边存在空气，但由于过孔700区域裸露出的是铝制金属层，由于铝容易失去电子，在有水气和离子的氛围中优先失去电子发生电化学反应，因此空气会先与铝制金属层发生电化学反应，从而延缓了GOF基板上的铜材料的焊接引线被腐蚀的时间，以及减缓了铜材料的焊接引线被腐蚀的速度。
在本发明实施例中，当裸露出的第二金属层400采用的材料为铜金属时，且当阵列基板上的端子走线600与COF基板上的焊接引线连接时，裸露的焊接引线由于位于过孔700区域边缘，即使裸露的焊接引线周边存在空气，但由于过孔700区域裸露出的是铜制金属层，铜制金属层也可以消耗部分水气和离子，因此分担了GOF基板上的铜材料的焊接引线被腐蚀的风险。
优选地，为了更好地防止焊接引线被腐蚀断裂的风险，在每相邻的所述端子走线600之间的所述焊接区域上均设置所述过孔700。如图7所示，为在阵列基板上的相邻端子走线600之间设置过孔700的结构示意图。
综上所述，通过对阵列基板上的相邻端子走线之间的焊接区域进行过孔蚀刻形成过孔，所述过孔裸露出所述阵列基板上的金属层，使得当阵列基板上的端子走线与COF基板上的焊接引线连接时，裸露的焊接引线由于位于过孔区域边缘，即使裸露的焊接引线周边存在空气，但由于过孔区域裸露出金属层，该金属层能够分担焊接引线被腐蚀的风险，从而能够延缓焊接引线被腐蚀的时间和速度。另外，当裸露出的金属层采用的材料为铝金属时，且当阵列基板上的端子走线与COF基板上的焊接引线连接时，裸露的焊接引线由于位于过孔区域边缘，即使裸露的焊接引线周边存在空气，但由于过孔区域裸露出的是铝制金属层，由于铝容易失去电子，在有水气和离子的氛围中优先失去电子发生电化学反应，因此空气会先与铝制金属层发生电化学反应，从而延缓了GOF基板上的铜材料的焊接引线被腐蚀的时间，以及减缓了铜材料的焊接引线被腐蚀的速度。再者，当裸露出的金属层采用的材料为铜金属时，且当阵列基板上的端子走线与COF基板上的焊接引线连接时，裸露的焊接引线由于位于过孔区域边缘，即使裸露的焊接引线周边存在空气，但由于过孔区域裸露出的是铜制金属层，铜制金属层也可以消耗部分水气和离子，因此分担了GOF基板上的铜材料的焊接引线被腐蚀的风险。本发明实施例有效降低了COF基板上的焊接引线被腐蚀断裂的风险，从而增加了产品的使用时间，以及延长了产品的寿命。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。
Figure TP140379PCT-appb-I000002
Figure TP140379PCT-appb-I000002
Figure TP140379PCT-appb-I000002
 本发明的实施方式
工业实用性
序列表自由内容

Claims (20)

  1. 一种显示面板，包括一阵列基板以及一COF基板，所述COF基板上设置有多条焊接引线；其中
    所述阵列基板包括：
    一基板；
    一第一金属层，设置于所述基板表面上；
    一第一氮化硅层，设置于所述第一金属层上；
    一第二金属层，设置于所述第一氮化硅层上；
    一第二氮化硅层，设置于所述第二金属层上；以及
    多条端子走线，间隔排列设置于焊接区域的所述第二氮化硅层表面上，所述焊接区域为所述端子走线与所述焊接引线进行连接的区域；
    Figure TP140379PCT-appb-I000002
    其中所述多条端子走线分别与COF基板上的所述多条焊接引线一一对应压合连接；在每相邻的所述端子走线之间的所述焊接区域上均设置有过孔，所述过孔用于裸露出所述金属层。
  2. 如权利要求1所述的显示面板，其中在相邻所述端子走线之间的所述焊接区域上设置有过孔，所述过孔用于裸露出所述第一金属层。
    Figure TP140379PCT-appb-I000002
  3. 如权利要求1所述的显示面板，其中在相邻所述端子走线之间的所述焊接区域上设置有过孔，所述过孔用于裸露出所述第二金属层。
  4. 如权利要求1所述的显示面板，其中所述第一氮化硅层采用的材料为G-氮化硅，所述第二氮化硅层采用的材料为D-氮化硅。
  5. 如权利要求1所述的显示面板，其中所述第一金属层和所述第二金属层采用的材料是铝。
    Figure TP140379PCT-appb-I000002
  6. 如权利要求1所述的显示面板，其中所述第一金属层和所述第二金属层采用的材料是铜。
    Figure TP140379PCT-appb-I000002
  7. 一种显示面板的制作方法，所述显示面板包括一阵列基板以及一覆晶薄膜COF基板，所述COF基板上设置多条焊接引线，其中所述显示面板的制作方法包括以下步骤：
    提供一基板，在所述基板上依次形成金属层和氮化硅层；
    在所述基板的焊接区域的所述氮化硅层表面上间隔排列设置多条端子走线，所述焊接区域为所述端子走线与所述焊接引线进行连接的区域；
    对相邻所述端子走线之间的所述焊接区域进行过孔蚀刻形成过孔，所述过孔裸露出所述金属层；以及
    将所述多条端子走线分别与所述COF基板上的所述多条焊接引线一一对应压合连接。
  8. 如权利要求7所述的显示面板的制作方法，其中所述在所述基板上依次形成金属层和氮化硅层的步骤包括：
    在所述基板上形成第一金属层；
    在所述第一金属层上形成第一氮化硅层；
    在所述第一氮化硅层上形成第二金属层；
    Figure TP140379PCT-appb-I000002
    在所述第二金属层上形成第二氮化硅层；
    Figure TP140379PCT-appb-I000002
    所述在所述基板的焊接区域的所述氮化硅层表面上间隔排列设置多条端子走线的步骤包括：
    在所述基板的焊接区域的所述第二氮化硅层表面上间隔排列设置多条端子走线。
  9. 如权利要求8所述的显示面板的制作方法，其中对相邻所述端子走线之间的所述焊接区域进行过孔蚀刻形成过孔，所述过孔裸露出所述金属层的步骤包括：
    对相邻所述端子走线之间的第二氮化硅层、第二金属层及第一氮化硅层依次进行过孔蚀刻形成过孔，所述过孔裸露出所述第一金属层。
    Figure TP140379PCT-appb-I000002
  10. 如权利要求8所述的显示面板的制作方法，其中对相邻所述端子走线之间的所述焊接区域进行过孔蚀刻形成过孔，所述过孔裸露出所述金属层的步骤包括：
    对相邻所述端子走线之间的第二氮化硅层进行过孔蚀刻形成过孔，所述过孔裸露出所述第二金属层。
  11. 如权利要求7所述的显示面板的制作方法，其中在每相邻的所述端子走线之间的所述焊接区域上均设置所述过孔。
  12. 12、如权利要求7所述的显示面板的制作方法，其中所述第一氮化硅层采用的材料为G-氮化硅，所述第二氮化硅层采用的材料为D-氮化硅。
    Figure TP140379PCT-appb-I000002
  13. 一种显示面板，包括一阵列基板以及一COF基板，所述COF基板上设置有多条焊接引线；其中
    所述阵列基板包括：
    一基板；
    金属层，设置于所述基板表面上；
    氮化硅层，设置于所述金属层表面上；以及
    多条端子走线，间隔排列设置于焊接区域的所述氮化硅层表面上，所述焊接区域为所述端子走线与所述焊接引线进行连接的区域；
    其中所述多条端子走线分别与COF基板上的所述多条焊接引线一一对应压合连接；在相邻所述端子走线之间的所述焊接区域上设置有过孔，所述过孔用于裸露出所述金属层。
    Figure TP140379PCT-appb-I000002
  14. 如权利要求13所述的显示面板，其中所述金属层包括第一金属层和第二金属层，所述氮化硅层包括第一氮化硅层和第二氮化硅层；
    所述第一金属层设置于所述基板表面上；
    所述第一氮化硅层设置于所述第一金属层上；
    所述第二金属层设置于所述第一氮化硅层上；
    所述第二氮化硅层设置于所述第二金属层上；
    所述多条端子走线间隔排列设置于所述焊接区域的所述第二氮化硅层表面上。
  15. 如权利要求14所述的显示面板，其中在相邻所述端子走线之间的所述焊接区域上设置有过孔，所述过孔用于裸露出所述第一金属层。
    Figure TP140379PCT-appb-I000002
  16. 如权利要求14所述的显示面板，其中在相邻所述端子走线之间的所述焊接区域上设置有过孔，所述过孔用于裸露出所述第二金属层。
    Figure TP140379PCT-appb-I000002
  17. 如权利要求13所述的显示面板，其中在每相邻的所述端子走线之间的所述焊接区域上均设置所述过孔。
  18. 如权利要求13所述的显示面板，其中所述第一氮化硅层采用的材料为G-氮化硅，所述第二氮化硅层采用的材料为D-氮化硅。
  19. 如权利要求13所述的显示面板，其中所述第一金属层和所述第二金属层采用的材料是铝。
    Figure TP140379PCT-appb-I000002
  20. 如权利要求13所述的显示面板，其中所述第一金属层和所述第二金属层采用的材料是铜。
PCT/CN2014/081097 2014-06-19 2014-06-30 一种显示面板及其制作方法 WO2015192394A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107564918A (zh) * 2016-06-30 2018-01-09 三星显示有限公司 显示装置

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867924B (zh) * 2015-05-06 2018-10-23 深圳市华星光电技术有限公司 Tft显示器件及其制作方法
CN105093758A (zh) * 2015-09-07 2015-11-25 深圳市华星光电技术有限公司 一种液晶显示面板及装置
CN105652538A (zh) * 2016-03-15 2016-06-08 深圳市华星光电技术有限公司 一种显示面板及其制造工艺
CN110571224B (zh) * 2019-08-05 2021-12-28 深圳市华星光电半导体显示技术有限公司 显示装置及其制备方法
CN112241223B (zh) * 2020-10-27 2022-09-27 武汉华星光电半导体显示技术有限公司 显示屏及电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11264998A (ja) * 1998-03-18 1999-09-28 Nec Corp 配線端子およびその形成方法
JP2003068795A (ja) * 2001-08-24 2003-03-07 Sharp Corp 表示装置およびその製造方法
CN101106117A (zh) * 2006-07-11 2008-01-16 瀚宇彩晶股份有限公司 显示面板与其控制电路封装结构
CN202693965U (zh) * 2012-07-25 2013-01-23 北京京东方光电科技有限公司 一种阵列基板及显示装置
CN202735643U (zh) * 2012-07-06 2013-02-13 北京京东方光电科技有限公司 一种引线连接装置及显示器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11264998A (ja) * 1998-03-18 1999-09-28 Nec Corp 配線端子およびその形成方法
JP2003068795A (ja) * 2001-08-24 2003-03-07 Sharp Corp 表示装置およびその製造方法
CN101106117A (zh) * 2006-07-11 2008-01-16 瀚宇彩晶股份有限公司 显示面板与其控制电路封装结构
CN202735643U (zh) * 2012-07-06 2013-02-13 北京京东方光电科技有限公司 一种引线连接装置及显示器件
CN202693965U (zh) * 2012-07-25 2013-01-23 北京京东方光电科技有限公司 一种阵列基板及显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107564918A (zh) * 2016-06-30 2018-01-09 三星显示有限公司 显示装置
CN107564918B (zh) * 2016-06-30 2023-06-20 三星显示有限公司 显示装置

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