WO2020155893A1 - 过孔结构及其制造方法、电子器件、显示装置 - Google Patents

过孔结构及其制造方法、电子器件、显示装置 Download PDF

Info

Publication number
WO2020155893A1
WO2020155893A1 PCT/CN2019/125656 CN2019125656W WO2020155893A1 WO 2020155893 A1 WO2020155893 A1 WO 2020155893A1 CN 2019125656 W CN2019125656 W CN 2019125656W WO 2020155893 A1 WO2020155893 A1 WO 2020155893A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive layer
insulating layer
layer
interlayer insulating
via structure
Prior art date
Application number
PCT/CN2019/125656
Other languages
English (en)
French (fr)
Inventor
张雷
孙大庆
邱伟
闫方亮
Original Assignee
京东方科技集团股份有限公司
绵阳京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 绵阳京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/771,261 priority Critical patent/US11335625B2/en
Publication of WO2020155893A1 publication Critical patent/WO2020155893A1/zh
Priority to US17/729,695 priority patent/US20220254838A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads

Definitions

  • the present disclosure relates to the field of electronic technology, in particular to a via structure and a manufacturing method thereof, an electronic device, and a display device.
  • Display devices such as touch screens and display screens usually include a via structure.
  • the traditional via structure includes a first conductive layer, an interlayer insulating layer, and a second conductive layer arranged in sequence.
  • the interlayer insulating layer has via holes. The two conductive layers are overlapped with the first conductive layer through the via hole.
  • the embodiments of the present disclosure provide a via structure, a manufacturing method thereof, an electronic device, and a display device.
  • a via structure is provided, and the via structure includes:
  • the first conductive layer, the interlayer insulating layer, and the second conductive layer are arranged in sequence, the interlayer insulating layer has a via hole, and the second conductive layer overlaps the first conductive layer through the via hole, so At least a part of the surface of the interlayer insulating layer in contact with the second conductive layer is an uneven surface.
  • the inner wall surface of the via hole is an uneven surface.
  • the surface of the interlayer insulating layer away from the first conductive layer is an uneven surface.
  • the roughness of the uneven surface has a value range of 0.05d ⁇ r ⁇ 0.15d, where r represents the roughness, and d represents the thickness of the interlayer insulating layer.
  • the material of at least one of the first conductive layer and the second conductive layer is metal.
  • the first conductive layer includes a common electrode line
  • the second conductive layer includes a common electrode
  • the first conductive layer includes a drain electrode of a thin film transistor, and the second conductive layer includes a pixel electrode; or,
  • the first conductive layer includes touch sensing traces, and the second conductive layer includes touch sensing electrodes; or,
  • the first conductive layer includes horizontal metal strips, and the second conductive layer includes vertical metal strips.
  • a manufacturing method of a via structure includes:
  • a second conductive layer is formed on the interlayer insulating layer, the second conductive layer is overlapped with the first conductive layer through the via hole, and the interlayer insulating layer is in contact with the second conductive layer At least part of the surface is an uneven surface.
  • the forming a via hole on the initial insulating layer to obtain an interlayer insulating layer includes:
  • At least part of the surface of the interlayer insulating layer in contact with the second conductive layer is roughened.
  • the roughening of at least a part of the surface of the interlayer insulating layer in contact with the second conductive layer includes:
  • the roughening of at least a part of the surface of the interlayer insulating layer in contact with the second conductive layer includes:
  • Roughening is performed on the inner wall surface of the via hole and the side of the interlayer insulating layer away from the first conductive layer.
  • the performing roughening treatment on at least part of the surface of the interlayer insulating layer in contact with the second conductive layer includes: bombarding the interlayer insulating layer with the second conductive layer by plasma To roughen at least part of the surface of the interlayer insulating layer in contact with the second conductive layer.
  • the plasma includes at least one of an inert gas and a gas that does not react with the initial insulating layer.
  • the plasma includes at least one of helium, argon, and oxygen.
  • an electronic device in one aspect, includes the via structure as described in any one of the preceding items.
  • a display device includes the electronic device as described above.
  • FIG. 1 is a schematic structural diagram of a via structure provided by an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of another via structure provided by an embodiment of the present disclosure.
  • FIG. 3 is a method flowchart of a method for manufacturing a via structure provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a first conductive layer, an initial insulating layer, and a mask pattern layer are sequentially formed on a base substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram after forming a via hole in a region corresponding to the opening region of the mask pattern layer on the initial insulating layer according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram after roughening the inner wall surface of a via hole provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram after peeling off a mask pattern layer provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a second conductive layer formed on the side of the interlayer insulating layer away from the first conductive layer according to an embodiment of the present disclosure.
  • FIG. 9 is a method flowchart of another method for manufacturing a via structure provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of peeling off a mask pattern layer on an interlayer insulating layer according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of the inner wall surface of the via hole and the side of the interlayer insulating layer away from the first conductive layer after being roughened according to an embodiment of the present disclosure.
  • Display devices usually include a via structure.
  • the via structure usually includes a first conductive layer, an interlayer insulating layer, and a second conductive layer arranged in sequence.
  • the interlayer insulating layer has a via hole, and the second conductive layer passes through the via hole.
  • the first conductive layer overlaps.
  • the side of the interlayer insulating layer away from the first conductive layer is a smooth plane, and the inner wall of the via is a smooth curved surface, which makes the second conductive layer located in the via
  • the inner part and the part of the second conductive layer on the interlayer insulating layer are easy to fall off, resulting in poor bonding between the second conductive layer and the first conductive layer.
  • the etching parameters of the etching process are changed to correct the slope angle of the via (the slope angle refers to the over-hole).
  • the correction of the slope angle of the via requires frequent adjustment of the etching parameters, which is difficult to achieve.
  • the slope angle of the via is corrected, if the interlayer insulation layer has uneven film In this case, the expected correction effect cannot be achieved, so the uniformity of the formation of the interlayer insulating layer is required to be high.
  • the embodiments of the present disclosure provide a via structure and a manufacturing method thereof, an electronic device, and a display device.
  • the interlayer insulating layer has via holes, and at least part of the surface of the interlayer insulating layer in contact with the second conductive layer It is an uneven surface, so the adhesion between the second conductive layer and the interlayer insulating layer is relatively large, which can prevent the second conductive layer from falling off, thereby avoiding poor bonding between the second conductive layer and the first conductive layer.
  • the solution provided by the embodiment of the present disclosure does not need to modify the slope angle of the via hole by changing the etching parameters, which is easy to implement and has low requirements on the uniformity of the film formation of the interlayer insulating layer. Please refer to the description of the following embodiments for the detailed solution of the present disclosure.
  • FIG. 1 shows a schematic structural diagram of a via structure provided by an embodiment of the present disclosure.
  • the via structure includes: a first conductive layer 10, an interlayer insulating layer 20, and a second conductive layer 30 arranged in sequence.
  • the interlayer insulating layer 20 has a via hole 201.
  • the inner wall surface 201a of the via hole 201 (that is, the The inner side) is an uneven surface, and the second conductive layer 30 overlaps the first conductive layer 10 through the via 201.
  • the adhesion between the portion of the second conductive layer located in the via hole and the inner wall surface of the via hole is increased. It can prevent the part of the second conductive layer located in the via hole from falling off, thereby avoiding poor bonding between the second conductive layer and the first conductive layer, and improving the bonding effect between the second conductive layer and the first conductive layer.
  • the surface of the interlayer insulating layer 20 away from the first conductive layer 10 is an uneven surface.
  • the via structure has a via area and a non-via area.
  • the via area refers to the area where the via 201 of the interlayer insulating layer 20 is located (that is, the via hole of the interlayer insulating layer 20 corresponds to the via structure).
  • the non-via area refers to the area in the via structure excluding the via area
  • the surface of the interlayer insulating layer 20 away from the first conductive layer 10 is uneven surface refers to: the interlayer insulating layer
  • the surface of the portion 20 located in the non-via area away from the first conductive layer 10 is an uneven surface. In this way, since in the non-via area of the via structure, the surface of the interlayer insulating layer 20 away from the first conductive layer 10 is an uneven surface, the interlayer insulation is enlarged in the non-via area of the via structure.
  • the adhesion between the layer 20 and the second conductive layer 30 improves the bonding effect of the interlayer insulating film layer 20 and the second conductive layer 30.
  • both the inner wall surface 201a of the via 201 and the side of the interlayer insulating layer 20 away from the first conductive layer 10 may have uneven microstructures (not shown in FIGS. 1 and 2, the microstructures are, for example, microstructures). Grooves, etc.) so that the inner wall surface 201a of the via hole 201 and the side of the interlayer insulating layer 20 away from the first conductive layer 10 are both uneven surfaces, that is, the inner wall surface 201a of the via hole 201 and the layer The side of the inter-insulating layer 20 away from the first conductive layer 10 has a certain roughness.
  • the roughness of the side of the interlayer insulating layer 20 away from the first conductive layer 10 and the inner wall surface of the via hole are both 0.05d ⁇ r ⁇ 0.15d, where r represents the roughness, and d represents the interlayer
  • the material of at least one conductive layer of the first conductive layer 10 and the second conductive layer 30 may be metal, and the material of the interlayer insulating layer 20 may be silicon nitride, silicon oxide, silicon oxynitride, etc.
  • the aforementioned interlayer insulating layer 20 may be an insulating film layer, or may be an insulating layer formed by superimposing multiple insulating film layers, which is not limited in the embodiment of the present disclosure.
  • FIGS. 1 and 2 are only examples.
  • only the side of the interlayer insulating layer 20 away from the first conductive layer 10 may be an uneven surface.
  • the entire surface of the inner wall surface 201a of the via hole 201 or the entire surface of the interlayer insulating layer 20 away from the first conductive layer 10 being an uneven surface, only a part of the inner wall surface 201a of the via hole 201 or interlayer insulation The portion of the layer 20 away from the surface of the first conductive layer 10 is an uneven surface.
  • the via structure provided by the embodiments of the present disclosure may include two conductive layers and an insulating layer located between the two conductive layers, and the two conductive layers are overlapped by a via on the insulating layer. Hole structure.
  • the two conductive layers in the via structure have different manifestations.
  • an insulating layer is provided between the common electrode and the common electrode line, and the insulating layer has a via hole.
  • the common electrode is connected to the common electrode line through the via hole, so the common electrode, the common electrode line and the insulating layer
  • the layers constitute a via structure.
  • an insulating layer is provided between the pixel electrode and the drain of a thin film transistor (Thin Film Transistor, TFT), the insulating layer has a via hole, and the pixel electrode is connected to the drain of the thin film transistor through the via hole. Therefore, the pixel electrode, the drain electrode of the thin film transistor, and the insulating layer constitute a via structure.
  • TFT Thin Film Transistor
  • an insulating layer is provided between the touch sensing trace and the touch sensing electrode, and the insulating layer has a via hole, and the touch sensing trace is overlapped with the touch sensing electrode through the via hole. Therefore, the touch sensing trace, the touch sensing electrode and the insulating layer constitute a via structure.
  • an insulating layer is provided between the horizontal metal strips and the vertical metal strips, and the insulating layer has vias.
  • the horizontal metal strips overlap the vertical metal strips through the vias.
  • the strip and the insulating layer constitute a via structure.
  • an insulating layer is provided between two transmission lines, and the insulating layer has a via hole. The two transmission lines overlap through the via hole, so the two transmission lines and the insulating layer form a via structure.
  • the via structures listed in this article are only exemplary and are not used to limit the solutions of the embodiments of the present disclosure. Those skilled in the art should understand that any two conductive layers pass between the two conductive layers.
  • the overlapping structures of the vias on the insulating layer all fall within the scope of the embodiments of the present disclosure, and will not be repeated here.
  • the inner wall surface of the via hole is an uneven surface, the adhesion between the portion of the second conductive layer located in the via hole and the inner wall surface of the via hole is increased. It can prevent the part of the second conductive layer located in the via hole from falling off, thereby avoiding poor bonding between the second conductive layer and the first conductive layer, and improving the bonding effect between the second conductive layer and the first conductive layer.
  • the solution provided by the embodiment of the present disclosure does not need to modify the slope angle of the via hole by changing the etching parameters, is easy to implement, and has low requirements on the uniformity of the film formation of the interlayer insulating layer.
  • the via structure provided by the embodiment of the present disclosure can be applied to the following method.
  • the manufacturing method of the via structure and the manufacturing principle of the via structure of the embodiment of the present disclosure please refer to the description in the following embodiments.
  • FIG. 3 shows a method flow chart of a method for manufacturing a via structure provided by an embodiment of the present disclosure.
  • the method for manufacturing a via structure can manufacture the via structure as shown in FIG.
  • the manufacturing method of the structure includes the following steps:
  • Step 101 A first conductive layer, an initial insulating layer and a mask pattern layer are sequentially formed on a base substrate, and the mask pattern layer has an open area.
  • FIG. 4 shows a schematic diagram after the first conductive layer 10, the initial insulating layer 20a and the mask pattern layer 50 are sequentially formed on the base substrate 40 provided by the embodiment of the present disclosure.
  • the mask pattern The layer 50 has an open area 501, and the mask pattern layer 50 may be a photoresist (PR) glue pattern layer.
  • sequentially forming the first conductive layer 10, the initial insulating layer 20a, and the mask pattern layer 50 on the base substrate 40 may include the following three steps:
  • Step (1) forming a conductive material layer on the base substrate 40 by means of deposition, coating or sputtering, and then processing the conductive material layer through a patterning process to obtain the first conductive layer 10.
  • Step (2) forming the initial insulating layer 20a on the base substrate 40 on which the first conductive layer 10 is formed by deposition, coating, or sputtering.
  • Step (3) forming a PR material layer on the base substrate 40 on which the initial insulating layer 20a is formed by deposition, coating or sputtering, and sequentially exposing and developing the PR material layer to obtain a mask pattern layer 50.
  • Step 102 forming a via hole in the area corresponding to the opening area on the initial insulating layer to obtain an interlayer insulating layer.
  • FIG. 5 shows a schematic diagram after forming a via hole on the initial insulating layer 20 a corresponding to the opening area 501 of the mask pattern layer 50 according to an embodiment of the present disclosure.
  • the area on the initial insulating layer 20a corresponding to the opening area 501 of the mask pattern layer 50 can be etched by a dry etching process, so as to be in contact with the opening on the initial insulating layer 20a.
  • a via hole is formed in the region corresponding to the region 501, thereby obtaining the interlayer insulating layer 20.
  • Step 103 Roughen the inner wall surface of the via hole.
  • FIG. 6 shows a schematic diagram after roughening the inner wall surface of a via hole provided by an embodiment of the present disclosure.
  • a preset plasma may be used to bombard the inner wall surface of the via hole (not shown in FIG. 6) to roughen the inner wall surface of the via hole.
  • the structure shown in FIG. 5 can be set in a plasma etching machine, and plasma is introduced into the plasma etching machine to bombard the inner wall surface of the via hole through the plasma to achieve The purpose of roughening the inner wall surface.
  • the mask pattern layer 50 may also bombard the side of the mask pattern layer 50 away from the interlayer insulating layer 20.
  • the bombardment is physical bombardment
  • the plasma may be an inert gas or a gas that does not react with the initial insulating layer.
  • the plasma includes at least one of helium (He), argon (Ar), and oxygen (O2).
  • helium and argon are inert gases
  • oxygen is a gas that does not react with the initial insulating layer.
  • the plasma etching machine is a common equipment in the electronic technology field, so this step 103 can be performed in the existing equipment, which is simple to implement. In this implementation manner, after the roughening treatment is performed, the entire film structure can be cleaned to remove substances generated on the surface of the conductive layer by the reaction between the plasma and the conductive layer.
  • the plasma may be an inert gas or a gas that neither reacts with the initial insulating layer nor with the conductive layer, so that the plasma does not react with the conductive layer, which avoids the production of other substances on the surface of the conductive layer.
  • Step 104 Peel off the mask pattern layer.
  • FIG. 7 shows a schematic diagram after peeling off the mask pattern layer 50 provided by an embodiment of the present disclosure.
  • the interlayer insulating layer 20 has a via 201, and the inner wall surface of the via 201 is an uneven curve.
  • the mask pattern layer may be peeled off by a peeling process, and the peeling process may be an ashing process, a photoresist peeling process, or the like.
  • Step 105 forming a second conductive layer on the side of the interlayer insulating layer away from the first conductive layer, and the second conductive layer overlaps the first conductive layer through the via hole.
  • FIG. 8 shows a schematic diagram of the second conductive layer 30 formed on the side of the interlayer insulating layer 20 away from the first conductive layer 10 according to an embodiment of the present disclosure, wherein the first conductive layer 10 , The interlayer insulating layer 20 and the second conductive layer 30 constitute a via structure.
  • a physical vapor deposition (Physical Vapor Deposition, PVD) process may be used to deposit a conductive material on the side of the interlayer insulating layer 20 away from the first conductive layer 10 to obtain a conductive material layer, and then conduct a patterning process to the conductive material. The material layer is processed to obtain the second conductive layer 30.
  • PVD Physical Vapor Deposition
  • the via 201 of the interlayer insulating layer 20 Conductive material is also deposited inside, so that the part of the second conductive layer 30 that is finally made in the via 201 is in contact with the first conductive layer 10, so that the second conductive layer 30 overlaps the first conductive layer 10 through the via 201 .
  • the inner wall surface of the via hole is roughened, so the inner wall surface of the via hole is relatively rough.
  • the second conductive layer is deposited, It is easier to deposit conductive materials in the via hole, avoiding the part of the second conductive layer located in the via hole from falling down, thereby avoiding the occurrence of faults in the second conductive layer, and improving the poor connection between the first conductive layer and the second conductive layer.
  • the method for manufacturing the via structure provided by the embodiments of the present disclosure, since the inner wall surface of the via is roughened, the portion of the second conductive layer located in the via hole and the inner wall surface of the via are enlarged.
  • the adhesion force of the second conductive layer prevents the part of the second conductive layer located in the via hole from falling off, thereby avoiding poor bonding between the second conductive layer and the first conductive layer, and improving the bonding effect between the second conductive layer and the first conductive layer.
  • the solution provided by the embodiment of the present disclosure does not need to modify the slope angle of the via hole by changing the etching parameters, is easy to implement, and has low requirements on the uniformity of the film formation of the interlayer insulating layer.
  • FIG. 9 shows a method flow chart of another method for manufacturing a via structure provided by an embodiment of the present disclosure.
  • the method for manufacturing the via structure can manufacture the via structure as shown in FIG.
  • the manufacturing method of the hole structure includes the following steps:
  • Step 201 sequentially forming a first conductive layer, an initial insulating layer and a mask pattern layer on a base substrate, and the mask pattern layer has an open area.
  • Step 202 forming a via hole in the area corresponding to the opening area on the initial insulating layer to obtain an interlayer insulating layer.
  • step 201 and step 202 For the implementation process of step 201 and step 202, reference may be made to step 101 and step 102 in the embodiment shown in FIG. 3, which will not be repeated in the embodiment of the present disclosure.
  • Step 203 Peel off the mask pattern layer.
  • FIG. 10 shows a schematic diagram of peeling off the mask pattern layer on the interlayer insulating layer provided by an embodiment of the present disclosure.
  • this step 203 For the implementation process of this step 203, reference may be made to step 104 of the embodiment shown in FIG. 3, which will not be repeated in the embodiment of the present disclosure.
  • Step 204 Perform roughening treatment on the inner wall surface of the via hole and the side of the interlayer insulating layer away from the first conductive layer.
  • FIG. 11 shows a schematic diagram of roughening the inner wall surface of the via 201 and the side of the interlayer insulating layer 20 away from the first conductive layer 10 according to an embodiment of the present disclosure.
  • step 204 For the implementation process of step 204, reference may be made to step 103 of the embodiment shown in FIG. 3, which will not be repeated in the embodiment of the present disclosure.
  • step 203 since the mask pattern layer on the interlayer insulating layer 20 has been peeled off in step 203, as shown in FIG.
  • the inner wall of the hole 201 is bombarded, and the side of the interlayer insulating layer 20 away from the first conductive layer 10 can be bombarded, so that the inner wall of the via 201 and the side of the interlayer insulating layer 20 away from the first conductive layer 10 are both Uneven surface.
  • Step 205 forming a second conductive layer on the side of the interlayer insulating layer away from the first conductive layer, and the second conductive layer overlaps the first conductive layer through the via hole.
  • step 205 For the implementation process of step 205, reference may be made to step 105 of the embodiment shown in FIG. 3, which will not be repeated in the embodiment of the present disclosure.
  • the inner wall surface of the via hole and the side of the interlayer insulating layer 20 away from the first conductive layer 10 are roughened in step 204, the inner wall surface of the via hole and the interlayer insulating layer The side of 20 away from the first conductive layer 10 is an uneven surface, which can increase the adhesion between the second conductive layer and the inner wall surface of the via 201 and the adhesion between the second conductive layer and the interlayer insulating layer 20 , To prevent the second conductive layer from falling off, and improve the bonding effect between the second conductive layer and the first conductive layer.
  • the second conductive layer is increased.
  • the first conductive layer has poor overlap, which improves the overlap effect between the second conductive layer and the first conductive layer.
  • the solution provided by the embodiment of the present disclosure does not need to modify the slope angle of the via hole by changing the etching parameters, is easy to implement, and has low requirements on the uniformity of the film formation of the interlayer insulating layer.
  • the patterning process involved includes photoresist coating, exposure, development, etching, and photoresist stripping.
  • the layer processing to obtain the corresponding structure may include: coating a layer of photoresist on the material layer (for example, the conductive material layer) to form a photoresist layer, using a mask The plate exposes the photoresist layer so that the photoresist layer forms a fully exposed area and a non-exposed area, and then uses a development process to completely remove the photoresist in the fully exposed area, and all the photoresist in the non-exposed area remains An etching process is used to etch the area corresponding to the fully exposed area on the material layer (such as the conductive material layer), and finally the photoresist in the non-exposed area is stripped to obtain the corresponding structure (such as the first conductive layer).
  • the photoresist is a positive photoresist as an example.
  • the process of one patterning process can refer to the description in this paragraph, and the embodiments of the present disclosure will not be omitted here. Repeat.
  • An embodiment of the present disclosure also provides an electronic device, which includes: the via structure shown in FIG. 1 or FIG. 2.
  • An embodiment of the present disclosure also provides a display device, which includes an electronic device, and the electronic device includes the via structure shown in FIG. 1 or FIG. 2.
  • the display device can be a touch screen, a thin film transistor liquid crystal display (Liquid Crystal Display, TFT-LCD), an organic light-emitting diode (Organic Light-Emitting Diode, OLED) display, mobile phone, tablet computer, TV, notebook computer, digital photo frame Or navigator products or parts.
  • TFT-LCD Thiquid Crystal Display
  • OLED Organic Light-Emitting Diode

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Human Computer Interaction (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种过孔结构及其制造方法、电子器件、显示装置，属于电子技术领域。所述过孔结构包括：依次设置的第一导电层(10)、层间绝缘层(20)和第二导电层(30)，所述层间绝缘层(20)具有过孔(201)，所述第二导电层(30)通过所述过孔(201)与所述第一导电层(10)搭接，所述层间绝缘层(20)与所述第二导电层(30)接触的至少部分表面为凹凸不平的表面。避免了第二导电层(30)位于过孔(201)内的部分脱落，从而避免了第二导电层(30)与第一导电层(10)出现搭接不良。用于导电层的搭接。

Description

过孔结构及其制造方法、电子器件、显示装置
本申请要求于2019年1月31日提交的申请号为201910098927.6、发明名称为“过孔结构及其制造方法、电子器件、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及电子技术领域，特别涉及一种过孔结构及其制造方法、电子器件、显示装置。
背景技术
诸如触控屏、显示屏等显示装置中通常包括过孔结构，传统的过孔结构包括依次设置的第一导电层、层间绝缘层和第二导电层，层间绝缘层具有过孔，第二导电层通过该过孔与第一导电层搭接。
发明内容
本公开实施例提供了一种过孔结构及其制造方法、电子器件、显示装置。
一方面，提供一种过孔结构，所述过孔结构包括：
依次设置的第一导电层、层间绝缘层和第二导电层，所述层间绝缘层具有过孔，所述第二导电层通过所述过孔与所述第一导电层搭接，所述层间绝缘层与所述第二导电层接触的至少部分表面为凹凸不平的表面。
可选的，所述过孔的内壁面为凹凸不平的表面。
可选的，所述层间绝缘层远离所述第一导电层的一面为凹凸不平的表面。
可选的，所述凹凸不平的表面的粗糙度的取值范围为0.05d≤r≤0.15d，所述r表示所述粗糙度，所述d表示所述层间绝缘层的厚度。
可选的，r＝0.05d或者r＝0.1d或者r＝0.15d。
可选的，所述第一导电层和所述第二导电层中的至少一个导电层的材料为金属。
可选的，所述第一导电层包括公共电极线，所述第二导电层包括公共电极；或者，
所述第一导电层包括薄膜晶体管的漏极，所述第二导电层包括像素电极；或者，
所述第一导电层包括触控感应走线，所述第二导电层包括触控感应电极；或者，
所述第一导电层包括横向金属条，所述第二导电层包括纵向金属条。
一方面，提供一种过孔结构的制造方法，所述方法包括：
依次形成第一导电层和初始绝缘层；
在所述初始绝缘层上形成过孔，得到层间绝缘层；
在所述层间绝缘层上形成第二导电层，所述第二导电层通过所述过孔与所述第一导电层搭接，所述层间绝缘层与所述第二导电层接触的至少部分表面为凹凸不平的表面。
可选的，所述在所述初始绝缘层上形成过孔，得到层间绝缘层，包括：
在所述初始绝缘层上形成掩膜图形层，所述掩膜图形层具有开口区域；
在所述初始绝缘层上与所述开口区域对应的区域形成过孔，得到层间绝缘层；
对所述层间绝缘层与所述第二导电层接触的至少部分表面进行粗糙化处理。
可选的，所述对所述层间绝缘层与所述第二导电层接触的至少部分表面进行粗糙化处理，包括：
在所述掩膜图形层覆盖的情况下对所述过孔的内壁面进行粗糙化处理；
剥离所述掩膜图形层。
可选的，所述对所述层间绝缘层与所述第二导电层接触的至少部分表面进行粗糙化处理，包括：
剥离所述掩膜图形层；
对所述过孔的内壁面和所述层间绝缘层远离所述第一导电层的一面进行粗糙化处理。
可选的，所述对所述层间绝缘层与所述第二导电层接触的至少部分表面进行粗糙化处理，包括：采用等离子体轰击所述层间绝缘层与所述第二导电层接触的至少部分表面，以对所述层间绝缘层与所述第二导电层接触的至少部分表面进行粗糙化处理。
可选的，所述等离子体包括惰性气体和不与所述初始绝缘层反应的气体中的至少一种。
可选的，所述等离子体包括氦气、氩气和氧气中的至少一种。
一方面，提供一种电子器件，所述电子器件包括：如前任一项所述的过孔结构。
一方面，提供一种显示装置，所述显示装置包括：如前所述的电子器件。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性的，并不能限制本公开。
附图说明
图1是本公开实施例提供的一种过孔结构的结构示意图。
图2是本公开实施例提供的另一种过孔结构的结构示意图。
图3是本公开实施例提供的一种过孔结构的制造方法的方法流程图。
图4是本公开实施例提供的一种在衬底基板上依次形成第一导电层、初始绝缘层和掩膜图形层后的示意图。
图5是本公开实施例提供的一种在初始绝缘层上与掩膜图形层的开口区域对应的区域形成过孔后的示意图。
图6是本公开实施例提供的一种对过孔的内壁面进行粗糙化处理后的示意图。
图7是本公开实施例提供的一种剥离掩膜图形层后的示意图。
图8是本公开实施例提供的一种在层间绝缘层远离第一导电层的一侧形成第二导电层后的示意图。
图9是本公开实施例提供的另一种过孔结构的制造方法的方法流程图。
图10是本公开实施例提供的一种剥离层间绝缘层上掩膜图形层的示意图。
图11是本公开实施例提供的一种对过孔的内壁面和层间绝缘层远离第一导电层的一面进行粗糙化处理后的示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公 开作进一步地详细描述，显然，所描述的实施例仅仅是本公开一部份实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
显示装置中通常包括过孔结构，过孔结构通常包括依次设置的第一导电层、层间绝缘层和第二导电层，层间绝缘层上具有过孔，第二导电层通过该过孔与第一导电层搭接，在传统的过孔结构中，层间绝缘层远离第一导电层的一面为光滑的平面，过孔的内壁面为光滑的曲面，这使得第二导电层位于过孔内的部分以及第二导电层位于层间绝缘层上的部分均容易脱落，导致第二导电层与第一导电层出现搭接不良。
为了避免第二导电层脱落，目前主要在通过刻蚀工艺在层间绝缘层上形成过孔的过程中，改变刻蚀工艺的刻蚀参数来修正过孔的坡度角(坡度角指的是过孔的内壁面与第一导电层靠近层间绝缘层的一面所在平面的夹角)。但是，受刻蚀工艺的限制，修正过孔的坡度角需要对刻蚀参数进行频繁调整，实现难度较大，同时，修正过孔的坡度角时，若该层间绝缘层存在膜层不均匀的情况，则无法达到预期的修正效果，因此对层间绝缘层的成膜的均匀性的要求较高。
本公开实施例提供了一种过孔结构及其制造方法、电子器件、显示装置，在过孔结构中，层间绝缘层具有过孔，层间绝缘层与第二导电层接触的至少部分表面为凹凸不平的表面，因此第二导电层与层间绝缘层的粘结力较大，可以避免第二导电层脱落，从而避免第二导电层与第一导电层出现搭接不良。并且本公开实施例提供的方案无需通过改变刻蚀参数来修正过孔的坡度角，易于实现且对层间绝缘层的成膜的均匀性的要求较低。本公开的详细方案请参考下述实施例的描述。
下面结合附图，对层间绝缘层与第二导电层接触的至少部分表面(也即前述凹凸不平的表面)进行举例说明。
请参考图1，其示出了本公开实施例提供的一种过孔结构的结构示意图。该过孔结构包括：依次设置的第一导电层10、层间绝缘层20和第二导电层30，层间绝缘层20具有过孔201，过孔201的内壁面201a(也即过孔的内侧面)为凹凸不平的表面，第二导电层30通过该过孔201与第一导电层10搭接。
综上所述，本公开实施例提供的过孔结构，由于过孔的内壁面为凹凸不平 的表面，因此增大了第二导电层位于过孔内的部分与过孔的内壁面的粘结力，避免第二导电层位于过孔内的部分脱落，从而避免第二导电层和第一导电层出现搭接不良，提高第二导电层和第一导电层的搭接效果。
可选的，如图2所示，其示出了本公开实施例提供的另一种过孔结构的结构示意图，层间绝缘层20远离第一导电层10的一面为凹凸不平的表面。其中，过孔结构具有过孔区域和非过孔区域，过孔区域指的是层间绝缘层20的过孔201所在区域(也即是层间绝缘层20的过孔在过孔结构的对应区域)，非过孔区域指的是过孔结构中除该过孔区域之外的区域，层间绝缘层20远离第一导电层10的一面为凹凸不平的表面指的是：层间绝缘层20上位于该非过孔区域中的部分远离第一导电层10的表面为凹凸不平的表面。这样，由于在过孔结构的非过孔区域中，层间绝缘层20远离第一导电层10的表面为凹凸不平的表面，因此增大了过孔结构的非过孔区域中，层间绝缘层20和第二导电层30的粘结力，提高了层间绝缘膜层20和第二导电层30的搭接效果。
可选的，上述过孔201的内壁面201a和层间绝缘层20远离第一导电层10的一面均可以具有凹凸不平的微结构(图1和图2中未示出，该微结构例如微型凹槽等)，以使该过孔201的内壁面201a和层间绝缘层20远离第一导电层10的一面均为凹凸不平的表面，也即是，使过孔201的内壁面201a和层间绝缘层20远离第一导电层10的一面均具有一定粗糙度。可选的，该层间绝缘层20远离第一导电层10的一面和过孔的内壁面的粗糙度的取值范围均为0.05d≤r≤0.15d，r表示粗糙度，d表示层间绝缘层20的厚度，示例的，r＝0.05d或者r＝0.1d或者r＝0.15d。
可选的，上述第一导电层10和第二导电层30中的至少一个导电层的材料可以是金属，上述层间绝缘层20的材料可以是氮化硅、氧化硅或氮氧化硅等，且上述层间绝缘层20可以是一个绝缘膜层，可以是由多个绝缘膜层叠加形成的绝缘层，本公开实施例对此不做限定。
值得说明的是，图1和图2提供的结构仅为举例，在其他实现方式中，也可以仅层间绝缘层20远离第一导电层10的一面为凹凸不平的表面。另外，除了过孔201的内壁面201a整面或者层间绝缘层20远离第一导电层10的整面为凹凸不平的表面外，也可以仅过孔201的内壁面201a的部分或者层间绝缘层20远离第一导电层10的表面的部分为凹凸不平的表面。
需要说明的是，本公开实施例提供的过孔结构可以是包括两个导电层以及 位于该两个导电层之间的绝缘层，两个导电层通过绝缘层上的过孔搭接的任意过孔结构，在不同的产品中，该过孔结构中的两个导电层的体现形式不同。例如，在显示屏中，公共电极与公共电极线之间设置有绝缘层，绝缘层上具有过孔，公共电极通过该过孔与公共电极线搭接，因此公共电极、公共电极线以及该绝缘层构成过孔结构。又例如，在显示基板中，像素电极与薄膜晶体管(Thin Film Transistor，TFT)的漏极之间设置有绝缘层，绝缘层上具有过孔，像素电极通过该过孔与薄膜晶体管的漏极搭接，因此像素电极、薄膜晶体管的漏极和绝缘层构成过孔结构。再例如，在触控屏中，触控感应走线和触控感应电极之间设置有绝缘层，绝缘层上具有过孔，触控感应走线通过该过孔与触控感应电极搭接，因此触控感应走线、触控感应电极和绝缘层构成过孔结构。还例如，在触控面板中，横向金属条和纵向金属条之间设置有绝缘层，绝缘层上具有过孔，横向金属条通过过孔和纵向金属条搭接，因此横向金属条、纵向金属条和绝缘层构成过孔结构。还例如，在基板电路中，两条传输线之间设置有绝缘层，绝缘层上具有过孔，两条传输线通过该过孔搭接，因此两条传输线与绝缘层构成过孔结构。需要指出的是，本文所列举的过孔结构仅仅是示例性的，并不用以限制本公开实施例的方案，本领域技术人员应当明白，任何两个导电层通过该两个导电层之间的绝缘层上的过孔搭接的结构，都属于本公开实施例所涵盖的范围，在此不再一一赘述。
综上所述，本公开实施例提供的过孔结构，由于过孔的内壁面为凹凸不平的表面，因此增大了第二导电层位于过孔内的部分与过孔的内壁面的粘结力，避免第二导电层位于过孔内的部分的脱落，从而避免第二导电层和第一导电层出现搭接不良，提高第二导电层和第一导电层的搭接效果。本公开实施例提供的方案无需通过改变刻蚀参数来修正过孔的坡度角，易于实现且对层间绝缘层的成膜的均匀性的要求较低。
本公开实施例提供的过孔结构可以应用于下文的方法，本公开实施例的过孔结构的制造方法和过孔结构的制造原理可以参见下文各实施例中的描述。
请参考图3，其示出了本公开实施例提供的一种过孔结构的制造方法的方法流程图，该过孔结构的制造方法可以制造如图1所示的过孔结构，该过孔结构的制造方法包括如下步骤：
步骤101、在衬底基板上依次形成第一导电层、初始绝缘层和掩膜图形层， 掩膜图形层具有开口区域。
如图4所示，其示出了本公开实施例提供的一种在衬底基板40上依次形成第一导电层10、初始绝缘层20a和掩膜图形层50后的示意图，该掩膜图形层50具有开口区域501，掩膜图形层50可以为光刻(photoresist，PR)胶图形层。示例的，在衬底基板40上依次形成第一导电层10、初始绝缘层20a和掩膜图形层50可以包括如下三个步骤：
步骤(1)、通过沉积、涂覆或者溅射等方式在衬底基板40上形成导电材料层，然后通过一次构图工艺对该导电材料层进行处理得到第一导电层10。
步骤(2)、通过沉积、涂覆或者溅射等方式在形成有第一导电层10的衬底基板40上形成初始绝缘层20a。
步骤(3)、通过沉积、涂覆或者溅射等方式在形成有初始绝缘层20a的衬底基板40上形成PR材料层，对PR材料层依次进行曝光和显影得到掩膜图形层50。
步骤102、在初始绝缘层上与开口区域对应的区域形成过孔，得到层间绝缘层。
如图5所示，其示出了本公开实施例提供的一种在初始绝缘层20a上与掩膜图形层50的开口区域501对应的区域形成过孔后的示意图。示例的，结合图4和图5，可以通过干法刻蚀工艺对初始绝缘层20a上与掩膜图形层50的开口区501对应的区域进行刻蚀，以在初始绝缘层20a上与该开口区域501对应的区域形成过孔，从而得到层间绝缘层20。
步骤103、对过孔的内壁面进行粗糙化处理。
如图6所示，其示出了本公开实施例提供的一种对过孔的内壁面进行粗糙化处理后的示意图。示例的，可以采用预设的等离子体轰击过孔(图6中未标出)的内壁面，以对过孔的内壁面进行粗糙化处理。例如，可以将图5所示的结构设置在等离子刻蚀机中，并向该等离子刻蚀机中通入等离子体，以通过等离子体对过孔的内壁面进轰击，达到对该过孔的内壁面进行粗糙化处理的目的。需要说明的是，根据图6容易理解，等离子体在对过孔的内壁面进行轰击时，也可以对掩膜图形层50远离层间绝缘层20的一面进行轰击。
其中，上述轰击为物理轰击，上述等离子体可以是惰性气体或者不与初始绝缘层反应的气体，例如，该等离子体包括氦气(He)、氩气(Ar)和氧气(O2)中的至少一种，氦气和氩气为惰性气体，氧气是不与初始绝缘层反应的气体。 等离子刻蚀机为电子技术领域中常见的设备，因此该步骤103可以在现有设备中进行，实现简单。在这种实现方式中，在进行粗糙化处理后还可以对整个膜层结构进行清洗，以去除等离子体与导电层反应在导电层表面产生的物质。
在其他实现方式中，等离子体可以是惰性气体或者既不与初始绝缘层反应也不与导电层反应的气体，这样该等离子体与导电层不会反应，避免了在导电层表面反应产生其他物质。
步骤104、剥离掩膜图形层。
如图7所示，其示出了本公开实施例提供的一种剥离掩膜图形层50后的示意图，层间绝缘层20上具有过孔201，过孔201的内壁面为凹凸不平的曲线。示例的，可以通过剥离工艺剥离掩膜图形层，该剥离工艺可以是灰化工艺、光刻胶剥离工艺等。
步骤105、在层间绝缘层远离第一导电层的一侧形成第二导电层，第二导电层通过过孔与第一导电层搭接。
如图8所示，其示出了本公开实施例提供的一种在层间绝缘层20远离第一导电层10的一侧形成第二导电层30后的示意图，其中，第一导电层10、层间绝缘层20和第二导电层30构成过孔结构。
可选的，可以采用物理气相沉积(Physical Vapor Deposition，PVD)工艺在层间绝缘层20远离第一导电层10的一侧沉积一层导电材料得到导电材料层，然后通过一次构图工艺对该导电材料层进行处理得到第二导电层30，结合图7，在采用PVD工艺在层间绝缘层20远离第一导电层10的一侧沉积导电材料的过程中，层间绝缘层20的过孔201内也会沉积导电材料，使得最终制成的第二导电层30位于过孔201内的部分与第一导电层10接触，从而第二导电层30通过过孔201与第一导电层10搭接。
本公开实施例中，在层间绝缘层上形成过孔后，对该过孔的内壁面进行了粗糙化处理，因此该过孔的内壁面较为粗糙，在进行第二导电层的沉积时，过孔内更容易沉积导电材料，避免第二导电层位于过孔的内的部分塌落，从而避免第二导电层出现断层现象，改善第一导电层与第二导电层的搭接不良。
综上所述，本公开实施例提供的过孔结构的制造方法，由于对过孔的内壁面进行粗糙化处理，因此增大了第二导电层位于过孔内的部分与过孔的内壁面的粘结力，避免第二导电层位于过孔内的部分的脱落，从而避免第二导电层和第一导电层出现搭接不良，提高第二导电层和第一导电层的搭接效果。本公开 实施例提供的方案无需通过改变刻蚀参数来修正过孔的坡度角，易于实现且对层间绝缘层的成膜的均匀性的要求较低。
请参考图9，其示出了本公开实施例提供的另一种过孔结构的制造方法的方法流程图，该过孔结构的制造方法可以制造如图2所示的过孔结构，该过孔结构的制造方法包括如下步骤：
步骤201、在衬底基板上依次形成第一导电层、初始绝缘层和掩膜图形层，掩膜图形层具有开口区域。
步骤202、在初始绝缘层上与开口区域对应的区域形成过孔，得到层间绝缘层。
该步骤201和步骤202的实现过程可以参考图3所示实施例的步骤101和步骤102，本公开实施例对此不再赘述。
步骤203、剥离掩膜图形层。
示例的，如图10所示，其示出了本公开实施例提供的一种剥离层间绝缘层上掩膜图形层的示意图。其中，该步骤203的实现过程可以参考图3所示实施例的步骤104，本公开实施例对此不再赘述。
步骤204、对过孔的内壁面和层间绝缘层远离第一导电层的一面进行粗糙化处理。
示例的，如图11所示，其示出了本公开实施例提供的一种对过孔201的内壁面和层间绝缘层20远离第一导电层10的一面进行粗糙化处理后的示意图。其中，该步骤204的实现过程可以参考图3所示实施例的步骤103，本公开实施例对此不再赘述。但是需要说明的是，在本实施例中，由于在步骤203中已经剥离位于层间绝缘层20上的掩膜图形层，因此，如图11所示，在采用等离子体轰击时，可以对过孔201的内壁面进行轰击，且可以对层间绝缘层20远离第一导电层10的一面进行轰击，使得过孔201的内壁面和层间绝缘层20远离第一导电层10的一面均为凹凸不平的表面。
步骤205、在层间绝缘层远离第一导电层的一侧形成第二导电层，第二导电层通过过孔与第一导电层搭接。
该步骤205的实现过程可以参考图3所示实施例的步骤105，本公开实施例对此不再赘述。但是需要说明的是，由于在步骤204中对过孔的内壁面和层间绝缘层20远离该第一导电层10的一面均进行了粗糙化处理，因此过孔的内壁 面和层间绝缘层20远离该第一导电层10的一面均为凹凸不平的表面，可以增大第二导电层与过孔201的内壁面的粘结力以及第二导电层与层间绝缘层20的粘结力，避免第二导电层脱落，改善第二导电层与第一导电层的搭接效果。
综上所述，本公开实施例提供的过孔结构的制造方法，由于对过孔的内壁面和层间绝缘层远离第一导电层的一面均进行粗糙化处理，因此增大了第二导电层位于过孔内的部分与过孔内壁面的粘结力，以及第二导电层与层间绝缘层的粘结力，避免了该第二导电层的脱落，从而避免了第二导电层和第一导电层出现搭接不良，提高了该第二导电层和第一导电层的搭接效果。本公开实施例提供的方案无需通过改变刻蚀参数来修正过孔的坡度角，易于实现且对层间绝缘层的成膜的均匀性的要求较低。
需要说明的是，本公开实施例提供的过孔结构的制造方法中，所涉及的一次构图工艺包括光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离，通过一次构图工艺对材质层进行处理得到相应的结构(例如对导电材料层进行处理得到第一导电层)可以包括：在材质层(例如导电材料层)上涂覆一层光刻胶形成光刻胶层，采用掩膜版对光刻胶层进行曝光，使得光刻胶层形成完全曝光区和非曝光区，之后采用显影工艺处理，使完全曝光区的光刻胶被完全去除，非曝光区的光刻胶全部保留，采用刻蚀工艺对材质层(例如导电材料层)上完全曝光区对应的区域进行刻蚀，最后剥离非曝光区的光刻胶得到相应的结构(例如第一导电层)。这里是以光刻胶为正性光刻胶为例进行说明的，当光刻胶为负性光刻胶时，一次构图工艺的过程可以参考本段的描述，本公开实施例在此不再赘述。
还需要说明的是，本公开实施例提供的过孔结构的制造方法步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本公开的保护范围之内，因此不再赘述。
本公开实施例还提供了一种电子器件，该电子器件包括：图1或图2所示的过孔结构。
本公开实施例还提供了一种显示装置，该显示装置包括：电子器件，该电子器件包括图1或图2所示的过孔结构。该显示装置可以为触控屏、薄膜晶体 管液晶显示器(Liquid Crystal Display，TFT-LCD)、有机发光二极管(Organic Light-Emitting Diode，OLED)显示器、手机、平板电脑、电视机、笔记本电脑、数码相框或导航仪产品或部件。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (16)

  1. 一种过孔结构，其中，所述过孔结构包括：
    依次设置的第一导电层(10)、层间绝缘层(20)和第二导电层(30)，所述层间绝缘层(20)具有过孔(201)，所述第二导电层(30)通过所述过孔(201)与所述第一导电层(10)搭接，所述层间绝缘层(20)与所述第二导电层(30)接触的至少部分表面为凹凸不平的表面。
  2. 根据权利要求1所述的过孔结构，所述过孔(201)的内壁面(201a)为凹凸不平的表面。
  3. 根据权利要求1或2所述的过孔结构，所述层间绝缘层(20)远离所述第一导电层(10)的一面为凹凸不平的表面。
  4. 根据权利要求1至3任一项所述的过孔结构，
    所述凹凸不平的表面的粗糙度的取值范围为0.05d≤r≤0.15d，所述r表示所述粗糙度，所述d表示所述层间绝缘层(20)的厚度。
  5. 根据权利要求4所述的过孔结构，r＝0.05d或者r＝0.1d或者r＝0.15d。
  6. 根据权利要求1至5任一项所述的过孔结构，所述第一导电层(10)和所述第二导电层(30)中的至少一个导电层的材料为金属。
  7. 根据权利要求1至5任一项所述的过孔结构，所述第一导电层(10)包括公共电极线，所述第二导电层(30)包括公共电极；或者，
    所述第一导电层(10)包括薄膜晶体管的漏极，所述第二导电层(30)包括像素电极；或者，
    所述第一导电层(10)包括触控感应走线，所述第二导电层(30)包括触控感应电极；或者，
    所述第一导电层(10)包括横向金属条，所述第二导电层(30)包括纵向金属条。
  8. 一种过孔结构的制造方法，其中，所述方法包括：
    依次形成第一导电层和初始绝缘层；
    在所述初始绝缘层上形成过孔，得到层间绝缘层；
    在所述层间绝缘层上形成第二导电层，所述第二导电层通过所述过孔与所述第一导电层搭接，所述层间绝缘层与所述第二导电层接触的至少部分表面为凹凸不平的表面。
  9. 根据权利要求8所述的方法，所述在所述初始绝缘层上形成过孔，得到层间绝缘层，包括：
    在所述初始绝缘层上形成掩膜图形层，所述掩膜图形层具有开口区域；
    在所述初始绝缘层上与所述开口区域对应的区域形成过孔，得到层间绝缘层；
    对所述层间绝缘层与所述第二导电层接触的至少部分表面进行粗糙化处理。
  10. 根据权利要求9所述的方法，所述对所述层间绝缘层与所述第二导电层接触的至少部分表面进行粗糙化处理，包括：
    在所述掩膜图形层覆盖的情况下对所述过孔的内壁面进行粗糙化处理；
    剥离所述掩膜图形层。
  11. 根据权利要求9所述的方法，所述对所述层间绝缘层与所述第二导电层接触的至少部分表面进行粗糙化处理，包括：
    剥离所述掩膜图形层；
    对所述过孔的内壁面和所述层间绝缘层远离所述第一导电层的一面进行粗糙化处理。
  12. 根据权利要求9至11任一所述的方法，所述对所述层间绝缘层与所述第二导电层接触的至少部分表面进行粗糙化处理，包括：
    采用等离子体轰击所述层间绝缘层与所述第二导电层接触的至少部分表 面，以对所述层间绝缘层与所述第二导电层接触的至少部分表面进行粗糙化处理。
  13. 根据权利要求12所述的方法，所述等离子体包括惰性气体和不与所述初始绝缘层反应的气体中的至少一种。
  14. 根据权利要求13所述的方法，所述等离子体包括氦气、氩气和氧气中的至少一种。
  15. 一种电子器件，其中，所述电子器件包括：权利要求1至7任一所述的过孔结构。
  16. 一种显示装置，其中，所述显示装置包括：权利要求15所述的电子器件。
PCT/CN2019/125656 2019-01-31 2019-12-16 过孔结构及其制造方法、电子器件、显示装置 WO2020155893A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/771,261 US11335625B2 (en) 2019-01-31 2019-12-16 Via hole structure, manufacturing method thereof, electronic device, and display device
US17/729,695 US20220254838A1 (en) 2019-01-31 2022-04-26 Oled display panel and oled display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910098927.6 2019-01-31
CN201910098927.6A CN109801874A (zh) 2019-01-31 2019-01-31 过孔结构及其制造方法、电子器件、显示装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US16/771,261 A-371-Of-International US11335625B2 (en) 2019-01-31 2019-12-16 Via hole structure, manufacturing method thereof, electronic device, and display device
US17/729,695 Continuation-In-Part US20220254838A1 (en) 2019-01-31 2022-04-26 Oled display panel and oled display device

Publications (1)

Publication Number Publication Date
WO2020155893A1 true WO2020155893A1 (zh) 2020-08-06

Family

ID=66560747

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/125656 WO2020155893A1 (zh) 2019-01-31 2019-12-16 过孔结构及其制造方法、电子器件、显示装置

Country Status (3)

Country Link
US (1) US11335625B2 (zh)
CN (1) CN109801874A (zh)
WO (1) WO2020155893A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109801874A (zh) * 2019-01-31 2019-05-24 绵阳京东方光电科技有限公司 过孔结构及其制造方法、电子器件、显示装置
US10818625B1 (en) * 2019-06-19 2020-10-27 Nanya Technology Corporation Electronic device
CN112752994B (zh) * 2019-08-30 2022-08-02 京东方科技集团股份有限公司 背板、背光源、显示装置及背板的制造方法
CN112259500B (zh) * 2020-10-21 2024-01-30 京东方科技集团股份有限公司 一种显示面板及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200834869A (en) * 2007-02-07 2008-08-16 Shinko Electric Ind Co Method of manufacturing semiconductor device
CN102573280A (zh) * 2010-12-16 2012-07-11 日本特殊陶业株式会社 多层布线基板及制造多层布线基板的方法
US20140292159A1 (en) * 2013-03-29 2014-10-02 NGK Ceramic Device Ltd. Piezoelectric/electrostrictive element and method for manufacturing the same
CN107887361A (zh) * 2016-09-30 2018-04-06 三星电机株式会社 扇出型半导体封装件
CN109003944A (zh) * 2018-07-27 2018-12-14 京东方科技集团股份有限公司 一种基板的制作方法及基板、显示装置
CN109801874A (zh) * 2019-01-31 2019-05-24 绵阳京东方光电科技有限公司 过孔结构及其制造方法、电子器件、显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3395621B2 (ja) * 1997-02-03 2003-04-14 イビデン株式会社 プリント配線板及びその製造方法
CN105975136B (zh) * 2016-06-30 2019-03-26 京东方科技集团股份有限公司 显示基板及其制造方法和显示装置
TWI601279B (zh) * 2016-08-22 2017-10-01 群創光電股份有限公司 發光二極體觸控顯示裝置
JP2018170363A (ja) * 2017-03-29 2018-11-01 東芝メモリ株式会社 半導体装置の製造方法及び半導体装置
CN107193144A (zh) * 2017-04-26 2017-09-22 武汉华星光电技术有限公司 Ltps阵列基板及其制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200834869A (en) * 2007-02-07 2008-08-16 Shinko Electric Ind Co Method of manufacturing semiconductor device
CN102573280A (zh) * 2010-12-16 2012-07-11 日本特殊陶业株式会社 多层布线基板及制造多层布线基板的方法
US20140292159A1 (en) * 2013-03-29 2014-10-02 NGK Ceramic Device Ltd. Piezoelectric/electrostrictive element and method for manufacturing the same
CN107887361A (zh) * 2016-09-30 2018-04-06 三星电机株式会社 扇出型半导体封装件
CN109003944A (zh) * 2018-07-27 2018-12-14 京东方科技集团股份有限公司 一种基板的制作方法及基板、显示装置
CN109801874A (zh) * 2019-01-31 2019-05-24 绵阳京东方光电科技有限公司 过孔结构及其制造方法、电子器件、显示装置

Also Published As

Publication number Publication date
US11335625B2 (en) 2022-05-17
CN109801874A (zh) 2019-05-24
US20210225738A1 (en) 2021-07-22

Similar Documents

Publication Publication Date Title
WO2020155893A1 (zh) 过孔结构及其制造方法、电子器件、显示装置
US9543338B2 (en) Array substrate, method for manufacturing the same, and display device
US20210048851A1 (en) Flexible display substrate, method for manufacturing the same and flexible display device
US11537016B2 (en) Method of manufacturing array substrate, and array substrate
US20170110587A1 (en) Array substrate and manufacturing method thereof, display panel, display device
CN106653774B (zh) 阵列基板及其制造方法、掩膜版、显示装置
WO2016119324A1 (zh) 阵列基板及其制作方法、显示装置
JP2014527288A (ja) アレイ基板、及びその製造方法、液晶パネル、ディスプレー
US10381382B2 (en) Array substrate, method for manufacturing the same and display device
US9666727B2 (en) Display device
US10504943B2 (en) Method for manufacturing an array substrate motherboard
WO2019114357A1 (zh) 阵列基板及其制造方法、显示装置
US10204802B2 (en) Method of forming via hole, array substrate and method of forming the same and display device
CN108269736B (zh) 通过光阻剥离实现电极层图案化的方法
US10921662B2 (en) Manufacturing method of array substrate, array substrate, display panel and display device
WO2015062265A1 (zh) 像素结构、阵列基板、显示装置及像素结构的制造方法
US10879278B2 (en) Display substrate, manufacturing method therefor, and display device
US6329300B1 (en) Method for manufacturing conductive pattern layer by two-step wet etching process
US10134769B2 (en) Array substrate, method for manufacturing thereof, and display device
WO2015024337A1 (zh) 阵列基板及其制作方法和显示装置
WO2016026207A1 (zh) 阵列基板及其制作方法和显示装置
WO2019218822A1 (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
CN107170679B (zh) 一种导电图形的制作方法、导电图形及显示基板
US20170012065A1 (en) Array substrate, a method for manufacturing the same, and display device
WO2020147575A1 (zh) 薄膜晶体管的制备方法及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19913859

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19913859

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 19913859

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 21/01/2022)

122 Ep: pct application non-entry in european phase

Ref document number: 19913859

Country of ref document: EP

Kind code of ref document: A1