WO2015188732A1 - 动态随机存取存储器dram的刷新方法、设备以及系统 - Google Patents

动态随机存取存储器dram的刷新方法、设备以及系统 Download PDF

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Publication number
WO2015188732A1
WO2015188732A1 PCT/CN2015/080989 CN2015080989W WO2015188732A1 WO 2015188732 A1 WO2015188732 A1 WO 2015188732A1 CN 2015080989 W CN2015080989 W CN 2015080989W WO 2015188732 A1 WO2015188732 A1 WO 2015188732A1
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Prior art keywords
refresh
unit
dram
information
address
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PCT/CN2015/080989
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English (en)
French (fr)
Inventor
崔泽汉
陈明宇
黄永兵
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华为技术有限公司
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Priority to KR1020167033881A priority Critical patent/KR20160148700A/ko
Priority to EP15805953.5A priority patent/EP3142120B1/en
Priority to SG11201609766RA priority patent/SG11201609766RA/en
Priority to KR1020187036935A priority patent/KR102048762B1/ko
Priority to JP2016572231A priority patent/JP6429258B2/ja
Priority to RU2016151308A priority patent/RU2665883C2/ru
Priority to MX2016016024A priority patent/MX357812B/es
Priority to CA2949282A priority patent/CA2949282C/en
Publication of WO2015188732A1 publication Critical patent/WO2015188732A1/zh
Priority to US15/373,888 priority patent/US10007599B2/en

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Definitions

  • the present invention relates to the field of computers, and in particular, to a method, device and system for refreshing a dynamic random access memory DRAM.
  • DRAM Dynamic Random Access Memory
  • the DRAM is composed of a plurality of banks, each of which is a two-dimensional storage array, horizontally referred to as a row (Row) and vertically as a column (Column).
  • a row which becomes a memory row
  • all the data of the row is extracted into the sense amplifier (also called Row Buffer).
  • This process is called activation operation ( Active)
  • the corresponding data is read and written in the line buffer
  • the data in the line buffer is rewritten into the storage array, called pre-charge operation, which is realized by the activation operation and the pre-charge operation.
  • pre-charge operation which is realized by the activation operation and the pre-charge operation.
  • the entire refresh process. DRAM refresh brings a large overhead to the computer system. Because it cannot respond to the normal memory access request during the refresh process, it brings certain performance overhead. At the same time, the refresh operation is a very power-consuming operation, which will bring A certain amount of energy consumption.
  • the existing refresh method is to refresh all the rows of the DRAM with a uniform cycle to ensure The unit with the most severe leakage does not lose data.
  • the method, device, and system for refreshing the dynamic random access memory DRAM provided by the embodiments of the present invention are implemented to effectively reduce the overhead in the process of refreshing.
  • a first aspect of the embodiments of the present invention provides a method for processing DRAM refresh information of a dynamic random access memory, where the method includes:
  • the refresh unit is a storage space included in the DRAM for one refresh, and the refresh information of the refresh unit includes a refresh period of the refresh unit;
  • the refresh data space is a preset storage space in the DRAM.
  • the method before the address of the refresh unit and the refresh information of the refresh unit are written into the refresh data space by using the DRAM access request, the method further includes: The preset storage space is allocated in the DRAM as the refresh data space.
  • the address of the acquired refresh unit includes a physical address of the refresh unit
  • Decapsulating the address of the refresh unit and the refresh information of the refresh unit into a DRAM access request, and writing, by the DRAM access request, an address of the refresh unit and refresh information of the refresh unit to the Refresh the data space including:
  • the address of the acquired refresh unit includes a virtual address of the refresh unit; Before the address and the refresh information of the refresh unit are encapsulated into a DRAM access request, the method further includes:
  • Decapsulating the address of the refresh unit and the refresh information of the refresh unit into a DRAM access request, and writing, by the DRAM access request, an address of the refresh unit and refresh information of the refresh unit to the Refresh the data space including:
  • the physical address of the refresh unit and the refresh information of the refresh unit are encapsulated into a DRAM access request, and the physical address of the refresh unit and the refresh information are written into the refresh data space by the DRAM access request.
  • a second aspect of the embodiments of the present invention provides a processing apparatus for DRAM refresh information of a dynamic random access memory, where the apparatus includes:
  • An obtaining unit configured to acquire an address of a refresh unit in the DRAM and refresh information of the refresh unit, where the refresh unit is a storage space included in the DRAM for one refresh, and the refresh information of the refresh unit includes the refresh Unit refresh cycle;
  • a packaging unit configured to seal an address of the refresh unit and refresh information of the refresh unit Installed as a DRAM access request
  • a writing unit configured to write, by the DRAM access request, an address of the refresh unit and refresh information of the refresh unit into a refresh data space, where the refresh data space is a preset storage in the DRAM space.
  • the apparatus further includes: an allocating unit, configured to allocate the preset storage space in the DRAM as the refresh data space.
  • the address of the refresh unit acquired by the acquiring unit includes a physical address of the refresh unit
  • the encapsulating unit is specifically configured to encapsulate the physical address of the refresh unit and the refresh information of the refresh unit into a DRAM access request;
  • the writing unit is specifically configured to write the physical address of the refresh unit and the refresh information into the refresh data space by using the DRAM access request.
  • the address of the refresh unit acquired by the acquiring unit includes a virtual address of the refresh unit;
  • the device also includes:
  • a conversion processing unit configured to translate a virtual address of the refresh unit into a physical address of the refresh unit by querying a page table
  • the encapsulating unit is specifically configured to encapsulate the physical address of the refresh unit and the refresh information of the refresh unit into the DRAM access request;
  • the writing unit is specifically configured to write the physical address of the refresh unit and the refresh information into the refresh data space by using the DRAM access request.
  • a third aspect of the embodiments of the present invention provides a processing apparatus for DRAM refresh information of a dynamic random access memory, wherein the processing apparatus includes:
  • processor a processor, a memory, a communication interface, and a bus, wherein the processor, the memory, and the communication interface communicate via the bus;
  • the memory is used to store a program
  • the communication interface is for communicating with a DRAM
  • the processor when the processing device is in operation, executes the program stored by the memory to perform the method of any of the first aspect and the various possible implementations of the first aspect.
  • a fourth aspect of the embodiments of the present invention provides a method for refreshing a dynamic random access memory (DRAM) DRAM, the method comprising:
  • the refresh command including a physical address of the refresh unit, and the refresh unit is a storage space included in the DRAM for one refresh;
  • the refresh information of the refresh unit is read from the refresh data space by using a DRAM read command according to the physical address of the refresh unit, and the refresh information of the refresh unit includes a refresh period of the refresh unit;
  • the reading, by the DRAM read command, the refresh information corresponding to the refreshing unit from the refresh data space, according to the physical address of the refreshing unit includes:
  • a read command reads refresh information of the refresh unit from the refresh data space.
  • the refresh data space is preset in the DRAM to store multiple refreshes in the DRAM
  • the storage space of the refresh information of the unit further includes:
  • the method further includes:
  • a fifth aspect of the embodiments of the present invention provides a DRAM controller, where the DRAM controller includes:
  • a refresh command generating module configured to generate a refresh command for the refresh unit in the DRAM, the refresh command includes a physical address of the refresh unit, and the refresh unit is a storage space included in the DRAM for performing one refresh;
  • An obtaining module configured to acquire refresh information of the refresh unit from a refresh data space by using a DRAM read command according to a physical address of the refresh unit, where the refresh information of the refresh unit includes a refresh period of the refresh unit;
  • an execution module configured to perform a refresh operation on the refresh unit according to the refresh information.
  • the acquiring module includes:
  • a query unit configured to determine refresh information of the refresh unit according to a physical address of the refresh unit, and a correspondence between a physical address of the refresh unit and a refresh information of the refresh unit stored in the refresh data space ;
  • a reading unit configured to read refresh information of the refresh unit from the refresh data space by using the DRAM read command.
  • the acquiring module is further configured to acquire, after the refreshing the data space, the refreshing unit Refresh information of consecutive refresh units.
  • the executing module includes:
  • a receiving unit configured to receive a refresh command for a plurality of consecutive refresh units after the refresh unit
  • a determining unit configured to determine whether the number of refreshing units that need to perform a refresh operation in the plurality of consecutive refreshing units exceeds a threshold
  • An execution unit configured to perform an Auto Refresh refresh operation on the plurality of consecutive refresh units when determining that the number of refresh units that need to perform a refresh operation exceeds the threshold; and when determining that the refresh operation needs to be performed When the number of units does not exceed the threshold, a RAS-only Refresh operation is performed on the plurality of consecutive refresh units.
  • a sixth aspect of the embodiments of the present invention provides a refresh system for a dynamic random access memory DRAM, the system comprising: a dynamic random access memory DRAM including at least one refresh unit, and the fifth aspect and various possible implementations thereof The DRAM controller of any of the modes.
  • Embodiments of the present invention provide a method, a device, and a system for refreshing a dynamic random access memory (DRAM), by acquiring refresh information of a DRAM refresh unit, the refresh information including a refresh period of the refresh unit, and writing the refresh information to the DRAM.
  • a preset storage space that is, refreshing the data space, in the process of the DRAM controller performing the DRAM refresh unit refresh, reading the refresh information for the refresh unit from the refresh data space by using the DRAM read command, and using the The information is refreshed and the refresh operation of the corresponding refresh unit is performed.
  • FIG. 1 is a system architecture diagram supported by an embodiment of the present invention.
  • FIG. 2A is a flowchart of a first implementation manner of Embodiment 1 of the method of the present invention.
  • FIG. 2B is a flowchart of a second implementation manner of Embodiment 1 of the method of the present invention.
  • 2C is a flow chart of a first implementation of step 230 of the first embodiment of the method of the present invention.
  • 2D is a flow chart of a second implementation of step 230 of the first embodiment of the method of the present invention.
  • 3A is a flow chart of a second embodiment of the method of the present invention.
  • FIG. 3B is a flowchart of an implementation manner of step 330 of Embodiment 2 of the method of the present invention.
  • 3C is a flow chart showing an implementation of an additional step of the second embodiment of the method of the present invention.
  • Fig. 4 is a structural diagram of a first embodiment of the apparatus of the present invention.
  • Figure 5 is a structural diagram of a second embodiment of the apparatus of the present invention.
  • Fig. 6A is a structural diagram of a second embodiment of the apparatus of the present invention.
  • FIG. 6B is a structural diagram of an implementation manner of an acquisition module in Embodiment 2 of the device of the present invention.
  • FIG. 6C is a structural diagram of an implementation manner of an execution module in Embodiment 2 of the device of the present invention.
  • Figure 7 is a networking diagram of a system embodiment of the present invention.
  • DRAM devices DRAM devices
  • the claimed invention can be implemented to support any memory that requires multiple refreshes or other means of maintaining its contents at regular intervals to retain its contents.
  • Device type DRAM devices
  • the memory cells can be organized in a variety of ways, including being organized into multiple banks and performing Or not interleaved, organized into two-dimensional arrays, organized into content-addressable, and so on.
  • the claimed invention can be implemented in conjunction with other electronic devices or systems having memory devices.
  • FIG. 1 is a schematic diagram of networking of a memory refresh system provided by an embodiment of the present invention.
  • the memory refresh system includes a processor 100, a memory controller 200, and a memory chip 300.
  • the processor 100 implements reading and writing of data in the memory chip 300 through the memory controller 200.
  • the processor 100 and the memory controller 200 may be integrated in the same chip or implemented by two different chips.
  • a storage space is preset in the memory chip 300 as the refresh data space 310, and the refresh data space may be a continuous area or a plurality of discrete areas. Operating system in the application These memory regions cannot be used when allocating memory in sequence.
  • the memory chip 300 is generally implemented by using a DRAM chip.
  • the memory controller 200 can be implemented by a DRAM controller.
  • the refresh method widely used in the industry is to refresh all the rows in the memory in a uniform cycle to ensure that the cells with the most severe leakage will not lose data.
  • AR (Auto Refresh) mode maintain a counter RAC in the memory chip, pointing to the next line to be refreshed.
  • the memory controller sends a refresh command every tREFI time. After the memory chip receives the command, all banks in the bank point to a set of rows (the number is determined by the density of the memory chip) and the refresh operation is performed at the same time. The duration of the refresh operation is tRFC, during this time, the memory chip cannot respond to normal memory access requests. After the tRFC time, the memory chip updates the value of the counter to point to the next set of rows to be refreshed.
  • ROR (RAS-Only Refresh) mode The memory controller sends a row strobe (RAS, Row Address Strobe) command to take a row of data in the memory into the line buffer, and then the row data will be pre-fetched. The charging command is rewritten back to the storage unit to complete the refresh of one row of data.
  • the memory controller internally maintains the counter RAC and periodically sends RAS commands. In this refresh mode, only one row is refreshed at a time, and when the row is refreshed, other banks can still be accessed.
  • the granularity of the refresh is relatively large, and the average refresh overhead per row is small, but when some rows in the memory store invalid data (that is, the invalid data does not need to be refreshed) or the non-critical data is stored (the Non-critical data does not require a higher frequency for refreshing.
  • the above AR method has a larger overhead; the ROR mode refresh has a smaller granularity, and which row is refreshed by the memory controller allows the memory controller to be flexibly controlled, but The average refresh overhead per line is large.
  • Each row of data in the above memory to be refreshed constitutes a refresh unit.
  • the refresh unit may be a memory row, a plurality of memory rows, or may be smaller than the memory row.
  • the granularity of the present invention is not limited in this regard to all embodiments of the present invention.
  • Data criticality ⁇ is used to measure the keyness of the data stored in a refresh unit. According to the level of data criticality, the key value range of the data stored in the refresh unit is 0 ⁇ 1.
  • the criticality of the data can be set by the operating system, or set by the user, and the operating system is notified.
  • the data retention time T 0 (ie, the preset refresh period) is 64 milliseconds
  • the data validity ⁇ is 1
  • the data criticality ⁇ is 0.5
  • the refresh cycle of the unit is 64*2 (milliseconds).
  • refresh information of different data critical refresh units can be represented by Table 1.
  • the storage format of the refresh information of one refresh unit can be expressed by 4 bits. It should be noted that the use of several bits to represent the refresh information is based on the user's custom settings. The more the number of bits, the more selective the refresh period can be represented. For those skilled in the art, the choice is made. How many bits are used to indicate refresh information according to specific refresh requirements, and all embodiments of the present invention are not limited thereto. Table 1 below is for illustrative purposes only.
  • the refresh information indicated by 4bit actually contains the refresh period corresponding to the refresh unit.
  • the embodiment provides a method for processing DRAM refresh information of a dynamic random access memory.
  • the process is as follows:
  • the execution body of the method embodiment may be an operating system.
  • the address of a refresh unit may be the physical address of the refresh unit or the virtual address of the refresh unit.
  • Acquisition of refresh information There are various acquisition methods in the prior art, such as: software can be tested by data retention time, page allocation/release monitoring, or determined by user tags; in hardware, data can be passed. The test of the hold time, the history of the most recently accessed data, and the like are determined. In this regard, embodiments of the invention are not described herein.
  • the method before acquiring the refresh information of a refresh unit of the DRAM, the method further includes: converting the data retention time, data validity, data criticality, and the like of the refresh unit to the refresh information of the refresh unit .
  • the specific conversion process please refer to the relevant texts in Table 1 above.
  • the information included in the refresh information of the refresh unit is the refresh period of the refresh unit.
  • the refresh data space is a preset storage space in the DRAM.
  • the operating system can write the address of the refresh unit and the refresh information into the refresh data space through an existing DRAM access request.
  • the method further includes:
  • step 210 may be performed first, then step 220 may be performed, or step 220 may be performed first, and then step 210 is performed.
  • step 210 may be performed first, then step 220 may be performed, or step 220 may be performed first, and then step 210 is performed.
  • embodiments of the invention are not limited.
  • allocating a storage space in the DRAM as the refresh data space can be implemented as follows:
  • the operating system requests an area from the memory space for storing refresh information, and notifies the memory controller of the address range of the area.
  • BIOS Basic Input/Output System
  • the memory controller reserves an area from the memory space for storing refresh information, and notifies the operating system of the address range of the area.
  • the refresh data space may be a continuous area or a plurality of discrete areas.
  • the operating system cannot use these memory regions when the application allocates memory.
  • the correspondence between the physical address of the refresh unit and the refresh information of the refresh unit is established in the refresh data space.
  • the structure of the refresh data space is as shown in Table 2. It can be understood that the correspondence between the physical address of the refresh unit and the refresh information of the refresh unit in the form of a table is only an implementation manner, and an embodiment of the present invention Other implementations are not excluded):
  • Manner 1 The implementation process of the steps 231-232, the address of the acquired refresh unit includes the physical address of the refresh unit. Referring to FIG. 2C, the specific process of step 230 is:
  • the operating system when the operating system obtains the physical address of the refresh unit and the refresh information of the refresh unit, the operating system may write the physical address of the refresh unit and the refresh information of the refresh unit to the refresh data space.
  • Manner 2 The implementation process of the step 233-235 is performed.
  • the address of the acquired refresh unit includes the virtual address of the refresh unit.
  • the specific process of step 230 is:
  • the refresh information of a refresh unit and the virtual address of the refresh unit are acquired by the user mode program, and the user mode program refreshes the virtual address of the unit.
  • the refresh information of the refresh unit is sent to the operating system, and the operating system obtains the physical address of the refresh unit by querying the page table according to the virtual address of the refresh unit, and writes the physical address and the refresh information of the refresh unit to Refresh the data space.
  • the above provides an embodiment of a method for processing dynamic random access memory DRAM refresh information, enabling writing of refresh information into a pre-allocated refresh data space of a DRAM by using an existing DRAM access request, so that the method can satisfy DRAM storage.
  • the capacity is not increased, resulting in the need to refresh the information storage space, and the existing DRAM access request is used to realize the storage of refresh information, and the implementation scheme is simple and easy.
  • the embodiment provides a method for refreshing a dynamic random access memory (DRAM).
  • the method is implemented by the memory controller as a main body. The process is as follows:
  • the memory controller periodically generates a refresh command, where the refresh command includes a physical address of the unit to be refreshed.
  • the refresh information of the refresh unit is read from the refresh data space according to the physical address of the refresh unit, and the refresh information of the refresh unit includes a refresh period of the refresh unit.
  • the memory controller when the memory controller performs a refresh operation on the refresh unit according to the refresh information, in combination with Table 2, the memory controller performs different refresh operations for different refresh information:
  • the DRAM is used to read according to the pointer of the refresh unit.
  • the command reads the refresh information corresponding to the refresh unit from the refresh data space. Referring to FIG. 3B, the method includes:
  • the memory controller reads the refresh information of the refresh unit through the DRAM read command.
  • the refresh data space is a storage space preset for storing the refresh information of the plurality of refresh units in the DRAM in the DRAM, and the method further includes:
  • the method further includes:
  • the memory controller when the refresh operation is performed on the multiple consecutive refresh units by using the Auto Refresh method, the memory controller also sends a Silent refresh command to the DRAM, and the command is used to make the pair During the continuous refresh unit refresh process, the refresh unit storing the invalid data can be skipped, and the counter of the refresh address is incremented by 1 to ensure that the subsequent line to be refreshed is subsequently pointed.
  • the refreshing information of the refresh unit stored in the refresh data space can be refreshed according to the refresh information, thereby avoiding the performance overhead caused by the refreshing of the unified cycle in the prior art.
  • a problem that consumes a lot of money the refresh information of the refresh unit is directly read from the refresh data space by the existing memory access command, so that the refresh process is simple and easy.
  • the embodiment provides a processing apparatus for DRAM refresh information of a dynamic random access memory, and the apparatus 400 includes:
  • the obtaining unit 410 is configured to acquire an address of a refresh unit in the DRAM and refresh information of the refresh unit, where the refresh unit is a storage space included in the DRAM for one refresh, and the refresh information of the refresh unit includes the Refreshing the refresh cycle of the unit;
  • the encapsulating unit 420 is configured to encapsulate the address of the refresh unit and the refresh information of the refresh unit into a DRAM access request;
  • a writing unit 430 configured to write, by the DRAM access request, an address of the refresh unit and refresh information of the refresh unit into a refresh data space, where the refresh data space is a preset storage space in the DRAM .
  • the device 400 further includes:
  • the allocating unit 440 is configured to allocate the preset storage space in the DRAM as the refresh data space.
  • the address of the refresh unit acquired by the acquiring unit includes a physical address of the refresh unit
  • the encapsulating unit 420 is further configured to encapsulate the physical address of the refresh unit and the refresh information of the refresh unit into a DRAM access request;
  • the writing unit 430 is configured to write the physical address of the refresh unit and the refresh information into the refresh data space by using the DRAM access request.
  • the address of the refresh unit acquired by the acquiring unit includes a virtual address of the refresh unit; the device further includes:
  • the conversion processing unit 450 is configured to convert the virtual address of the refresh unit by querying a page table Is the physical address of the refresh unit;
  • the encapsulating unit 420 is specifically configured to encapsulate the physical address of the refresh unit and the refresh information of the refresh unit and the physical address of the refresh unit into a DRAM access request;
  • the writing unit 430 is specifically configured to write the physical address of the refresh unit and the refresh information into the refresh data space by using the DRAM access request.
  • the embodiment further provides a processing device for DRAM refresh information of a dynamic random access memory, and the processing device 500 includes:
  • processor 510 a processor 510, a memory 520, a communication interface 530, and a bus 540, wherein the processor 510, the memory 520, and the communication interface 530 communicate via the bus;
  • the memory 520 is configured to store a program
  • the communication interface 530 is configured to communicate with a DRAM
  • the processor 510 When the processing device 500 is running, the processor 510 is configured to execute the program stored by the memory 520 to perform the method described in any of the possible implementation manners of the method embodiment 1.
  • the embodiment provides a controller for a DRAM, and the controller 600 includes:
  • a refresh command generating module 610 configured to generate a refresh command for a refresh unit, where the refresh command includes a physical address of the refresh unit, and the refresh unit is a storage space included in the DRAM for one refresh;
  • the obtaining module 620 is configured to acquire the refresh information of the refresh unit from the refresh data space by using a DRAM read command according to the physical address of the refresh unit, where the refresh information of the refresh unit includes a refresh period of the refresh unit;
  • the executing module 630 is configured to perform a refresh operation on the refresh unit according to the refresh information.
  • the obtaining module 620 includes:
  • the query unit 621 is configured to determine, according to a physical address of the refresh unit, a correspondence between a physical address of the refresh unit and a refresh information of the refresh unit stored in the refresh data space, and a refresh of the refresh unit. information;
  • a reading unit 622 configured to read the refresh data space from the refresh data space by using a DRAM read command Refresh the refresh information of the unit.
  • the obtaining module 620 is further configured to acquire, from the refresh data space, refresh information of the plurality of consecutive refresh units after the refresh unit.
  • the execution module 630 includes:
  • the receiving unit 631 is configured to receive a refresh command for the plurality of consecutive refresh units after the refresh unit;
  • the determining unit 632 is configured to determine whether the number of refreshing units that need to perform a refresh operation in the plurality of consecutive refreshing units exceeds a threshold;
  • the executing unit 633 is configured to perform an Auto Refresh refresh operation on the plurality of consecutive refresh units when determining that the number of the refresh units that need to perform the refresh operation exceeds the threshold; when determining that the refresh operation needs to be performed When the number of refresh units does not exceed the threshold, a RAS-only Refresh operation is performed on the plurality of consecutive refresh units.
  • the Auto Refresh refresh mode needs to be refreshed in multiple consecutive refresh units to reduce the refresh overhead, and the efficiency is relatively high
  • the RAS-Only Refresh refresh mode is adapted to refresh characteristics of a refresh unit. If the number of refreshing units that perform the refresh operation exceeds the threshold of the number of refreshing units, the Auto Refresh mode or the RAS-Only Refresh mode is selected to perform refreshing, thereby improving the refreshing efficiency.
  • the embodiment provides a refresh system for a dynamic random access memory (DRAM) DRAM.
  • the system 700 includes a dynamic random access memory (DRAM) 710 including a plurality of refresh units, and a DRAM controller 720 of the third embodiment of the apparatus.
  • DRAM dynamic random access memory
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, or an electrical, mechanical or other form of connection.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present invention.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • the technical solution of the present invention contributes in essence or to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium.
  • a number of instructions are included to cause a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention.
  • the foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like. .

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Abstract

一种动态随机存取存储器DRAM的刷新方法、设备以及系统。获取DRAM的某一刷新单元的地址以及刷新单元的刷新信息，刷新单元为DRAM中进行一次刷新所包括的存储空间，刷新单元的刷新信息包括刷新单元的刷新周期；将刷新单元的地址以及刷新单元的刷新信息封装为DRAM访问请求，并通过DRAM访问请求将刷新单元的地址以及刷新单元的刷新信息写入到刷新数据空间（310），刷新数据空间（310）为所述DRAM中预设的，用来存储DRAM中至少一个刷新单元的地址以及所述至少一个刷新单元的刷新信息的存储空间。上述方案可根据刷新单元的刷新信息进行针对性的刷新，解决采用统一周期进行刷新所带来的性能开销以及能耗开销比较大的问题。

Description

动态随机存取存储器DRAM的刷新方法、设备以及系统
本申请要求于2014年6月9日提交中国专利局、申请号为201410253514.8、发明名称为“动态随机存取存储器DRAM的刷新方法、设备以及系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及计算机领域，尤其涉及一种动态随机存取存储器DRAM的刷新方法、设备以及系统。
背景技术
现有计算机系统普遍采用廉价的、高密度的DRAM(Dynamic Random Access Memory，动态随机存取存储器)作为系统主存，又叫做内存。DRAM利用电容里的电荷存储数据，但这些电荷会随着漏电的存在而不断流失。因此，电容里的数据必须被定期读出并重新写入，以补偿流失的电荷，这种操作叫做刷新(Refresh)。
DRAM有多个库(Bank)组成，每个Bank为二维的存储阵列，横向称为行(Row)，纵向称为列(Column)。在刷新的过程中，每次DRAM会选定一个行(又成为内存行)，把该行的全部数据提取到感应放大器中(又称为行缓冲区，Row Buffer)，这个过程叫做激活操作(Active)，接着在行缓冲区中完成对应数据的读写，行缓冲区中的数据被重新写入存储阵列，称为预充电操作(Pre-charge)，通过激活操作以及预充电操作就实现了整个刷新的过程。DRAM刷新给计算机系统带来较大的开销，由于在刷新的过程中不能响应正常的访存请求，带来了一定的性能开销，同时，刷新操作是一种很耗电的操作，会带来一定的能耗开销。
现有的刷新方法是对DRAM的所有的行采用统一的周期进行刷新，以保 证漏电最严重的单元不丢失数据。
在完成本发明的过程中，发现现有技术存在如下问题：随着DRAM容量的不断增大，采用统一的周期对DRAM的所有内存行进行刷新的方式，其性能开销以及能耗开销变得越来越大，从而严重影响到系统的能效。。
发明内容
基于此，本发明实施例所提供的动态随机存取存储器DRAM的刷新方法、设备以及系统，以实现在刷新的过程中，有效地降低开销。
本发明实施例第一方面提供了一种动态随机存取存储器DRAM刷新信息的处理方法，该方法包括：
获取DRAM中刷新单元的地址以及所述刷新单元的刷新信息，所述刷新单元为所述DRAM中进行一次刷新所包括的存储空间，所述刷新单元的刷新信息包括所述刷新单元的刷新周期；
将所述刷新单元的地址以及所述刷新单元的刷新信息封装为DRAM访问请求，并通过所述DRAM访问请求将所述刷新单元的地址以及所述刷新单元的刷新信息写入到刷新数据空间，所述刷新数据空间为所述DRAM中预设的存储空间。
结合第一方面，在第一种可能的实现方式中，在将所述刷新单元的地址以及所述刷新单元的刷新信息通过DRAM访问请求写入到刷新数据空间中之前，所述方法还包括：在所述DRAM中分配所述预设的存储空间作为所述刷新数据空间。
结合第一方面以及第一方面的第一种可能的实现方式，在第二种可能的实现方式中，所述获取的刷新单元的地址包括所述刷新单元的物理地址；
所述将所述刷新单元的地址以及所述刷新单元的刷新信息封装为DRAM访问请求，并通过所述DRAM访问请求将所述刷新单元的地址以及所述刷新单元的刷新信息写入到所述刷新数据空间，包括：
将所述刷新单元的物理地址以及所述刷新单元的刷新信息封装为DRAM访问请求，并通过所述DRAM访问请求将所述刷新单元的地址以及所述刷新信息写入所述刷新数据空间。
结合第一方面以及第一方面的第一种可能的实现方式，在第三种可能的实现方式中，所述获取的刷新单元的地址包括所述刷新单元的虚拟地址；在将所述刷新单元的地址以及所述刷新单元的刷新信息封装为DRAM访问请求之前，所述方法还包括：
通过查询页表，将所述刷新单元的虚拟地址转化为所述刷新单元的物理地址；
所述将所述刷新单元的地址以及所述刷新单元的刷新信息封装为DRAM访问请求，并通过所述DRAM访问请求将所述刷新单元的地址以及所述刷新单元的刷新信息写入到所述刷新数据空间，包括：
将所述刷新单元的物理地址以及所述刷新单元的刷新信息封装为DRAM访问请求，并通过所述DRAM访问请求将所述刷新单元的物理地址以及所述刷新信息写入所述刷新数据空间。
本发明实施例第二方面提供了一种动态随机存取存储器DRAM刷新信息的处理装置，该装置包括：
获取单元，用于获取DRAM中刷新单元的地址以及所述刷新单元的刷新信息，所述刷新单元为所述DRAM中进行一次刷新所包括的存储空间，所述刷新单元的刷新信息包括所述刷新单元的刷新周期；
封装单元，用于将所述刷新单元的地址以及所述刷新单元的刷新信息封 装为DRAM访问请求；
写入单元，用于通过所述DRAM访问请求将所述刷新单元的地址以及所述刷新单元的刷新信息写入到刷新数据空间中，所述刷新数据空间为所述DRAM中一块预设的存储空间。
结合第二方面，在第一种可能的实现方式中，所述装置还包括：分配单元，用于在所述DRAM中分配所述预设的存储空间作为所述刷新数据空间。
结合第二方面以及第二方面的第一种可能的实现方式，在第二种可能的实现方式中，所述获取单元获取的所述刷新单元的地址包括所述刷新单元的物理地址；
所述封装单元，具体用于将所述刷新单元的物理地址以及所述刷新单元的刷新信息封装为DRAM访问请求；
所述写入单元，具体用于通过所述DRAM访问请求将所述刷新单元的物理地址以及所述刷新信息写入所述刷新数据空间。
结合第二方面以及第二方面的第一种可能的实现方式，在第三种可能的实现方式中，所述获取单元获取的所述刷新单元的地址包括所述刷新单元的虚拟地址；所述装置还包括：
转化处理单元，用于通过查询页表，将所述刷新单元的虚拟地址转化为所述刷新单元的物理地址；
所述封装单元，具体用于将所述刷新单元的物理地址以及所述刷新单元的刷新信息封装为所述DRAM访问请求；
所述写入单元，具体用于通过所述DRAM访问请求将所述刷新单元的物理地址以及所述刷新信息写入所述刷新数据空间。
本发明实施例第三方面提供了一种动态随机存取存储器DRAM刷新信息的处理装置，其特征在于，所述处理装置包括：
处理器，存储器，通信接口，和总线，其中，所述处理器、所述存储器和所述通信接口通过所述总线通信；
所述存储器用于存放程序；
所述通信接口用于与DRAM通信；
当所述处理装置运行时，所述处理器用于执行所述存储器存储的所述程序，以执行第一方面以及第一方面的各个可能实现方式任一所述的方法。
本发明实施例第四方面提供了一种动态随机存取存储器DRAM的刷新方法，该方法包括：
产生针对DRAM中刷新单元的刷新命令，所述刷新命令包括所述刷新单元的物理地址，所述刷新单元为所述DRAM中进行一次刷新所包括的存储空间；
根据所述刷新单元的物理地址，采用DRAM读取命令从刷新数据空间中读取所述刷新单元的刷新信息，所述刷新单元的刷新信息包括所述刷新单元的刷新周期；
根据所述刷新信息执行对所述刷新单元的刷新操作。
结合第四方面，在第一种可能的实现方式中，所述根据所述刷新单元的物理地址，采用DRAM读取命令从刷新数据空间中读取对应所述刷新单元的刷新信息，包括：
根据所述刷新单元的物理地址，以及所述刷新数据空间中存储的所述刷新单元的物理地址和所述刷新单元的刷新信息的对应关系，确定所述刷新单元的刷新信息，采用所述DRAM读取命令从所述刷新数据空间读取所述刷新单元的刷新信息。
结合第四方面以及第四方面的第一种可能的实现方式，在第二种可能的实现方式中，所述刷新数据空间为所述DRAM中预设的用来存储所述DRAM中多个刷新单元的刷新信息的存储空间，所述方法还包括：
从所述刷新数据空间中获取所述刷新单元之后的多个连续的刷新单元的刷新信息。
结合第四方面的第二种可能的实现方式，在第三种可能的实现方式中，在从所述刷新数据空间中读取所述刷新单元之后的多个连续的刷新单元的刷新信息之后，所述方法还包括：
接收对所述刷新单元之后的多个连续的刷新单元的刷新命令；
判断所述多个连续的刷新单元中需要执行刷新操作的刷新单元的个数是否超过阈值；
当确定所述需要执行刷新操作的刷新单元的个数超过所述阈值时，对所述多个连续的刷新单元执行Auto Refresh刷新操作；
当确定所述需要执行刷新操作的刷新单元的个数不超过所述阈值时，对所述多个连续的刷新单元执行RAS-only Refresh刷新操作。
本发明实施例第五方面提供了一种DRAM控制器，该DRAM控制器包括：
刷新命令产生模块，用于产生针对DRAM中刷新单元的刷新命令，所述刷新命令包括所述刷新单元的物理地址，所述刷新单元为所述DRAM中进行一次刷新所包括的存储空间；
获取模块，用于根据所述刷新单元的物理地址，采用DRAM读取命令从刷新数据空间中获取所述刷新单元的刷新信息，所述刷新单元的刷新信息包括所述刷新单元的刷新周期；
执行模块，用于根据所述刷新信息执行对所述刷新单元的刷新操作。
结合第五方面，在第一种可能的实现方式中，上述获取模块包括：
查询单元，用于根据所述刷新单元的物理地址，以及所述刷新数据空间中存储的所述刷新单元的物理地址和所述刷新单元的刷新信息的对应关系，确定所述刷新单元的刷新信息；
读取单元，用于采用所述DRAM读取命令从所述刷新数据空间读取所述刷新单元的刷新信息。
结合第五方面以及第五方面的第一种可能的实现方式，在第二种可能的实现方式中，所述获取模块，还用于从所述刷新数据空间中获取所述刷新单元之后的多个连续的刷新单元的刷新信息。
结合第五方面的第二种可能的实现方式，在第三种可能的实现方式中，所述执行模块包括：
接收单元，用于接收对所述刷新单元之后的多个连续的刷新单元的刷新命令；
判断单元，用于判断所述多个连续的刷新单元中需要执行刷新操作的刷新单元的个数是否超过阈值；
执行单元，用于当确定所述需要执行刷新操作的刷新单元的个数超过所述阈值时，对所述多个连续的刷新单元执行Auto Refresh刷新操作；当确定所述需要执行刷新操作的刷新单元的个数不超过所述阈值时，对所述多个连续的刷新单元执行RAS-only Refresh刷新操作。
本发明实施例第六方面提供了一种动态随机存取存储器DRAM的刷新系统，该系统包括：包含至少一个刷新单元的动态随机存取存储器DRAM，以及如第五方面及其各种可能的实现方式中任一所述的DRAM控制器。
本发明实施例提供一种动态随机存取存储器DRAM的刷新方法、设备以及系统，通过获取DRAM刷新单元的刷新信息，该刷新信息包括该刷新单元的刷新周期，并将刷新信息写入到DRAM中一块预设的存储空间，即刷新数据空间，在DRAM控制器进行DRAM刷新单元刷新的过程中，通过DRAM读取命令从刷新数据空间中，读取出针对该刷新单元的刷新信息，并利用该刷新信息进行相应刷新单元的刷新操作。采用上述方式，面对DRAM容量不断增大的情况下，一方面，使得能够根据刷新单元的刷新信息进行针对性的刷新，避免了现有技术中采用统一的周期进行刷新所带来的性能开销以及能耗开销比较大的问题，另一方面，通过将刷新单元的刷新信息存储在DRAM空间中，能够满足在DRAM容量不断增大情况下，刷新信息的数据量增多带来的存储空间的要求。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例所依托的系统架构图。
图2A是本发明的方法实施例一的第一实现方式流程图。
图2B是本发明的方法实施例一的第二实现方式流程图。
图2C是本发明的方法实施例一的步骤230的第一实现方式的流程图。
图2D是本发明的方法实施例一的步骤230的第二实现方式的流程图。
图3A是本发明的方法实施例二的流程图。
图3B是本发明的方法实施例二的步骤330的实现方式的流程图。
图3C是本发明的方法实施例二的附加步骤实现方式的流程图。
图4是本发明的设备实施例一的结构图。
图5是本发明的设备实施例二的结构图。
图6A是本发明的设备实施例二的结构图。
图6B是本发明的设备实施例二中的获取模块实现方式的结构图。
图6C是本发明的设备实施例二中的执行模块的实现方式结构图。
图7是本发明的系统实施例的组网连接图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明的一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域的普通技术人员在没有做出创造性劳动的前提下所获得其他实施例，都应属于本发明保护的范围。
虽然以下描述集中于DRAM器件，但是本领域的技术人员将会理解，所要求保护的本发明可被实现来支持需要每隔一定时间刷新或者其他方式维护以保留其内容的多个单元的任何存储器器件类型。本领域的技术人员还会理解，虽然以下描述集中于存储单元按二维行列阵列来组织的存储器器件，但是存储单元可以用多种方式来组织，包括被组织成多个库(Bank)并且进行或不进行交织，被组织成二维以上的阵列，被组织成可内容寻址的，等等。另外，虽然以下讨论中至少有一部分集中于计算机系统内的存储器，但是本领域的技术人员将会理解，所要求保护的本发明可以结合具有存储器器件的其他电子设备或系统来实现。
本发明实施例的系统架构
图1描绘了本发明实施例所提供的内存刷新系统的组网示意图。该内存刷新系统包括：处理器100、内存控制器200，以及内存芯片300组成。其中，处理器100通过内存控制器200实现内存芯片300中数据的读写。处理器100和内存控制器200在具体实现时，可以集成在同一个芯片中，也可以通过两个不同的芯片分别实现。
在内存芯片300中预设一块存储空间作为刷新数据空间310，该刷新数据空间可以是一段连续的区域，也可以是多段分散的区域。操作系统在应用程 序分配内存时，不能使用这些内存区域。
其中，内存芯片300一般采用DRAM芯片来实现，当内存芯片300采用DRAM芯片来实现时，内存控制器200即可由DRAM控制器来实现。
本发明实施例
随着目前内存的存储容量越做越大，如何能够降低内存刷新的性能和功耗开销成为一个问题。
业界广泛采用的刷新方法是对内存中的所有的行采用统一的周期进行刷新，以保证漏电最严重的单元不会丢失数据。具体的刷新方式有如下两种：
(1)AR(Auto Refresh,自动刷新)方式：在内存芯片中维护一个计数器RAC，指向下一次要刷新的行。内存控制器每隔tREFI时间发送一个刷新命令，内存芯片收到该命令后，所有的Bank里RAC指向的一组行(数量由内存芯片的密度决定)同时执行刷新操作，刷新操作的持续时间为tRFC，在此期间内，内存芯片不能响应正常的访存请求。在tRFC时间后，内存芯片更新计数器的值，使其指向下一组要刷新的行。
(2)ROR(RAS-Only Refresh)方式：内存控制器发送行选通(RAS，Row Address Strobe)命令，将内存中的一行数据取到行缓冲区中，随后该行数据会被后续的预充电命令重新写回到存储单元，完成对一行数据的刷新。在这种情况下，内存控制器在内部维护计数器RAC，并且周期性的发送RAS命令。这种刷新方式下，每次只刷新一行，并且在该行被刷新时，其他Bank仍然可以被访问。
上述的AR方式，刷新的粒度比较大，每行平均的刷新开销较小，但是当内存中的一些行存储的是无效数据(即该无效数据不需要刷新)或者存储的是非关键性数据(该非关键性数据不需要较高的频率进行刷新)，上述AR方式的开销就比较大；ROR方式刷新的粒度较小，并且刷新哪一行由内存控制器指定，允许内存控制器灵活控制，但是其每行平均的刷新开销较大。
上述内存中待刷新的每行数据就构成了一个刷新单元(Refresh Unit)，在具体的实现中，刷新单元可以是一个内存行，也可以是多个内存行，还可以是比内存行更小的粒度，对此，本发明的所有实施例均不加以限定。
为了提升内存数据刷新的效率，降低刷新的开销，对于每个刷新单元， 可以通过如下三个参数去确定其刷新参数：
(1)数据保持时间：用T0来表示，即某一刷新单元的预设的刷新周期，例如：每64毫秒刷新一次，则该预设的刷新周期T0＝64ms。
(2)数据有效性：用μ来表示，衡量某一刷新单元中所存储数据的有效性，如果该刷新单元存储的数据有效数据，则μ＝1，如果存储的是无效数据，则μ＝0。数据有效性由操作系统来判断。
(3)数据关键性：用λ表示，衡量某一刷新单元中所存储数据的关键性，按照数据关键性的等级，刷新单元所存储数据的数据关键性取值范围为0＜λ≤1。数据的关键性可以有操作系统来设定，或者由用户来设定，并通知操作系统。
某一个刷新单元的刷新周期和上述三个参数存在如下的关系：刷新周期＝预订的刷新周期*数据有效性/数据关键性，通过符号来表示为：刷新周期T＝T0*μ/λ(适用于μ≠0的情形)。需要说明的是，当某刷新单元的刷新数据为无效数据时，此时，该刷新单元的刷新周期为无穷大，即不会对该刷新单元进行刷新。
举例说明：对于存储有数据关键性为1的有效数据的刷新单元，则该刷新单元的刷新周期＝T0*1/1＝T；对于存储有非关键性的有效数据的刷新单元，可以根据操作系统对数据关键性的设定来确定数据关键性λ(其中，0＜λ≤1)，由系统选择预定的刷新周期和调整因子的乘积，即T0*(1/λ)进行刷新。
作为举例，对于某一刷新单元，其数据保持时间T0(即预设的刷新周期)为64毫秒，数据有效性μ为1，数据关键性λ为0.5，则根据上述计算公式，确定该刷新单元的刷新周期为64*2(毫秒)。
作为举例，采用一种信息的存储格式，可以将不同数据关键性的刷新单元的刷新信息通过表一来表示。在下表中，一个刷新单元的刷新信息的存储格式可通过4bit来表示。需要说明的是，采用几个bit来表示刷新信息是基于用户的自定义设置，bit数目越多，可表示的刷新周期的选择性就会越多，对于本领域的普通技术人员来说，选择多少个bit来表示刷新信息根据具体的刷新需求，对此，本发明的所有实施例不加以限制。下面的表一仅作为举例来说明。
从下面的表一可以看出，通过4bit所表示该刷新信息其实包含的就是该刷新单元对应的刷新周期。
Figure PCTCN2015080989-appb-000001
表一
方法实施例一
参看图2A，本实施例提供了一种动态随机存取存储器DRAM刷新信息的处理方法，其过程为：
210、获取DRAM中刷新单元的地址以及所述刷新单元的刷新信息，该刷新单元为所述DRAM中进行一次刷新所包括的存储空间，上述刷新单元的刷新信息包括该刷新单元的刷新周期；
具体的，该方法实施例的执行主体可以是操作系统。
某一刷新单元的地址可以为该刷新单元的物理地址，或该刷新单元的虚拟地址。
刷新信息的获取在现有技术中存在多种获取方式，譬如：在软件上可以通过数据保持时间的测试，页面分配/释放的监控，或者通过用户的标记来确定；在硬件上，可以通过数据保持时间的测试、数据最近被访问的历史记录等来进行确定。对此，本发明的实施例不加以赘述。
具体的，在获取DRAM的某一刷新单元的刷新信息之前，还包括：将针对某一刷新单元的数据保持时间、数据有效性、数据关键性等参数，转化为该刷新单元的刷新信息的步骤。具体的转化过程可以参考上述表一相关的文字介绍。
上述刷新单元的刷新信息中，所包含的信息是该刷新单元的刷新周期。
230、将所述刷新单元的地址以及所述刷新单元的刷新信息封装为DRAM访问请求，并通过所述DRAM访问请求将所述刷新单元的地址以及所述刷新单元的刷新信息写入到刷新数据空间，所述刷新数据空间为所述DRAM中预设的存储空间。
具体的，操作系统可以通过现有的DRAM访问请求将刷新单元的地址以及刷新信息写入到刷新数据空间中。
进一步的，在步骤230将所述刷新单元的地址以及所述刷新单元的刷新信息通过DRAM访问请求写入到刷新数据空间中之前，参看图2B，所述方法还包括：
220、在上述DRAM中分配前述预设的存储空间作为所述刷新数据空间。
需要说明的是，步骤220和步骤210之间并没有严格意义上的顺序关系，在具体实现过程中，可以先执行步骤210，然后执行步骤220，也可以先执行步骤220，然后执行步骤210，对此，本发明的实施例不加以限定。
上述步骤220中在上述DRAM中分配一块存储空间作为所述刷新数据空间，可以通过如下的方式实现：
(1)操作系统从内存空间中申请一个区域用于存储刷新信息，并把该区域的地址范围通知内存控制器。
(2)BIOS(Basic Input/Output System，即基本输入输出系统)从内存空间中预留一个区域用于存储刷新信息，并把这个区域的地址范围通知操作系统和内存控制器。
(3)内存控制器从内存空间中预留一个区域用于存储刷新信息，并把该区域的地址范围通知操作系统。
该刷新数据空间可以是一段连续的区域，也可以是多段分散的区域。操作系统在应用程序分配内存时，不能使用这些内存区域。
需要说明的是，通过将刷新单元的地址以及刷新单元的刷新信息写入到刷新数据空间中，这样，在刷新数据空间中就建立刷新单元的物理地址和该刷新单元的刷新信息的对应关系。作为举例，该刷新数据空间的结构如表二所示(可以理解，采用表的形式来存储刷新单元的物理地址和该刷新单元的刷新信息的对应关系只是一种实现方式，本发明的实施例不排除其他的实现方式)：
Figure PCTCN2015080989-appb-000002
表二
进一步的，根据具体实现过程的不同，在执行步骤230的过程中存在两种实现方式：
方式一：包括步骤231-232的实现过程，所述获取的刷新单元的地址包括所述刷新单元的物理地址，参看图2C，步骤230的具体过程是：
231、将所述刷新单元的物理地址以及所述刷新单元的刷新信息封装为DRAM访问请求；
232、通过所述DRAM访问请求将刷新单元的物理地址以及刷新信息写刷新数据空间。
具体的，上述实现过程中，当操作系统获得刷新单元的物理地址以及该刷新单元的刷新信息时，则操作系统可将刷新单元的物理地址以及刷新单元的刷新信息写入到刷新数据空间。
方式二：包括步骤233-235的实现过程，所述获取的刷新单元的地址包括所述刷新单元的虚拟地址，参看图2D，步骤230的具体过程是：
233、通过查询页表，将所述刷新单元的虚拟地址转化为所述刷新单元的物理地址；
234、将所述刷新单元的物理地址以及所述刷新单元的刷新信息封装为DRAM访问请求；
235、通过所述DRAM访问请求将所述刷新单元的物理地址以及所述刷新信息写入所述刷新数据空间。
具体的，上述实现过程中，某一刷新单元的刷新信息以及该刷新单元的虚拟地址是通过用户态程序获取的，此时用户态程序将刷新单元的虚拟地址以 及刷新单元的刷新信息发送给操作系统，由操作系统根据刷新单元的虚拟地址通过查询页表(Page Table)，获得该刷新单元的物理地址，将该刷新单元的物理地址以及刷新信息写入到刷新数据空间。
上述提供一种动态随机存取存储器DRAM刷新信息的处理方法的实施例，使得能够利用现有的DRAM访问请求将刷新信息写入到DRAM预先分配的刷新数据空间中，使得该方法能够满足DRAM存储容量不算增大从而导致刷新信息存储空间不断扩大的需求，且利用现有的DRAM访问请求实现刷新信息的存储，实现方案简单易行。
方法实施例二
参看图3A，本实施例提供了一种动态随机存取存储器DRAM的刷新方法，该方法实施例是内存控制器作为主体执行的，其过程为：
310、产生针对DRAM中刷新单元的刷新命令，所述刷新命令包括指向所述刷新单元的物理地址，所述刷新单元为所述DRAM中进行一次刷新所包括的存储空间；
具体的，内存控制器周期性的产生刷新命令，该刷新命令中包含待刷新单元的物理地址。
330、根据所述刷新单元的物理地址，从刷新数据空间中读取所述刷新单元的刷新信息，所述刷新单元的刷新信息包括所述刷新单元的刷新周期；
350、根据所述刷新信息执行对所述刷新单元的刷新操作。
具体的，在内存控制器根据刷新信息执行对刷新单元的刷新操作时，结合表二，针对不同的刷新信息，内存控制器执行不同的刷新操作：
(1)当内存控制器所读取的刷新信息中数据有效性标识为0，则表明该刷新信息所对应的刷新单元存储的数据是无效数据，则内存控制器丢弃该刷新命令。
(2)当内存控制器所读取的刷新信息中数据有效性标识为1，且刷新周期标识为abc时(其中，a、b、c的取值均为1或0)，则根据表二、以及表一的内容，确定该刷新单元的刷新周期，并按照刷新周期进行该刷新单元的刷新。
进一步的，上述步骤330中根据所述刷新单元的指针，采用DRAM读取 命令从刷新数据空间中读取对应所述刷新单元的刷新信息，参看图3B，包括：
331、根据所述刷新单元的物理地址，查询所述刷新数据空间中存储的所述刷新单元的物理地址和所述刷新单元的刷新信息的对应关系，确定所述刷新单元的刷新信息；
332、采用DRAM读取命令从所述刷新数据空间读取所述刷新单元的刷新信息。
根据刷新单元的物理地址，从刷新单元的物理地址和刷新单元的刷新信息的对应关系中，内存控制器通过DRAM读取命令读取刷新单元的刷新信息。
进一步的，所述刷新数据空间为所述DRAM中预设的用来存储所述DRAM中多个刷新单元的刷新信息的存储空间，所述方法还包括：
340、从所述刷新数据空间中获取所述刷新单元之后的多个连续的刷新单元的刷新信息。
需要说明的是，由于DRAM数据的读写的粒度比较大，一般是64字节，而根据上面的实施例，一个刷新单元的刷新信息的存储采用4个比特表示，因此，DRAM一次性读取128个刷新单元的刷新信息。
进一步的，在从所述刷新数据空间中读取所述刷新单元之后的多个刷新单元的刷新信息之后，参看图3C，所述方法还包括：
341、接收对所述刷新单元之后的多个连续的刷新单元的刷新命令；
342、判断所述多个连续的刷新单元中需要执行刷新操作的刷新单元的个数是否超过阈值；
343、当确定所述需要执行刷新操作的刷新单元的个数超过所述阈值时，对所述多个连续的刷新单元执行Auto Refresh刷新操作；
344、当确定所述需要执行刷新操作的刷新单元的个数不超过所述阈值时，对所述多个连续的刷新单元执行RAS-only Refresh刷新操作。
在具体实现的过程中，当采用Auto Refresh方式对所述多个连续的刷新单元进行刷新操作时，内存控制器还会向DRAM发送Silent refresh(沉默刷新)命令，通过该命令，使得在对多个连续的刷新单元刷新的过程中，能够跳过存储有无效数据的刷新单元，并且对刷新地址的计数器加1，以保证后续指向接下来要刷新的行。
需要说明的是，采用Auto Refresh以及采用RAS-Only Refresh为本领域 普通技术人员的公知常识，具体执行过程不再赘述。
上述的实施例，通过访问刷新数据空间中所存储的刷新单元的刷新信息，能够根据刷新信息进行针对性的刷新，避免了现有技术中采用统一的周期进行刷新所带来的性能开销以及能耗开销比较大的问题。同时，通过现有的访存命令直接从刷新数据空间中读取刷新单元的刷新信息，使得刷新过程简单易行。
设备实施例一
参看图4，本实施例提供一种动态随机存取存储器DRAM刷新信息的处理装置，该装置400包括：
获取单元410，用于获取DRAM中刷新单元的地址以及所述刷新单元的刷新信息，所述刷新单元为所述DRAM中进行一次刷新所包括的存储空间，所述刷新单元的刷新信息包括所述刷新单元的刷新周期；
封装单元420，用于将所述刷新单元的地址以及所述刷新单元的刷新信息封装为DRAM访问请求；
写入单元430，用于通过所述DRAM访问请求将所述刷新单元的地址以及所述刷新单元的刷新信息写入刷新数据空间，所述刷新数据空间为所述DRAM中一块预设的存储空间。
进一步的，所述装置400还包括：
分配单元440，用于在所述DRAM中分配所述预设的存储空间作为所述刷新数据空间。
进一步的，所述获取单元获取的所述刷新单元的地址包括所述刷新单元的物理地址；
所述封装单元420，还用于将所述刷新单元的物理地址以及所述刷新单元的刷新信息封装为DRAM访问请求；
所述写入单元430，用于通过所述DRAM访问请求将所述刷新单元的物理地址以及所述刷新信息写入所述刷新数据空间。
进一步的，所述获取单元获取的所述刷新单元的地址包括所述刷新单元的虚拟地址；所述装置还包括：
转化处理单元450，用于通过查询页表，将所述刷新单元的虚拟地址转化 为所述刷新单元的物理地址；
所述封装单元420，具体用于将所述刷新单元的物理地址以及所述刷新单元的刷新信息以及所述刷新单元的物理地址封装为DRAM访问请求；
所述写入单元430，具体用于通过所述DRAM访问请求将所述刷新单元的物理地址以及所述刷新信息写入所述刷新数据空间。
设备实施例二
参看图5，本实施例还提供一种动态随机存取存储器DRAM刷新信息的处理装置，该处理装置500包括：
处理器510，存储器520，通信接口530，和总线540，其中，所述处理器510、所述存储器520和所述通信接口530通过所述总线通信；
所述存储器520用于存放程序；
所述通信接口530用于与DRAM通信；
当所述处理装置500运行时，所述处理器510用于执行所述存储器520存储的所述程序，以执行方法实施例一的任一可能实现方式所述的方法。
设备实施例三
参看图6A，本实施例提供一种DRAM的控制器，该控制器600包括：
刷新命令产生模块610，用于产生针对某一刷新单元的刷新命令，所述刷新命令包括所述刷新单元的物理地址，所述刷新单元为所述DRAM中进行一次刷新所包括的存储空间；
获取模块620，用于根据所述刷新单元的物理地址，采用DRAM读取命令从刷新数据空间中获取所述刷新单元的刷新信息，所述刷新单元的刷新信息包括所述刷新单元的刷新周期；
执行模块630，用于根据所述刷新信息执行对所述刷新单元的刷新操作。
进一步的，参看图6B，所述获取模块620包括：
查询单元621，用于根据所述刷新单元的物理地址，以及所述刷新数据空间中存储的所述刷新单元的物理地址和所述刷新单元的刷新信息的对应关系，确定所述刷新单元的刷新信息；
读取单元622，用于采用DRAM读取命令从所述刷新数据空间读取所述 刷新单元的刷新信息。
进一步的，所述获取模块620，还用于从所述刷新数据空间中获取所述刷新单元之后的多个连续的刷新单元的刷新信息。
进一步的，参看图6C，所述执行模块630包括：
接收单元631，用于接收对所述刷新单元之后的多个连续的刷新单元的刷新命令；
判断单元632，用于判断所述多个连续的刷新单元中需要执行刷新操作的刷新单元的个数是否超过阈值；
执行单元633，用于当确定所述需要执行刷新操作的刷新单元的个数超过所述阈值时，对所述多个连续的刷新单元执行Auto Refresh刷新操作；当确定所述需要执行刷新操作的刷新单元的个数不超过所述阈值时，对所述多个连续的刷新单元执行RAS-only Refresh刷新操作。
采用上述的实现方式，考虑到Auto Refresh刷新方式在多个连续的刷新单元均需要刷新能够降低刷新开销，效率比较高的特点，以及RAS-Only Refresh刷新方式适应于针对某一刷新单元刷新的特点，根据实际需要执行刷新操作的刷新单元的数目是否超过刷新单元的数量的阈值，分别选择Auto Refresh方式或者RAS-Only Refresh方式进行刷新，从而提升了刷新的效率。
系统实施例
参看图7，本实施例提供一种动态随机存取存储器DRAM的刷新系统，该系统700包括：包含多个刷新单元的动态随机存取存储器DRAM 710，以及设备实施例三的DRAM控制器720。
在本发明所提供的几个实施例中，应该理解的是，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本发明实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以权利要求的保护范围为准。

Claims (18)

  1. 一种动态随机存取存储器DRAM刷新信息的处理方法，其特征在于，
    获取DRAM中刷新单元的地址以及所述刷新单元的刷新信息，所述刷新单元为所述DRAM中进行一次刷新所包括的存储空间，所述刷新单元的刷新信息包括所述刷新单元的刷新周期；
    将所述刷新单元的地址以及所述刷新单元的刷新信息封装为DRAM访问请求，并通过所述DRAM访问请求将所述刷新单元的地址以及所述刷新单元的刷新信息写入到刷新数据空间，所述刷新数据空间为所述DRAM中预设的存储空间。
  2. 根据权利要求1所述的方法，其特征在于，在通过所述DRAM访问请求将所述刷新单元的地址以及所述刷新单元的刷新信息写入到刷新数据空间之前，所述方法还包括：
    在所述DRAM中分配所述预设的存储空间作为所述刷新数据空间。
  3. 根据权利要求1或2所述的方法，其特征在于，所述获取的刷新单元的地址包括所述刷新单元的物理地址；
    所述将所述刷新单元的地址以及所述刷新单元的刷新信息封装为DRAM访问请求，并通过所述DRAM访问请求将所述刷新单元的地址以及述刷新单元的刷新信息写入到所述刷新数据空间，包括：
    将所述刷新单元的物理地址以及所述刷新单元的刷新信息封装为DRAM访问请求，并通过所述DRAM访问请求将所述刷新单元的物理地址以及所述刷新信息写入所述刷新数据空间。
  4. 根据权利要求1或2所述的方法，其特征在于，所述获取的刷新单元的地址包括所述刷新单元的虚拟地址；
    在将所述刷新单元的地址以及所述刷新单元的刷新信息封装为DRAM访问请求之前，所述方法还包括：
    通过查询页表，将所述刷新单元的虚拟地址转化为所述刷新单元的物理地址；
    所述将所述刷新单元的地址以及所述刷新单元的刷新信息封装为DRAM访问请求，并通过所述DRAM访问请求将所述刷新单元的地址以及所述刷新单元的刷新信息写入到所述刷新数据空间，包括：
    将所述刷新单元的物理地址以及所述刷新单元的刷新信息封装为DRAM访问请求，并通过所述DRAM访问请求将所述刷新信息写入所述刷新数据空间。
  5. 一种动态随机存取存储器DRAM刷新信息的处理装置，其特征在于，所述装置包括：
    获取单元，用于获取DRAM中刷新单元的地址以及所述刷新单元的刷新信息，所述刷新单元为所述DRAM中进行一次刷新所包括的存储空间，所述刷新单元的刷新信息包括所述刷新单元的刷新周期；
    封装单元，用于将所述刷新单元的地址以及所述刷新单元的刷新信息封装为DRAM访问请求；
    写入单元，用于通过所述DRAM访问请求将所述刷新单元的地址以及所述刷新单元的刷新信息写入刷新数据空间，所述刷新数据空间为所述DRAM中预设的存储空间。
  6. 根据权利要求5所述的装置，其特征在于，所述装置还包括：
    分配单元，用于在所述DRAM中分配所述预设的存储空间作为所述刷新数据空间。
  7. 根据权利要求5或6所述的装置，其特征在于，所述获取单元获取的所述刷新单元的地址包括所述刷新单元的物理地址；
    所述封装单元，具体用于将所述刷新单元的物理地址以及所述刷新单元的刷新信息封装为DRAM访问请求；
    所述写入单元，具体用于通过所述DRAM访问请求将所述刷新单元的物理 地址以及所述刷新信息写入所述刷新数据空间。
  8. 根据权利要求5或6所述的装置，其特征在于，
    所述获取单元获取的所述刷新单元的地址包括所述刷新单元的虚拟地址；
    所述装置还包括：转化处理单元，用于通过查询页表，将所述刷新单元的虚拟地址转化为所述刷新单元的物理地址；
    所述封装单元，具体用于将所述刷新单元的物理地址以及所述刷新单元的刷新信息封装为所述DRAM访问请求；
    所述写入单元，具体用于通过所述DRAM访问请求将所述刷新单元的物理地址以及所述刷新信息写入所述刷新数据空间。
  9. 一种动态随机存取存储器DRAM刷新信息的处理装置，其特征在于，所述处理装置包括：
    处理器，存储器，通信接口，和总线，其中，所述处理器、所述存储器和所述通信接口通过所述总线通信；
    所述存储器用于存放程序；
    所述通信接口用于与DRAM通信；
    当所述处理装置运行时，所述处理器用于执行所述存储器存储的所述程序，以执行所述权利要求1-4任一所述的方法。
  10. 一种动态随机存取存储器DRAM的刷新方法，其特征在于，
    产生针对DRAM中刷新单元的刷新命令，所述刷新命令包括所述刷新单元的物理地址，所述刷新单元为所述DRAM中进行一次刷新所包括的存储空间；
    根据所述刷新单元的物理地址，采用DRAM读取命令从刷新数据空间中读取所述刷新单元的刷新信息，所述刷新单元的刷新信息包括所述刷新单元的刷新周期；
    根据所述刷新信息执行对所述刷新单元的刷新操作。
  11. 根据权利要求10所述的方法，其特征在于，所述根据所述刷新单元的物理地址，采用DRAM读取命令从刷新数据空间中读取所述刷新单元的刷新信息，包括：
    根据所述刷新单元的物理地址，以及所述刷新数据空间中存储的所述刷新单元的物理地址和所述刷新单元的刷新信息的对应关系，确定所述刷新单元的刷新信息，采用所述DRAM读取命令从所述刷新数据空间读取所述刷新单元的刷新信息。
  12. 根据权利要求10或11所述的方法，其特征在于，所述刷新数据空间为所述DRAM中预设的用来存储所述DRAM中多个刷新单元的刷新信息的存储空间，所述方法还包括：
    从所述刷新数据空间中获取所述刷新单元之后的多个连续的刷新单元的刷新信息。
  13. 根据权利要求12所述的方法，其特征在于，在从所述刷新数据空间中读取所述刷新单元之后的多个连续的刷新单元的刷新信息之后，所述方法还包括：
    接收对所述刷新单元之后的所述多个连续的刷新单元的刷新命令；
    判断所述多个连续的刷新单元中需要执行刷新操作的刷新单元的个数是否超过阈值；
    当确定所述需要执行刷新操作的刷新单元的个数超过所述阈值时，对所述多个连续的刷新单元执行Auto Refresh刷新操作；
    当确定所述需要执行刷新操作的刷新单元的个数不超过所述阈值时，对所述多个连续的刷新单元执行RAS-only Refresh刷新操作。
  14. 一种DRAM控制器，其特征在于，所述控制器包括：
    刷新命令产生模块，用于产生针对DRAM中刷新单元的刷新命令，所述刷新命令包括所述刷新单元的物理地址，所述刷新单元为所述DRAM中进行一次 刷新所包括的存储空间；
    获取模块，用于根据所述刷新单元的物理地址，采用DRAM读取命令从刷新数据空间中获取所述刷新单元的刷新信息，所述刷新单元的刷新信息包括所述刷新单元的刷新周期；
    执行模块，用于根据所述刷新信息执行对所述刷新单元的刷新操作。
  15. 根据权利要求14所述的控制器，所述获取模块包括：
    查询单元，用于根据所述刷新单元的物理地址，以及所述刷新数据空间中存储的所述刷新单元的物理地址和所述刷新单元的刷新信息的对应关系，确定所述刷新单元的刷新信息；
    读取单元，用于采用所述DRAM读取命令从所述刷新数据空间读取所述刷新单元的刷新信息。
  16. 根据权利要求14或15所述的控制器，其特征在于，所述获取模块，还用于从所述刷新数据空间中获取所述刷新单元之后的多个连续的刷新单元的刷新信息。
  17. 根据权利要求16所述的控制器，其特征在于，所述执行模块包括：
    接收单元，用于接收对所述刷新单元之后的所述多个连续的刷新单元的刷新命令；
    判断单元，用于判断所述多个连续的刷新单元中需要执行刷新操作的刷新单元的个数是否超过阈值；
    执行单元，用于当确定所述需要执行刷新操作的刷新单元的个数超过所述阈值时，对所述多个连续的刷新单元执行Auto Refresh刷新操作；当确定所述需要执行刷新操作的刷新单元的个数不超过所述阈值时，对所述多个连续的刷新单元执行RAS-only Refresh刷新操作。
  18. 一种动态随机存取存储器DRAM的刷新系统，其特征在于，所述系统 包括：包含至少一个刷新单元的动态随机存取存储器DRAM，以及如权利要求14-17任一所述的DRAM控制器。
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