WO2015168927A1 - 阵列面板及其制作方法 - Google Patents

阵列面板及其制作方法 Download PDF

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Publication number
WO2015168927A1
WO2015168927A1 PCT/CN2014/077124 CN2014077124W WO2015168927A1 WO 2015168927 A1 WO2015168927 A1 WO 2015168927A1 CN 2014077124 W CN2014077124 W CN 2014077124W WO 2015168927 A1 WO2015168927 A1 WO 2015168927A1
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WIPO (PCT)
Prior art keywords
pixel electrode
film layer
color film
array panel
groove
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Ceased
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PCT/CN2014/077124
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English (en)
French (fr)
Inventor
徐向阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/379,734 priority Critical patent/US9263483B2/en
Publication of WO2015168927A1 publication Critical patent/WO2015168927A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/805—Coatings
    • H10F39/8053—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array panel and a method of fabricating the same.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display, thin film transistor liquid crystal display panel
  • CF Color Filter
  • TFT Thin Film
  • the array of transistors, thin film transistors are respectively formed on different substrates, wherein the TFT array substrate comprises: a thin film transistor, a peripheral line and a pixel electrode, and the color filter substrate comprises: a common electrode, an R/G/B color film, and a PS (Position). Spacer, spacer) and BM (Black Matrix, black matrix layer). Since the CF and TFT arrays are respectively fabricated on different glass substrates, process production time can be saved.
  • the thin film transistor and the pixel electrode or the extension portion thereof in the TFT array substrate have overlapping portions, so that the thin film transistor and the pixel electrode form a capacitance, which may affect the display of the pixel unit because the existence of the capacitor may be This can cause the voltage input to the pixel electrode to fail to reach the desired value, thereby degrading the display quality.
  • An array panel comprising: a substrate; at least one scan line; at least one data line; and a pixel array, the pixel array comprising at least one pixel unit, wherein the pixel unit comprises: a thin film transistor a pixel electrode; and a color film layer disposed between the first plane and the second plane, wherein the first plane is a plane where a gate of the thin film transistor is located, and the second plane is the a plane in which the pixel electrode is located; wherein the scan line, the data line, and the pixel array are both disposed on the substrate; the color film layer is disposed on the first area and the second area; The region and the second region are respectively a region corresponding to the pixel electrode and the thin film transistor on the substrate; the surface of the color film layer is provided with at least one groove, and the shape and shape of the groove Corresponding to the shape of the pixel electrode, the pixel electrode is clamped in the groove.
  • the thin film transistor further includes a source and a drain, and the color film layer covers the source and the drain.
  • the color filter layer is provided with a through hole, and the through hole is provided with a connection line, and the connection line connects the pixel electrode and the drain.
  • the pixel electrode is obtained by disposing a transparent conductive material on the surface of the color film layer and in the groove, and then removing the transparent conductive material on the surface. of.
  • the bottom surface or the side surface of the groove is provided with a recess or a protrusion.
  • An array panel comprising: a substrate; at least one scan line; at least one data line; and a pixel array, the pixel array comprising at least one pixel unit, wherein the pixel unit comprises: a thin film transistor a pixel electrode; and a color film layer disposed between the first plane and the second plane, wherein the first plane is a plane where a gate of the thin film transistor is located, and the second plane is the a plane in which the pixel electrode is located; wherein the scan line, the data line, and the pixel array are both disposed on the substrate.
  • the color film layer is disposed on the first region and the second region; wherein the first region and the second region are respectively the pixel electrode and the thin film transistor on the substrate The corresponding area on the top.
  • the thin film transistor further includes a source and a drain, and the color film layer covers the source and the drain.
  • the color filter layer is provided with a through hole, and the through hole is provided with a connection line, and the connection line connects the pixel electrode and the drain.
  • the surface of the color filter layer is provided with at least one groove, and the shape of the groove corresponds to the shape of the pixel electrode, and the pixel electrode is trapped in the groove.
  • the pixel electrode is obtained by disposing a transparent conductive material on the surface of the color film layer and in the groove, and then removing the transparent conductive material on the surface. of.
  • the bottom surface or the side surface of the groove is provided with a recess or a protrusion.
  • a method of fabricating the above array panel comprising the steps of: separately disposing the scan line, the thin film transistor and the data line on the substrate; and setting the first region and the second region a color film layer, wherein the first region is a region corresponding to a pixel electrode to be disposed, the second region is a region corresponding to the thin film transistor; and the pixel electrode is disposed on the color film layer.
  • the method further includes: providing a through hole in the color film layer; in the through hole A connection line is disposed such that the connection line is connected to a drain of the thin film transistor, and the connection line extends to a surface of the color filter layer.
  • the method further includes: providing a conductive layer between the pixel electrode and the connection line, so that The pixel electrode is connected to the connection line.
  • the connecting line is formed by coating and depositing a first conductive layer on the via hole.
  • the method further includes the step of: providing a second conductive on the drain of the thin film transistor a layer, wherein a thickness of the second conductive layer is greater than or equal to a thickness of the color film layer to be disposed on the thin film transistor; photolithography is performed on the second conductive layer by using a mask to make the film A conductive pillar is formed on the drain of the transistor; and a portion of the second conductive layer except the conductive pillar is stripped.
  • the method further includes: providing at least one groove on a surface of the color film layer, wherein The shape of the groove corresponds to the shape of the pixel electrode; the step of disposing the pixel electrode on the color film layer includes: disposing the pixel electrode in the groove, so that the concave The slot is provided with the pixel electrode.
  • the step of disposing the pixel electrode in the recess includes: providing a transparent conductive material on the surface of the color filter layer and in the recess, The transparent conductive material on the surface is then removed to form the pixel electrode within the recess.
  • the method further comprises the step of: performing light on a bottom surface or a side surface of the groove Engraved or etched so that the bottom or side of the groove has a recess or protrusion.
  • the array panel of the present invention and the manufacturing method thereof can reduce the coupling capacitance formed by the gate electrode and the pixel electrode of the thin film transistor, thereby reducing the power consumption of the pixel unit and reducing the power consumption of the array panel.
  • FIG. 1 is a schematic view of a pixel unit in an array panel of the present invention
  • Figure 2 is a schematic view of the first embodiment of the A-A' section of Figure 1;
  • Figure 3 is a schematic view of a second embodiment of the A-A' section of Figure 1;
  • FIG. 4 is a flow chart of a first embodiment of a method for fabricating an array panel of the present invention
  • FIG. 5 is a flow chart of a second embodiment of a method of fabricating an array panel of the present invention.
  • FIG. 1 is a schematic diagram of a pixel unit in an array panel of the present invention.
  • Figure 2 is a schematic view of the first embodiment of the A-A' section of Figure 1.
  • the array panel of this embodiment includes a substrate 201, a pixel array, at least one scan line 101, and at least one data line 102.
  • the scan line 101, the data line 102, and the pixel array are all disposed on the substrate 201.
  • the pixel array includes at least one pixel unit, wherein the pixel unit includes a thin film transistor 103, a pixel electrode 104, and a color film (Color Film/Color) Filter) layer 105.
  • the color film layer 105 is disposed between the first plane and the second plane, wherein the first plane is a plane where the gate 1031 of the thin film transistor 103 is located, and the second plane is the pixel electrode 104. The plane in which it is located.
  • the color film layer 105 is disposed on the first region and the second region.
  • the first region and the second region are regions corresponding to the pixel electrode 104 and the thin film transistor 103 on the substrate 201, respectively.
  • the thin film transistor 103 further includes a source 1033 and a drain 1034, and the color film layer 105 covers the source 1033 and the drain 1034.
  • the gate electrode 105 is increased by providing the color film layer 105 between the first plane where the gate electrode 1031 of the thin film transistor 103 is located and the second plane where the pixel electrode 104 is located. a distance between the first plane where 1031 is located and a second plane where the pixel electrode 104 is located, thereby reducing a coupling capacitance formed by the gate 1031 and the pixel electrode 104, thereby reducing the pixel
  • the power consumption of the unit reduces the power consumption of the array panel.
  • the color film layer 105 is provided with a through hole 106, and the through hole 106 is provided with a connection line 204, and the connection line 204 connects the pixel electrode 104 and the drain 1034. .
  • the through hole 106 is formed by photolithography or etching the color film layer 105.
  • the connection line 204 may be formed by coating and depositing a first conductive layer (eg, a metal layer) on the via hole 106, the connection line 204 extending to a surface of the color film layer 105.
  • the surface of the color film layer 105 is a side of the color film layer 105 facing away from the substrate 201.
  • connection line 204 may also be formed by: after forming the thin film transistor 103, and before forming the color filter layer 105, in the thin film transistor 103 A second conductive layer (eg, a metal layer) having a thickness greater than or equal to the color film layer 105 to be disposed on the thin film transistor 103 (the drain 1034) is disposed on the drain electrode 1034.
  • the thickness of the second conductive layer is then photolithographically patterned by using a mask such that a conductive pillar (corresponding to the connecting line 204) is formed on the drain 1034 of the thin film transistor 103, and finally A portion of the two conductive layers excluding the conductive pillars is peeled off.
  • the color film layer 105 covers a side surface of the conductive pillar, and a top surface of the conductive pillar is connected to the pixel electrode 104.
  • Figure 3 is a schematic view of a second embodiment of the A-A' section of Figure 1. This embodiment is similar to the first embodiment described above, except that:
  • the surface of the color film layer 105 is provided with at least one groove 301, the shape of the groove 301 corresponding to the shape of the pixel electrode 104, and the pixel electrode 104 card It is disposed in the groove 301.
  • the groove 301 is obtained by exposing and developing the color film layer 105 by a photolithography process.
  • the pixel electrode 104 is obtained by providing a transparent conductive material on the surface of the color film layer 105 and in the recess 301, and then removing the transparent conductive material on the surface.
  • the above technical solution is advantageous in that the pixel electrode 104 is firmly stuck in the groove 301 of the color film layer 105, so that the pixel electrode 104 is not easily detached from the surface of the color film layer 105.
  • the bottom surface or the side surface of the groove 301 may also be provided as an uneven shape.
  • the bottom surface or the side surface of the groove 301 may also be provided with a recess or a protrusion. The recess or the protrusion is obtained by photolithography or etching the groove 301.
  • the above technical solution is advantageous for increasing the friction between the inner surface (bottom surface and side surface) of the groove 301 and the pixel electrode 104, so that the groove 301 can firmly clamp the pixel. Therefore, the pixel electrode 104 is not easily detached from the color film layer 105.
  • FIG. 4 is a flowchart of a first embodiment of a method for fabricating an array panel of the present invention.
  • the manufacturing method of the array panel of this embodiment includes the following steps:
  • Step 401, the scan line 101, the thin film transistor 103, and the data line 102 are respectively disposed on the substrate 201.
  • Step 402 the color film layer 105 is disposed on the first region and the second region, wherein the first region is a region corresponding to the pixel electrode 104 to be disposed, and the second region is the thin film transistor 103. The corresponding area.
  • Step 403 the pixel electrode 104 is disposed on the color film layer 105.
  • the gate electrode 105 is increased by providing the color film layer 105 between the first plane where the gate electrode 1031 of the thin film transistor 103 is located and the second plane where the pixel electrode 104 is located. a distance between the first plane where 1031 is located and a second plane where the pixel electrode 104 is located, thereby reducing a coupling capacitance formed by the gate 1031 and the pixel electrode 104, thereby reducing the pixel
  • the power consumption of the unit reduces the power consumption of the array panel.
  • the gate metal material Cr, Mo, Al, Cu... is plated on the substrate 201 with an appropriate thickness (2000 to 5000 angstroms, wherein 1 angstrom is equal to 10 minus 10 square meters). And exposing and developing the gate metal material according to a first lithography process, and then wet etching the gate metal material with a mask, and then PR (Photoresist, light) Peeling/photoresist) peeling.
  • PECVD Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition
  • insulating film 202 2000 to 5000 angstroms
  • an appropriate film thickness 2000 to 4000 angstroms
  • a coating is performed on the insulating film 202 and the semiconductor layer 1032 with a certain thickness (1000 to 6000 angstroms) to form a source/drain metal material according to the third light.
  • the source/drain metal material is exposed and developed in a certain pattern, wet etching and channel N+ dry etching are performed with a mask, and then PR is stripped to form a source 1033/drain 1034 and Data line 102.
  • an insulating protective film 203 (SiNx) is deposited by PECVD at an appropriate film thickness (1000 to 6000 angstroms), according to a fourth lithography process.
  • the insulating protective film 203 is exposed and developed, dried by a mask, and then PR is peeled off.
  • the insulating protective film 203 is formed, according to an appropriate film thickness (7000 to 20000) Coating a layer of red (R, Red) color film material, exposing and developing the red color film material according to a fifth lithography process to form a red color film layer;
  • the film thickness (7000 ⁇ 20000 angstroms) is coated with a green (G, Green) color film material, and the green color film material is exposed and developed according to a sixth lithography process to form a green color film.
  • a layer of blue (B, Blue) color film material is applied according to a suitable film thickness (7000 to 20000 angstrom), and the blue color film material is exposed in a certain form according to a seventh photolithography process.
  • the order in which the red color film layer, the green color film layer, and the blue color film layer are formed may be arbitrary.
  • a transparent electrode material (ITO or IZO) is plated at an appropriate thickness (100 to 1000 angstroms). The transparent electrode material is exposed and developed in a certain form according to the eighth photolithography process, dried by a mask, and then PR is peeled off.
  • FIG. 5 is a flow chart of a second embodiment of a method for fabricating an array panel of the present invention. This embodiment is similar to the first embodiment described above, except that:
  • the method before the step of disposing the pixel electrode 104 on the color film layer 105 (ie, step 403), the method further includes:
  • Step 501 a through hole 106 is disposed on the color film layer 105.
  • a connection line 204 is disposed in the through hole 106 such that the connection line 204 is connected to the drain 1034 of the thin film transistor 103, and the connection line 204 extends to the surface of the color film layer 105. .
  • the surface of the color film layer 105 is a side of the color film layer 105 facing away from the substrate 201.
  • the through hole 106 is formed by photolithography or etching the color film layer 105.
  • the connection line 204 may be formed by coating and depositing a first conductive layer (eg, a metal layer) on the via hole 106.
  • connection line 204 may also be formed by: after forming the thin film transistor 103, and before forming the color filter layer 105, in the thin film transistor 103
  • a second conductive layer (for example, a metal layer) is disposed on the drain electrode 1034, and the thickness of the second conductive layer is greater than or equal to a thickness of the color film layer 105 to be disposed on the thin film transistor 103, and then a mask is used.
  • Photolithography is performed on the second conductive layer such that a conductive pillar (corresponding to the connecting line 204) is formed on the drain electrode 1034 of the thin film transistor 103, and finally the second conductive layer is divided into the second conductive layer.
  • the portion other than the conductive column is peeled off.
  • the color film layer 105 covers a side surface of the conductive pillar, and a top surface of the conductive pillar is connected to the pixel electrode 104.
  • the method further includes:
  • a conductive layer is disposed between the pixel electrode 104 and the connection line 204 such that the pixel electrode 104 and the connection line 204 are connected.
  • the step of disposing the conductive layer may be performed simultaneously with the step of setting the pixel electrode 104 (ie, step 403).
  • the third embodiment of the method of fabricating the array panel of the present invention is similar to the first or second embodiment described above, except that:
  • the method further includes:
  • At least one groove 301 is disposed on the surface of the color film layer 105, wherein the shape of the groove 301 corresponds to the shape of the pixel electrode 104.
  • the step of setting the groove 301 may be performed simultaneously with the step of setting the through hole 106 (ie, step 501).
  • the step of disposing the pixel electrode 104 on the color film layer 105 includes:
  • the pixel electrode 104 is disposed in the recess 301 such that the recess 301 latches the pixel electrode 104.
  • the groove 301 is obtained by exposing and developing the color film layer 105 by a photolithography process.
  • the pixel electrode 104 is obtained by providing a transparent conductive material on the surface of the color film layer 105 and in the recess 301, and then removing the transparent conductive material on the surface.
  • the above technical solution is advantageous in that the pixel electrode 104 is firmly stuck in the groove 301 of the color film layer 105, so that the pixel electrode 104 is not easily detached from the surface of the color film layer 105.
  • the fourth embodiment of the method for fabricating the array panel of the present invention is similar to the third embodiment described above, except that:
  • the bottom surface or the side surface of the groove 301 is photolithographically or etched so that the bottom surface or the side surface of the groove 301 is concave or convex.
  • An uneven shape, for example, the bottom surface or the side surface of the groove 301 is provided to have a recess or a protrusion, that is, the recess or the protrusion is obtained by photolithography or etching the groove 301. .
  • the above technical solution is advantageous for increasing the friction between the inner surface (bottom surface and side surface) of the groove 301 and the pixel electrode 104, so that the groove 301 can firmly clamp the pixel. Therefore, the pixel electrode 104 is not easily detached from the color film layer 105.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列面板，包括：基板（201）；扫描线（101）；数据线（102）；像素阵列，像素阵列中的像素单元包括：薄膜晶体管（103）；像素电极（104）；设置于第一平面和第二平面之间的彩膜层（105），其中，第一平面为薄膜晶体管（103）的栅极所在的平面，第二平面为像素电极（104）所在的平面；其中，扫描线（101）、数据线（102）和像素阵列均设置于基板上。该阵列面板有利于降低功耗。

Description

阵列面板及其制作方法 技术领域
本发明涉及显示技术领域，特别涉及一种阵列面板及其制作方法。
 背景技术
传统的TFT-LCD（Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示面板）将彩膜（CF，Color Filter）和TFT（Thin Film Transistor，薄膜晶体管）阵列分别做在不同的基板上，其中，TFT阵列基板包括：薄膜晶体管、外围线路和像素电极，彩膜基板包括：公共电极、R/G/B彩膜、PS（Position Spacer，间隔件）和BM（Black Matrix，黑色矩阵层）。由于CF和TFT阵列分别做在不同的玻璃基板上，因此可以节省工艺生产时间。
在实践中，发明人发现现有技术至少存在以下问题：
TFT阵列基板中的薄膜晶体管和像素电极或者其延伸部具有重叠部分，因此薄膜晶体管和像素电极会形成一个电容，该电容会对像素单元的显示造成一定的影响，原因是：该电容的存在可能会导致输入至像素电极中的电压无法达到预期值，从而降低显示质量。
而为了确保显示质量，需要加大电压，以排除该电容的影响，此时则需要耗费更多的电能。
故，有必要提出一种新的技术方案，以解决上述技术问题。
 技术问题
本发明的目的在于提供一种阵列面板及其制作方法，其能降低像素单元的电量消耗，从而降低阵列面板的功耗。
 技术解决方案
一种阵列面板，所述阵列面板包括：一基板；至少一扫描线；至少一数据线；以及一像素阵列，所述像素阵列包括至少一像素单元，其中，所述像素单元包括：一薄膜晶体管；一像素电极；以及一彩膜层，设置于第一平面和第二平面之间，其中，所述第一平面为所述薄膜晶体管的栅极所在的平面，所述第二平面为所述像素电极所在的平面；其中，所述扫描线、所述数据线和所述像素阵列均设置于所述基板上；所述彩膜层设置于第一区域和第二区域上；所述第一区域和所述第二区域分别为所述像素电极和所述薄膜晶体管在所述基板上所对应的区域；所述彩膜层的表面设置有至少一凹槽，所述凹槽的形状与所述像素电极的形状对应，所述像素电极卡设于所述凹槽内。
在上述阵列面板中，所述薄膜晶体管还包括源极和漏极，所述彩膜层覆盖所述源极和所述漏极。
在上述阵列面板中，所述彩膜层设置有通孔，所述通孔中设置有连接线，所述连接线连接所述像素电极和所述漏极。
在上述阵列面板中，所述像素电极是通过在所述彩膜层的所述表面上以及在所述凹槽内设置透明导电材料，然后对所述表面上的所述透明导电材料进行清除得到的。
在上述阵列面板中，所述凹槽的底面或侧面设置有凹陷部或突起部。
一种阵列面板，所述阵列面板包括：一基板；至少一扫描线；至少一数据线；以及一像素阵列，所述像素阵列包括至少一像素单元，其中，所述像素单元包括：一薄膜晶体管；一像素电极；以及一彩膜层，设置于第一平面和第二平面之间，其中，所述第一平面为所述薄膜晶体管的栅极所在的平面，所述第二平面为所述像素电极所在的平面；其中，所述扫描线、所述数据线和所述像素阵列均设置于所述基板上。
在上述阵列面板中，所述彩膜层设置于第一区域和第二区域上；其中，所述第一区域和所述第二区域分别为所述像素电极和所述薄膜晶体管在所述基板上所对应的区域。
在上述阵列面板中，所述薄膜晶体管还包括源极和漏极，所述彩膜层覆盖所述源极和所述漏极。
在上述阵列面板中，所述彩膜层设置有通孔，所述通孔中设置有连接线，所述连接线连接所述像素电极和所述漏极。
在上述阵列面板中，所述彩膜层的表面设置有至少一凹槽，所述凹槽的形状与所述像素电极的形状对应，所述像素电极卡设于所述凹槽内。
在上述阵列面板中，所述像素电极是通过在所述彩膜层的所述表面上以及在所述凹槽内设置透明导电材料，然后对所述表面上的所述透明导电材料进行清除得到的。
在上述阵列面板中，所述凹槽的底面或侧面设置有凹陷部或突起部。
一种上述阵列面板的制作方法，所述方法包括以下步骤：在所述基板上分别设置所述扫描线、所述薄膜晶体管和所述数据线；在第一区域和第二区域上设置所述彩膜层，其中，所述第一区域为待设置的像素电极所对应的区域，所述第二区域为所述薄膜晶体管所对应的区域；在所述彩膜层上设置所述像素电极。
在上述阵列面板的制作方法中，所述在所述彩膜层上设置所述像素电极的步骤之前，所述方法还包括：在所述彩膜层上设置一通孔；在所述通孔中设置一连接线，使得所述连接线与所述薄膜晶体管的漏极连接，并且所述连接线延伸至所述彩膜层的表面。
在上述阵列面板的制作方法中，在在所述彩膜层上设置所述像素电极的过程中，所述方法还包括：在所述像素电极和所述连接线之间设置导电层，使得所述像素电极和所述连接线相连。
在上述阵列面板的制作方法中，所述连接线是通过在所述通孔上涂布、沉积第一导电层来形成的。
在上述阵列面板的制作方法中，在形成所述薄膜晶体管之后，以及在形成所述彩膜层之前，所述方法还包括以下步骤：在所述薄膜晶体管的所述漏极上设置第二导电层，其中，所述第二导电层的厚度大于或等于待设置的所述彩膜层在所述薄膜晶体管上的厚度；利用掩膜对所述第二导电层进行光刻，使得所述薄膜晶体管的所述漏极上形成有一导电柱；对所述第二导电层中除所述导电柱以外的部分进行剥离。
在上述阵列面板的制作方法中，所述在所述彩膜层上设置所述像素电极的步骤之前，所述方法还包括：在所述彩膜层的表面上设置至少一凹槽，其中，所述凹槽的形状与所述像素电极的形状对应；所述在所述彩膜层上设置所述像素电极的步骤包括：将所述像素电极设置于所述凹槽内，使得所述凹槽卡设所述像素电极。
在上述阵列面板的制作方法中，所述将所述像素电极设置于所述凹槽内的步骤包括：在所述彩膜层的所述表面上以及在所述凹槽内设置透明导电材料，然后对所述表面上的所述透明导电材料进行清除，以在所述凹槽内形成所述像素电极。
在上述阵列面板的制作方法中，所述在所述彩膜层的所述表面上设置至少一凹槽的步骤之后，所述方法还包括以下步骤：对所述凹槽的底面或侧面进行光刻或蚀刻，以使所述凹槽的底面或侧面具有凹陷部或突起部。
 有益效果
相对现有技术，本发明的阵列面板及其制作方法能够降低薄膜晶体管的栅极和像素电极所形成的耦合电容，从而降低了像素单元的电量消耗，降低了所述阵列面板的功耗。
 附图说明
图1为本发明的阵列面板中的像素单元的示意图；
图2为图1中A-A’截面的第一实施例的示意图；
图3为图1中A-A’截面的第二实施例的示意图；
图4为本发明的阵列面板的制作方法的第一实施例的流程图；
图5为本发明的阵列面板的制作方法的第二实施例的流程图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。
参考图1和图2，图1为本发明的阵列面板中的像素单元的示意图。图2为图1中A-A’截面的第一实施例的示意图。
本实施例的阵列面板包括基板201、像素阵列、至少一扫描线101以及至少一数据线102。其中，所述扫描线101、所述数据线102和所述像素阵列均设置于所述基板201上。
所述像素阵列包括至少一像素单元，其中，所述像素单元包括薄膜晶体管103、像素电极104以及彩膜（Color Film/Color Filter）层105。所述彩膜层105设置于第一平面和第二平面之间，其中，所述第一平面为所述薄膜晶体管103的栅极1031所在的平面，所述第二平面为所述像素电极104所在的平面。
在本实施例的阵列面板中，所述彩膜层105设置于第一区域和第二区域上。其中，所述第一区域和所述第二区域分别为所述像素电极104和所述薄膜晶体管103在所述基板201上所对应的区域。
在本实施例的阵列面板中，所述薄膜晶体管103还包括源极1033和漏极1034，所述彩膜层105覆盖所述源极1033和所述漏极1034。
在上述技术方案中，通过在所述薄膜晶体管103的栅极1031所在的第一平面和所述像素电极104所在的第二平面之间设置所述彩膜层105，增大了所述栅极1031所在的所述第一平面与所述像素电极104所在的第二平面之间的距离，从而降低了所述栅极1031和所述像素电极104所形成的耦合电容，因此降低了所述像素单元的电量消耗，降低了所述阵列面板的功耗。
在本实施例的阵列面板中，所述彩膜层105设置有通孔106，所述通孔106中设置有连接线204，所述连接线204连接所述像素电极104和所述漏极1034。
所述通孔106是通过对所述彩膜层105进行光刻或蚀刻来形成的。此外，所述连接线204可以通过在所述通孔106上涂布、沉积第一导电层（例如，金属层）来形成，所述连接线204延伸至所述彩膜层105的表面。其中，所述彩膜层105的所述表面为所述彩膜层105背向所述基板201的一面。
此外，在本实施例中，所述连接线204还可以通过以下方式来形成：在形成所述薄膜晶体管103之后，以及在形成所述彩膜层105之前，在所述薄膜晶体管103的所述漏极1034上设置第二导电层（例如，金属层），所述第二导电层的厚度大于或等于待设置的所述彩膜层105在所述薄膜晶体管103（所述漏极1034）上的厚度，然后利用掩膜对所述第二导电层进行光刻，使得所述薄膜晶体管103的所述漏极1034上形成有一导电柱（相当于所述连接线204），最后对所述第二导电层中除所述导电柱以外的部分进行剥离。所述彩膜层105包覆所述导电柱的侧面，所述导电柱的顶面与所述像素电极104相连接。
参考图1和图3，其中，图3为图1中A-A’截面的第二实施例的示意图。本实施例与上述第一实施例相似，不同之处在于：
在本实施例的阵列面板中，所述彩膜层105的所述表面设置有至少一凹槽301，所述凹槽301的形状与所述像素电极104的形状对应，所述像素电极104卡设于所述凹槽301内。所述凹槽301是通过对所述彩膜层105利用光刻工艺进行曝光和显影得到的。所述像素电极104是通过在所述彩膜层105的所述表面上以及在所述凹槽301内设置透明导电材料，然后对所述表面上的所述透明导电材料进行清除得到的。
上述技术方案有利于使得像素电极104稳固地卡设于所述彩膜层105的所述凹槽301内，从而使得所述像素电极104不容易从所述彩膜层105的所述表面脱离。
此外，作为一种改进，所述凹槽301的底面或侧面还可以设置为凹凸不平状，例如，所述凹槽301的底面或侧面还可以设置有凹陷部或突起部。所述凹陷部或所述突起部是通过对所述凹槽301进行光刻或蚀刻得到的。
上述技术方案有利于增大所述凹槽301的内部表面（底面和侧面）与所述像素电极104之间的摩擦力，从而使得所述凹槽301能够稳固地对所述像素进行卡设，因此，所述像素电极104不容易从所述彩膜层105上脱离出来。
参考图4，图4为本发明的阵列面板的制作方法的第一实施例的流程图。本实施例的阵列面板的制作方法包括以下步骤：
步骤401，在所述基板201上分别设置所述扫描线101、所述薄膜晶体管103和所述数据线102。
步骤402，在第一区域和第二区域上设置所述彩膜层105，其中，所述第一区域为待设置的像素电极104所对应的区域，所述第二区域为所述薄膜晶体管103所对应的区域。
步骤403，在所述彩膜层105上设置所述像素电极104。
在上述技术方案中，通过在所述薄膜晶体管103的栅极1031所在的第一平面和所述像素电极104所在的第二平面之间设置所述彩膜层105，增大了所述栅极1031所在的所述第一平面与所述像素电极104所在的第二平面之间的距离，从而降低了所述栅极1031和所述像素电极104所形成的耦合电容，因此降低了所述像素单元的电量消耗，降低了所述阵列面板的功耗。
具体地，首先在所述基板201上面按适当的厚度（2000~5000埃，其中，1埃等于10的负10次方米）镀上栅极金属材料（Cr，Mo，Al，Cu...），根据第一次光刻工艺对所述栅极金属材料按一定的形态进行曝光和显影，然后用掩膜（Mask）对所述栅极金属材料进行湿刻，然后将PR（Photoresist，光刻胶/光致抗蚀剂）进行剥离。
在形成所述薄膜晶体管103的所述栅极1031之后，通过PECVD（Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学气相沉积法）形成沉积一层绝缘膜202（2000~5000埃），在所述绝缘膜202形成之后，按照适当的膜厚（2000~4000埃） 通过PECVD形成一半导体层1032，即，激活层（Active layer（a-Si:H）），根据第二次光刻工艺按一定的形态对所述半导体层1032进行曝光和显影，用掩膜进行干刻，然后将PR进行剥离。
在形成所述半导体层1032后，在所述绝缘膜202和所述半导体层1032上按一定的厚度（1000~6000埃）进行镀膜，以形成源极/漏极金属材料，根据第三次光刻工艺按一定的形态对所述源极/漏极金属材料进行曝光和显影，用掩膜进行湿刻和沟道N+干刻，然后将PR进行剥离，从而形成源极1033/漏极1034以及数据线102。
在形成所述源极1033/漏极1034后，按适当的膜厚（1000~6000埃），通过PECVD形成沉积一层绝缘保护膜203（SiNx），根据第四次光刻工艺按一定的形态对所述绝缘保护膜203进行曝光和显影，用掩膜进行干刻，然后将PR进行剥离。
在所述绝缘保护膜203形成后，按照适当的膜厚（7000~20000 埃）涂布一层红色（R，Red）彩膜材料，根据第五次光刻工艺按一定的形态对所述红色彩膜材料进行曝光和显影，以形成红色彩膜层；然后按照适当的膜厚（7000~20000埃）涂布一层绿色（G，Green）彩膜材料，根据第六次光刻工艺按一定的形态对所述绿色彩膜材料进行曝光和显影，以形成绿色彩膜层；然后按照适当的膜厚（7000~20000埃）涂布一层蓝色（B，Blue）彩膜材料，根据第七次光刻工艺按一定的形态对所述蓝色彩膜材料进行曝光和显影，以形成蓝色彩膜层。其中，所述红色彩膜层、所述绿色彩膜层和所述蓝色彩膜层的形成顺序可以是任意的。
在彩膜层（所述红色彩膜层、所述绿色彩膜层、所述蓝色彩膜层）行成后，按适当的厚度（100~1000埃）镀上透明电极材料（ITO或IZO），根据第八次光刻工艺按一定的形态对所述透明电极材料进行曝光和显影，用掩膜进行干刻，然后将PR进行剥离。
参考图5，图5为本发明的阵列面板的制作方法的第二实施例的流程图。本实施例与上述第一实施例相似，不同之处在于：
在本实施例的阵列面板的制作方法中，所述在所述彩膜层105上设置所述像素电极104的步骤（即，步骤403）之前，所述方法还包括：
步骤501，在所述彩膜层105上设置一通孔106。
步骤502，在所述通孔106中设置一连接线204，使得所述连接线204与所述薄膜晶体管103的漏极1034连接，并且所述连接线204延伸至所述彩膜层105的表面。
其中，所述彩膜层105的所述表面为所述彩膜层105背向所述基板201的一面。所述通孔106是通过对所述彩膜层105进行光刻或蚀刻来形成的。此外，所述连接线204可以通过在所述通孔106上涂布、沉积第一导电层（例如，金属层）来形成。
此外，在本实施例中，所述连接线204还可以通过以下方式来形成：在形成所述薄膜晶体管103之后，以及在形成所述彩膜层105之前，在所述薄膜晶体管103的所述漏极1034上设置第二导电层（例如，金属层），所述第二导电层的厚度大于或等于待设置的所述彩膜层105在所述薄膜晶体管103上的厚度，然后利用掩膜对所述第二导电层进行光刻，使得所述薄膜晶体管103的所述漏极1034上形成有一导电柱（相当于所述连接线204），最后对所述第二导电层中除所述导电柱以外的部分进行剥离。所述彩膜层105包覆所述导电柱的侧面，所述导电柱的顶面与所述像素电极104相连接。
在本实施例的阵列面板的制作方法中，在在所述彩膜层105上设置所述像素电极104的过程中，所述方法还包括：
在所述像素电极104和所述连接线204之间设置导电层，使得所述像素电极104和所述连接线204相连。其中，设置所述导电层这一步骤可以与设置所述像素电极104的步骤（即，步骤403）同时进行。
本发明的阵列面板的制作方法的第三实施例与上述第一或第二实施例相似，不同之处在于：
所述在所述彩膜层105上设置所述像素电极104的步骤之前，所述方法还包括：
在所述彩膜层105的所述表面上设置至少一凹槽301，其中，所述凹槽301的形状与所述像素电极104的形状对应。其中，设置所述凹槽301的步骤可以与设置所述通孔106的步骤（即，步骤501）同时进行。
所述在所述彩膜层105上设置所述像素电极104的步骤包括：
将所述像素电极104设置于所述凹槽301内，使得所述凹槽301卡设所述像素电极104。
所述凹槽301是通过对所述彩膜层105利用光刻工艺进行曝光和显影得到的。所述像素电极104是通过在所述彩膜层105的所述表面上以及在所述凹槽301内设置透明导电材料，然后对所述表面上的所述透明导电材料进行清除得到的。
上述技术方案有利于使得像素电极104稳固地卡设于所述彩膜层105的所述凹槽301内，从而使得所述像素电极104不容易从所述彩膜层105的所述表面脱离。
本发明的阵列面板的制作方法的第四实施例与上述第三实施例相似，不同之处在于：
在在所述彩膜层105的所述表面上形成所述凹槽301后，对所述凹槽301的底面或侧面进行光刻或蚀刻，以使所述凹槽301的底面或侧面为凹凸不平状，例如，将所述凹槽301的底面或侧面设置为具有凹陷部或突起部，即，所述凹陷部或所述突起部是通过对所述凹槽301进行光刻或蚀刻得到的。
上述技术方案有利于增大所述凹槽301的内部表面（底面和侧面）与所述像素电极104之间的摩擦力，从而使得所述凹槽301能够稳固地对所述像素进行卡设，因此，所述像素电极104不容易从所述彩膜层105上脱离出来。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
序列表自由内容

Claims (20)

  1. 一种阵列面板，其中
    所述阵列面板包括：
    一基板；
    至少一扫描线；
    至少一数据线；以及
    一像素阵列，所述像素阵列包括至少一像素单元，其中，所述像素单元包括：
    一薄膜晶体管；
    一像素电极；以及
    一彩膜层，设置于第一平面和第二平面之间，其中，所述第一平面为所述薄膜晶体管的栅极所在的平面，所述第二平面为所述像素电极所在的平面；
    其中，所述扫描线、所述数据线和所述像素阵列均设置于所述基板上；
    所述彩膜层设置于第一区域和第二区域上；
    所述第一区域和所述第二区域分别为所述像素电极和所述薄膜晶体管在所述基板上所对应的区域；
    所述彩膜层的表面设置有至少一凹槽，所述凹槽的形状与所述像素电极的形状对应，所述像素电极卡设于所述凹槽内。
  2. 根据权利要求1所述的阵列面板，其中
    所述薄膜晶体管还包括源极和漏极，所述彩膜层覆盖所述源极和所述漏极。
  3. 根据权利要求2所述的阵列面板，其中
    所述彩膜层设置有通孔，所述通孔中设置有连接线，所述连接线连接所述像素电极和所述漏极。
  4. 根据权利要求1所述的阵列面板，其中
    所述像素电极是通过在所述彩膜层的所述表面上以及在所述凹槽内设置透明导电材料，然后对所述表面上的所述透明导电材料进行清除得到的。
  5. 根据权利要求4所述的阵列面板，其中
    所述凹槽的底面或侧面设置有凹陷部或突起部。
  6. 一种阵列面板，其中
    所述阵列面板包括：
    一基板；
    至少一扫描线；
    至少一数据线；以及
    一像素阵列，所述像素阵列包括至少一像素单元，其中，所述像素单元包括：
    一薄膜晶体管；
    一像素电极；以及
    一彩膜层，设置于第一平面和第二平面之间，其中，所述第一平面为所述薄膜晶体管的栅极所在的平面，所述第二平面为所述像素电极所在的平面；
    其中，所述扫描线、所述数据线和所述像素阵列均设置于所述基板上。
  7. 根据权利要求6所述的阵列面板，其中
    所述彩膜层设置于第一区域和第二区域上；
    其中，所述第一区域和所述第二区域分别为所述像素电极和所述薄膜晶体管在所述基板上所对应的区域。
  8. 根据权利要求7所述的阵列面板，其中
    所述薄膜晶体管还包括源极和漏极，所述彩膜层覆盖所述源极和所述漏极。
  9. 根据权利要求8所述的阵列面板，其中
    所述彩膜层设置有通孔，所述通孔中设置有连接线，所述连接线连接所述像素电极和所述漏极。
  10. 根据权利要求6所述的阵列面板，其中
    所述彩膜层的表面设置有至少一凹槽，所述凹槽的形状与所述像素电极的形状对应，所述像素电极卡设于所述凹槽内。
  11. 根据权利要求10所述的阵列面板，其中
    所述像素电极是通过在所述彩膜层的所述表面上以及在所述凹槽内设置透明导电材料，然后对所述表面上的所述透明导电材料进行清除得到的。
  12. 根据权利要求10所述的阵列面板，其中
    所述凹槽的底面或侧面设置有凹陷部或突起部。
  13. 一种如权利要求6所述的阵列面板的制作方法，其中
    所述方法包括以下步骤：
    在所述基板上分别设置所述扫描线、所述薄膜晶体管和所述数据线；
    在第一区域和第二区域上设置所述彩膜层，其中，所述第一区域为待设置的像素电极所对应的区域，所述第二区域为所述薄膜晶体管所对应的区域；
    在所述彩膜层上设置所述像素电极。
  14. 根据权利要求13所述的阵列面板的制作方法，其中
    所述在所述彩膜层上设置所述像素电极的步骤之前，所述方法还包括：
    在所述彩膜层上设置一通孔；
    在所述通孔中设置一连接线，使得所述连接线与所述薄膜晶体管的漏极连接，并且所述连接线延伸至所述彩膜层的表面。
  15. 根据权利要求14所述的阵列面板的制作方法，其中
    在在所述彩膜层上设置所述像素电极的过程中，所述方法还包括：
    在所述像素电极和所述连接线之间设置导电层，使得所述像素电极和所述连接线相连。
  16. 根据权利要求14所述的阵列面板的制作方法，其中
    所述连接线是通过在所述通孔上涂布、沉积第一导电层来形成的。
  17. 根据权利要求14所述的阵列面板的制作方法，其中
    在形成所述薄膜晶体管之后，以及在形成所述彩膜层之前，所述方法还包括以下步骤：
    在所述薄膜晶体管的所述漏极上设置第二导电层，其中，所述第二导电层的厚度大于或等于待设置的所述彩膜层在所述薄膜晶体管上的厚度；
    利用掩膜对所述第二导电层进行光刻，使得所述薄膜晶体管的所述漏极上形成有一导电柱；
    对所述第二导电层中除所述导电柱以外的部分进行剥离。
  18. 根据权利要求13所述的阵列面板的制作方法，其中
    所述在所述彩膜层上设置所述像素电极的步骤之前，所述方法还包括：
    在所述彩膜层的表面上设置至少一凹槽，其中，所述凹槽的形状与所述像素电极的形状对应；
    所述在所述彩膜层上设置所述像素电极的步骤包括：
    将所述像素电极设置于所述凹槽内，使得所述凹槽卡设所述像素电极。
  19. 根据权利要求18所述的阵列面板的制作方法，其中
    所述将所述像素电极设置于所述凹槽内的步骤包括：
    在所述彩膜层的所述表面上以及在所述凹槽内设置透明导电材料，然后对所述表面上的所述透明导电材料进行清除，以在所述凹槽内形成所述像素电极。
  20. 根据权利要求18所述的阵列面板的制作方法，其中
    所述在所述彩膜层的所述表面上设置至少一凹槽的步骤之后，所述方法还包括以下步骤：
    对所述凹槽的底面或侧面进行光刻或蚀刻，以使所述凹槽的底面或侧面具有凹陷部或突起部。
PCT/CN2014/077124 2014-05-04 2014-05-09 阵列面板及其制作方法 Ceased WO2015168927A1 (zh)

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