WO2015156075A1 - Substrat de support en verre et élément multicouche l'utilisant - Google Patents

Substrat de support en verre et élément multicouche l'utilisant Download PDF

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Publication number
WO2015156075A1
WO2015156075A1 PCT/JP2015/057092 JP2015057092W WO2015156075A1 WO 2015156075 A1 WO2015156075 A1 WO 2015156075A1 JP 2015057092 W JP2015057092 W JP 2015057092W WO 2015156075 A1 WO2015156075 A1 WO 2015156075A1
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Prior art keywords
glass substrate
supporting glass
less
supporting
substrate
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PCT/JP2015/057092
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English (en)
Japanese (ja)
Inventor
光 池田
鈴木　良太
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日本電気硝子株式会社
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Application filed by 日本電気硝子株式会社 filed Critical 日本電気硝子株式会社
Priority to CN201580014823.2A priority Critical patent/CN106103369A/zh
Priority to CN202211243837.XA priority patent/CN115636582A/zh
Priority to CN202211243838.4A priority patent/CN115636583A/zh
Priority to KR1020167025079A priority patent/KR102436789B1/ko
Publication of WO2015156075A1 publication Critical patent/WO2015156075A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67103—Apparatus for thermal treatment mainly by conduction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the present invention relates to a supporting glass substrate and a laminate using the same, and more specifically to a supporting glass substrate used for supporting a processed substrate in a manufacturing process of a semiconductor package (semiconductor device) and a laminate using the same.
  • Portable electronic devices such as mobile phones, notebook personal computers, and PDAs (Personal Data Assistance) are required to be smaller and lighter.
  • the mounting space of semiconductor chips used in these electronic devices is also strictly limited, and high-density mounting of semiconductor chips has become a problem. Therefore, in recent years, high-density mounting of semiconductor packages has been achieved by three-dimensional mounting technology, that is, by stacking semiconductor chips and interconnecting the semiconductor chips.
  • a conventional wafer level package is manufactured by forming bumps in a wafer state and then separating them by dicing.
  • the semiconductor chip is likely to be chipped.
  • the fan-out type WLP can increase the number of pins, and can prevent chipping of the semiconductor chip by protecting the end portion of the semiconductor chip.
  • a plurality of semiconductor chips are molded with a resin sealing material to form a processed substrate, and then a step of wiring on one surface of the processed substrate, a step of forming a solder bump, and the like are included. .
  • the sealing material may be deformed and the processed substrate may change in dimensions.
  • the dimension of the processed substrate changes, it becomes difficult to perform wiring with high density on one surface of the processed substrate, and it becomes difficult to accurately form solder bumps.
  • an object of the present invention is to contribute to high-density mounting of a semiconductor package by creating a support substrate that hardly causes a dimensional change of a processed substrate and a laminate using the support substrate.
  • the present inventors have found that the above technical problem can be solved by adopting a glass substrate as a support substrate and strictly regulating the thermal expansion coefficient of the glass substrate.
  • This is proposed as the present invention. That is, the support glass substrate of the present invention has an average linear thermal expansion coefficient in the temperature range of 20 to 200 ° C. of 66 ⁇ 10 ⁇ 7 / ° C. or more and 81 ⁇ 10 ⁇ 7 / ° C. or less.
  • the “average thermal expansion coefficient in the temperature range of 20 to 200 ° C.” can be measured with a dilatometer.
  • the glass substrate is easy to smooth the surface and has rigidity. For this reason, when a glass substrate is used as the support substrate, the processed substrate can be supported firmly and accurately. In addition, the glass substrate easily transmits light such as ultraviolet light and infrared light. For this reason, when a glass substrate is used as the support substrate, the processed substrate and the support glass substrate can be easily fixed by providing an adhesive layer or the like with an ultraviolet curable adhesive or the like. Further, the processing substrate and the supporting glass substrate can be easily separated by providing a release layer or the like that absorbs infrared rays. As another method, the processed substrate and the supporting glass substrate can be easily separated by providing an adhesive layer or the like with an ultraviolet curable tape or the like.
  • the average linear thermal expansion coefficient in the temperature range of 20 to 200 ° C. is regulated to 66 ⁇ 10 ⁇ 7 / ° C. or more and 81 ⁇ 10 ⁇ 7 / ° C. or less.
  • the thermal expansion coefficients of the processed substrate and the supporting glass substrate are easily matched.
  • the thermal expansion coefficients of the two match, it becomes easy to suppress a dimensional change (particularly warp deformation) of the processed substrate during processing.
  • wiring on one surface of the processed substrate can be performed with high density, and solder bumps can be accurately formed.
  • the supporting glass substrate of the present invention has an average linear thermal expansion coefficient in the temperature range of 30 to 380 ° C. of 70 ⁇ 10 ⁇ 7 / ° C. or more and 85 ⁇ 10 ⁇ 7 / ° C. or less.
  • the “average thermal expansion coefficient in the temperature range of 30 to 380 ° C.” can be measured with a dilatometer.
  • the supporting glass substrate of the present invention is preferably used for supporting a processed substrate in a semiconductor package manufacturing process.
  • the supporting glass substrate of the present invention preferably has an ultraviolet transmittance in the thickness direction at a wavelength of 300 nm of 40% or more.
  • the “UV transmittance in the thickness direction at a wavelength of 300 nm” can be evaluated by measuring the spectral transmittance at a wavelength of 300 nm using, for example, a double beam spectrophotometer.
  • the supporting glass substrate of the present invention preferably has a Young's modulus of 65 GPa or more.
  • Young's modulus refers to a value measured by a bending resonance method. 1 GPa corresponds to approximately 101.9 kgf / mm 2 .
  • the supporting glass substrate of the present invention has a glass composition, in mass%, SiO 2 40 ⁇ 80% , Al 2 O 3 1 ⁇ 20%, B 2 O 3 0 ⁇ 20%, MgO 0 ⁇ 12% CaO 0 to 10%, SrO 0 to 20%, BaO 0 to 20%, ZnO 0 to 10%, Na 2 O 4 to 20%, K 2 O 0 to 15% are preferably contained.
  • the supporting glass substrate of the present invention has a glass composition, in mass%, SiO 2 60 ⁇ 75% , Al 2 O 3 5 ⁇ 15%, B 2 O 3 5 ⁇ 20%, MgO 0 ⁇ 5% CaO 0 to 10%, SrO 0 to 5%, BaO 0 to 5%, ZnO 0 to 5%, Na 2 O 7 to 16%, K 2 O 0 to 8% are preferably contained.
  • the supporting glass substrate of the present invention has a glass composition of mass%, SiO 2 50-80%, Al 2 O 3 1-20%, B 2 O 3 0-20%, MgO 0-5%, It is preferable to contain CaO 0 to 10%, SrO 0 to 5%, BaO 0 to 5%, ZnO 0 to 5%, Na 2 O 5 to 20%, K 2 O 0 to 10%.
  • the supporting glass substrate of the present invention has a glass composition of SiO 2 60 to 75%, Al 2 O 3 10 to 20%, B 2 O 3 0 to 10%, MgO 0 to 5% in terms of glass composition.
  • CaO 0 to 5%, SrO 0 to 5%, BaO 0 to 5%, ZnO 0 to 5%, Na 2 O 6 to 18%, and K 2 O 0 to 8% are preferable.
  • the supporting glass substrate of the present invention has a glass composition of mass%, SiO 2 40-60%, Al 2 O 3 5-20%, B 2 O 3 0-20%, MgO 0-5%, It is preferable to contain CaO 0 to 10%, SrO 0 to 20%, BaO 0 to 20%, Na 2 O 4 to 20%, K 2 O 0 to 10%.
  • the supporting glass substrate of the present invention has a glass composition of SiO 2 44 to 54%, Al 2 O 3 10 to 15%, B 2 O 3 0 to 15%, MgO 0 to 3 in terms of glass composition.
  • it contains 0.6%, CaO 3-8%, SrO 4-15%, BaO 0-14%, Na 2 O 4-15%, K 2 O 0-10%.
  • the supporting glass substrate of the present invention has a plate thickness of less than 2.0 mm, a disk shape with a diameter of 100 to 500 mm, an overall plate thickness deviation of 30 ⁇ m or less, and a warp amount of 60 ⁇ m or less.
  • the “warp amount” refers to the sum of the absolute value of the maximum distance between the highest point and the least square focal plane in the entire supporting glass substrate and the absolute value of the lowest point and the least square focal plane. For example, it can be measured by a Bow / Warp measuring apparatus SBW-331ML / d manufactured by Kobelco Kaken.
  • the laminated body of this invention is a laminated body provided with a processed substrate and the support glass substrate for supporting a processed substrate, Comprising: It is preferable that a support glass substrate is said support glass substrate.
  • the laminated body of this invention is provided with the semiconductor chip by which the process board
  • the manufacturing method of the semiconductor package of this invention provides the process of preparing a laminated body provided with a process substrate and the support glass substrate for supporting a process substrate, and the process of processing with respect to a process substrate It is preferable that the supporting glass substrate is the above supporting glass substrate.
  • the processing includes a step of wiring on one surface of the processed substrate.
  • the processing includes a step of forming solder bumps on one surface of the processed substrate.
  • the semiconductor package of the present invention is manufactured by the above-described method for manufacturing a semiconductor device.
  • an electronic device of the present invention is an electronic device including a semiconductor package, and the semiconductor package is the above-described semiconductor package.
  • FIG. 6 is a conceptual cross-sectional view showing a manufacturing process of a fan-out type WLP.
  • FIG. 6 is a conceptual cross-sectional view showing a manufacturing process of a fan-out type WLP.
  • FIG. 6 is a conceptual cross-sectional view showing a manufacturing process of a fan-out type WLP.
  • FIG. 6 is a conceptual cross-sectional view showing a manufacturing process of a fan-out type WLP.
  • FIG. 6 is a conceptual cross-sectional view showing a manufacturing process of a fan-out type WLP.
  • FIG. 6 is a conceptual cross-sectional view showing a manufacturing process of a fan-out type WLP.
  • FIG. 6 is a conceptual cross-sectional view showing a manufacturing process of a fan-out type WLP.
  • FIG. 6 is a conceptual cross-sectional view showing a manufacturing process of a fan-out type WLP.
  • the average thermal expansion coefficient in the temperature range of 20 to 200 ° C. is 66 ⁇ 10 ⁇ 7 / ° C. or more and 81 ⁇ 10 ⁇ 7 / ° C. or less, preferably 66 ⁇ 10 ⁇ 7 / ° C. More than 77 ⁇ 10 ⁇ 7 / ° C. or 68 ⁇ 10 ⁇ 7 / ° C. and 76 ⁇ 10 ⁇ 7 / ° C., particularly preferably 70 ⁇ 10 ⁇ 7 / ° C. and 75 ⁇ 10 ⁇ 7 / ° C. It is below °C. If the average thermal expansion coefficient in the temperature range of 20 to 200 ° C. is outside the above range, the thermal expansion coefficients of the processed substrate and the supporting glass substrate are difficult to match. If the thermal expansion coefficients of the two are mismatched, a dimensional change (particularly warp deformation) of the processed substrate is likely to occur during processing.
  • the average coefficient of thermal expansion in the temperature range of 30 to 380 ° C. is 70 ⁇ 10 ⁇ 7 / ° C. or more and 85 ⁇ 10 ⁇ 7 / ° C. or less, preferably more than 70 ⁇ 10 ⁇ 7 / ° C. and 83 ⁇ 10 ⁇ 7. / ° C. or less, or 72 ⁇ 10 ⁇ 7 / ° C. or more and 81 ⁇ 10 ⁇ 7 / ° C. or less, particularly preferably 74 ⁇ 10 ⁇ 7 / ° C. or more and 80 ⁇ 10 ⁇ 7 / ° C. or less.
  • the average thermal expansion coefficient in the temperature range of 30 to 380 ° C. is outside the above range, the thermal expansion coefficients of the processed substrate and the supporting glass substrate are difficult to match. If the thermal expansion coefficients of the two are mismatched, a dimensional change (particularly warp deformation) of the processed substrate is likely to occur during processing.
  • the UV transmittance in the thickness direction at a wavelength of 300 nm is preferably 40% or more, 45% or more, 50% or more, 55% or more, 60% or more, 65% or more, or 70% or more. And particularly preferably 80% or more. If the ultraviolet transmittance is too low, it becomes difficult to bond the processed substrate and the support substrate by the adhesive layer. If the ultraviolet transmittance is too low, it becomes difficult to bond the processed substrate and the support substrate by the adhesive layer due to the irradiation of ultraviolet light. Further, when an adhesive layer or the like is provided with an ultraviolet curable tape or the like, it becomes difficult to easily separate the processed substrate and the supporting glass substrate.
  • the “ultraviolet transmittance in the thickness direction at a wavelength of 300 nm” can be evaluated by measuring the spectral transmittance at a wavelength of 300 nm using, for example, a double beam spectrophotometer.
  • Supporting glass substrate of the present invention has a glass composition, in mass%, SiO 2 40 ⁇ 80% , Al 2 O 3 1 ⁇ 20%, B 2 O 3 0 ⁇ 20%, MgO 0 ⁇ 12%, CaO 0 ⁇ It preferably contains 10%, SrO 0-20%, BaO 0-20%, ZnO 0-10%, Na 2 O 4-20%, K 2 O 0-15%.
  • the reason for limiting the content of each component as described above will be described below.
  • % display represents the mass% unless there is particular notice.
  • SiO 2 is a main component that forms a glass skeleton.
  • the Young's modulus acid resistance tends to decrease.
  • the lower limit of the content of SiO 2 is preferably 40% or 44%, and particularly preferably 50%.
  • the lower limit of the content of SiO 2 is preferably 58%, 60%, or 62%, particularly preferably 64% when priority is given to the improvement of Young's modulus.
  • the upper limit of the content of SiO 2 is preferably 80%, 75%, or 72%, and particularly preferably 70%. Further, the upper limit of the content of SiO 2 is preferably 65% or 60%, particularly preferably 54%, when the meltability is given priority.
  • Al 2 O 3 is a component that enhances the Young's modulus and a component that suppresses phase separation and devitrification.
  • the lower limit of the content of Al 2 O 3 is preferably 1%, 3%, or 5%, and particularly preferably 6%.
  • the lower limit of the content of Al 2 O 3 is preferably 8%, particularly preferably 10% when priority is given to the improvement of Young's modulus.
  • the upper limit of the content of Al 2 O 3 is preferably 20%, particularly preferably 15%.
  • the upper limit of the content of Al 2 O 3 is preferably 10%, particularly preferably 9% when priority is given to meltability.
  • B 2 O 3 is a component that enhances meltability and devitrification resistance, and is a component that improves the ease of scratching and increases strength.
  • meltability, devitrification resistance is liable to lower, also resistance tends to decrease with respect to hydrofluoric acid chemical.
  • the Young's modulus, acid resistance tends to decrease. Therefore, the lower limit of the content of B 2 O 3 is preferably 0%, 3%, 5%, or 6%, and particularly preferably 7%.
  • the upper limit of the content of B 2 O 3 is preferably 20%, 18%, 15%, or 12%, and particularly preferably 10% or less. Further, the upper limit of the content of B 2 O 3 is preferably 5% or 3%, particularly preferably 1% or less, when priority is given to improvement of Young's modulus.
  • B 2 O 3 —Al 2 O 3 is preferably 0% or more, or 0.5% or more, and particularly preferably 1% or more.
  • B 2 O 3 —Al 2 O 3 is preferably 10% or less, 5 or less, 0% or less, ⁇ 3% or less, or ⁇ 5% or less, particularly preferably ⁇ from the viewpoint of increasing the Young's modulus. 7% or less.
  • “B 2 O 3 —Al 2 O 3 ” refers to a value obtained by subtracting the content of Al 2 O 3 from the content of B 2 O 3 .
  • MgO is a component that lowers the viscosity at high temperature and increases meltability.
  • MgO is a component that significantly increases Young's modulus.
  • the content of MgO is preferably 0 to 12%, 0 to 8%, 0 to 5%, 0 to 4%, 0 to 3.8%, 0 to 3%, or 0 to 2%. Particularly preferably, it is 0 to less than 1%.
  • CaO is a component that lowers the high temperature viscosity and remarkably increases the meltability. Further, among the alkaline earth metal oxides, since the introduced raw material is relatively inexpensive, it is a component that lowers the raw material cost.
  • the CaO content is preferably 0 to 10%, 1 to 8%, 3 to 8%, or 2 to 6%, particularly preferably 2 to 5%. When there is too much content of CaO, it will become easy to devitrify glass. In addition, when there is too little content of CaO, it will become difficult to receive the said effect.
  • SrO is a component that suppresses phase separation and is a component that improves devitrification resistance.
  • the SrO content is preferably 0 to 20%, 0 to 15%, 0 to 9%, 0 to 5%, 0 to 4%, 0 to 3%, or 0 to 2%, particularly preferably. Is 0 to less than 1%.
  • the lower limit of the SrO content is preferably 0.1%, 1%, 2%, or 4%, and particularly preferably 7%.
  • BaO is a component that increases devitrification resistance.
  • the content of BaO is preferably 0 to 20%, 0 to 14%, 0 to 9%, 0 to 5%, 0 to 4%, 0 to 3%, or 0 to 2%, particularly preferably 0. Less than 1%.
  • the lower limit of the BaO content is preferably 0.1% or more, or 1% or more, and particularly preferably 3% or more.
  • the mass ratio CaO / (MgO + CaO + SrO + BaO) is preferably 0.5 or more, 0.6 or more, 0.7 or more, or 0.8 or more, and particularly preferably 0.9 or more. If the mass ratio CaO / (MgO + CaO + SrO + BaO) is too small, the raw material cost is likely to increase. “CaO / (MgO + CaO + SrO + BaO)” indicates a value obtained by dividing the content of CaO by the total amount of MgO, CaO, SrO, and BaO.
  • ZnO is a component that lowers the high temperature viscosity and remarkably increases the meltability.
  • the content of ZnO is preferably 0 to 10%, 0 to 5%, or 0.1 to 4%, particularly preferably 0.5 to 3%. When there is too little content of ZnO, it will become difficult to receive the said effect. In addition, when there is too much content of ZnO, it will become easy to devitrify glass.
  • Na 2 O is an important component for adjusting the thermal expansion coefficient within the above range, and is a component that contributes to the initial melting of the glass raw material while lowering the high-temperature viscosity to significantly increase the meltability. If the content of Na 2 O is too small, the meltability tends to be lowered, and the thermal expansion coefficient may be unduly lowered. On the other hand, when the content of Na 2 O is too large, there is a concern that the thermal expansion coefficient becomes unduly high. Therefore, the lower limit of the content of Na 2 O is preferably 4%, 5%, 6%, or 7%, particularly preferably 9% or more. Moreover, the upper limit of the content of Na 2 O is preferably 20%, 18%, or 16%, and particularly preferably 15%.
  • B 2 O 3 —Na 2 O is preferably ⁇ 7 to 4%, ⁇ 6 to 3%, or ⁇ 5 to 2%, particularly preferably ⁇ 4 to 1%. This makes it easy to adjust the thermal expansion coefficient within the above range.
  • B 2 O 3 —Na 2 O refers to a value obtained by subtracting the Na 2 O content from the B 2 O 3 content.
  • K 2 O is a component for adjusting the thermal expansion coefficient, and is a component that contributes to the initial melting of the glass raw material while lowering the high-temperature viscosity to increase the meltability.
  • the content of K 2 O is preferably 0 to 15%, 0 to 10%, or 0.1 to 8%, particularly preferably 1 to 5%.
  • the thermal expansion coefficient becomes unduly high.
  • the K 2 O content is too small, the melting property tends to decrease.
  • Fe 2 O 3 is a component that can be introduced as an impurity component or a fining agent component.
  • the content of Fe 2 O 3 is preferably 0.05% or less, 0.03% or less, or 0.001 to 0.02%, particularly preferably 0.005 to 0.01%.
  • “Fe 2 O 3 ” referred to in the present invention includes divalent iron oxide and trivalent iron oxide, and the divalent iron oxide is handled in terms of Fe 2 O 3 . Similarly, other oxides are handled based on the indicated oxide.
  • As 2 O 3 acts effectively as a fining agent, but it is preferable to reduce these components as much as possible from an environmental point of view.
  • the content of As 2 O 3 is preferably 1% or less, or 0.5% or less, particularly preferably 0.1% or less, and most preferably not substantially contained.
  • substantially does not contain As 2 O 3 refers to the case where the content of As 2 O 3 in the glass composition is less than 0.05%.
  • Sb 2 O 3 is a component having a good clarification action in a low temperature range.
  • the content of Sb 2 O 3 is preferably 0 to 1%, 0.001 to 1%, or 0.01 to 0.9%, particularly preferably 0.05 to 0.7%.
  • the glass tends to color.
  • SnO 2 is a component having a good clarification action in a high temperature region and a component that lowers the high temperature viscosity.
  • the content of SnO 2 is preferably 0 to 1%, 0.001 to 1%, or 0.01 to 0.9%, particularly preferably 0.05 to 0.7%.
  • the content of SnO 2 is too large, the devitrification crystal SnO 2 is likely to precipitate. Incidentally, when the content of SnO 2 is too small, it becomes difficult to enjoy the above-mentioned effects.
  • SO 3 is a component having a clarification action.
  • the content of SO 3 is preferably 0 to 1%, 0.001 to 1%, or 0.01 to 0.5%, particularly preferably 0.05 to 0.3%. When the content of SO 3 is too large, SO 2 reboyl tends to be generated.
  • metal powders such as F, C, Al, Si, etc. may be introduced up to about 1% as fining agents.
  • CeO 2 or the like can also be introduced up to about 1%, but it is necessary to pay attention to a decrease in the ultraviolet transmittance.
  • Cl is a component that promotes melting of glass. If Cl is introduced into the glass composition, the melting temperature can be lowered and the clarification action can be promoted. As a result, the melting cost can be lowered and the glass production kiln can be easily extended. However, when there is too much Cl content, there is a possibility of corroding the metal parts around the glass manufacturing kiln. Therefore, the Cl content is preferably 3% or less, 1% or less, or 0.5% or less, and particularly preferably 0.1% or less.
  • P 2 O 5 is a component that can suppress the precipitation of devitrified crystals.
  • the content of P 2 O 5 is preferably 0 to 2.5%, 0 to 1.5%, or 0 to 0.5%, particularly preferably 0 to 0.3%.
  • TiO 2 is a component that lowers the high-temperature viscosity and increases the meltability, and also suppresses solarization. However, when a large amount of TiO 2 is introduced, the glass is colored and the transmittance tends to decrease. Therefore, the content of TiO 2 is preferably 0 to 5%, 0 to 3%, or 0 to 1%, particularly preferably 0 to 0.02%.
  • ZrO 2 is a component that improves chemical resistance and Young's modulus.
  • the content of ZrO 2 is preferably 0 to 10%, 0 to 7%, 0 to 5%, 0.001 to 3%, or 0.01 to 1%, particularly preferably 0.1 to 1%. 0.5%.
  • Y 2 O 3 , Nb 2 O 5 , and La 2 O 3 have a function of increasing the strain point, Young's modulus, and the like. However, if the content of these components is 1%, particularly more than 5%, the raw material cost and product cost may increase.
  • a suitable content range of each component can be appropriately selected to constitute a suitable glass composition range, but the average linear thermal expansion coefficient in the temperature range of 20 to 200 ° C. is 66 ⁇ 10 6.
  • the following glass composition ranges are particularly suitable.
  • the glass composition is mass%, SiO 2 50-80%, Al 2 O 3 1-20%, B 2 O 3 0-20%, MgO 0-5%, CaO 0-10%, SrO 0- 5%, BaO 0-5%, ZnO 0-5%, Na 2 O 5-20%, K 2 O 0-10%.
  • the support glass substrate of the present invention is preferably not subjected to ion exchange treatment, and preferably has no compressive stress layer on the surface.
  • the manufacturing cost of the supporting glass substrate increases, but when the ion exchange processing is not performed, the manufacturing cost of the supporting glass substrate can be reduced. Further, when ion exchange treatment is performed, it becomes difficult to reduce the overall thickness deviation of the supporting glass substrate. However, if the ion exchange treatment is not performed, it is easy to eliminate such a problem.
  • the support glass substrate of this invention does not exclude the aspect which performs an ion exchange process and forms a compressive-stress layer in the surface. From the viewpoint of increasing mechanical strength, it is preferable to perform ion exchange treatment to form a compressive stress layer on the surface.
  • the supporting glass substrate of the present invention preferably has the following characteristics.
  • the Young's modulus is preferably 65 GPa or more, 68 GPa or more, 70 GPa or more, 72 GPa or more, or 73 GPa or more, and particularly preferably 74 GPa or more. If the Young's modulus is too low, it is difficult to maintain the rigidity of the laminate, and the processed substrate is likely to be deformed, warped, or damaged.
  • the liquidus temperature is preferably less than 1150 ° C, 1100 ° C or less, 1050 ° C or less, 1000 ° C or less, 950 ° C or less, 900 ° C or less, or 870 ° C or less, and particularly preferably 850 ° C or less. If it does in this way, it will become easy to shape
  • the “liquid phase temperature” is obtained by passing the standard sieve 30 mesh (500 ⁇ m) and putting the glass powder remaining on the 50 mesh (300 ⁇ m) in a platinum boat, and holding it in a temperature gradient furnace for 24 hours. It can be calculated by measuring the temperature at which precipitation occurs.
  • the viscosity at the liquidus temperature is preferably 10000 dPa ⁇ s or more, 30000 dPa ⁇ s or more, 60000 dPa ⁇ s or more, 100000 dPa ⁇ s or more, 200000 dPa ⁇ s or more, 300000 dPa ⁇ s or more, 500000 dPa ⁇ s or more, or 800000 dPa ⁇ s or more. Yes, particularly preferably 1000000 dPa ⁇ s or more. If it does in this way, it will become easy to shape
  • the overall plate thickness deviation can be reduced to less than 2.0 ⁇ m, particularly less than 1.0 ⁇ m. Cost can be reduced. Furthermore, it becomes easy to prevent a situation where devitrification crystals are generated during the glass substrate manufacturing process and the productivity of the glass substrate is lowered.
  • the “viscosity at the liquidus temperature” can be measured by a platinum ball pulling method. The viscosity at the liquidus temperature is an index of moldability. The higher the viscosity at the liquidus temperature, the better the moldability.
  • the temperature at 10 2.5 dPa ⁇ s is preferably 1580 ° C. or lower, 1520 ° C. or lower, 1480 ° C. or lower, 1450 ° C. or lower, or 1420 ° C. or lower, particularly preferably 1400 ° C. or lower.
  • “temperature at 10 2.5 dPa ⁇ s” can be measured by a platinum ball pulling method. The temperature at 10 2.5 dPa ⁇ s corresponds to the melting temperature, and the lower the temperature, the better the melting property.
  • the support glass substrate of the present invention is preferably formed by a downdraw method, particularly an overflow downdraw method.
  • molten glass overflows from both sides of a heat-resistant bowl-shaped structure, and the overflowed molten glass joins at the lower top end of the bowl-shaped structure and is formed downward to produce a glass substrate. It is a method to do.
  • the surface to be the surface of the glass substrate is not in contact with the bowl-shaped refractory, and is formed in a free surface state. For this reason, it becomes easy to produce a glass substrate with a small plate thickness, and with a small amount of polishing, the overall plate thickness deviation can be reduced to less than 2.0 ⁇ m, particularly less than 1.0 ⁇ m. Cost can be reduced.
  • the glass substrate forming method in addition to the overflow downdraw method, for example, a slot down method, a redraw method, a float method, or the like can be adopted.
  • the support glass substrate of the present invention preferably has a disc shape (for example, a wafer shape or a substantially disc shape), and the diameter is preferably 100 mm or more and 500 mm or less, particularly preferably 150 mm or more and 450 mm or less. In this way, it becomes easy to apply to the manufacturing process of a semiconductor package. You may process into other shapes, for example, shapes, such as a rectangle, as needed.
  • the roundness is preferably 1 mm or less, 0.1 mm or less, or 0.05 mm or less, and particularly preferably 0.03 mm or less.
  • the definition of the roundness is a value obtained by subtracting the minimum value from the maximum value of the outer shape of the wafer.
  • the plate thickness is preferably less than 2.0 mm, 1.5 mm or less, 1.2 mm or less, 1.1 mm or less, or 1.0 mm or less, particularly preferably 0.9 mm or less. is there.
  • the plate thickness decreases, the mass of the laminate becomes lighter, and thus handling properties are improved.
  • the plate thickness is preferably 0.1 mm or more, 0.2 mm or more, 0.3 mm or more, 0.4 mm or more, 0.5 mm or more, or 0.6 mm or more, and particularly more than 0.7 mm.
  • the total thickness deviation is preferably 30 ⁇ m or less, 20 ⁇ m or less, 10 ⁇ m or less, 5 ⁇ m or less, 4 ⁇ m or less, 3 ⁇ m or less, 2 ⁇ m or less, or 1 ⁇ m or less, particularly preferably 0.1 to It is less than 1 ⁇ m.
  • the arithmetic average roughness Ra is preferably 100 nm or less, 50 nm or less, 20 nm or less, 10 nm or less, 5 nm or less, 2 nm or less, or 1 nm or less, and particularly preferably 0.5 nm or less. The higher the surface accuracy, the easier it is to improve the processing accuracy.
  • the “arithmetic average roughness Ra” can be measured by a stylus type surface roughness meter or an atomic force microscope (AFM).
  • the support glass substrate of the present invention is preferably formed by polishing the surface after being formed by the overflow downdraw method. If it does in this way, it will become easy to regulate the whole board thickness deviation to less than 2.0 micrometers.
  • the total thickness deviation is preferably 1.5 ⁇ m or less, or 1.0 ⁇ m or less, and particularly preferably 0.1 to less than 1.0 ⁇ m.
  • the warp amount is preferably 60 ⁇ m or less, 55 ⁇ m or less, 50 ⁇ m or less, or 1 to 45 ⁇ m, and particularly preferably 5 to 40 ⁇ m.
  • the smaller the warp amount the easier it is to improve the accuracy of the processing. In particular, since the wiring accuracy can be increased, high-density wiring is possible.
  • the laminate of the present invention is a laminate comprising at least a processed substrate and a supporting glass substrate for supporting the processed substrate, wherein the supporting glass substrate is the supporting glass substrate described above.
  • the technical characteristics (preferable structure and effect) of the laminate of the present invention overlap with the technical characteristics of the support glass substrate of the present invention. Therefore, in the present specification, detailed description of the overlapping portions is omitted.
  • the laminate of the present invention preferably has an adhesive layer between the processed substrate and the supporting glass substrate.
  • the adhesive layer is preferably a resin, for example, a thermosetting resin, a photocurable resin (particularly an ultraviolet curable resin), or the like.
  • a resin for example, a thermosetting resin, a photocurable resin (particularly an ultraviolet curable resin), or the like.
  • what has the heat resistance which can endure the heat processing in the manufacturing process of a semiconductor package is preferable. Thereby, it becomes difficult to melt
  • an ultraviolet curable tape can also be used as an adhesive layer.
  • the laminate of the present invention further has a release layer between the processed substrate and the supporting glass substrate, more specifically between the processed substrate and the adhesive layer, or between the supporting glass substrate and the adhesive layer. It is preferable to have a layer. If it does in this way, it will become easy to peel a processed substrate from a support glass substrate, after performing predetermined processing processing to a processed substrate. Peeling of the processed substrate is preferably performed with irradiation light such as laser light from the viewpoint of productivity.
  • the laser light source an infrared laser light source such as a YAG laser (wavelength 1064 nm) or a semiconductor laser (wavelength 780 to 1300 nm) can be used.
  • a resin that decomposes when irradiated with an infrared laser can be used for the release layer.
  • a substance that efficiently absorbs infrared rays and converts it into heat can also be added to the resin.
  • carbon black, graphite powder, fine metal powder, dye, pigment or the like can be added to the resin.
  • the peeling layer is made of a material that causes “in-layer peeling” or “interfacial peeling” by irradiation light such as laser light. That is, when light of a certain intensity is irradiated, the bonding force between atoms or molecules in an atom or molecule disappears or decreases, and ablation or the like is caused to cause peeling.
  • the component contained in the release layer is released as a gas due to irradiation of irradiation light, the separation layer is released, and when the release layer absorbs light and becomes a gas, and its vapor is released, resulting in separation There is.
  • the supporting glass substrate is preferably larger than the processed substrate.
  • the method for manufacturing a semiconductor package of the present invention includes a step of preparing a laminate including at least a processed substrate and a supporting glass substrate for supporting the processed substrate, and a step of processing the processed substrate.
  • the glass substrate is the support glass substrate described above.
  • the technical characteristics (preferable structure and effect) of the manufacturing method of the semiconductor package of the present invention overlap with the technical characteristics of the supporting glass substrate and the laminate of the present invention. Therefore, in the present specification, detailed description of the overlapping portions is omitted.
  • the method for manufacturing a semiconductor package of the present invention further includes a step of transporting the stacked body.
  • the processing efficiency of a processing process can be improved.
  • the “process of transporting the laminated body” and the “process of processing the processed substrate” may be performed separately or simultaneously. That is, after the laminate is transported to the processing position and stopped, the processing substrate may be processed, or the processing substrate may be processed while the stack is being transported.
  • the processing is preferably performed by wiring on one surface of the processed substrate or forming solder bumps on one surface of the processed substrate.
  • the processing since the processed substrate is difficult to change in dimensions during these processes, these steps can be appropriately performed.
  • one surface of a processed substrate (usually the surface opposite to the supporting glass substrate) is mechanically polished, and one surface of the processed substrate (usually a supporting glass substrate) Either a process of dry-etching the surface on the opposite side or a process of wet-etching one surface of the processed substrate (usually the surface opposite to the supporting glass substrate) may be used.
  • the processed substrate is unlikely to warp and the rigidity of the stacked body can be maintained. As a result, the above processing can be performed appropriately.
  • the semiconductor package of the present invention is manufactured by the above-described semiconductor package manufacturing method.
  • the technical characteristics (preferable configuration and effect) of the semiconductor package of the present invention overlap with the technical characteristics of the manufacturing method of the supporting glass substrate, the laminate, and the semiconductor package of the present invention. Therefore, in the present specification, detailed description of the overlapping portions is omitted.
  • An electronic device of the present invention is an electronic device including a semiconductor package, and the semiconductor package is the semiconductor package described above.
  • the technical characteristics (preferable configuration and effect) of the electronic device of the present invention overlap with the technical characteristics of the supporting glass substrate, the laminate, the semiconductor package manufacturing method, and the semiconductor package of the present invention. Therefore, in the present specification, detailed description of the overlapping portions is omitted.
  • FIG. 1 is a conceptual perspective view showing an example of a laminate 1 of the present invention.
  • the laminate 1 includes a supporting glass substrate 10 and a processed substrate 11.
  • the supporting glass substrate 10 is attached to the processed substrate 11 in order to prevent a dimensional change of the processed substrate 11.
  • a release layer 12 and an adhesive layer 13 are disposed between the support glass substrate 10 and the processed substrate 11.
  • the peeling layer 12 is in contact with the supporting glass substrate 10, and the adhesive layer 13 is in contact with the processed substrate 11.
  • the laminate 1 is laminated in the order of the supporting glass substrate 10, the release layer 12, the adhesive layer 13, and the processed substrate 11.
  • the shape of the support glass substrate 10 is determined according to the processed substrate 11, in FIG. 1, the shape of the support glass substrate 10 and the processed substrate 11 is a disk shape.
  • the release layer 12 for example, a resin that decomposes when irradiated with a laser can be used. A substance that efficiently absorbs laser light and converts it into heat can also be added to the resin. For example, carbon black, graphite powder, fine metal powder, dye, pigment and the like.
  • the release layer 12 is formed by plasma CVD, spin coating by a sol-gel method, or the like.
  • the adhesive layer 13 is made of a resin, and is applied and formed by, for example, various printing methods, inkjet methods, spin coating methods, roll coating methods, and the like.
  • An ultraviolet curable tape can also be used.
  • the adhesive layer 13 is removed by dissolution with a solvent or the like after the supporting glass substrate 10 is peeled from the processed substrate 11 by the peeling layer 12.
  • the ultraviolet curable tape can be removed with a peeling tape after being irradiated with ultraviolet rays.
  • FIG. 2A to 2G are conceptual cross-sectional views showing manufacturing processes of a fan-out type WLP.
  • FIG. 2A shows a state in which the adhesive layer 21 is formed on one surface of the support member 20. A peeling layer may be formed between the support member 20 and the adhesive layer 21 as necessary.
  • FIG. 2B a plurality of semiconductor chips 22 are pasted on the adhesive layer 21. At that time, the surface on the active side of the semiconductor chip 22 is brought into contact with the adhesive layer 21.
  • FIG. 2C the semiconductor chip 22 is molded with a resin sealing material 23.
  • the sealing material 23 is made of a material having little dimensional change after compression molding and little dimensional change when forming a wiring. Subsequently, as shown in FIGS.
  • the processed substrate 24 on which the semiconductor chip 22 is molded is separated from the support member 20, and then bonded and fixed to the support glass substrate 26 through the adhesive layer 25.
  • the surface of the processed substrate 24 opposite to the surface on which the semiconductor chip 22 is embedded is disposed on the supporting glass substrate 26 side.
  • the laminate 27 can be obtained.
  • a plurality of solder bumps 29 are formed. .
  • the processed substrate 24 is cut for each semiconductor chip 22 and used for a subsequent packaging process.
  • Table 1 shows Examples (Sample Nos. 1 to 22) of the present invention.
  • a glass batch in which glass raw materials were prepared so as to have the glass composition in the table was put in a platinum crucible and melted at 1600 ° C. for 4 hours.
  • the mixture was stirred and homogenized using a platinum stirrer.
  • the molten glass was poured out on a carbon plate, formed into a plate shape, and then gradually cooled from a temperature about 20 ° C. higher than the annealing point to room temperature at 3 ° C./min.
  • the temperature at s, the liquidus temperature TL, the viscosity ⁇ and Young's modulus E at the liquidus temperature TL, and the ultraviolet transmittance T at a wavelength of 300 nm were evaluated.
  • Average thermal expansion coefficient alpha 30 ⁇ 380 in the temperature range of average thermal expansion coefficient ⁇ 20 ⁇ 200, 30 ⁇ 380 °C in the temperature range of 20 ⁇ 200 ° C. is a value measured by a dilatometer.
  • the density ⁇ is a value measured by the well-known Archimedes method.
  • strain point Ps, the annealing point Ta, and the softening point Ts are values measured based on the method of ASTM C336.
  • the temperature at a high temperature viscosity of 10 4.0 dPa ⁇ s, 10 3.0 dPa ⁇ s, and 10 2.5 dPa ⁇ s is a value measured by a platinum ball pulling method.
  • the liquid phase temperature TL is the temperature at which crystals pass after passing through a standard sieve 30 mesh (500 ⁇ m), putting the glass powder remaining on 50 mesh (300 ⁇ m) into a platinum boat and holding it in a temperature gradient furnace for 24 hours. It is the value measured by microscopic observation.
  • the viscosity ⁇ at the liquidus temperature TL is a value obtained by measuring the viscosity of the glass at the liquidus temperature TL by a platinum ball pulling method.
  • the Young's modulus E refers to a value measured by the resonance method.
  • the ultraviolet transmittance T at a wavelength of 300 nm is a value obtained by measuring the spectral transmittance in the plate thickness direction at a wavelength of 300 nm using a double beam spectrophotometer.
  • a plate having a thickness of 0.7 mm and both surfaces polished to an optically polished surface (mirror surface) was used as a measurement sample.
  • the arithmetic surface roughness Ra of this evaluation sample was measured by AFM, it was 0.5 to 1.0 nm in a measurement region of 10 ⁇ m ⁇ 10 ⁇ m.
  • sample No. 1 to 22 are average thermal expansion coefficients ⁇ in the temperature range of 20 to 200 ° C., in which the average thermal expansion coefficient ⁇ 30 to 200 is 66 ⁇ 10 ⁇ 7 / ° C. to 81 ⁇ 10 ⁇ 7 / ° C. and the temperature range of 30 to 380 ° C. ⁇ 30 to 380 was 70 ⁇ 10 ⁇ 7 / ° C. to 84 ⁇ 10 ⁇ 7 / ° C.
  • Sample No. Nos. 1 to 22 have Young's modulus E of 68 GPa or more. 1 to 7 and 15 to 22 had Young's modulus E of 73 GPa or more. Furthermore, sample no. For Nos.
  • sample no. Nos. 1 to 22 are considered to be suitable as supporting glass substrates used for supporting a processed substrate, particularly for bonding, in the manufacturing process of a semiconductor manufacturing apparatus.
  • sample Nos. Listed in Table 1 were used. After preparing the glass raw material so as to have a glass composition of 1 to 14 and 18 to 22, it is supplied to a glass melting furnace and melted at 1500 to 1600 ° C., and then the molten glass is supplied to an overflow downdraw molding apparatus, Each was formed so that the plate thickness was 0.7 mm. After processing the obtained glass substrate (overall plate thickness deviation of about 6.0 ⁇ m) to a thickness of ⁇ 300 mm ⁇ 0.7 mm, both surfaces thereof were polished by a polishing apparatus. Specifically, both surfaces of the glass substrate were sandwiched between a pair of polishing pads having different outer diameters, and both surfaces of the glass substrate were polished while rotating the glass substrate and the pair of polishing pads together.
  • the polishing pad was made of urethane, the average particle size of the polishing slurry used in the polishing treatment was 2.5 ⁇ m, and the polishing rate was 15 m / min.
  • the whole board thickness deviation and curvature amount were measured by Bow / Warp measuring apparatus SBW-331ML / d by Kobelco Kaken. As a result, the overall plate thickness deviation was 0.55 ⁇ m or less, and the warpage amount was 35 ⁇ m or less.
  • glass raw materials are prepared so as to have the glass compositions of Samples 15 to 17 shown in Table 1, and then supplied to a glass melting furnace and melted at 1500 to 1600 ° C. Then, the molten glass is supplied to a float forming apparatus. Then, each was formed so that the plate thickness was 0.8 mm. About the obtained glass substrate, both surfaces were machine-polished and the whole board thickness deviation was reduced to less than 1 micrometer. After processing the obtained glass substrate to ⁇ 300 mm ⁇ 0.8 mm thickness, both surfaces thereof were polished by a polishing apparatus. Specifically, both surfaces of the glass substrate were sandwiched between a pair of polishing pads having different outer diameters, and both surfaces of the glass substrate were polished while rotating the glass substrate and the pair of polishing pads together.
  • the polishing pad was made of urethane, the average particle size of the polishing slurry used in the polishing treatment was 2.5 ⁇ m, and the polishing rate was 15 m / min.
  • the whole board thickness deviation and curvature amount were measured by Bow / Warp measuring apparatus SBW-331ML / d by Kobelco Kaken. As a result, the overall plate thickness deviation was 0.85 ⁇ m or less, and the amount of warpage was 35 ⁇ m or less.

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Abstract

　La présente invention concerne un substrat de support en verre ayant un coefficient moyen de dilatation thermique linéaire compris entre 66 × 10-7/°C et 81 × 10-7/°C dans la plage de température de 20-200 °C.
PCT/JP2015/057092 2014-04-07 2015-03-11 Substrat de support en verre et élément multicouche l'utilisant WO2015156075A1 (fr)

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CN201580014823.2A CN106103369A (zh) 2014-04-07 2015-03-11 支承玻璃基板及使用其的层叠体
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CN202211243838.4A CN115636583A (zh) 2014-04-07 2015-03-11 支承玻璃基板及使用其的层叠体
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WO2016111152A1 (fr) * 2015-01-05 2016-07-14 日本電気硝子株式会社 Substrat de soutien en verre et son procédé de fabrication
WO2016111158A1 (fr) * 2015-01-05 2016-07-14 日本電気硝子株式会社 Plaque en verre et son procédé de fabrication
WO2017104513A1 (fr) * 2015-12-17 2017-06-22 日本電気硝子株式会社 Procédé de fabrication de substrat de support en verre
WO2017104514A1 (fr) * 2015-12-16 2017-06-22 日本電気硝子株式会社 Substrat de support en vitrocéramique, et stratifié mettant en œuvre celui-ci
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JP7172996B2 (ja) * 2017-04-27 2022-11-16 日本電気硝子株式会社 キャリアガラス及びその製造方法
JP7265224B2 (ja) * 2017-07-26 2023-04-26 日本電気硝子株式会社 支持ガラス基板及びこれを用いた積層基板
JP7276644B2 (ja) * 2017-08-31 2023-05-18 日本電気硝子株式会社 支持ガラス基板及びこれを用いた積層基板
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JP2013063880A (ja) * 2011-09-20 2013-04-11 Nippon Electric Glass Co Ltd ガラス板
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JP2022025147A (ja) * 2015-12-17 2022-02-09 日本電気硝子株式会社 支持ガラス基板の製造方法
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JPWO2017104513A1 (ja) * 2015-12-17 2018-10-04 日本電気硝子株式会社 支持ガラス基板の製造方法
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JP7268718B2 (ja) 2015-12-17 2023-05-08 日本電気硝子株式会社 支持ガラス基板の製造方法
WO2017104513A1 (fr) * 2015-12-17 2017-06-22 日本電気硝子株式会社 Procédé de fabrication de substrat de support en verre
CN108367961A (zh) * 2015-12-17 2018-08-03 日本电气硝子株式会社 支承玻璃基板的制造方法
TWI701221B (zh) * 2015-12-17 2020-08-11 日商日本電氣硝子股份有限公司 支持玻璃基板的製造方法及半導體封裝體的製造方法
JP2018095514A (ja) * 2016-12-14 2018-06-21 日本電気硝子株式会社 支持ガラス基板及びこれを用いた積層体
WO2018168342A1 (fr) * 2017-03-13 2018-09-20 日本電気硝子株式会社 Substrat de support en verre cristallisé et stratifié utilisant celui-ci
JP2018150188A (ja) * 2017-03-13 2018-09-27 日本電気硝子株式会社 支持結晶化ガラス基板及びこれを用いた積層体
JPWO2019021911A1 (ja) * 2017-07-26 2020-07-30 Ａｇｃ株式会社 半導体パッケージ用支持ガラス
WO2019021911A1 (fr) * 2017-07-26 2019-01-31 Ａｇｃ株式会社 Verre de support pour boîtiers de semi-conducteurs

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