WO2015132924A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2015132924A1
WO2015132924A1 PCT/JP2014/055714 JP2014055714W WO2015132924A1 WO 2015132924 A1 WO2015132924 A1 WO 2015132924A1 JP 2014055714 W JP2014055714 W JP 2014055714W WO 2015132924 A1 WO2015132924 A1 WO 2015132924A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
protective layer
conductive layer
opening
layer
Prior art date
Application number
PCT/JP2014/055714
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
肇 秋山
岡田　章
欽也 山下
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP2016506030A priority Critical patent/JP6207716B2/ja
Priority to US15/113,818 priority patent/US10192797B2/en
Priority to CN201480076887.0A priority patent/CN106068552A/zh
Priority to PCT/JP2014/055714 priority patent/WO2015132924A1/ja
Priority to KR1020167024445A priority patent/KR20160117597A/ko
Priority to DE112014006443.2T priority patent/DE112014006443T5/de
Publication of WO2015132924A1 publication Critical patent/WO2015132924A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2644—Adaptations of individual semiconductor devices to facilitate the testing thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H01L21/786—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being other than a semiconductor body, e.g. insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2608—Circuits therefor for testing bipolar transistors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device improved in evaluating the electrical characteristics.
  • the installation surface of the object is brought into contact with the surface of the chuck stage by vacuum suction or the like.
  • the contact probe is brought into contact in order to electrically input / output to a surface different from the mounting surface of the object to be measured.
  • the number of pins of the contact probe is increased in accordance with the conventional demand for applying a large current or a high voltage.
  • the partial discharge phenomenon refers to a phenomenon in which a partial discharge occurs, for example, between a contact probe and an object to be measured or between a contact probe.
  • the partial discharge generated in the above evaluation is missed, and the object under test (defective product) that originally generated the partial discharge is judged to be a good product in the above evaluation, it will be transferred to the later process. It is very difficult to extract an object to be measured in which partial discharge has occurred as a defective product. Therefore, it is important to suppress the partial discharge when evaluating the electrical characteristics of the object to be measured, in order not to shift the object to be measured in which the partial discharge has occurred to the subsequent process.
  • the present invention has been made to solve such a problem, and is a semiconductor device capable of suppressing the occurrence of partial discharge at the time of evaluation of electrical characteristics and performing failure analysis from above the object to be measured. Intended to provide.
  • a semiconductor device has at least one or more electrodes, and at least one or more openings provided so as to expose a part of the electrodes, and an opening An insulating protective layer formed to cover the other electrodes, and a conductive layer formed to cover the protective layer and the opening and to be directly connected to the electrode at the opening.
  • an insulation formed to cover at least one or more electrodes and at least one or more openings provided so as to expose a part of the electrodes and covering the electrodes other than the openings.
  • FIG. 1 is a plan view showing an example of a configuration of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 1 is a plan view showing an example of a configuration of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 1 is a plan view showing an example of a configuration of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing a cross section AA of FIG. 4; It is a top view which shows an example of a structure of the semiconductor device by Embodiment 2 of this invention.
  • FIG. 1 is a plan view showing an example of a configuration of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 1 is a plan view showing an example of a configuration of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing a cross section AA of FIG. 4; It is a top view which shows an example of a
  • FIG. 7 is a cross-sectional view showing a cross section BB of FIG. 6;
  • FIG. 18 is a cross sectional view showing an example of a configuration of a semiconductor device according to a third embodiment of the present invention.
  • FIG. 18 is a cross sectional view showing an example of a configuration of a semiconductor device according to a fourth embodiment of the present invention.
  • Embodiment 1 First, the configuration of a semiconductor evaluation apparatus for evaluating the electrical characteristics of a semiconductor device will be described.
  • FIG. 1 is a diagram showing an example of the configuration of a semiconductor evaluation device 2 according to a first embodiment of the present invention.
  • the semiconductor device 1 is described as having a vertical structure in which a large current flows in the Z direction in the drawing, that is, the out-of-plane direction.
  • the semiconductor device 1 is not limited to the vertical structure, and may be a horizontal structure that performs input and output on one side.
  • the semiconductor evaluation device 2 includes a probe base 3, a chuck stage 4, and an evaluation / control unit 5.
  • the probe base 3 and the evaluation / control unit 5 are electrically connected via the connection unit 9 and the signal line 10.
  • the chuck stage 4 and the evaluation / control unit 5 are electrically connected via the connection unit 11 and the signal line 12.
  • the probe base 3 includes an insulating base 6, a contact probe 7, and a connection portion 9.
  • the contact probe 7 is fixed to the insulating substrate 6 and a plurality of contact probes 7 are provided on the assumption that a large current is applied.
  • connection portion 9 is provided to connect the insulating base 6 and the signal line 10.
  • Each contact probe 7 and the connection portion 9 are connected, for example, by a metal plate (not shown) provided on the insulating substrate 6.
  • a through hole 13 is provided in the insulating substrate 6 to perform failure analysis from the upper side of the object during electrical evaluation by infrared spectroscopy or the like, and is used for failure analysis above the through hole 13
  • a camera 14 is installed.
  • the present invention is not limited to the camera 14 and may be anything as long as failure analysis can be performed.
  • the probe base 3 is movable in an arbitrary direction by a movable arm 8.
  • the chuck stage 4 is a pedestal for contacting and fixing the semiconductor device 1 on the surface thereof.
  • a method of fixing the semiconductor device 1 for example, it may be fixed by vacuum suction or may be fixed by electrostatic suction or the like.
  • the evaluation / control unit 5 evaluates the electrical characteristics of the semiconductor device 1. Also, at the time of evaluation, the current or voltage applied to the semiconductor device 1 is controlled.
  • connection portion 9 provided on the insulating substrate 6 and the connection portion 11 provided on the side surface of the chuck stage 4 is substantially the same regardless of which of the contact probes 7. It is provided in such a position.
  • the chuck stage 4 may be moved.
  • an electrode formed on the surface of the semiconductor device 1 contacts the plurality of contact probes 7. Further, the electrode formed on the back surface of the semiconductor device 1 comes in contact with the front surface of the chuck stage 4. In such a state, the electrical characteristics of the semiconductor device 1 are evaluated by applying a current or a voltage to the semiconductor device 1 through the contact probe 7 and the chuck stage 4.
  • FIG. 2 is a plan view showing an example of the configuration of the semiconductor device 1.
  • the semiconductor device 1 is described as one vertical IGBT (Insulated Gate Bipolar Transistor). However, the semiconductor device 1 may be another semiconductor element such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor). It may be.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the semiconductor device 1 has an element region 15 (inside region of broken line in the figure) and a termination region 16 (outside region of broken line in the figure).
  • a desired semiconductor element here, an IGBT is formed.
  • Emitter electrodes 17 and 18 and a gate electrode 19 are formed on the surface of the element region 15 as an electrode pad.
  • the positions and the number of the electrodes are not limited to those shown in FIG.
  • a collector electrode (corresponding to a collector electrode 29 shown in FIG. 5 described later) is formed.
  • the termination region 16 is provided at the outer peripheral portion of the element region 15 in order to maintain the withstand voltage.
  • FIG. 3 is a plan view showing an example of the configuration of the semiconductor device 1 after the protective layers 20, 22 and 24 are formed on the semiconductor device 1 of FIG.
  • the emitter electrode 17 has an opening 21 provided so as to expose a part of the emitter electrode 17, and insulating properties so as to cover the emitter electrode 17 other than the opening 21.
  • the protective layer 20 is formed.
  • An opening 23 is provided on the emitter electrode 18 so as to expose a part of the emitter electrode 18, and an insulating protective layer 22 is formed to cover the emitter electrode 18 other than the opening 23. ing.
  • An opening 25 is provided on the gate electrode 19 so that a part of the gate electrode 19 is exposed, and an insulating protective layer 24 is formed to cover the gate electrode 19 other than the opening 25. ing.
  • each of protective layers 20, 22 and 24 is formed to cover each of emitter electrodes 17 and 18 and gate electrode 19, it may be formed to cover the entire surface of semiconductor device 1. In this case, each of the protective layers 20, 22, 24 is integrally formed.
  • the protective layers 20, 22, 24 are made of a material that is thermally and chemically stable and has excellent insulation performance at the time of the evaluation of the electrical characteristics. Specific examples thereof include, but are not limited to, photoresists and insulating sheet materials (eg, polyimide, Kapton (registered trademark), polyhenylsesquiosaline, polyvinylsilsesquiosaline), etc. .
  • photoresists and insulating sheet materials eg, polyimide, Kapton (registered trademark), polyhenylsesquiosaline, polyvinylsilsesquiosaline), etc. .
  • FIG. 4 is a plan view showing an example of the configuration of the semiconductor device 1 after forming the conductive layers 26 to 28 with respect to the semiconductor device 1 of FIG.
  • FIG. 5 is a cross-sectional view taken along the line AA of FIG. In FIG. 4, the end region is not shown.
  • a conductive layer 26 is formed on the protective layer 20 and the opening 21 so as to cover the protective layer 20 and the opening 21 and to directly connect to the emitter electrode 17 at the opening 21. There is.
  • a conductive layer 27 is formed on the protective layer 22 and the opening 23 so as to cover the protective layer 22 and the opening 23 and to be directly connected to the emitter electrode 18 at the opening 23.
  • a conductive layer 28 is formed on the protective layer 24 and the opening 25 so as to cover the protective layer 24 and the opening 25 and to be directly connected to the gate electrode 19 at the opening 25.
  • the protective layers 20, 22, 24 are separately formed on the emitter electrodes 17, 18, and the gate electrode 19, respectively.
  • the protective layer 20 is formed to the end of the semiconductor device 1, and the conductive layer 26 is formed in a part of the termination region 16. That is, the conductive layer 26 is not formed at the end of the semiconductor device 1. This is to suppress the occurrence of discharge or short circuit between the exposed end surface (side surface) of the semiconductor device 1 and the conductive layer 26.
  • the conductive layer 26 may be formed only in the element region 15 without being formed in the termination region 16. The same applies to the other conductive layers 27 and 28.
  • the conductive layers 26 to 28 are made of a material that is thermally and chemically stable and has excellent electrical conductivity at the time of evaluating the electrical characteristics.
  • a metal film such as aluminum, gold or a compound may be mentioned, but it is not limited thereto.
  • the metal films may contain aluminum as a main component or gold as a main component.
  • the term "main component" refers to a component in which the proportion of the component present in the whole is more prominent than in the non-component, and refers to, for example, a component present in a proportion of several tens of times in excess of the non-component.
  • the conductive layers 26 to 28 may be formed by stacking a plurality of layers. At this time, each layer to be laminated may be made of the same type of material or may be made of different materials. With such a configuration, the effect of securing the electrical conductivity or suppressing the heat generation of the semiconductor device 1 due to the reduction of the current density can be obtained.
  • the formation of the conductive layers 26 to 28 is performed by sputtering or the like.
  • the protective layers 20, 22 and 24 are photoresists
  • sputtering may be performed using a sheet material for the protective layers 20, 22, 24, and using a photoresist as a mask.
  • emitter electrodes 17 and 18 and gate electrode 19 are roughened in order to ensure adhesion and contact between emitter electrodes 17 and 18 and gate electrode 19 and conductive layers 26 to 28. Good.
  • Examples of the method of roughening the surface include a method of performing slight etching on the surface and a method of performing sandblasting on the surface for a short time.
  • the semiconductor device 1 of FIG. 4 is mounted on the chuck stage 4 of FIG. Specifically, the contact probe 7 is brought into contact with part of the conductive layers 26-28. At this time, the plurality of contact probes 7 are in contact with the respective conductive layers 26 to 28. Thereafter, by applying a current or a voltage to the semiconductor device 1, the electrical characteristics of the semiconductor device 1 are evaluated.
  • the protective layers 20, 22, 24 are decomposed and removed or peeled and removed, and the process proceeds to the later step.
  • the conductive layers 26 to 28 are also removed simultaneously.
  • the protective layers 20, 22 and 24 are photoresists
  • the photoresists are decomposed and removed in an ashing process, and then cleaning is performed as necessary.
  • the protective layers 20, 22 and 24 are sheet materials, basically peeling and removing are performed, but without peeling and removing, the process proceeds to a mounting process which is a post process, and the discharge preventing effect is maintained. Good.
  • the protective layers 20, 22, 24 are sheet materials having an adhesive layer (for example, a sheet material made of Kapton), the attachment and detachment are easy.
  • the occurrence of partial discharge can be suppressed at the time of evaluation of the electrical characteristics of the semiconductor device 1.
  • processing in a normal process can be performed, so cost reduction can be achieved.
  • the position of the contact probe 7 can be moved to the end of the semiconductor device 1 while suppressing partial discharge, failure analysis from above the semiconductor device 1 becomes easy.
  • the semiconductor device 1 may be a wafer. That is, the semiconductor device 1 may be a wafer having a plurality of sets of the emitter electrodes 17 and 18, the gate electrode 19, the protective layers 20, 22 and 24, and the conductive layers 26 to 28. In this case, effects such as shortening of evaluation time, improvement of throughput, and reduction of test cost can be obtained.
  • the present invention is not limited to this. Since the emitter electrodes 17 and 18 basically have the same potential, the conductive layers 26 and 27 may be formed integrally over the emitter electrodes 17 and 18. In this case, selection of the formation region of the conductive layer is facilitated, and an effect of facilitating processing in the step of forming the conductive layer is obtained.
  • the second embodiment of the present invention is characterized in that a plurality of openings and a conductive layer are formed corresponding to each contact probe 7 of FIG.
  • the other configuration is the same as that of the first embodiment (see FIG. 4), and thus the description thereof is omitted here.
  • FIG. 6 is a plan view showing an example of the configuration of the semiconductor device 1 according to the second embodiment.
  • FIG. 7 is a cross-sectional view taken along the line BB in FIG.
  • the emitter electrode 17 has three openings 21 provided so as to expose a part (three places) of the emitter electrode 17, and the emitter electrodes other than the respective openings 21.
  • a protective layer 20 is formed to cover 17.
  • three conductive layers 26 are formed on the protective layer 20 and the respective openings 21 so as to cover the protective layer 20 and the respective openings 21 and to be directly connected to the emitter electrode 17 in the respective openings 21. There is. That is, the conductive layer 26 is separately formed for each opening 21.
  • a protective layer is provided on the emitter electrode 18 so as to have three openings 23 provided so as to expose a part (three places) of the emitter electrode 18 and to cover the emitter electrode 18 other than the respective openings 23. 22 are formed.
  • a conductive layer 27 is formed on the protective layer 22 and each opening 23 so as to cover the protective layer 22 and each opening 23 and to be directly connected to the emitter electrode 18 in each opening 23. That is, the conductive layer 27 is separately formed for each opening 23.
  • the configuration of the gate electrode 19 is the same as that of the first embodiment.
  • the semiconductor device 1 of FIG. 6 is mounted on the chuck stage 4 of FIG. Specifically, the contact probe 7 is brought into contact with part of the conductive layers 26-28. At this time, one contact probe 7 contacts each of the conductive layers 26 to 28. Thereafter, by applying a current or a voltage to the semiconductor device 1, the electrical characteristics of the semiconductor device 1 are evaluated.
  • the present invention is not limited to this.
  • the number of openings may be changed to correspond to the number of contact probes to be changed depending on the size of each electrode in the semiconductor device, the size of the applied current, and the like.
  • the second embodiment it is possible to more effectively suppress the partial discharge generated in the vicinity of each contact probe 7 and between the contact probes 7. Further, since the current distribution in the semiconductor device 1 to which the current is applied can be made uniform at the time of the evaluation of the electrical characteristics, the heat generation of the semiconductor device 1 can be suppressed.
  • Embodiment 3 The third embodiment of the present invention is characterized in that the protective film is formed by laminating a plurality of layers.
  • the other configuration is the same as that of Embodiment 1 (see FIG. 4) or Embodiment 2 (see FIG. 6), and thus the description thereof is omitted here.
  • FIG. 8 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the third embodiment. 8 shows a cross section of the region where the emitter electrode 17 is formed (A-A cross section in FIG. 4 and a B-B cross section in FIG. 7), and the conductive layer 26 and the termination region 16 are illustrated. Is omitted.
  • the emitter electrode 17 has an opening 21 provided to expose a part of the emitter electrode 17, and a protective layer so as to cover the emitter electrode 17 other than the opening 21. 20 and a protective layer 30 are formed in layers.
  • the protective layer 20 and the protective layer 30 are formed such that the protective layer 30 (upper layer) covers the protective layer 20 (lower layer) on the inner side surface of the opening 21.
  • the protective layer 20 and the protective layer 30 may be made of the same type of material or may be made of different materials.
  • the protective layer 20 may be a sheet material
  • the protective layer 30 may be a photoresist, and after the evaluation of the electrical characteristics, only the protective layer 30 may be removed, and the subsequent steps may be performed with the protective layer 20 remaining. By doing this, it becomes effective when performing wire bonding in a post process that requires a larger opening.
  • the protective layer formed later should just be a structure which covers the protective layer formed previously. With such a configuration, the conductive layer to be formed later can be easily formed without interruption.
  • the region in which the emitter electrode 17 is formed is described above as an example, the other electrodes have the same configuration.
  • the fourth embodiment of the present invention is characterized in that the protective layer formed in the vicinity of the termination region is formed of a plurality of layers.
  • the other configuration is the same as that of Embodiment 1 (see FIG. 4) or Embodiment 2 (see FIG. 6), and thus the description thereof is omitted here.
  • FIG. 9 is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the fourth embodiment.
  • FIG. 9 shows a cross section (corresponding to the cross section AA in FIG. 4 and the cross section BB in FIG. 7) of the region where the emitter electrode 17 is formed.
  • the protective layer 20 and the protective layer 31 are formed to be stacked.
  • the region where the emitter electrode 17 is formed has been described above as an example, the other electrodes have the same configuration.
  • the side surface of the semiconductor device 1 and the conductive layer 26 are further separated (the distance between the semiconductor device 1 and the conductive layer 26 is further extended). A discharge or a short circuit generated between the conductive layer 26 can be further suppressed.
  • the embodiment can be appropriately modified or omitted.
  • Reference Signs List 1 semiconductor device, 2 semiconductor evaluation device, 3 probe base, 4 chuck stage, 5 evaluation / control unit, 6 insulating base, 7 contact probe, 8 moving arm, 9 connection part, 10 signal line, 11 connection part, 12 signal Wire, 13 through holes, 14 cameras, 15 element regions, 16 terminal regions, 17, 18 emitter electrodes, 19 gate electrodes, 20 protective layers, 21 openings, 22 protective layers, 23 openings, 24 protective layers, 25 openings , 26-28 conductive layer, 29 collector electrode, 30 protective layer.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
PCT/JP2014/055714 2014-03-06 2014-03-06 半導体装置 WO2015132924A1 (ja)

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JP2016506030A JP6207716B2 (ja) 2014-03-06 2014-03-06 半導体装置
US15/113,818 US10192797B2 (en) 2014-03-06 2014-03-06 Semiconductor device and electrical contact structure thereof
CN201480076887.0A CN106068552A (zh) 2014-03-06 2014-03-06 半导体装置
PCT/JP2014/055714 WO2015132924A1 (ja) 2014-03-06 2014-03-06 半導体装置
KR1020167024445A KR20160117597A (ko) 2014-03-06 2014-03-06 반도체 장치
DE112014006443.2T DE112014006443T5 (de) 2014-03-06 2014-03-06 Halbleitervorrichtung

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JP6207716B2 (ja) 2017-10-04
US20160343627A1 (en) 2016-11-24
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US10192797B2 (en) 2019-01-29
CN106068552A (zh) 2016-11-02
KR20160117597A (ko) 2016-10-10

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