WO2015015937A1 - Procédé de production de dispositif à semi-conducteurs en carbure de silicium - Google Patents

Procédé de production de dispositif à semi-conducteurs en carbure de silicium Download PDF

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WO2015015937A1
WO2015015937A1 PCT/JP2014/066265 JP2014066265W WO2015015937A1 WO 2015015937 A1 WO2015015937 A1 WO 2015015937A1 JP 2014066265 W JP2014066265 W JP 2014066265W WO 2015015937 A1 WO2015015937 A1 WO 2015015937A1
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alignment mark
epitaxial layer
silicon carbide
protective film
semiconductor device
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PCT/JP2014/066265
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English (en)
Japanese (ja)
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秀人 玉祖
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住友電気工業株式会社
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Definitions

  • the present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a method for manufacturing a silicon carbide semiconductor device using a silicon carbide substrate including a main surface having an off angle.
  • a method for manufacturing a semiconductor device includes a plurality of steps.
  • steps in processes that require alignment of the substrate to form a device pattern on the main surface of the substrate, such as lithography and ion implantation, alignment marks formed on the main surface in the previous step Use and align. Thereby, it is possible to suppress the occurrence of positional deviation in the device pattern formed in each step, and a semiconductor device having a fine device pattern can be obtained.
  • Japanese Patent Application Laid-Open No. 2011-1000092 discloses an SiC semiconductor device including a step of forming a trench serving as an alignment mark in a silicon carbide substrate, growing an epitaxial layer, and then placing a mask on the silicon carbide substrate using the alignment mark.
  • a manufacturing method is disclosed.
  • the alignment mark is formed as a trench having a polygonal shape in which the shape of the opening is symmetric with respect to the off direction and the apex is located at the most downstream side in the off direction.
  • the silicon carbide substrate used in the method for manufacturing the silicon carbide semiconductor device includes a main surface having an off angle with respect to the ⁇ 0001 ⁇ plane
  • the alignment mark formed on the main surface is epitaxially grown before the epitaxial growth step. In some cases, sufficient alignment accuracy cannot be obtained when used for alignment after the process.
  • the semiconductor manufacturing apparatus may not be able to accurately recognize the deformed alignment mark, or the semiconductor manufacturing apparatus may not be able to recognize the deformed alignment mark.
  • the present invention has been made to solve the above-described problems.
  • the main object of the present invention is to enable precise alignment before and after the step of forming an epitaxial layer in a method for manufacturing a silicon carbide semiconductor device using a silicon carbide substrate having a main surface having an off angle.
  • An object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device.
  • a step of preparing a silicon carbide substrate including a main surface having an off angle with respect to the ⁇ 0001 ⁇ plane, and forming the first alignment mark 1 on the main surface A step of forming a protective film for protecting the first alignment mark 1, a step of forming an epitaxial layer on the main surface in a state where the protective film is formed, and a step of using the first alignment mark 1. And a step of processing the epitaxial layer.
  • FIG. 3 is a flowchart of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • 5 is a schematic plan view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 5 is a schematic plan view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • 5 is a flowchart of a method for manufacturing a silicon carbide semiconductor device according to a second embodiment.
  • FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 11 is a cross sectional view for illustrating a modification of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment and the second embodiment.
  • a method for manufacturing a silicon carbide semiconductor device includes a step (S10) of preparing a silicon carbide substrate including first main surface 10a having an off angle with respect to a ⁇ 0001 ⁇ plane.
  • the step of forming the first alignment mark 1 on the first main surface 10a (S20), the step of forming the protective film 30 that protects the first alignment mark 1 (S30), and the formation of the protective film 30 In this state, an epitaxial layer (second epitaxial layer) is formed by using the first alignment mark 1 and a step (S40) of forming an epitaxial layer (second epitaxial layer 12) on the first main surface 10a.
  • the first alignment mark 1 formed on the first main surface 10a having an off angle with respect to the ⁇ 0001 ⁇ plane is a step of forming an epitaxial layer (second epitaxial layer 12).
  • step flow growth proceeds with respect to the first alignment mark 1 and is formed on the first alignment mark 1.
  • the shape of the upper surface of the epitaxial layer can be prevented from being deformed to a shape different from the shape of the first alignment mark 1.
  • step (S50) of processing the epitaxial layer (second epitaxial layer 12) performed after the step (S40) the first alignment mark 1 is used for precise alignment.
  • the first alignment mark 1 is used to place an etching mask at a predetermined position on the second main surface 12a. Can be formed.
  • the etching mask formed in this manner is suppressed in positional deviation with respect to the pattern formed on the first main surface 10a before the step (S40). That is, according to the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, precise alignment can be performed before and after the step of forming the epitaxial layer (second epitaxial layer 12). Therefore, in the method for manufacturing the silicon carbide semiconductor device, it is not necessary to limit the process conditions, order, and the like of the step (S40) of forming the epitaxial layer (second epitaxial layer 12) from the viewpoint of alignment.
  • the step (S50) of processing the epitaxial layer (second epitaxial layer 12) is performed after removing the protective film 30. May be.
  • the first alignment mark 1 is protected by the protective film 30 in the step (S40) of forming the epitaxial layer (second epitaxial layer 12). Step flow growth does not progress. Therefore, in the step (S50) of processing the epitaxial layer (second epitaxial layer 12), the first alignment mark 1 that maintains the shape during the step (S30) of forming the protective film 30 is used. Thus, alignment can be performed. As a result, in the step (S50), for example, the first alignment mark 1 is used before the step (S30) to precisely align the pattern formed on the first main surface 10a. Can do.
  • the first alignment mark 1 protects the step (S50) of processing the epitaxial layer (second epitaxial layer 12). You may implement in the state protected by the film
  • an uneven mark corresponding to the shape of the first alignment mark 1 is formed on the upper surface of the protective film 30, and no epitaxial layer is formed on the upper surface of the protective film 30. Therefore, in the step of forming the epitaxial layer (second epitaxial layer 12) (S40), the first alignment mark 1 is protected by the protective film 30, so that step flow growth is performed on the first alignment mark 1. Does not progress. Therefore, in the step (S50) of processing the epitaxial layer (second epitaxial layer 12), the first alignment mark 1 that maintains the shape during the step (S30) of forming the protective film 30 is used. Thus, alignment can be performed.
  • the first alignment mark 1 protected by the protective film 30 is used on the first main surface 10a. Precise alignment can be performed on the formed pattern.
  • the first alignment mark 1 is used for the silicon carbide substrate 10 before the step (S30) of forming the protective film 30.
  • the process (S25) which performs a process may be further provided.
  • the step (S30) of forming protective film 30 protecting first alignment mark 1 and the epitaxial layer (second epitaxial layer 12) are formed.
  • the process for the silicon carbide substrate 10 that uses the first alignment mark 1 (S25) and the process for the epitaxial layer (second epitaxial layer 12) are performed.
  • step (S50) Even in this case, as described above, since the first alignment mark 1 is protected by the protective film 30 in the step (S40), the step flow growth thereon is prevented. Therefore, in the step (S25) and the step (S50) (that is, before and after the step (S40)), precise alignment can be performed using the first alignment mark 1.
  • the second alignment mark is formed on the first main surface 10a before the step (S20) of forming the first alignment mark 1.
  • the protective film 30 that protects at least the first alignment mark 1 may be formed. Good.
  • the first alignment mark 1 used in the step (S50) of processing the epitaxial layer (second epitaxial layer 12) is the second alignment on the first main surface 10a.
  • the mark is formed using the second alignment mark (step (step ( S20)).
  • the first alignment mark 1 is protected by the protective film 30 in the step (S30).
  • step flow growth proceeds with respect to the first alignment mark 1, and the first alignment mark 1 is It is possible to suppress the shape of the upper surface of the epitaxial layer formed in the step from being deformed to a shape different from the shape of the first alignment mark 1. Therefore, the pattern formed by using the first alignment mark 1 in the step (S50) is misaligned with the pattern formed by using the second alignment mark before the step (S40). Is suppressed. In other words, it is used in the step (S17) for processing the silicon carbide substrate and the step (S50) for processing the epitaxial layer (second epitaxial layer 12) performed before and after the step (S40).
  • step (S30) of forming the protective film 30 by forming the protective film 30 that protects at least the first alignment mark 1 used in the step (S50).
  • step (S17) and the step (S50) precise alignment can be performed.
  • the material forming protective film 30 may include tantalum carbide (TaC x ) or a carbon material.
  • the protective film 30 can have a high melting point. Therefore, the protective film 30 protects the first alignment mark 1 also in the step (S40) of forming an epitaxial layer (second epitaxial layer 12) performed under a temperature condition of, for example, about 1500 ° C. to 1700 ° C. Thus, it is possible to suppress the step-flow growth of the epitaxial layer on the first alignment mark 1. That is, in this way, silicon carbide does not grow on protective film 30. Therefore, even when the step (S50) of processing the epitaxial layer (second epitaxial layer 12) is performed in a state where the first alignment mark 1 is protected by the protective film 30, the second of the silicon carbide substrate.
  • the first alignment mark 1 is easily detected when the main surface 12a is viewed in plan (when the second main surface 12a is viewed from above along the direction perpendicular to the second main surface 12a). Can do.
  • the carbon material for example, diamond or graphite may be used.
  • protective film 30 in the step of forming protective film 30 (S30), in the step of forming epitaxial layer (second epitaxial layer 12) (S40) A protective film 30 having a thickness of 0.5 to 1.5 times the thickness of the formed epitaxial layer (second epitaxial layer 12) may be formed.
  • the epitaxial layer (second epitaxial layer 12) projects over the protective film 30. May grow (overhang). In this case, foreign matter or the like tends to accumulate in a region surrounded by the epitaxial layer (second epitaxial layer 12) grown so as to overhang the protective film 30. Further, the overhanging epitaxial layer (second epitaxial layer 12) may be a starting point of film peeling of a film formed on the second main surface 12a thereafter.
  • the thickness of the protective film 30 is 0.5 times or more the thickness of the epitaxial layer (second epitaxial layer 12), the epitaxial layer (second epitaxial layer 12) overlies the protective film 30. Hang can be suppressed. Furthermore, it is possible to suppress the occurrence of abnormality due to the overhang of the epitaxial layer (second epitaxial layer 12). Moreover, when the thickness of the protective film 30 is thicker than the thickness of the epitaxial layer (second epitaxial layer 12), the above-described overhang of the epitaxial layer (second epitaxial layer 12) can be reliably prevented.
  • the thickness of the protective film 30 exceeds 1.5 times the thickness of the epitaxial layer (second epitaxial layer 12), it is thicker than necessary from the viewpoint of preventing overhang, and the epitaxial layer (first Depending on the thickness of the second epitaxial layer 12), the processing of the protective film 30 becomes difficult. Therefore, if the thickness of the protective film 30 is 0.5 to 1.5 times the thickness of the epitaxial layer (second epitaxial layer 12), an overhang of the epitaxial layer (second epitaxial layer 12) is prevented. In addition, the protective film 30 can be easily processed.
  • the first alignment mark 1 and the second alignment mark are generic names including a plurality of alignment marks formed on the main surfaces 10a and 12a of the silicon carbide substrate in one step.
  • a plurality of first alignment marks 1 are formed on the dicing line on the first main surface 10a.
  • a reticle pattern corresponding to the first alignment mark 1 is formed on the reticle, and the number of the first alignment marks 1 is about the number of shots.
  • "using the first alignment mark 1" is formed on the first main surface 10a in the step (S20).
  • a necessary and sufficient number of first alignment marks 1 formed at positions effective for aligning the silicon carbide substrate can be extracted and used for alignment. Contains.
  • “using the first alignment mark 1” means a step of processing the silicon carbide substrate 10.
  • a necessary and sufficient number of first alignment marks formed at positions effective for aligning the silicon carbide substrate It also includes detecting only one alignment mark 1 and using it for alignment.
  • the first alignment mark 1 used for alignment in the step (S25) and the step (S50) needs to be the same alignment mark formed at the same position on the first main surface 10a. Alternatively, different first alignment marks 1 formed at different positions may be used for alignment.
  • the step (S25) and The alignment accuracy (superposition accuracy) with the step (S50) can be increased.
  • an LSA Laser Step Alignment
  • FIA Field Image Alignment
  • Either method is applicable. That is, according to the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, as described above, it is possible to prevent the epitaxial layer from growing in the step flow on the alignment mark, so that the alignment mark is deformed. Can be prevented.
  • the laser is applied to the alignment mark, the reflected light of the laser is analyzed and alignment is performed, and the LIA method (optical alignment method) that performs alignment, or the FIA method that recognizes the edge of the image recognized by the camera and performs alignment (image recognition) Method), the alignment mark can be detected with high accuracy even after the epitaxial layer (second epitaxial layer 12) is formed.
  • the silicon carbide substrate according to the present embodiment may be an epitaxial substrate in which an epitaxial layer is formed on a base substrate such as a single crystal substrate, or an epitaxial layer in which the base substrate is removed from the epitaxial substrate. May be.
  • silicon carbide substrate 10 including first main surface 10a having an off angle with respect to the ⁇ 0001 ⁇ plane is prepared (step (S10)).
  • Silicon carbide substrate 10 is an epitaxial substrate having a silicon carbide single crystal substrate 80 and a first epitaxial layer 81 a made of silicon carbide formed on silicon carbide single crystal substrate 80.
  • First epitaxial layer 81a has, for example, an n-type conductivity and an impurity concentration of about 4 ⁇ 10 15 cm ⁇ 3 .
  • first main surface 10a is included in first epitaxial layer 81a.
  • the first major surface 10a is a ⁇ 0001 ⁇ plane and off only off direction a 1 off angle ⁇ from (surface indicated by the broken line) (inclined) surface.
  • the off angle ⁇ is preferably an angle of 1 ° to 8 °.
  • the first major surface 10a is from the ⁇ 0001 ⁇ plane so that the normal vector z of the first major surface 10a has at least one component of ⁇ 11-20> and ⁇ 1-100>. It is a surface that has been turned off.
  • the first main surface 10a is a surface off from the ⁇ 0001 ⁇ plane so that the normal vector z of the first main surface 10a has a component of ⁇ 11-20>.
  • direction c is the [0001] direction (that is, the c-axis of hexagonal silicon carbide), and direction a 1 is, for example, the ⁇ 11-20> direction.
  • the normal vector z of the first major surface 10a is inclined in the ⁇ 11-20> direction from the [0001] direction.
  • direction a 11 in which the orientation flat (OF: see FIG. 4) extends is, for example, the ⁇ 1-100> direction.
  • the first alignment mark 1 is formed on the first main surface 10a (step (S20)).
  • resist mask 20 is formed on first main surface 10a
  • first alignment mark 1 is formed using resist mask 20 as an etching mask.
  • First alignment mark 1 is formed by etching first epitaxial layer 81a of silicon carbide substrate 10 exposed in the opening of resist mask 20 by a dry etching method such as a reactive ion etching (RIE) method. , Provided by forming a stepped portion with respect to the first main surface 10a. That is, as shown in FIG.
  • RIE reactive ion etching
  • the first alignment mark 1 includes a first convex portion 1a including the first main surface 10a, and a first concave portion 1b having an opening in the first main surface 10a. And so as to include.
  • the depth of the first recess 1b with respect to the first main surface 10a is, for example, about 0.5 ⁇ m to 2 ⁇ m, preferably about 0.7 ⁇ m to 1.5 ⁇ m, and more preferably 0.7 ⁇ m or more. It is about 1.0 ⁇ m or less.
  • the resist mask 20 is removed by an arbitrary method after forming the first alignment mark 1.
  • first alignment mark 1 may be formed on dicing line 102 formed on first main surface 10 a of silicon carbide substrate 10.
  • the dicing line 102 is a position where cutting is planned when a plurality of semiconductor devices are formed on the silicon carbide substrate 10 and then separated into individual semiconductor devices in the dicing process. That is, the dicing lines 102, for example, the direction a 11 parallel to the direction in which the orientation flat extends, a plurality of dicing lines may be formed along the respective perpendicular direction a 12 in the direction a 11.
  • a plurality of semiconductor device formation regions 101 may be formed so as to be surrounded by the dicing lines 102.
  • the first convex portion 1a of the first alignment mark 1 may be formed in a rectangular shape having, for example, a longitudinal direction and a lateral direction when viewed in plan.
  • the longitudinal direction of the 1st convex part 1a may be formed in parallel with the direction where the dicing line 102 is extended, and may be formed so that it may cross
  • the length L1 in the longitudinal direction of the first protrusion 1a is, for example, 80 ⁇ m, and the length in the short direction of the first protrusion 1a is, for example, 9 ⁇ m.
  • the width L3 of the dicing line 102 in the direction perpendicular to the direction in which the dicing line 102 extends is, for example, 120 ⁇ m.
  • FIG. 6 is a cross-sectional view taken along line VI-VI in FIG.
  • step (S25) processing is performed on silicon carbide substrate 10 (step (S25)).
  • an ion implantation mask (not shown) is formed on first main surface 10a using first alignment mark 1, and the first alignment mark 1 is used to form the first alignment mark 1 through the ion implantation mask.
  • the ion-implanted region 11 is formed at a predetermined position on the first epitaxial layer 81a in the formation region 101 of the semiconductor device.
  • Ion implantation region 11 has, for example, a p-type conductivity and an impurity concentration of about 1 ⁇ 10 17 cm ⁇ 3 .
  • a protective film 30 is formed to protect the first alignment mark 1 (step (S30)) Specifically, referring to Fig. 8, first, on first main surface 10a of silicon carbide substrate 10. A protective film 30 is formed on the protective film 30.
  • the material constituting the protective film 30 is, for example, tantalum carbide (TaC) or a carbon material, which may be any material containing carbon atoms, such as graphite or diamond.
  • the thickness h1 (see FIG. 9) of the protective film 30 may be determined according to the thickness h2 (see FIG. 10) of the second epitaxial layer 12 to be formed in the subsequent step S40.
  • the thickness h1 is preferably 0.5 times or more and 1.5 times or less than the thickness h2 of the second epitaxial layer 12.
  • the thickness of the protective film 30 is set. 1 is provided so as to be equal to the thickness h2 of the second epitaxial layer 12.
  • the protective film 30 formed on the region for forming the second epitaxial layer 12 in the subsequent step (S40) is removed.
  • a resist mask 35 is formed on the protective film 30, and the protective film 30 is patterned using the resist mask 35 as an etching mask.
  • the resist mask 35 is removed by an arbitrary method.
  • second epitaxial layer 12 is formed (step (S40)). Specifically, referring to FIG. 10, second epitaxial layer 12 is formed on first main surface 10 a of silicon carbide substrate 10 after ion implantation region 11 is formed in first epitaxial layer 81 a. It is formed. Second epitaxial layer 12 has an n-type conductivity, for example, and an impurity concentration of about 7 ⁇ 10 15 cm ⁇ 3 . At this time, the second epitaxial layer 12 is formed on the first main surface 10a having an off angle by performing step flow growth. On the other hand, step flow growth does not occur on the protective film 30 (on the first alignment mark 1 protected by the protective film 30), and the second epitaxial layer 12 does not grow. Therefore, the pattern shape of the first alignment mark 1 and the pattern shape of the protective film 30 formed so as to cover the pattern shape of the first alignment mark 1 are suppressed from being deformed by step flow growth.
  • the second epitaxial layer 12 includes a second main surface 12a and a back surface 12b that is located opposite to the second main surface 12a and is in contact with the first main surface 10a in a region where the protective film 30 is not formed. Including. In the present embodiment, the thickness h2 of the second epitaxial layer 12 is equivalent to the thickness h1 of the protective film 30 as described above.
  • FIG. 12 is a cross-sectional view of the formation region 101 of the semiconductor device after the second epitaxial layer 12 is formed in this step (S40). By this step (S40), ion implantation region 11 is embedded in silicon carbide substrate 10 (first epitaxial layer 81a) and second epitaxial layer 12. In this step (S40), after forming the second epitaxial layer 12, the protective film 30 protecting the first alignment mark 1 may be removed as shown in FIG.
  • the second epitaxial layer 12 is processed (step (S50)). Specifically, referring to FIG. 13, first, ions are implanted into second main surface 12a to form p base layer 82 and n on second epitaxial layer 12 in formation region 101 of the semiconductor device. Region 83 is formed. Next, referring to FIG. 14, an ion implantation mask (not shown) is formed on second main surface 12 a using first alignment mark 1. Next, the p contact region 84 is formed on the p base layer 82 by implanting ions into the second major surface 12a through the ion implantation mask. As described above, the detection method of the first alignment mark 1 may be either the LSA method or the FIA method.
  • an impurity for imparting p-type such as aluminum (Al)
  • Al aluminum
  • an impurity such as phosphorus (P) for imparting n-type is ion-implanted.
  • the temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C.
  • the heat treatment time is, for example, about 30 minutes.
  • the atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an Ar atmosphere.
  • a trench having an opening in the second main surface 12a is formed.
  • mask layer 40 having an opening is formed on main surface 12 a formed of n region 83 and p contact region 84.
  • As mask layer 40 for example, a silicon oxide film or the like can be used.
  • the opening is formed corresponding to the position of trench TR (see FIG. 19).
  • the mask layer 40 uses a second alignment mark different from the first alignment mark 1 formed on the first alignment mark 1 or the second epitaxial layer 12, and the position corresponding to the opening is exposed. It may be formed in an aligned manner.
  • n region 83, p base layer 82, and part of second epitaxial layer 12 are removed by etching in the opening of mask layer 40.
  • etching method for example, reactive ion etching (RIE), particularly inductively coupled plasma (ICP) RIE can be used.
  • ICP-RIE using SF 6 or a mixed gas of SF 6 and O 2 as a reaction gas can be used.
  • thermal etching is performed in the recess TQ.
  • the thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms.
  • the at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom.
  • This atmosphere is, for example, Cl 2 , BCL 3 , SF 6 , or CF 4 .
  • thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and a heat treatment temperature of, for example, 700 ° C. or more and 1000 ° C. or less.
  • the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas.
  • a carrier gas for example, nitrogen (N 2 ) gas, argon gas, helium gas or the like can be used.
  • N 2 nitrogen
  • argon gas argon gas
  • helium gas helium gas or the like
  • the heat treatment temperature is set to 700 ° C. or higher and 1000 ° C. or lower as described above
  • the etching rate of silicon carbide is about 70 ⁇ m / hour, for example.
  • the mask layer 40 made of silicon oxide has a very high selectivity with respect to silicon carbide, and therefore is not substantially etched during the etching of silicon carbide.
  • a trench TR is formed on the upper surfaces of the first epitaxial layer 81a and the second epitaxial layer 12 by the thermal etching described above.
  • Trench TR has side wall surface SW passing through n region 83 and p base layer 82 to second epitaxial layer 12, and bottom surface BT located on second epitaxial layer 12.
  • Each of sidewall surface SW and bottom surface BT is separated from ion implantation region 11.
  • the mask layer 40 is removed by an arbitrary method such as etching.
  • Gate oxide film 91 covering each of the sidewall surface SW and the bottom surface BT of the trench TR is formed.
  • Gate oxide film 91 can be formed, for example, by thermal oxidation. Thereafter, NO annealing using nitrogen monoxide (NO) gas as the atmospheric gas may be performed.
  • NO nitrogen monoxide
  • the temperature profile has, for example, conditions of a temperature of 1100 ° C. to 1300 ° C. and a holding time of about 1 hour. Thereby, nitrogen atoms are introduced into the interface region between gate oxide film 91 and p base layer 82. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved.
  • a gas other than NO gas may be used as the atmospheric gas.
  • Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing.
  • the heating temperature for Ar annealing is preferably higher than the heating temperature for NO annealing and lower than the melting point of the gate oxide film 91.
  • the time during which this heating temperature is maintained is, for example, about 1 hour. Thereby, the formation of interface states in the interface region between gate oxide film 91 and p base layer 82 is further suppressed.
  • other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.
  • Sidewall surface SW of trench TR has a plane orientation ⁇ 0-33-8 ⁇ , and may preferably include a predetermined plane having a plane orientation (0-33-8).
  • a gate electrode 92 is formed on the gate oxide film 91.
  • gate electrode 92 is formed on gate oxide film 91 so as to fill the region inside trench TR with gate oxide film 91 interposed therebetween.
  • the gate electrode 92 can be formed, for example, by film formation of conductor or doped polysilicon and CMP (Chemical Mechanical Polishing).
  • an interlayer insulating film 93 is formed on gate electrode 92 and gate oxide film 91 so as to cover the exposed surface of gate electrode 92. Thereafter, etching is performed so that openings are formed in the interlayer insulating film 93 and the gate oxide film 91. Through this opening, each of n region 83 and p contact region 84 is exposed on upper surface P2. Next, source electrode 94 in contact with each of n region 83 and n contact region 84 is formed on upper surface P2. Drain electrode 98 is formed on lower surface P ⁇ b> 1 made of first epitaxial layer 81 a through silicon carbide single crystal substrate 80.
  • a source wiring layer 95 is formed.
  • the silicon carbide substrate 10, the second epitaxial layer 12, the gate oxide film 91, the gate electrode 92, the interlayer insulating film 93, the source electrode 94, the source wiring layer 95, and the drain electrode 98 are formed.
  • MOSFET 100 as a silicon carbide semiconductor device is completed.
  • Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 80, a first epitaxial layer 81 a, and an ion implantation region 11.
  • Second epitaxial layer 12 includes a p base layer 82, an n region 83, and a p contact region 84.
  • first alignment mark 1 formed on first main surface 10a having an off angle with respect to the ⁇ 0001 ⁇ plane is formed by second epitaxial layer 12 It is protected by the protective film 30 in the step of forming (S40). For this reason, in the step of forming the second epitaxial layer 12 (S40), it is possible to prevent the first alignment mark 1 from undergoing step flow growth and the shape of the first alignment mark 1 from being deformed. it can. As a result, the first alignment mark 1 is used also in the step (S50) of processing the second epitaxial layer 12 performed after the step (S40) of forming the second epitaxial layer 12. Precise alignment can be performed.
  • the step (S50) of processing the second epitaxial layer 12 is performed after removing the protective film 30.
  • the process (S50) which processes with respect to the 2nd epitaxial layer 12 since it protected by the protective film 30 in the process (S40) of forming the 2nd epitaxial layer 12, it is a step on that Position alignment can be performed using the first alignment mark 1 that is not flow-grown and maintains the shape during the step of forming the protective film 30 (S30).
  • the first main surface is used by using the first alignment mark 1 before the step (S30) of forming the protective film 30, for example. Precise alignment can be performed on the pattern formed on 10a.
  • silicon carbide substrate 10 is utilized using first alignment mark 1 before the step of protecting first alignment mark 1 (S30).
  • the process (S25) which performs a process with respect to is provided. That is, before and after the step of forming the second epitaxial layer 12 (S40), the step of processing the silicon carbide substrate 10 using the first alignment mark 1 (S25) and the second epitaxial layer. And a step (S50) of processing the layer 12.
  • step (S25) and the step (S50) that is, before and after the step (S40)
  • precise alignment can be performed using the first alignment mark 1.
  • the material forming protective film 30 includes TaC. Therefore, also in the step (S40) of forming the second epitaxial layer 12 performed under a temperature condition of, for example, 1500 ° C. or more and 1700 ° C. or less, the protective film 30 protects the first alignment mark 1 and the first It is possible to suppress the epitaxial layer from growing in step flow on the alignment mark 1. Further, if this is done, silicon carbide does not grow on the protective film 30. Therefore, even when the process (S50) for processing the second epitaxial layer 12 is performed in a state where the first alignment mark 1 is protected by the protective film 30, the second main surface 12a of the silicon carbide substrate.
  • the material constituting protective film 30 may be a carbon material such as diamond or graphite.
  • the second epitaxial layer formed in the step of forming second epitaxial layer 12 (S40).
  • a protective film 30 having a thickness equivalent to the thickness of the layer 12 is formed. In this way, overhang of the second epitaxial layer 12 can be prevented and the protective film 30 can be easily processed.
  • first alignment mark 1 is used.
  • the protective film 30 for protecting the film is formed (step (S30)), but is not limited thereto.
  • silicon carbide substrate 10 may be processed using first alignment mark 1 protected by protective film 30.
  • first alignment mark 1 is protected by protective film 30 in the step of forming second epitaxial layer 12 (S40).
  • the first alignment mark 1 is used to perform precise alignment. Can do.
  • the second epitaxial layer 12 may be processed using the first alignment mark 1 that is not covered by the protective film 30. That is, in the step (S25), processing is performed using the first alignment mark 1 protected by the protective film 30, and in the step (S50), the first alignment mark 1 from which the protective film 30 has been removed is used. Processing may be performed using this. Whether or not the first alignment mark 1 is protected by the protective film 30 does not cause an unacceptable positional shift at the time of alignment using the first alignment mark 1. Therefore, as long as the first alignment mark 1 is protected by the protective film 30 in the step (S40), the first alignment mark 1 in the steps (S25) and (S50) regardless of the presence or absence of the protective film 30. Can be used for precise positioning.
  • the method for manufacturing the silicon carbide semiconductor device according to the present embodiment basically has the same configuration as the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, but performs processing on silicon carbide substrate 10.
  • the step (S25) is different from the step (S50) in which the second epitaxial layer 12 is processed in that different alignment marks are used for alignment.
  • the second alignment mark 2 formed prior to the step (S25) is used and the second epitaxial layer 12 is formed.
  • the method Prior to (S40), the method further includes a step (S15) of forming the second alignment mark 2, and in the step (S30) of forming the protective film 30, at least the first alignment mark 1 is protected.
  • silicon carbide substrate 10 including first main surface 10a having an off angle with respect to the ⁇ 0001 ⁇ plane is prepared (step (S10)).
  • Second alignment mark 2 is formed (step (S15)).
  • Second alignment mark 2 may be formed in the same manner as the step (S20) of forming first alignment mark 1 in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, for example.
  • a resist mask (not shown) is formed on the first main surface 10a, and the second alignment mark 2 is formed using the resist mask as an etching mask.
  • Second alignment mark 2 is formed by etching first epitaxial layer 81a of silicon carbide substrate 10 exposed in the opening of the resist mask by a dry etching method such as a reactive ion etching (RIE) method, for example. It is provided by forming a step portion with respect to the first main surface 10a. That is, the second alignment mark 2 is formed so as to include, for example, a second convex portion 2a including the first main surface 10a and a second concave portion 2b having an opening in the first main surface 10a.
  • RIE reactive ion etching
  • the depth of the second recess 2b with respect to the first main surface 10a is, for example, about 0.5 ⁇ m to 2 ⁇ m, preferably about 0.7 ⁇ m to 1.5 ⁇ m, and more preferably 0.7 ⁇ m or more. It is about 1.0 ⁇ m or less.
  • the resist mask is removed by an arbitrary method after the second alignment mark 2 is formed.
  • Second alignment mark 2 may be formed on dicing line 102 formed on first main surface 10a of silicon carbide substrate 10.
  • the second protrusion 2a of the second alignment mark 2 may be formed in a rectangular shape having, for example, a longitudinal direction and a short direction when viewed in plan.
  • the longitudinal direction of the 2nd convex part 2a may be formed in parallel with the direction where the dicing line 102 is extended, and may be formed so that it may cross
  • step (S25) the silicon carbide substrate 10 is processed (step (S25)). Specifically, referring to FIG. 24, an ion implantation mask (not shown) is formed on first main surface 10a using second alignment mark 2, and the second alignment mark 2 is used to form the first implantation mask through the ion implantation mask. By ion-implanting into one main surface 10a, the ion-implanted region 11 is formed at a predetermined position on the first epitaxial layer 81a in the formation region 101 of the semiconductor device.
  • first alignment mark 1 is formed (step (S10)). Specifically, referring to FIG. 25, first alignment mark 1 may be formed in any region other than the region where second alignment mark 2 is formed in dicing line 102, for example. Formed using.
  • the first alignment mark 1 is formed so as to include, for example, a first convex portion 1a including the first main surface 10a and a first concave portion 1b having an opening in the first main surface 10a. .
  • the first alignment mark 1 is protected by the protective film 30 (step (S30)).
  • protective film 30 is formed on first main surface 10a of silicon carbide substrate 10.
  • the material constituting the protective film 30 is, for example, tantalum carbide (TaC), or a carbon material such as graphite or diamond.
  • the thickness h1 (see FIG. 26) of the protective film 30 may be determined according to the thickness h2 (see FIG. 27) of the second epitaxial layer 12 formed in the subsequent step S40.
  • the thickness h1 of the protective film 30 is preferably formed to be not less than 0.5 times and not more than 1.5 times the thickness h2 of the second epitaxial layer 12. In the present embodiment, the thickness h 1 of the protective film 30 is provided to be equal to the thickness h 2 of the second epitaxial layer 12.
  • the protective film 30 formed on the region for forming the second epitaxial layer 12 in the subsequent step (S40) is removed.
  • a resist mask 35 is formed on the protective film 30, and the protective film 30 is patterned using the resist mask 35 as an etching mask.
  • step (S40) the second epitaxial layer 12 is formed (step (S40)). Specifically, referring to FIG. 27, second epitaxial layer 12 is formed on first main surface 10a of silicon carbide substrate 10 after ion implantation region 11 is formed in first epitaxial layer 81a. It is formed. Second epitaxial layer 12 has an n-type conductivity, for example, and an impurity concentration of about 7 ⁇ 10 15 cm ⁇ 3 . At this time, the second epitaxial layer 12 is formed on the first main surface 10a having an off angle by performing step flow growth. At this time, step flow growth also proceeds on the second alignment mark 2.
  • the shape of the upper surface of the second epitaxial layer 12 formed on the convex portion 2 a and the concave portion 2 b of the second alignment mark 2 is deformed to a shape different from the shape of the second alignment mark 2.
  • the second main surface 12a of the second epitaxial layer 12 formed on the second alignment mark 2 has an inclined surface whose normal is the c-axis of hexagonal silicon carbide. Yes.
  • the second epitaxial layer 12 includes a second main surface 12a and a back surface 12b that is located opposite to the second main surface 12a and is in contact with the first main surface 10a in a region where the protective film 30 is not formed. Including. In the present embodiment, the thickness h2 of the second epitaxial layer 12 is equivalent to the thickness h1 of the protective film 30 as described above.
  • ion implantation region 11 is embedded in silicon carbide substrate 10 (first epitaxial layer 81a) and second epitaxial layer 12.
  • the protective film 30 that has protected the first alignment mark 1 may be removed.
  • the second epitaxial layer 12 is processed (step (S50)). Specifically, similarly to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, first, the p base layer 82 is formed on the second epitaxial layer 12 in the semiconductor device formation region 101 by ion implantation. An n region 83 is formed. Next, using the first alignment mark 1, an ion implantation mask is formed on the second main surface 12a. Next, the p contact region 84 is formed on the p base layer 82 by implanting ions into the second major surface 12a through the ion implantation mask.
  • MOSFET 100 as the silicon carbide semiconductor device according to the second embodiment is completed by being carried out in the same manner as the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • Use different alignment marks for alignment Specifically, in the step (S25), the second alignment mark 2 is used, and in the step (S50), the first alignment mark 1 is used for alignment.
  • the second alignment mark 2 is also processed.
  • first alignment mark 1 is newly formed using second alignment mark 2 before second alignment mark 2 is deformed.
  • the number of processes processed is smaller than that of the second alignment mark 2, and the first alignment mark is less deformed. 1 can be used.
  • step (S30) at least the first alignment mark 1 may be protected by the protective film 30.
  • step (S50) alignment can be performed by using the first alignment mark 1 that has not undergone deformation due to the execution of multiple steps or deformation due to step flow growth. Thereby, precise alignment can be performed in the step (S17) and the step (S50).
  • first alignment mark 1 is protected by protective film 30, but second alignment mark 2 May be protected by the protective film 30.
  • the process (S25) of processing silicon carbide substrate 10 is performed only once using second alignment mark 2. It is not limited to this.
  • a step of processing silicon carbide substrate 10 using first alignment mark 1 may be further provided before the step of forming epitaxial layer 12 (S40).
  • the process of processing silicon carbide substrate 10 using first alignment mark 1 is either before or after the process of protecting first alignment mark 1 with protective film 30 (S30). It may be carried out at any time before or after the step (S30). Even in this case, since the first alignment mark 1 is protected by the protective film 30 in the step of forming the second epitaxial layer 12 (S40), the silicon carbide semiconductor device according to the second embodiment described above. The same operational effects as those of the manufacturing method can be obtained.
  • the first alignment mark 1 and the second alignment mark 2 in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment and the second embodiment are rectangular in shape when the first protrusions 1a and 1b are viewed in plan view.
  • the first alignment mark 1 and the second alignment mark 2 may be any shape that can be detected by the semiconductor manufacturing apparatus.
  • the first alignment mark 1 and / or the second alignment mark 2 may be cross-shaped or circular when viewed in plan. Even if it does in this way, there can exist an effect similar to Embodiment 1 or Embodiment 2.
  • first alignment mark 1 and the second alignment mark 2 may be configured such that the first convex portions 1a and 2a and the first concave portions 1b and 2b have an arbitrary composition ratio.
  • the first alignment mark 1 and / or the second alignment mark 2 is formed by the first protrusions 1a and 2a partially in the first recesses 1b and 2b formed in a wide area of the dicing line 102.
  • the structure currently formed may be sufficient (convex type).
  • the first alignment mark 1 and / or the second alignment mark 2 may be such that the first concave portions 1b and 2b are partially formed in the first convex portions 1a and 2a formed in a wide area of the dicing line 102.
  • the structure currently formed may be sufficient (concave type).
  • the first alignment mark 1 is protected after the step of forming the second epitaxial layer 12 (S40).
  • membrane 30 is removed, it is not restricted to this.
  • the protective film 30 may be left on the first alignment mark 1 even after the step (S40).
  • the first alignment mark 1 is used on the first main surface 10a before the step (S30) of forming the protective film 30. Precise alignment can be performed on the pattern formed by using the first alignment mark 1 protected by the protective film 30.
  • protective film 30 is formed at second epitaxial layer 12 at the time of the step of forming second epitaxial layer 12 (S40).
  • the thickness may be 0.5 times or more and 1.5 times or less (see FIG. 28). In this way, overhang of the second epitaxial layer 12 can be prevented and the protective film 30 can be easily processed.
  • the step (S50) of processing the second epitaxial layer 12 using the first alignment mark 1 includes Although it was an ion implantation process, it is not restricted to this.
  • First alignment mark 1 may be used, for example, in a process such as a silicon carbide dry etching process, a gate electrode forming process, or an interlayer insulating film contact hole forming process.
  • p base layer 82, n region 83, and p contact region 84 are formed by ion implantation. In this case, it may be formed by epitaxial growth. In this case, the process (S50) for processing the second epitaxial layer 12 is, for example, a silicon carbide dry etching process.
  • silicon carbide semiconductor device 100 is a MOSFET, but may be, for example, a Schottky barrier diode or an IGBT (Insulated Gate Bipolar Transistor).
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • the first conductivity type is p-type and the second conductivity type is n-type. May be.
  • the present invention is particularly advantageously applied to a method for manufacturing a silicon carbide semiconductor device using a silicon carbide substrate including a main surface having an off angle with respect to the ⁇ 0001 ⁇ plane.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne un procédé de production d'un dispositif à semi-conducteurs en carbure de silicium comprenant : une étape (S10) au cours de laquelle est préparé un substrat de carbure de silicium qui comprend une première surface principale (10a) ayant un angle décalé par rapport au plan {0001}; une étape (S20) au cours de laquelle est formé un premier repère d'alignement (1) sur la première surface principale (10a) ; une étape (S30) au cours de laquelle est formé un film de protection (30) qui protège le premier repère d'alignement (1) ; une étape (S40) au cours de laquelle une couche épitaxiale (une seconde couche épitaxiale (12)) est formée sur la première surface principale (10a) dans un état dans lequel le film de protection (30) a été formé ; et une étape (S50) au cours de laquelle est utilisé le premier repère d'alignement (1) et au cours de laquelle est traitée la couche épitaxiale (la seconde couche épitaxiale (12)). En conséquence, il est possible de réaliser un procédé de production d'un dispositif à semi-conducteurs en carbure de silicium au moyen d'un substrat de carbure de silicium comprenant une surface principale ayant un angle décalé et qui permet de réaliser un positionnement précis même avant ou après une étape cours de laquelle est formée une couche épitaxiale.
PCT/JP2014/066265 2013-07-31 2014-06-19 Procédé de production de dispositif à semi-conducteurs en carbure de silicium WO2015015937A1 (fr)

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JP6287193B2 (ja) * 2013-12-26 2018-03-07 住友電気工業株式会社 炭化珪素半導体装置の製造方法
JP6696122B2 (ja) * 2015-07-10 2020-05-20 住友電気工業株式会社 ワイドバンドギャップ半導体装置の製造方法、ワイドバンドギャップ半導体ウエハおよびワイドバンドギャップ半導体チップ
JP6705670B2 (ja) * 2016-03-15 2020-06-03 富士電機株式会社 炭化珪素半導体素子および炭化珪素半導体素子の製造方法
JP6164672B1 (ja) * 2016-07-19 2017-07-19 国立研究開発法人産業技術総合研究所 半導体装置およびその製造方法
JP6673232B2 (ja) * 2017-01-17 2020-03-25 株式会社デンソー 炭化珪素半導体装置
JP2020141105A (ja) * 2019-03-01 2020-09-03 トヨタ自動車株式会社 半導体装置の製造方法

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