WO2015015937A1 - Production method for silicon carbide semiconductor device - Google Patents

Production method for silicon carbide semiconductor device Download PDF

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Publication number
WO2015015937A1
WO2015015937A1 PCT/JP2014/066265 JP2014066265W WO2015015937A1 WO 2015015937 A1 WO2015015937 A1 WO 2015015937A1 JP 2014066265 W JP2014066265 W JP 2014066265W WO 2015015937 A1 WO2015015937 A1 WO 2015015937A1
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Prior art keywords
alignment mark
epitaxial layer
silicon carbide
protective film
semiconductor device
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PCT/JP2014/066265
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French (fr)
Japanese (ja)
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秀人 玉祖
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住友電気工業株式会社
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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Definitions

  • the present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a method for manufacturing a silicon carbide semiconductor device using a silicon carbide substrate including a main surface having an off angle.
  • a method for manufacturing a semiconductor device includes a plurality of steps.
  • steps in processes that require alignment of the substrate to form a device pattern on the main surface of the substrate, such as lithography and ion implantation, alignment marks formed on the main surface in the previous step Use and align. Thereby, it is possible to suppress the occurrence of positional deviation in the device pattern formed in each step, and a semiconductor device having a fine device pattern can be obtained.
  • Japanese Patent Application Laid-Open No. 2011-1000092 discloses an SiC semiconductor device including a step of forming a trench serving as an alignment mark in a silicon carbide substrate, growing an epitaxial layer, and then placing a mask on the silicon carbide substrate using the alignment mark.
  • a manufacturing method is disclosed.
  • the alignment mark is formed as a trench having a polygonal shape in which the shape of the opening is symmetric with respect to the off direction and the apex is located at the most downstream side in the off direction.
  • the silicon carbide substrate used in the method for manufacturing the silicon carbide semiconductor device includes a main surface having an off angle with respect to the ⁇ 0001 ⁇ plane
  • the alignment mark formed on the main surface is epitaxially grown before the epitaxial growth step. In some cases, sufficient alignment accuracy cannot be obtained when used for alignment after the process.
  • the semiconductor manufacturing apparatus may not be able to accurately recognize the deformed alignment mark, or the semiconductor manufacturing apparatus may not be able to recognize the deformed alignment mark.
  • the present invention has been made to solve the above-described problems.
  • the main object of the present invention is to enable precise alignment before and after the step of forming an epitaxial layer in a method for manufacturing a silicon carbide semiconductor device using a silicon carbide substrate having a main surface having an off angle.
  • An object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device.
  • a step of preparing a silicon carbide substrate including a main surface having an off angle with respect to the ⁇ 0001 ⁇ plane, and forming the first alignment mark 1 on the main surface A step of forming a protective film for protecting the first alignment mark 1, a step of forming an epitaxial layer on the main surface in a state where the protective film is formed, and a step of using the first alignment mark 1. And a step of processing the epitaxial layer.
  • FIG. 3 is a flowchart of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • 5 is a schematic plan view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 5 is a schematic plan view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • 5 is a flowchart of a method for manufacturing a silicon carbide semiconductor device according to a second embodiment.
  • FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 11 is a cross sectional view for illustrating a modification of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment and the second embodiment.
  • a method for manufacturing a silicon carbide semiconductor device includes a step (S10) of preparing a silicon carbide substrate including first main surface 10a having an off angle with respect to a ⁇ 0001 ⁇ plane.
  • the step of forming the first alignment mark 1 on the first main surface 10a (S20), the step of forming the protective film 30 that protects the first alignment mark 1 (S30), and the formation of the protective film 30 In this state, an epitaxial layer (second epitaxial layer) is formed by using the first alignment mark 1 and a step (S40) of forming an epitaxial layer (second epitaxial layer 12) on the first main surface 10a.
  • the first alignment mark 1 formed on the first main surface 10a having an off angle with respect to the ⁇ 0001 ⁇ plane is a step of forming an epitaxial layer (second epitaxial layer 12).
  • step flow growth proceeds with respect to the first alignment mark 1 and is formed on the first alignment mark 1.
  • the shape of the upper surface of the epitaxial layer can be prevented from being deformed to a shape different from the shape of the first alignment mark 1.
  • step (S50) of processing the epitaxial layer (second epitaxial layer 12) performed after the step (S40) the first alignment mark 1 is used for precise alignment.
  • the first alignment mark 1 is used to place an etching mask at a predetermined position on the second main surface 12a. Can be formed.
  • the etching mask formed in this manner is suppressed in positional deviation with respect to the pattern formed on the first main surface 10a before the step (S40). That is, according to the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, precise alignment can be performed before and after the step of forming the epitaxial layer (second epitaxial layer 12). Therefore, in the method for manufacturing the silicon carbide semiconductor device, it is not necessary to limit the process conditions, order, and the like of the step (S40) of forming the epitaxial layer (second epitaxial layer 12) from the viewpoint of alignment.
  • the step (S50) of processing the epitaxial layer (second epitaxial layer 12) is performed after removing the protective film 30. May be.
  • the first alignment mark 1 is protected by the protective film 30 in the step (S40) of forming the epitaxial layer (second epitaxial layer 12). Step flow growth does not progress. Therefore, in the step (S50) of processing the epitaxial layer (second epitaxial layer 12), the first alignment mark 1 that maintains the shape during the step (S30) of forming the protective film 30 is used. Thus, alignment can be performed. As a result, in the step (S50), for example, the first alignment mark 1 is used before the step (S30) to precisely align the pattern formed on the first main surface 10a. Can do.
  • the first alignment mark 1 protects the step (S50) of processing the epitaxial layer (second epitaxial layer 12). You may implement in the state protected by the film
  • an uneven mark corresponding to the shape of the first alignment mark 1 is formed on the upper surface of the protective film 30, and no epitaxial layer is formed on the upper surface of the protective film 30. Therefore, in the step of forming the epitaxial layer (second epitaxial layer 12) (S40), the first alignment mark 1 is protected by the protective film 30, so that step flow growth is performed on the first alignment mark 1. Does not progress. Therefore, in the step (S50) of processing the epitaxial layer (second epitaxial layer 12), the first alignment mark 1 that maintains the shape during the step (S30) of forming the protective film 30 is used. Thus, alignment can be performed.
  • the first alignment mark 1 protected by the protective film 30 is used on the first main surface 10a. Precise alignment can be performed on the formed pattern.
  • the first alignment mark 1 is used for the silicon carbide substrate 10 before the step (S30) of forming the protective film 30.
  • the process (S25) which performs a process may be further provided.
  • the step (S30) of forming protective film 30 protecting first alignment mark 1 and the epitaxial layer (second epitaxial layer 12) are formed.
  • the process for the silicon carbide substrate 10 that uses the first alignment mark 1 (S25) and the process for the epitaxial layer (second epitaxial layer 12) are performed.
  • step (S50) Even in this case, as described above, since the first alignment mark 1 is protected by the protective film 30 in the step (S40), the step flow growth thereon is prevented. Therefore, in the step (S25) and the step (S50) (that is, before and after the step (S40)), precise alignment can be performed using the first alignment mark 1.
  • the second alignment mark is formed on the first main surface 10a before the step (S20) of forming the first alignment mark 1.
  • the protective film 30 that protects at least the first alignment mark 1 may be formed. Good.
  • the first alignment mark 1 used in the step (S50) of processing the epitaxial layer (second epitaxial layer 12) is the second alignment on the first main surface 10a.
  • the mark is formed using the second alignment mark (step (step ( S20)).
  • the first alignment mark 1 is protected by the protective film 30 in the step (S30).
  • step flow growth proceeds with respect to the first alignment mark 1, and the first alignment mark 1 is It is possible to suppress the shape of the upper surface of the epitaxial layer formed in the step from being deformed to a shape different from the shape of the first alignment mark 1. Therefore, the pattern formed by using the first alignment mark 1 in the step (S50) is misaligned with the pattern formed by using the second alignment mark before the step (S40). Is suppressed. In other words, it is used in the step (S17) for processing the silicon carbide substrate and the step (S50) for processing the epitaxial layer (second epitaxial layer 12) performed before and after the step (S40).
  • step (S30) of forming the protective film 30 by forming the protective film 30 that protects at least the first alignment mark 1 used in the step (S50).
  • step (S17) and the step (S50) precise alignment can be performed.
  • the material forming protective film 30 may include tantalum carbide (TaC x ) or a carbon material.
  • the protective film 30 can have a high melting point. Therefore, the protective film 30 protects the first alignment mark 1 also in the step (S40) of forming an epitaxial layer (second epitaxial layer 12) performed under a temperature condition of, for example, about 1500 ° C. to 1700 ° C. Thus, it is possible to suppress the step-flow growth of the epitaxial layer on the first alignment mark 1. That is, in this way, silicon carbide does not grow on protective film 30. Therefore, even when the step (S50) of processing the epitaxial layer (second epitaxial layer 12) is performed in a state where the first alignment mark 1 is protected by the protective film 30, the second of the silicon carbide substrate.
  • the first alignment mark 1 is easily detected when the main surface 12a is viewed in plan (when the second main surface 12a is viewed from above along the direction perpendicular to the second main surface 12a). Can do.
  • the carbon material for example, diamond or graphite may be used.
  • protective film 30 in the step of forming protective film 30 (S30), in the step of forming epitaxial layer (second epitaxial layer 12) (S40) A protective film 30 having a thickness of 0.5 to 1.5 times the thickness of the formed epitaxial layer (second epitaxial layer 12) may be formed.
  • the epitaxial layer (second epitaxial layer 12) projects over the protective film 30. May grow (overhang). In this case, foreign matter or the like tends to accumulate in a region surrounded by the epitaxial layer (second epitaxial layer 12) grown so as to overhang the protective film 30. Further, the overhanging epitaxial layer (second epitaxial layer 12) may be a starting point of film peeling of a film formed on the second main surface 12a thereafter.
  • the thickness of the protective film 30 is 0.5 times or more the thickness of the epitaxial layer (second epitaxial layer 12), the epitaxial layer (second epitaxial layer 12) overlies the protective film 30. Hang can be suppressed. Furthermore, it is possible to suppress the occurrence of abnormality due to the overhang of the epitaxial layer (second epitaxial layer 12). Moreover, when the thickness of the protective film 30 is thicker than the thickness of the epitaxial layer (second epitaxial layer 12), the above-described overhang of the epitaxial layer (second epitaxial layer 12) can be reliably prevented.
  • the thickness of the protective film 30 exceeds 1.5 times the thickness of the epitaxial layer (second epitaxial layer 12), it is thicker than necessary from the viewpoint of preventing overhang, and the epitaxial layer (first Depending on the thickness of the second epitaxial layer 12), the processing of the protective film 30 becomes difficult. Therefore, if the thickness of the protective film 30 is 0.5 to 1.5 times the thickness of the epitaxial layer (second epitaxial layer 12), an overhang of the epitaxial layer (second epitaxial layer 12) is prevented. In addition, the protective film 30 can be easily processed.
  • the first alignment mark 1 and the second alignment mark are generic names including a plurality of alignment marks formed on the main surfaces 10a and 12a of the silicon carbide substrate in one step.
  • a plurality of first alignment marks 1 are formed on the dicing line on the first main surface 10a.
  • a reticle pattern corresponding to the first alignment mark 1 is formed on the reticle, and the number of the first alignment marks 1 is about the number of shots.
  • "using the first alignment mark 1" is formed on the first main surface 10a in the step (S20).
  • a necessary and sufficient number of first alignment marks 1 formed at positions effective for aligning the silicon carbide substrate can be extracted and used for alignment. Contains.
  • “using the first alignment mark 1” means a step of processing the silicon carbide substrate 10.
  • a necessary and sufficient number of first alignment marks formed at positions effective for aligning the silicon carbide substrate It also includes detecting only one alignment mark 1 and using it for alignment.
  • the first alignment mark 1 used for alignment in the step (S25) and the step (S50) needs to be the same alignment mark formed at the same position on the first main surface 10a. Alternatively, different first alignment marks 1 formed at different positions may be used for alignment.
  • the step (S25) and The alignment accuracy (superposition accuracy) with the step (S50) can be increased.
  • an LSA Laser Step Alignment
  • FIA Field Image Alignment
  • Either method is applicable. That is, according to the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, as described above, it is possible to prevent the epitaxial layer from growing in the step flow on the alignment mark, so that the alignment mark is deformed. Can be prevented.
  • the laser is applied to the alignment mark, the reflected light of the laser is analyzed and alignment is performed, and the LIA method (optical alignment method) that performs alignment, or the FIA method that recognizes the edge of the image recognized by the camera and performs alignment (image recognition) Method), the alignment mark can be detected with high accuracy even after the epitaxial layer (second epitaxial layer 12) is formed.
  • the silicon carbide substrate according to the present embodiment may be an epitaxial substrate in which an epitaxial layer is formed on a base substrate such as a single crystal substrate, or an epitaxial layer in which the base substrate is removed from the epitaxial substrate. May be.
  • silicon carbide substrate 10 including first main surface 10a having an off angle with respect to the ⁇ 0001 ⁇ plane is prepared (step (S10)).
  • Silicon carbide substrate 10 is an epitaxial substrate having a silicon carbide single crystal substrate 80 and a first epitaxial layer 81 a made of silicon carbide formed on silicon carbide single crystal substrate 80.
  • First epitaxial layer 81a has, for example, an n-type conductivity and an impurity concentration of about 4 ⁇ 10 15 cm ⁇ 3 .
  • first main surface 10a is included in first epitaxial layer 81a.
  • the first major surface 10a is a ⁇ 0001 ⁇ plane and off only off direction a 1 off angle ⁇ from (surface indicated by the broken line) (inclined) surface.
  • the off angle ⁇ is preferably an angle of 1 ° to 8 °.
  • the first major surface 10a is from the ⁇ 0001 ⁇ plane so that the normal vector z of the first major surface 10a has at least one component of ⁇ 11-20> and ⁇ 1-100>. It is a surface that has been turned off.
  • the first main surface 10a is a surface off from the ⁇ 0001 ⁇ plane so that the normal vector z of the first main surface 10a has a component of ⁇ 11-20>.
  • direction c is the [0001] direction (that is, the c-axis of hexagonal silicon carbide), and direction a 1 is, for example, the ⁇ 11-20> direction.
  • the normal vector z of the first major surface 10a is inclined in the ⁇ 11-20> direction from the [0001] direction.
  • direction a 11 in which the orientation flat (OF: see FIG. 4) extends is, for example, the ⁇ 1-100> direction.
  • the first alignment mark 1 is formed on the first main surface 10a (step (S20)).
  • resist mask 20 is formed on first main surface 10a
  • first alignment mark 1 is formed using resist mask 20 as an etching mask.
  • First alignment mark 1 is formed by etching first epitaxial layer 81a of silicon carbide substrate 10 exposed in the opening of resist mask 20 by a dry etching method such as a reactive ion etching (RIE) method. , Provided by forming a stepped portion with respect to the first main surface 10a. That is, as shown in FIG.
  • RIE reactive ion etching
  • the first alignment mark 1 includes a first convex portion 1a including the first main surface 10a, and a first concave portion 1b having an opening in the first main surface 10a. And so as to include.
  • the depth of the first recess 1b with respect to the first main surface 10a is, for example, about 0.5 ⁇ m to 2 ⁇ m, preferably about 0.7 ⁇ m to 1.5 ⁇ m, and more preferably 0.7 ⁇ m or more. It is about 1.0 ⁇ m or less.
  • the resist mask 20 is removed by an arbitrary method after forming the first alignment mark 1.
  • first alignment mark 1 may be formed on dicing line 102 formed on first main surface 10 a of silicon carbide substrate 10.
  • the dicing line 102 is a position where cutting is planned when a plurality of semiconductor devices are formed on the silicon carbide substrate 10 and then separated into individual semiconductor devices in the dicing process. That is, the dicing lines 102, for example, the direction a 11 parallel to the direction in which the orientation flat extends, a plurality of dicing lines may be formed along the respective perpendicular direction a 12 in the direction a 11.
  • a plurality of semiconductor device formation regions 101 may be formed so as to be surrounded by the dicing lines 102.
  • the first convex portion 1a of the first alignment mark 1 may be formed in a rectangular shape having, for example, a longitudinal direction and a lateral direction when viewed in plan.
  • the longitudinal direction of the 1st convex part 1a may be formed in parallel with the direction where the dicing line 102 is extended, and may be formed so that it may cross
  • the length L1 in the longitudinal direction of the first protrusion 1a is, for example, 80 ⁇ m, and the length in the short direction of the first protrusion 1a is, for example, 9 ⁇ m.
  • the width L3 of the dicing line 102 in the direction perpendicular to the direction in which the dicing line 102 extends is, for example, 120 ⁇ m.
  • FIG. 6 is a cross-sectional view taken along line VI-VI in FIG.
  • step (S25) processing is performed on silicon carbide substrate 10 (step (S25)).
  • an ion implantation mask (not shown) is formed on first main surface 10a using first alignment mark 1, and the first alignment mark 1 is used to form the first alignment mark 1 through the ion implantation mask.
  • the ion-implanted region 11 is formed at a predetermined position on the first epitaxial layer 81a in the formation region 101 of the semiconductor device.
  • Ion implantation region 11 has, for example, a p-type conductivity and an impurity concentration of about 1 ⁇ 10 17 cm ⁇ 3 .
  • a protective film 30 is formed to protect the first alignment mark 1 (step (S30)) Specifically, referring to Fig. 8, first, on first main surface 10a of silicon carbide substrate 10. A protective film 30 is formed on the protective film 30.
  • the material constituting the protective film 30 is, for example, tantalum carbide (TaC) or a carbon material, which may be any material containing carbon atoms, such as graphite or diamond.
  • the thickness h1 (see FIG. 9) of the protective film 30 may be determined according to the thickness h2 (see FIG. 10) of the second epitaxial layer 12 to be formed in the subsequent step S40.
  • the thickness h1 is preferably 0.5 times or more and 1.5 times or less than the thickness h2 of the second epitaxial layer 12.
  • the thickness of the protective film 30 is set. 1 is provided so as to be equal to the thickness h2 of the second epitaxial layer 12.
  • the protective film 30 formed on the region for forming the second epitaxial layer 12 in the subsequent step (S40) is removed.
  • a resist mask 35 is formed on the protective film 30, and the protective film 30 is patterned using the resist mask 35 as an etching mask.
  • the resist mask 35 is removed by an arbitrary method.
  • second epitaxial layer 12 is formed (step (S40)). Specifically, referring to FIG. 10, second epitaxial layer 12 is formed on first main surface 10 a of silicon carbide substrate 10 after ion implantation region 11 is formed in first epitaxial layer 81 a. It is formed. Second epitaxial layer 12 has an n-type conductivity, for example, and an impurity concentration of about 7 ⁇ 10 15 cm ⁇ 3 . At this time, the second epitaxial layer 12 is formed on the first main surface 10a having an off angle by performing step flow growth. On the other hand, step flow growth does not occur on the protective film 30 (on the first alignment mark 1 protected by the protective film 30), and the second epitaxial layer 12 does not grow. Therefore, the pattern shape of the first alignment mark 1 and the pattern shape of the protective film 30 formed so as to cover the pattern shape of the first alignment mark 1 are suppressed from being deformed by step flow growth.
  • the second epitaxial layer 12 includes a second main surface 12a and a back surface 12b that is located opposite to the second main surface 12a and is in contact with the first main surface 10a in a region where the protective film 30 is not formed. Including. In the present embodiment, the thickness h2 of the second epitaxial layer 12 is equivalent to the thickness h1 of the protective film 30 as described above.
  • FIG. 12 is a cross-sectional view of the formation region 101 of the semiconductor device after the second epitaxial layer 12 is formed in this step (S40). By this step (S40), ion implantation region 11 is embedded in silicon carbide substrate 10 (first epitaxial layer 81a) and second epitaxial layer 12. In this step (S40), after forming the second epitaxial layer 12, the protective film 30 protecting the first alignment mark 1 may be removed as shown in FIG.
  • the second epitaxial layer 12 is processed (step (S50)). Specifically, referring to FIG. 13, first, ions are implanted into second main surface 12a to form p base layer 82 and n on second epitaxial layer 12 in formation region 101 of the semiconductor device. Region 83 is formed. Next, referring to FIG. 14, an ion implantation mask (not shown) is formed on second main surface 12 a using first alignment mark 1. Next, the p contact region 84 is formed on the p base layer 82 by implanting ions into the second major surface 12a through the ion implantation mask. As described above, the detection method of the first alignment mark 1 may be either the LSA method or the FIA method.
  • an impurity for imparting p-type such as aluminum (Al)
  • Al aluminum
  • an impurity such as phosphorus (P) for imparting n-type is ion-implanted.
  • the temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C.
  • the heat treatment time is, for example, about 30 minutes.
  • the atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an Ar atmosphere.
  • a trench having an opening in the second main surface 12a is formed.
  • mask layer 40 having an opening is formed on main surface 12 a formed of n region 83 and p contact region 84.
  • As mask layer 40 for example, a silicon oxide film or the like can be used.
  • the opening is formed corresponding to the position of trench TR (see FIG. 19).
  • the mask layer 40 uses a second alignment mark different from the first alignment mark 1 formed on the first alignment mark 1 or the second epitaxial layer 12, and the position corresponding to the opening is exposed. It may be formed in an aligned manner.
  • n region 83, p base layer 82, and part of second epitaxial layer 12 are removed by etching in the opening of mask layer 40.
  • etching method for example, reactive ion etching (RIE), particularly inductively coupled plasma (ICP) RIE can be used.
  • ICP-RIE using SF 6 or a mixed gas of SF 6 and O 2 as a reaction gas can be used.
  • thermal etching is performed in the recess TQ.
  • the thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms.
  • the at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom.
  • This atmosphere is, for example, Cl 2 , BCL 3 , SF 6 , or CF 4 .
  • thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and a heat treatment temperature of, for example, 700 ° C. or more and 1000 ° C. or less.
  • the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas.
  • a carrier gas for example, nitrogen (N 2 ) gas, argon gas, helium gas or the like can be used.
  • N 2 nitrogen
  • argon gas argon gas
  • helium gas helium gas or the like
  • the heat treatment temperature is set to 700 ° C. or higher and 1000 ° C. or lower as described above
  • the etching rate of silicon carbide is about 70 ⁇ m / hour, for example.
  • the mask layer 40 made of silicon oxide has a very high selectivity with respect to silicon carbide, and therefore is not substantially etched during the etching of silicon carbide.
  • a trench TR is formed on the upper surfaces of the first epitaxial layer 81a and the second epitaxial layer 12 by the thermal etching described above.
  • Trench TR has side wall surface SW passing through n region 83 and p base layer 82 to second epitaxial layer 12, and bottom surface BT located on second epitaxial layer 12.
  • Each of sidewall surface SW and bottom surface BT is separated from ion implantation region 11.
  • the mask layer 40 is removed by an arbitrary method such as etching.
  • Gate oxide film 91 covering each of the sidewall surface SW and the bottom surface BT of the trench TR is formed.
  • Gate oxide film 91 can be formed, for example, by thermal oxidation. Thereafter, NO annealing using nitrogen monoxide (NO) gas as the atmospheric gas may be performed.
  • NO nitrogen monoxide
  • the temperature profile has, for example, conditions of a temperature of 1100 ° C. to 1300 ° C. and a holding time of about 1 hour. Thereby, nitrogen atoms are introduced into the interface region between gate oxide film 91 and p base layer 82. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved.
  • a gas other than NO gas may be used as the atmospheric gas.
  • Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing.
  • the heating temperature for Ar annealing is preferably higher than the heating temperature for NO annealing and lower than the melting point of the gate oxide film 91.
  • the time during which this heating temperature is maintained is, for example, about 1 hour. Thereby, the formation of interface states in the interface region between gate oxide film 91 and p base layer 82 is further suppressed.
  • other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.
  • Sidewall surface SW of trench TR has a plane orientation ⁇ 0-33-8 ⁇ , and may preferably include a predetermined plane having a plane orientation (0-33-8).
  • a gate electrode 92 is formed on the gate oxide film 91.
  • gate electrode 92 is formed on gate oxide film 91 so as to fill the region inside trench TR with gate oxide film 91 interposed therebetween.
  • the gate electrode 92 can be formed, for example, by film formation of conductor or doped polysilicon and CMP (Chemical Mechanical Polishing).
  • an interlayer insulating film 93 is formed on gate electrode 92 and gate oxide film 91 so as to cover the exposed surface of gate electrode 92. Thereafter, etching is performed so that openings are formed in the interlayer insulating film 93 and the gate oxide film 91. Through this opening, each of n region 83 and p contact region 84 is exposed on upper surface P2. Next, source electrode 94 in contact with each of n region 83 and n contact region 84 is formed on upper surface P2. Drain electrode 98 is formed on lower surface P ⁇ b> 1 made of first epitaxial layer 81 a through silicon carbide single crystal substrate 80.
  • a source wiring layer 95 is formed.
  • the silicon carbide substrate 10, the second epitaxial layer 12, the gate oxide film 91, the gate electrode 92, the interlayer insulating film 93, the source electrode 94, the source wiring layer 95, and the drain electrode 98 are formed.
  • MOSFET 100 as a silicon carbide semiconductor device is completed.
  • Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 80, a first epitaxial layer 81 a, and an ion implantation region 11.
  • Second epitaxial layer 12 includes a p base layer 82, an n region 83, and a p contact region 84.
  • first alignment mark 1 formed on first main surface 10a having an off angle with respect to the ⁇ 0001 ⁇ plane is formed by second epitaxial layer 12 It is protected by the protective film 30 in the step of forming (S40). For this reason, in the step of forming the second epitaxial layer 12 (S40), it is possible to prevent the first alignment mark 1 from undergoing step flow growth and the shape of the first alignment mark 1 from being deformed. it can. As a result, the first alignment mark 1 is used also in the step (S50) of processing the second epitaxial layer 12 performed after the step (S40) of forming the second epitaxial layer 12. Precise alignment can be performed.
  • the step (S50) of processing the second epitaxial layer 12 is performed after removing the protective film 30.
  • the process (S50) which processes with respect to the 2nd epitaxial layer 12 since it protected by the protective film 30 in the process (S40) of forming the 2nd epitaxial layer 12, it is a step on that Position alignment can be performed using the first alignment mark 1 that is not flow-grown and maintains the shape during the step of forming the protective film 30 (S30).
  • the first main surface is used by using the first alignment mark 1 before the step (S30) of forming the protective film 30, for example. Precise alignment can be performed on the pattern formed on 10a.
  • silicon carbide substrate 10 is utilized using first alignment mark 1 before the step of protecting first alignment mark 1 (S30).
  • the process (S25) which performs a process with respect to is provided. That is, before and after the step of forming the second epitaxial layer 12 (S40), the step of processing the silicon carbide substrate 10 using the first alignment mark 1 (S25) and the second epitaxial layer. And a step (S50) of processing the layer 12.
  • step (S25) and the step (S50) that is, before and after the step (S40)
  • precise alignment can be performed using the first alignment mark 1.
  • the material forming protective film 30 includes TaC. Therefore, also in the step (S40) of forming the second epitaxial layer 12 performed under a temperature condition of, for example, 1500 ° C. or more and 1700 ° C. or less, the protective film 30 protects the first alignment mark 1 and the first It is possible to suppress the epitaxial layer from growing in step flow on the alignment mark 1. Further, if this is done, silicon carbide does not grow on the protective film 30. Therefore, even when the process (S50) for processing the second epitaxial layer 12 is performed in a state where the first alignment mark 1 is protected by the protective film 30, the second main surface 12a of the silicon carbide substrate.
  • the material constituting protective film 30 may be a carbon material such as diamond or graphite.
  • the second epitaxial layer formed in the step of forming second epitaxial layer 12 (S40).
  • a protective film 30 having a thickness equivalent to the thickness of the layer 12 is formed. In this way, overhang of the second epitaxial layer 12 can be prevented and the protective film 30 can be easily processed.
  • first alignment mark 1 is used.
  • the protective film 30 for protecting the film is formed (step (S30)), but is not limited thereto.
  • silicon carbide substrate 10 may be processed using first alignment mark 1 protected by protective film 30.
  • first alignment mark 1 is protected by protective film 30 in the step of forming second epitaxial layer 12 (S40).
  • the first alignment mark 1 is used to perform precise alignment. Can do.
  • the second epitaxial layer 12 may be processed using the first alignment mark 1 that is not covered by the protective film 30. That is, in the step (S25), processing is performed using the first alignment mark 1 protected by the protective film 30, and in the step (S50), the first alignment mark 1 from which the protective film 30 has been removed is used. Processing may be performed using this. Whether or not the first alignment mark 1 is protected by the protective film 30 does not cause an unacceptable positional shift at the time of alignment using the first alignment mark 1. Therefore, as long as the first alignment mark 1 is protected by the protective film 30 in the step (S40), the first alignment mark 1 in the steps (S25) and (S50) regardless of the presence or absence of the protective film 30. Can be used for precise positioning.
  • the method for manufacturing the silicon carbide semiconductor device according to the present embodiment basically has the same configuration as the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, but performs processing on silicon carbide substrate 10.
  • the step (S25) is different from the step (S50) in which the second epitaxial layer 12 is processed in that different alignment marks are used for alignment.
  • the second alignment mark 2 formed prior to the step (S25) is used and the second epitaxial layer 12 is formed.
  • the method Prior to (S40), the method further includes a step (S15) of forming the second alignment mark 2, and in the step (S30) of forming the protective film 30, at least the first alignment mark 1 is protected.
  • silicon carbide substrate 10 including first main surface 10a having an off angle with respect to the ⁇ 0001 ⁇ plane is prepared (step (S10)).
  • Second alignment mark 2 is formed (step (S15)).
  • Second alignment mark 2 may be formed in the same manner as the step (S20) of forming first alignment mark 1 in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, for example.
  • a resist mask (not shown) is formed on the first main surface 10a, and the second alignment mark 2 is formed using the resist mask as an etching mask.
  • Second alignment mark 2 is formed by etching first epitaxial layer 81a of silicon carbide substrate 10 exposed in the opening of the resist mask by a dry etching method such as a reactive ion etching (RIE) method, for example. It is provided by forming a step portion with respect to the first main surface 10a. That is, the second alignment mark 2 is formed so as to include, for example, a second convex portion 2a including the first main surface 10a and a second concave portion 2b having an opening in the first main surface 10a.
  • RIE reactive ion etching
  • the depth of the second recess 2b with respect to the first main surface 10a is, for example, about 0.5 ⁇ m to 2 ⁇ m, preferably about 0.7 ⁇ m to 1.5 ⁇ m, and more preferably 0.7 ⁇ m or more. It is about 1.0 ⁇ m or less.
  • the resist mask is removed by an arbitrary method after the second alignment mark 2 is formed.
  • Second alignment mark 2 may be formed on dicing line 102 formed on first main surface 10a of silicon carbide substrate 10.
  • the second protrusion 2a of the second alignment mark 2 may be formed in a rectangular shape having, for example, a longitudinal direction and a short direction when viewed in plan.
  • the longitudinal direction of the 2nd convex part 2a may be formed in parallel with the direction where the dicing line 102 is extended, and may be formed so that it may cross
  • step (S25) the silicon carbide substrate 10 is processed (step (S25)). Specifically, referring to FIG. 24, an ion implantation mask (not shown) is formed on first main surface 10a using second alignment mark 2, and the second alignment mark 2 is used to form the first implantation mask through the ion implantation mask. By ion-implanting into one main surface 10a, the ion-implanted region 11 is formed at a predetermined position on the first epitaxial layer 81a in the formation region 101 of the semiconductor device.
  • first alignment mark 1 is formed (step (S10)). Specifically, referring to FIG. 25, first alignment mark 1 may be formed in any region other than the region where second alignment mark 2 is formed in dicing line 102, for example. Formed using.
  • the first alignment mark 1 is formed so as to include, for example, a first convex portion 1a including the first main surface 10a and a first concave portion 1b having an opening in the first main surface 10a. .
  • the first alignment mark 1 is protected by the protective film 30 (step (S30)).
  • protective film 30 is formed on first main surface 10a of silicon carbide substrate 10.
  • the material constituting the protective film 30 is, for example, tantalum carbide (TaC), or a carbon material such as graphite or diamond.
  • the thickness h1 (see FIG. 26) of the protective film 30 may be determined according to the thickness h2 (see FIG. 27) of the second epitaxial layer 12 formed in the subsequent step S40.
  • the thickness h1 of the protective film 30 is preferably formed to be not less than 0.5 times and not more than 1.5 times the thickness h2 of the second epitaxial layer 12. In the present embodiment, the thickness h 1 of the protective film 30 is provided to be equal to the thickness h 2 of the second epitaxial layer 12.
  • the protective film 30 formed on the region for forming the second epitaxial layer 12 in the subsequent step (S40) is removed.
  • a resist mask 35 is formed on the protective film 30, and the protective film 30 is patterned using the resist mask 35 as an etching mask.
  • step (S40) the second epitaxial layer 12 is formed (step (S40)). Specifically, referring to FIG. 27, second epitaxial layer 12 is formed on first main surface 10a of silicon carbide substrate 10 after ion implantation region 11 is formed in first epitaxial layer 81a. It is formed. Second epitaxial layer 12 has an n-type conductivity, for example, and an impurity concentration of about 7 ⁇ 10 15 cm ⁇ 3 . At this time, the second epitaxial layer 12 is formed on the first main surface 10a having an off angle by performing step flow growth. At this time, step flow growth also proceeds on the second alignment mark 2.
  • the shape of the upper surface of the second epitaxial layer 12 formed on the convex portion 2 a and the concave portion 2 b of the second alignment mark 2 is deformed to a shape different from the shape of the second alignment mark 2.
  • the second main surface 12a of the second epitaxial layer 12 formed on the second alignment mark 2 has an inclined surface whose normal is the c-axis of hexagonal silicon carbide. Yes.
  • the second epitaxial layer 12 includes a second main surface 12a and a back surface 12b that is located opposite to the second main surface 12a and is in contact with the first main surface 10a in a region where the protective film 30 is not formed. Including. In the present embodiment, the thickness h2 of the second epitaxial layer 12 is equivalent to the thickness h1 of the protective film 30 as described above.
  • ion implantation region 11 is embedded in silicon carbide substrate 10 (first epitaxial layer 81a) and second epitaxial layer 12.
  • the protective film 30 that has protected the first alignment mark 1 may be removed.
  • the second epitaxial layer 12 is processed (step (S50)). Specifically, similarly to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, first, the p base layer 82 is formed on the second epitaxial layer 12 in the semiconductor device formation region 101 by ion implantation. An n region 83 is formed. Next, using the first alignment mark 1, an ion implantation mask is formed on the second main surface 12a. Next, the p contact region 84 is formed on the p base layer 82 by implanting ions into the second major surface 12a through the ion implantation mask.
  • MOSFET 100 as the silicon carbide semiconductor device according to the second embodiment is completed by being carried out in the same manner as the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • Use different alignment marks for alignment Specifically, in the step (S25), the second alignment mark 2 is used, and in the step (S50), the first alignment mark 1 is used for alignment.
  • the second alignment mark 2 is also processed.
  • first alignment mark 1 is newly formed using second alignment mark 2 before second alignment mark 2 is deformed.
  • the number of processes processed is smaller than that of the second alignment mark 2, and the first alignment mark is less deformed. 1 can be used.
  • step (S30) at least the first alignment mark 1 may be protected by the protective film 30.
  • step (S50) alignment can be performed by using the first alignment mark 1 that has not undergone deformation due to the execution of multiple steps or deformation due to step flow growth. Thereby, precise alignment can be performed in the step (S17) and the step (S50).
  • first alignment mark 1 is protected by protective film 30, but second alignment mark 2 May be protected by the protective film 30.
  • the process (S25) of processing silicon carbide substrate 10 is performed only once using second alignment mark 2. It is not limited to this.
  • a step of processing silicon carbide substrate 10 using first alignment mark 1 may be further provided before the step of forming epitaxial layer 12 (S40).
  • the process of processing silicon carbide substrate 10 using first alignment mark 1 is either before or after the process of protecting first alignment mark 1 with protective film 30 (S30). It may be carried out at any time before or after the step (S30). Even in this case, since the first alignment mark 1 is protected by the protective film 30 in the step of forming the second epitaxial layer 12 (S40), the silicon carbide semiconductor device according to the second embodiment described above. The same operational effects as those of the manufacturing method can be obtained.
  • the first alignment mark 1 and the second alignment mark 2 in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment and the second embodiment are rectangular in shape when the first protrusions 1a and 1b are viewed in plan view.
  • the first alignment mark 1 and the second alignment mark 2 may be any shape that can be detected by the semiconductor manufacturing apparatus.
  • the first alignment mark 1 and / or the second alignment mark 2 may be cross-shaped or circular when viewed in plan. Even if it does in this way, there can exist an effect similar to Embodiment 1 or Embodiment 2.
  • first alignment mark 1 and the second alignment mark 2 may be configured such that the first convex portions 1a and 2a and the first concave portions 1b and 2b have an arbitrary composition ratio.
  • the first alignment mark 1 and / or the second alignment mark 2 is formed by the first protrusions 1a and 2a partially in the first recesses 1b and 2b formed in a wide area of the dicing line 102.
  • the structure currently formed may be sufficient (convex type).
  • the first alignment mark 1 and / or the second alignment mark 2 may be such that the first concave portions 1b and 2b are partially formed in the first convex portions 1a and 2a formed in a wide area of the dicing line 102.
  • the structure currently formed may be sufficient (concave type).
  • the first alignment mark 1 is protected after the step of forming the second epitaxial layer 12 (S40).
  • membrane 30 is removed, it is not restricted to this.
  • the protective film 30 may be left on the first alignment mark 1 even after the step (S40).
  • the first alignment mark 1 is used on the first main surface 10a before the step (S30) of forming the protective film 30. Precise alignment can be performed on the pattern formed by using the first alignment mark 1 protected by the protective film 30.
  • protective film 30 is formed at second epitaxial layer 12 at the time of the step of forming second epitaxial layer 12 (S40).
  • the thickness may be 0.5 times or more and 1.5 times or less (see FIG. 28). In this way, overhang of the second epitaxial layer 12 can be prevented and the protective film 30 can be easily processed.
  • the step (S50) of processing the second epitaxial layer 12 using the first alignment mark 1 includes Although it was an ion implantation process, it is not restricted to this.
  • First alignment mark 1 may be used, for example, in a process such as a silicon carbide dry etching process, a gate electrode forming process, or an interlayer insulating film contact hole forming process.
  • p base layer 82, n region 83, and p contact region 84 are formed by ion implantation. In this case, it may be formed by epitaxial growth. In this case, the process (S50) for processing the second epitaxial layer 12 is, for example, a silicon carbide dry etching process.
  • silicon carbide semiconductor device 100 is a MOSFET, but may be, for example, a Schottky barrier diode or an IGBT (Insulated Gate Bipolar Transistor).
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • the first conductivity type is p-type and the second conductivity type is n-type. May be.
  • the present invention is particularly advantageously applied to a method for manufacturing a silicon carbide semiconductor device using a silicon carbide substrate including a main surface having an off angle with respect to the ⁇ 0001 ⁇ plane.

Abstract

A production method for a silicon carbide semiconductor device comprising: a step (S10) in which a silicon carbide substrate is prepared that includes a first main surface (10a) having an off angle relative to the {0001} plane; a step (S20) in which a first alignment mark (1) is formed upon the first main surface (10a); a step (S30) in which a protective film (30) that protects the first alignment mark (1) is formed; a step (S40) in which an epitaxial layer (a second epitaxial layer (12)) is formed upon the first main surface (10a) in a state in which the protective film (30) has been formed; and a step (S50) in which the first alignment mark (1) is used and the epitaxial layer (the second epitaxial layer (12)) is treated. As a result, a production method for a silicon carbide semiconductor device using a silicon carbide substrate comprising a main surface having an off angle can be provided that is capable of precise positioning even before and after a step in which an epitaxial layer is formed.

Description

炭化珪素半導体装置の製造方法Method for manufacturing silicon carbide semiconductor device
　本発明は、炭化珪素半導体装置の製造方法に関し、特に、オフ角を有する主面を含む炭化珪素基板を用いる炭化珪素半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a method for manufacturing a silicon carbide semiconductor device using a silicon carbide substrate including a main surface having an off angle.
　一般に、炭化珪素（ＳｉＣ）に関わらず、半導体装置の製造方法は複数の工程を備えている。そのうち、基板の主面上にデバイスパターンを形成するために基板の位置合わせが必要とされる工程、たとえばリソグラフィ工程やイオン注入工程などでは、先の工程において主面上に形成されたアライメントマークを利用して、位置合わせを行う。これにより、各工程において形成されるデバイスパターンに位置ズレが生じることを抑制でき、微細なデバイスパターンを有する半導体装置を得ることができる。 Generally, regardless of silicon carbide (SiC), a method for manufacturing a semiconductor device includes a plurality of steps. Of these, in processes that require alignment of the substrate to form a device pattern on the main surface of the substrate, such as lithography and ion implantation, alignment marks formed on the main surface in the previous step Use and align. Thereby, it is possible to suppress the occurrence of positional deviation in the device pattern formed in each step, and a semiconductor device having a fine device pattern can be obtained.
　特開２０１１－１００９２８号公報には、炭化珪素基板にアライメントマークとなるトレンチを形成した後、エピタキシャル層を成長させ、その後アライメントマークを用いて炭化珪素基板にマスクを配置する工程を含むＳｉＣ半導体装置の製造方法が開示されている。アライメントマークは、開口部の形状がオフ方向に対して対称であり、かつオフ方向の最も下流側に位置する部分に頂点を有する多角形状を有するトレンチとして形成されている。 Japanese Patent Application Laid-Open No. 2011-1000092 discloses an SiC semiconductor device including a step of forming a trench serving as an alignment mark in a silicon carbide substrate, growing an epitaxial layer, and then placing a mask on the silicon carbide substrate using the alignment mark. A manufacturing method is disclosed. The alignment mark is formed as a trench having a polygonal shape in which the shape of the opening is symmetric with respect to the off direction and the apex is located at the most downstream side in the off direction.
特開２０１１－１００９２８号公報JP 2011-1000092 A
　しかしながら、炭化珪素半導体装置の製造方法に用いられる炭化珪素基板が｛０００１｝面に対しオフ角を有する主面を含む場合には、エピタキシャル成長工程前に当該主面上に形成されたアライメントマークをエピタキシャル成長工程後において位置合わせに用いる際に、十分なアライメント精度を得ることができない場合がある。 However, when the silicon carbide substrate used in the method for manufacturing the silicon carbide semiconductor device includes a main surface having an off angle with respect to the {0001} plane, the alignment mark formed on the main surface is epitaxially grown before the epitaxial growth step. In some cases, sufficient alignment accuracy cannot be obtained when used for alignment after the process.
　これは、オフ角を有する炭化珪素基板の主面上にエピタキシャル層を成長させると、ステップフロー成長により成長方向が制限される。そのため、エピタキシャル成長工程前にオフ角を有する主面上に形成されたアライメントマークに対し、等方的にエピタキシャル層が成長するのではなく、ある特定の方向にエピタキシャル層が成長することにより、アライメントマークの形状が変形してしまうためである。この結果、変形したアライメントマークを半導体製造装置が精密に認識することができずに位置ズレを生じたり、あるいは変形したアライメントマークを半導体製造装置が認識できない場合があった。 This is because when the epitaxial layer is grown on the main surface of the silicon carbide substrate having an off angle, the growth direction is limited by step flow growth. For this reason, the alignment mark formed on the main surface having an off angle before the epitaxial growth process does not grow isotropically, but rather grows in a specific direction. This is because the shape of is deformed. As a result, the semiconductor manufacturing apparatus may not be able to accurately recognize the deformed alignment mark, or the semiconductor manufacturing apparatus may not be able to recognize the deformed alignment mark.
　本発明は、上記のような課題を解決するためになされたものである。本発明の主たる目的は、オフ角を有する主面を備える炭化珪素基板を用いた炭化珪素半導体装置の製造方法において、エピタキシャル層を形成する工程の前後においても精密な位置合わせを行うことができる、炭化珪素半導体装置の製造方法を提供することにある。 The present invention has been made to solve the above-described problems. The main object of the present invention is to enable precise alignment before and after the step of forming an epitaxial layer in a method for manufacturing a silicon carbide semiconductor device using a silicon carbide substrate having a main surface having an off angle. An object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device.
　本発明に係る炭化珪素半導体装置の製造方法は、｛０００１｝面に対してオフ角を有する主面を含む炭化珪素基板を準備する工程と、主面上に第１のアライメントマーク１を形成する工程と、第１のアライメントマーク１を保護する保護膜を形成する工程と、保護膜が形成された状態で、主面上にエピタキシャル層を形成する工程と、第１のアライメントマーク１を利用して、エピタキシャル層に対して処理を行う工程とを備える。 In the method for manufacturing a silicon carbide semiconductor device according to the present invention, a step of preparing a silicon carbide substrate including a main surface having an off angle with respect to the {0001} plane, and forming the first alignment mark 1 on the main surface. A step of forming a protective film for protecting the first alignment mark 1, a step of forming an epitaxial layer on the main surface in a state where the protective film is formed, and a step of using the first alignment mark 1. And a step of processing the epitaxial layer.
　本発明によれば、オフ角を有する主面を備える炭化珪素基板を用いた炭化珪素半導体装置の製造方法において、エピタキシャル層を形成する工程の前後で精密な位置合わせを行うことができる。 According to the present invention, in a method for manufacturing a silicon carbide semiconductor device using a silicon carbide substrate having a main surface having an off angle, precise alignment can be performed before and after the step of forming an epitaxial layer.
実施の形態１に係る炭化珪素半導体装置の製造方法のフローチャートである。3 is a flowchart of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための平面模式図である。5 is a schematic plan view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための平面模式図である。5 is a schematic plan view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態１に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 6 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. 実施の形態２に係る炭化珪素半導体装置の製造方法のフローチャートである。5 is a flowchart of a method for manufacturing a silicon carbide semiconductor device according to a second embodiment. 実施の形態２に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment. 実施の形態２に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment. 実施の形態２に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment. 実施の形態２に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment. 実施の形態２に係る炭化珪素半導体装置の製造方法を説明するための断面図である。FIG. 11 is a cross sectional view for illustrating the method for manufacturing the silicon carbide semiconductor device according to the second embodiment. 実施の形態１および実施の形態２に係る炭化珪素半導体装置の製造方法の変形例を説明するための断面図である。FIG. 11 is a cross sectional view for illustrating a modification of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment and the second embodiment.
　以下、図面を参照して、本発明の実施の形態について説明する。なお、以下の図面において、同一または相当する部分には同一の参照番号を付し、その説明は繰り返さない。また、本明細書中の結晶学的記載においては、個別方位を［］、集合方位を＜＞、個別面を（）、集合面を｛｝でそれぞれ示している。また結晶学上の指数が負であることは、通常、”－”（バー）を数字の上に付すことによって表現されるが、本明細書中では数字の前に負の符号を付している。
［本願発明の実施形態の説明］
　はじめに、本発明の実施の形態の概要を列挙する。 Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding “-” (bar) above a number. In this specification, a negative sign is added before the number. Yes.
[Description of Embodiment of Present Invention]
First, the outline of the embodiment of the present invention will be enumerated.
　（１）本発明の実施の形態に係る炭化珪素半導体装置の製造方法は、｛０００１｝面に対してオフ角を有する第１の主面１０ａを含む炭化珪素基板を準備する工程（Ｓ１０）と、第１の主面１０ａ上に第１のアライメントマーク１を形成する工程（Ｓ２０）と、第１のアライメントマーク１を保護する保護膜３０を形成する工程（Ｓ３０）と、保護膜３０が形成された状態で、第１の主面１０ａ上にエピタキシャル層（第２のエピタキシャル層１２）を形成する工程（Ｓ４０）と、第１のアライメントマーク１を利用して、エピタキシャル層（第２のエピタキシャル層１２）に対して処理を行う工程（Ｓ５０）とを備える。 (1) A method for manufacturing a silicon carbide semiconductor device according to an embodiment of the present invention includes a step (S10) of preparing a silicon carbide substrate including first main surface 10a having an off angle with respect to a {0001} plane. The step of forming the first alignment mark 1 on the first main surface 10a (S20), the step of forming the protective film 30 that protects the first alignment mark 1 (S30), and the formation of the protective film 30 In this state, an epitaxial layer (second epitaxial layer) is formed by using the first alignment mark 1 and a step (S40) of forming an epitaxial layer (second epitaxial layer 12) on the first main surface 10a. And a step (S50) of processing the layer 12).
　このようにすれば、｛０００１｝面に対してオフ角を有する第１の主面１０ａ上に形成された第１のアライメントマーク１は、エピタキシャル層（第２のエピタキシャル層１２）を形成する工程（Ｓ４０）において保護膜３０により保護されている。そのため、工程（Ｓ４０）において、保護膜３０上にエピタキシャル層は形成されていないので、第１のアライメントマーク１に対しステップフロー成長が進行して、第１のアライメントマーク１の上に形成されるエピタキシャル層の上部表面の形状が第１のアライメントマーク１の形状と異なる形状へと変形することを抑制することができる。その結果、工程（Ｓ４０）後において実施されるエピタキシャル層（第２のエピタキシャル層１２）に対して処理を行う工程（Ｓ５０）においても、第１のアライメントマーク１を利用して、精密な位置合わせを行うことができる。たとえば、エピタキシャル層（第２のエピタキシャル層１２）に対してドライエッチング等の処理をする場合、第１のアライメントマーク１を利用して、第２の主面１２ａ上の所定の位置にエッチングマスクを形成することができる。このように形成されたエッチングマスクは、工程（Ｓ４０）前に第１の主面１０ａ上に形成されたパターンに対して、位置ズレが抑制されている。つまり、本実施の形態に係る炭化珪素半導体装置の製造方法によれば、エピタキシャル層（第２のエピタキシャル層１２）を形成する工程の前後で精密な位置合わせを行うことができる。そのため、炭化珪素半導体装置の製造方法において、位置合わせの観点から、エピタキシャル層（第２のエピタキシャル層１２）を形成する工程（Ｓ４０）の工程条件や順序等を制限する必要がない。 In this way, the first alignment mark 1 formed on the first main surface 10a having an off angle with respect to the {0001} plane is a step of forming an epitaxial layer (second epitaxial layer 12). In (S40), it is protected by the protective film 30. Therefore, since no epitaxial layer is formed on the protective film 30 in the step (S <b> 40), step flow growth proceeds with respect to the first alignment mark 1 and is formed on the first alignment mark 1. The shape of the upper surface of the epitaxial layer can be prevented from being deformed to a shape different from the shape of the first alignment mark 1. As a result, also in the step (S50) of processing the epitaxial layer (second epitaxial layer 12) performed after the step (S40), the first alignment mark 1 is used for precise alignment. It can be performed. For example, when a process such as dry etching is performed on the epitaxial layer (second epitaxial layer 12), the first alignment mark 1 is used to place an etching mask at a predetermined position on the second main surface 12a. Can be formed. The etching mask formed in this manner is suppressed in positional deviation with respect to the pattern formed on the first main surface 10a before the step (S40). That is, according to the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, precise alignment can be performed before and after the step of forming the epitaxial layer (second epitaxial layer 12). Therefore, in the method for manufacturing the silicon carbide semiconductor device, it is not necessary to limit the process conditions, order, and the like of the step (S40) of forming the epitaxial layer (second epitaxial layer 12) from the viewpoint of alignment.
　（２）本発明の実施の形態に係る炭化珪素半導体装置の製造方法において、エピタキシャル層（第２のエピタキシャル層１２）に対して処理を行う工程（Ｓ５０）は、保護膜３０を除去した後実施されてもよい。 (2) In the method for manufacturing a silicon carbide semiconductor device according to the embodiment of the present invention, the step (S50) of processing the epitaxial layer (second epitaxial layer 12) is performed after removing the protective film 30. May be.
　このようにしても、エピタキシャル層（第２のエピタキシャル層１２）を形成する工程（Ｓ４０）において第１のアライメントマーク１が保護膜３０で保護されていることにより、第１のアライメントマーク１上ではステップフロー成長が進行しない。そのため、エピタキシャル層（第２のエピタキシャル層１２）に対して処理を行う工程（Ｓ５０）では、保護膜３０を形成する工程（Ｓ３０）時の形状を維持している第１のアライメントマーク１を利用して、位置合わせを行うことができる。その結果、工程（Ｓ５０）では、たとえば工程（Ｓ３０）の前に第１のアライメントマーク１を利用して第１の主面１０ａ上に形成されたパターンに対して、精密な位置合わせを行うことができる。 Even in this case, the first alignment mark 1 is protected by the protective film 30 in the step (S40) of forming the epitaxial layer (second epitaxial layer 12). Step flow growth does not progress. Therefore, in the step (S50) of processing the epitaxial layer (second epitaxial layer 12), the first alignment mark 1 that maintains the shape during the step (S30) of forming the protective film 30 is used. Thus, alignment can be performed. As a result, in the step (S50), for example, the first alignment mark 1 is used before the step (S30) to precisely align the pattern formed on the first main surface 10a. Can do.
　（３）本発明の実施の形態に係る炭化珪素半導体装置の製造方法において、エピタキシャル層（第２のエピタキシャル層１２）に対して処理を行う工程（Ｓ５０）は、第１のアライメントマーク１が保護膜３０により保護された状態で実施されてもよい。 (3) In the method for manufacturing a silicon carbide semiconductor device according to the embodiment of the present invention, the first alignment mark 1 protects the step (S50) of processing the epitaxial layer (second epitaxial layer 12). You may implement in the state protected by the film | membrane 30. FIG.
　この場合、保護膜３０の上部表面には、第１のアライメントマーク１の形状に対応した凹凸マークが形成されており、かつ、保護膜３０の上部表面にはエピタキシャル層が形成されない。したがって、エピタキシャル層（第２のエピタキシャル層１２）を形成する工程（Ｓ４０）において第１のアライメントマーク１が保護膜３０で保護されていることにより、第１のアライメントマーク１上ではステップフロー成長が進行しない。そのため、エピタキシャル層（第２のエピタキシャル層１２）に対して処理を行う工程（Ｓ５０）では、保護膜３０を形成する工程（Ｓ３０）時の形状を維持している第１のアライメントマーク１を利用して、位置合わせを行うことができる。その結果、工程（Ｓ５０）では、たとえば工程（Ｓ３０）の後であって工程（Ｓ４０）前に保護膜３０によって保護された第１のアライメントマーク１を利用して第１の主面１０ａ上に形成されたパターンに対して、精密な位置合わせを行うことができる。 In this case, an uneven mark corresponding to the shape of the first alignment mark 1 is formed on the upper surface of the protective film 30, and no epitaxial layer is formed on the upper surface of the protective film 30. Therefore, in the step of forming the epitaxial layer (second epitaxial layer 12) (S40), the first alignment mark 1 is protected by the protective film 30, so that step flow growth is performed on the first alignment mark 1. Does not progress. Therefore, in the step (S50) of processing the epitaxial layer (second epitaxial layer 12), the first alignment mark 1 that maintains the shape during the step (S30) of forming the protective film 30 is used. Thus, alignment can be performed. As a result, in the step (S50), for example, after the step (S30) and before the step (S40), the first alignment mark 1 protected by the protective film 30 is used on the first main surface 10a. Precise alignment can be performed on the formed pattern.
　（４）本発明の実施の形態に係る炭化珪素半導体装置の製造方法は、保護膜３０を形成する工程（Ｓ３０）の前に、第１のアライメントマーク１を利用して炭化珪素基板１０に対して処理を行う工程（Ｓ２５）をさらに備えてもよい。 (4) In the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present invention, the first alignment mark 1 is used for the silicon carbide substrate 10 before the step (S30) of forming the protective film 30. The process (S25) which performs a process may be further provided.
　つまり、本実施の形態に係る炭化珪素半導体装置の製造方法は、第１のアライメントマーク１を保護する保護膜３０を形成する工程（Ｓ３０）およびエピタキシャル層（第２のエピタキシャル層１２）を形成する工程（Ｓ４０）の前後に、いずれも第１のアライメントマーク１を利用する、炭化珪素基板１０に対して処理を行う工程（Ｓ２５）とエピタキシャル層（第２のエピタキシャル層１２）に対して処理を行う工程（Ｓ５０）とを備えていてもよい。このようにしても、上述のように、第１のアライメントマーク１は、工程（Ｓ４０）において保護膜３０により保護されているため、その上でのステップフロー成長が防止されている。そのため、工程（Ｓ２５）および工程（Ｓ５０）において（つまり、工程（Ｓ４０）の前後で）、第１のアライメントマーク１を利用して精密な位置合わせを行うことができる。 In other words, in the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, the step (S30) of forming protective film 30 protecting first alignment mark 1 and the epitaxial layer (second epitaxial layer 12) are formed. Before and after the process (S40), the process for the silicon carbide substrate 10 that uses the first alignment mark 1 (S25) and the process for the epitaxial layer (second epitaxial layer 12) are performed. And performing step (S50). Even in this case, as described above, since the first alignment mark 1 is protected by the protective film 30 in the step (S40), the step flow growth thereon is prevented. Therefore, in the step (S25) and the step (S50) (that is, before and after the step (S40)), precise alignment can be performed using the first alignment mark 1.
　（５）本発明の実施の形態に係る炭化珪素半導体装置の製造方法は、第１のアライメントマーク１を形成する工程（Ｓ２０）の前に、第１の主面１０ａ上に第２のアライメントマークを形成する工程（Ｓ１５）と、第２のアライメントマークを利用して炭化珪素基板に対して処理を行う工程（Ｓ１７）とをさらに備え、第１のアライメントマーク１を形成する工程（Ｓ２０）では、第２のアライメントマークを利用して第１のアライメントマーク１を形成し、保護膜３０を形成する工程（Ｓ３０）では、少なくとも第１のアライメントマーク１を保護する保護膜３０を形成してもよい。 (5) In the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present invention, the second alignment mark is formed on the first main surface 10a before the step (S20) of forming the first alignment mark 1. In the step of forming the first alignment mark 1 (S15) and the step of processing the silicon carbide substrate using the second alignment mark (S17), and the step of forming the first alignment mark 1 (S20) In the step of forming the first alignment mark 1 using the second alignment mark and forming the protective film 30 (S30), the protective film 30 that protects at least the first alignment mark 1 may be formed. Good.
　このようにすれば、エピタキシャル層（第２のエピタキシャル層１２）に対して処理を行う工程（Ｓ５０）において利用される第１のアライメントマーク１は、第１の主面１０ａ上に第２のアライメントマークを形成する工程（Ｓ１５）と第２のアライメントマークを利用して炭化珪素基板に対して処理を行う工程（Ｓ１７）との後に、第２のアライメントマークを利用して形成される（工程（Ｓ２０））。その後、第１のアライメントマーク１は、工程（Ｓ３０）において保護膜３０により保護される。その結果、上述のようにエピタキシャル層（第２のエピタキシャル層１２）を形成する工程（Ｓ４０）において、第１のアライメントマーク１に対しステップフロー成長が進行して、第１のアライメントマーク１の上に形成されるエピタキシャル層の上部表面の形状が第１のアライメントマーク１の形状と異なる形状へと変形することを抑制することができる。このため、工程（Ｓ５０）において第１のアライメントマーク１を利用することにより形成されるパターンは、工程（Ｓ４０）の前に第２のアライメントマークを利用して形成されたパターンに対して位置ズレが抑制されている。つまり、工程（Ｓ４０）の前後で実施される、炭化珪素基板に対して処理を行う工程（Ｓ１７）とエピタキシャル層（第２のエピタキシャル層１２）に対して処理を行う工程（Ｓ５０）とで利用されるアライメントマークが異なる場合であっても、保護膜３０を形成する工程（Ｓ３０）において、少なくとも工程（Ｓ５０）において利用される第１のアライメントマーク１を保護する保護膜３０を形成することにより、工程（Ｓ１７）と工程（Ｓ５０）とにおいて精密な位置合わせを行うことができる。 In this way, the first alignment mark 1 used in the step (S50) of processing the epitaxial layer (second epitaxial layer 12) is the second alignment on the first main surface 10a. After the step of forming the mark (S15) and the step of processing the silicon carbide substrate using the second alignment mark (S17), the mark is formed using the second alignment mark (step (step ( S20)). Thereafter, the first alignment mark 1 is protected by the protective film 30 in the step (S30). As a result, in the step of forming the epitaxial layer (second epitaxial layer 12) (S40) as described above, step flow growth proceeds with respect to the first alignment mark 1, and the first alignment mark 1 is It is possible to suppress the shape of the upper surface of the epitaxial layer formed in the step from being deformed to a shape different from the shape of the first alignment mark 1. Therefore, the pattern formed by using the first alignment mark 1 in the step (S50) is misaligned with the pattern formed by using the second alignment mark before the step (S40). Is suppressed. In other words, it is used in the step (S17) for processing the silicon carbide substrate and the step (S50) for processing the epitaxial layer (second epitaxial layer 12) performed before and after the step (S40). Even if the alignment marks to be used are different, in the step (S30) of forming the protective film 30, by forming the protective film 30 that protects at least the first alignment mark 1 used in the step (S50). In the step (S17) and the step (S50), precise alignment can be performed.
　（６）本発明の実施の形態に係る炭化珪素半導体装置の製造方法において、保護膜３０を構成する材料は、炭化タンタル（ＴａＣｘ）または炭素材料を含んでもよい。 (6) In the method for manufacturing the silicon carbide semiconductor device according to the embodiment of the present invention, the material forming protective film 30 may include tantalum carbide (TaC x ) or a carbon material.
　このようにすれば、保護膜３０は高い融点を有することができる。そのため、たとえば１５００℃以上１７００℃以下程度の温度条件下において行われるエピタキシャル層（第２のエピタキシャル層１２）を形成する工程（Ｓ４０）においても、保護膜３０は第１のアライメントマーク１を保護して、第１のアライメントマーク１上においてエピタキシャル層がステップフロー成長することを抑制することができる。つまり、このようにすれば、炭化珪素は保護膜３０上に成長しない。そのため、エピタキシャル層（第２のエピタキシャル層１２）に対して処理を行う工程（Ｓ５０）が保護膜３０により第１のアライメントマーク１を保護した状態で行われる場合にも、炭化珪素基板の第２の主面１２ａを平面視したとき（第２の主面１２ａに垂直な方向に沿って上部から第２の主面１２ａを見たとき）に、第１のアライメントマーク１を容易に検出することができる。なお、炭素材料としては、たとえばダイヤモンドやグラファイトを用いてもよい。 In this way, the protective film 30 can have a high melting point. Therefore, the protective film 30 protects the first alignment mark 1 also in the step (S40) of forming an epitaxial layer (second epitaxial layer 12) performed under a temperature condition of, for example, about 1500 ° C. to 1700 ° C. Thus, it is possible to suppress the step-flow growth of the epitaxial layer on the first alignment mark 1. That is, in this way, silicon carbide does not grow on protective film 30. Therefore, even when the step (S50) of processing the epitaxial layer (second epitaxial layer 12) is performed in a state where the first alignment mark 1 is protected by the protective film 30, the second of the silicon carbide substrate. The first alignment mark 1 is easily detected when the main surface 12a is viewed in plan (when the second main surface 12a is viewed from above along the direction perpendicular to the second main surface 12a). Can do. As the carbon material, for example, diamond or graphite may be used.
　（７）本発明の実施の形態に係る炭化珪素半導体装置の製造方法において、保護膜３０を形成する工程（Ｓ３０）では、エピタキシャル層（第２のエピタキシャル層１２）を形成する工程（Ｓ４０）において形成されるエピタキシャル層（第２のエピタキシャル層１２）の厚みに対して、０．５倍以上１．５倍以下の厚みを有する保護膜３０が形成されてもよい。 (7) In the method for manufacturing a silicon carbide semiconductor device according to the embodiment of the present invention, in the step of forming protective film 30 (S30), in the step of forming epitaxial layer (second epitaxial layer 12) (S40) A protective film 30 having a thickness of 0.5 to 1.5 times the thickness of the formed epitaxial layer (second epitaxial layer 12) may be formed.
　保護膜３０の厚みがエピタキシャル層（第２のエピタキシャル層１２）の厚みの０．５倍未満である場合には、エピタキシャル層（第２のエピタキシャル層１２）が保護膜３０の上部に張り出すように成長（オーバーハング）する可能性がある。この場合、保護膜３０の上部に張り出すように成長したエピタキシャル層（第２のエピタキシャル層１２）に囲まれた領域には、異物等がたまりやすくなる。また、このようにオーバーハングしたエピタキシャル層（第２のエピタキシャル層１２）は、その後第２の主面１２ａ上に成膜される膜の膜剥がれの起点となる場合がある。そのため、保護膜３０の厚みを、エピタキシャル層（第２のエピタキシャル層１２）の厚みの０．５倍以上とすることにより、保護膜３０の上部にエピタキシャル層（第２のエピタキシャル層１２）がオーバーハングすることを抑制することができる。さらに、エピタキシャル層（第２のエピタキシャル層１２）のオーバーハングに起因した異常の発生を抑制することができる。また、保護膜３０の厚みがエピタキシャル層（第２のエピタキシャル層１２）の厚みより厚い場合には、上述したエピタキシャル層（第２のエピタキシャル層１２）のオーバーハングを確実に防止することができる。しかし、保護膜３０の厚みがエピタキシャル層（第２のエピタキシャル層１２）の厚みの１．５倍超えである場合には、オーバーハング防止の観点からは必要以上に厚く、かつ、エピタキシャル層（第２のエピタキシャル層１２）の厚みによっては保護膜３０の加工が困難になる。そのため、保護膜３０の厚みはエピタキシャル層（第２のエピタキシャル層１２）の厚みの０．５倍以上１．５倍以下とすれば、エピタキシャル層（第２のエピタキシャル層１２）のオーバーハングを防止することができるとともに、保護膜３０を容易に加工することができる。 When the thickness of the protective film 30 is less than 0.5 times the thickness of the epitaxial layer (second epitaxial layer 12), the epitaxial layer (second epitaxial layer 12) projects over the protective film 30. May grow (overhang). In this case, foreign matter or the like tends to accumulate in a region surrounded by the epitaxial layer (second epitaxial layer 12) grown so as to overhang the protective film 30. Further, the overhanging epitaxial layer (second epitaxial layer 12) may be a starting point of film peeling of a film formed on the second main surface 12a thereafter. Therefore, when the thickness of the protective film 30 is 0.5 times or more the thickness of the epitaxial layer (second epitaxial layer 12), the epitaxial layer (second epitaxial layer 12) overlies the protective film 30. Hang can be suppressed. Furthermore, it is possible to suppress the occurrence of abnormality due to the overhang of the epitaxial layer (second epitaxial layer 12). Moreover, when the thickness of the protective film 30 is thicker than the thickness of the epitaxial layer (second epitaxial layer 12), the above-described overhang of the epitaxial layer (second epitaxial layer 12) can be reliably prevented. However, when the thickness of the protective film 30 exceeds 1.5 times the thickness of the epitaxial layer (second epitaxial layer 12), it is thicker than necessary from the viewpoint of preventing overhang, and the epitaxial layer (first Depending on the thickness of the second epitaxial layer 12), the processing of the protective film 30 becomes difficult. Therefore, if the thickness of the protective film 30 is 0.5 to 1.5 times the thickness of the epitaxial layer (second epitaxial layer 12), an overhang of the epitaxial layer (second epitaxial layer 12) is prevented. In addition, the protective film 30 can be easily processed.
　なお、本発明において、第１のアライメントマーク１および第２のアライメントマークは、それぞれ１つの工程において炭化珪素基板の主面１０ａ，１２ａ上に形成された複数のアライメントマークを含む総称である。具体的には、たとえば第１のアライメントマーク１を形成する工程（Ｓ２０）において、第１の主面１０ａ上にはダイシングライン上に複数の第１のアライメントマーク１が形成される。たとえば、ステッパなどを用いて投影露光する場合には、レチクル上に第１のアライメントマーク１に相当するレチクルパターンが形成されており、第１のアライメントマーク１の数はショット数程度である。このとき、炭化珪素基板１０に対して処理を行う工程（Ｓ２５）において、「第１のアライメントマーク１を利用して」とは、工程（Ｓ２０）において第１の主面１０ａ上に形成された複数の第１のアライメントマーク１のうち、炭化珪素基板を位置合わせするのに効果的な位置に形成された必要十分な数の第１のアライメントマーク１を抜き取りで検出してアライメントに用いることも含んでいる。 In the present invention, the first alignment mark 1 and the second alignment mark are generic names including a plurality of alignment marks formed on the main surfaces 10a and 12a of the silicon carbide substrate in one step. Specifically, for example, in the step of forming the first alignment mark 1 (S20), a plurality of first alignment marks 1 are formed on the dicing line on the first main surface 10a. For example, when projection exposure is performed using a stepper or the like, a reticle pattern corresponding to the first alignment mark 1 is formed on the reticle, and the number of the first alignment marks 1 is about the number of shots. At this time, in the step (S25) of processing the silicon carbide substrate 10, "using the first alignment mark 1" is formed on the first main surface 10a in the step (S20). Of the plurality of first alignment marks 1, a necessary and sufficient number of first alignment marks 1 formed at positions effective for aligning the silicon carbide substrate can be extracted and used for alignment. Contains.
　また、エピタキシャル層（第２のエピタキシャル層１２）に対して処理を行う工程（Ｓ５０）において、「第１のアライメントマーク１を利用して」とは、炭化珪素基板１０に対して処理を行う工程（Ｓ２０）において第１の主面１０ａ上に形成された複数の第１のアライメントマーク１のうち、炭化珪素基板を位置合わせするのに効果的な位置に形成された、必要十分な数の第１のアライメントマーク１のみを検出してアライメントに用いることも含んでいる。さらにこのとき、工程（Ｓ２５）および工程（Ｓ５０）においてアライメントに利用される第１のアライメントマーク１は、第１の主面１０ａ上の同一の位置に形成された同一のアライメントマークである必要はなく、異なる位置に形成された異なる第１のアライメントマーク１をアライメントに用いてもよい。このようにしても、工程（Ｓ２０）において第１の主面１０ａ上に形成された複数の第１のアライメントマーク１同士は、互いに所定の位置関係で形成されているため、工程（Ｓ２５）と工程（Ｓ５０）との位置合わせ精度（重ね合わせ精度）を高めることができる。 Further, in the step (S50) of processing the epitaxial layer (second epitaxial layer 12), “using the first alignment mark 1” means a step of processing the silicon carbide substrate 10. Of the plurality of first alignment marks 1 formed on the first main surface 10a in (S20), a necessary and sufficient number of first alignment marks formed at positions effective for aligning the silicon carbide substrate. It also includes detecting only one alignment mark 1 and using it for alignment. Further, at this time, the first alignment mark 1 used for alignment in the step (S25) and the step (S50) needs to be the same alignment mark formed at the same position on the first main surface 10a. Alternatively, different first alignment marks 1 formed at different positions may be used for alignment. Even in this case, since the plurality of first alignment marks 1 formed on the first main surface 10a in the step (S20) are formed in a predetermined positional relationship with each other, the step (S25) and The alignment accuracy (superposition accuracy) with the step (S50) can be increased.
　また、一般に、アライメントマークの検出方法には、ＬＳＡ（Laser　Step　Alignment）方式とＦＩＡ（Field　Image　Alignment）方式との２つの方式があるが、本実施の形態に係る炭化珪素半導体装置の製造方法ではいずれの方式であっても適用可能である。つまり、本実施の形態に係る炭化珪素半導体装置の製造方法によれば、上述のように、アライメントマーク上にエピタキシャル層がステップフロー成長することを防止することができるため、アライメントマークが変形することを防止することができる。そのため、レーザーをアライメントマークにあててレーザーの反射光を分析し、位置合わせを行うＬＳＡ方式（光学式アライメント方式）や、カメラで認識した画像のエッジを認識してアライメントを行うＦＩＡ方式（画像認識方式）でも、エピタキシャル層（第２のエピタキシャル層１２）を形成後においても高い精度でアライメントマークを検出することができる。 In general, there are two methods for detecting an alignment mark: an LSA (Laser Step Alignment) method and an FIA (Field Image Alignment) method. In the method for manufacturing a silicon carbide semiconductor device according to the present embodiment, Either method is applicable. That is, according to the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, as described above, it is possible to prevent the epitaxial layer from growing in the step flow on the alignment mark, so that the alignment mark is deformed. Can be prevented. Therefore, the laser is applied to the alignment mark, the reflected light of the laser is analyzed and alignment is performed, and the LIA method (optical alignment method) that performs alignment, or the FIA method that recognizes the edge of the image recognized by the camera and performs alignment (image recognition) Method), the alignment mark can be detected with high accuracy even after the epitaxial layer (second epitaxial layer 12) is formed.
　また、本実施の形態に係る炭化珪素基板は、単結晶基板などのベース基板上にエピタキシャル層が形成されたエピタキシャル基板であってもよいし、エピタキシャル基板からベース基板が除去されたエピタキシャル層であってもよい。
［本願発明の実施の形態の詳細］
　次に、本発明の実施の形態についてより詳細に説明する。 The silicon carbide substrate according to the present embodiment may be an epitaxial substrate in which an epitaxial layer is formed on a base substrate such as a single crystal substrate, or an epitaxial layer in which the base substrate is removed from the epitaxial substrate. May be.
[Details of the embodiment of the present invention]
Next, embodiments of the present invention will be described in more detail.
　（実施の形態１）
　図１～図２１を参照して、本発明の実施の形態１に係る炭化珪素半導体装置の製造方法について説明する。まず、｛０００１｝面に対してオフ角を有する第１の主面１０ａを含む炭化珪素基板１０を準備する（工程（Ｓ１０））。炭化珪素基板１０は、炭化珪素単結晶基板８０と、炭化珪素単結晶基板８０上に形成された炭化珪素からなる第１のエピタキシャル層８１ａとを有する、エピタキシャル基板である。第１のエピタキシャル層８１ａは、たとえば導電型がｎ型であって、不純物濃度が４×１０１５ｃｍ－３程度である。 (Embodiment 1)
A method for manufacturing a silicon carbide semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. First, silicon carbide substrate 10 including first main surface 10a having an off angle with respect to the {0001} plane is prepared (step (S10)). Silicon carbide substrate 10 is an epitaxial substrate having a silicon carbide single crystal substrate 80 and a first epitaxial layer 81 a made of silicon carbide formed on silicon carbide single crystal substrate 80. First epitaxial layer 81a has, for example, an n-type conductivity and an impurity concentration of about 4 × 10 15 cm −3 .
　図２を参照して、第１の主面１０ａは、第１のエピタキシャル層８１ａに含まれている。第１の主面１０ａは、｛０００１｝面（破線で示す面）からオフ角θだけオフ方向ａ１にオフした（傾いた）面である。オフ角θは、好ましくは１°以上８°以下の角度である。具体的には、第１の主面１０ａの法線ベクトルｚが＜１１－２０＞および＜１－１００＞の少なくとも一方の成分を有するように、第１の主面１０ａは｛０００１｝面からオフした面である。好ましくは、第１の主面１０ａの法線ベクトルｚが＜１１－２０＞の成分を有するように、第１の主面１０ａは｛０００１｝面からオフした面である。 Referring to FIG. 2, first main surface 10a is included in first epitaxial layer 81a. The first major surface 10a is a {0001} plane and off only off direction a 1 off angle θ from (surface indicated by the broken line) (inclined) surface. The off angle θ is preferably an angle of 1 ° to 8 °. Specifically, the first major surface 10a is from the {0001} plane so that the normal vector z of the first major surface 10a has at least one component of <11-20> and <1-100>. It is a surface that has been turned off. Preferably, the first main surface 10a is a surface off from the {0001} plane so that the normal vector z of the first main surface 10a has a component of <11-20>.
　図２において、方向ｃは［０００１］方向（つまり六方晶炭化珪素のｃ軸）であり、方向ａ１はたとえば＜１１－２０＞方向である。第１の主面１０ａの法線ベクトルｚは、［０００１］方向から＜１１－２０＞方向に傾斜している。またオリエンテーションフラット（ＯＦ：図４参照）が延在する方向ａ１１は、たとえば＜１－１００＞方向である。 In FIG. 2, direction c is the [0001] direction (that is, the c-axis of hexagonal silicon carbide), and direction a 1 is, for example, the <11-20> direction. The normal vector z of the first major surface 10a is inclined in the <11-20> direction from the [0001] direction. Further, the direction a 11 in which the orientation flat (OF: see FIG. 4) extends is, for example, the <1-100> direction.
　次に、第１の主面１０ａ上に第１のアライメントマーク１を形成する（工程（Ｓ２０））。具体的には、図３を参照して、たとえばレジストマスク２０を第１の主面１０ａ上に形成し、レジストマスク２０をエッチングマスクとして第１のアライメントマーク１を形成する。第１のアライメントマーク１は、たとえば反応性イオンエッチング（ＲＩＥ）法などのドライエッチング法により、レジストマスク２０の開口部に露出している炭化珪素基板１０の第１のエピタキシャル層８１ａがエッチングされて、第１の主面１０ａに対する段差部が形成されることにより設けられる。つまり、第１のアライメントマーク１は、たとえば図６に示すように、第１の主面１０ａを含む第１の凸部１ａと、第１の主面１０ａに開口部を有する第１の凹部１ｂとを含むように形成される。第１の主面１０ａに対する第１の凹部１ｂの深さは、たとえば０．５μｍ以上２μｍ以下程度であり、好ましくは、０．７μｍ以上１．５μｍ以下程度であり、さらに好ましくは０．７μｍ以上１．０μｍ以下程度である。レジストマスク２０は、第１のアライメントマーク１を形成後、任意の方法で除去される。 Next, the first alignment mark 1 is formed on the first main surface 10a (step (S20)). Specifically, referring to FIG. 3, for example, resist mask 20 is formed on first main surface 10a, and first alignment mark 1 is formed using resist mask 20 as an etching mask. First alignment mark 1 is formed by etching first epitaxial layer 81a of silicon carbide substrate 10 exposed in the opening of resist mask 20 by a dry etching method such as a reactive ion etching (RIE) method. , Provided by forming a stepped portion with respect to the first main surface 10a. That is, as shown in FIG. 6, for example, the first alignment mark 1 includes a first convex portion 1a including the first main surface 10a, and a first concave portion 1b having an opening in the first main surface 10a. And so as to include. The depth of the first recess 1b with respect to the first main surface 10a is, for example, about 0.5 μm to 2 μm, preferably about 0.7 μm to 1.5 μm, and more preferably 0.7 μm or more. It is about 1.0 μm or less. The resist mask 20 is removed by an arbitrary method after forming the first alignment mark 1.
　図３および図４を参照して、第１のアライメントマーク１は、炭化珪素基板１０の第１の主面１０ａ上に形成されるダイシングライン１０２上に形成されてもよい。ダイシングライン１０２は、炭化珪素基板１０上に複数の半導体装置を形成した後、ダイシング工程において個々の半導体装置に切断分離するときの、切断が予定されている位置である。つまり、ダイシングライン１０２は、たとえばオリエンテーションフラットが延びる方向に平行な方向ａ１１と、該方向ａ１１に垂直な方向ａ１２のそれぞれに沿って複数のダイシングラインが形成されてもよい。半導体装置の形成領域１０１は、ダイシングライン１０２に囲まれるように複数形成されてもよい。 Referring to FIGS. 3 and 4, first alignment mark 1 may be formed on dicing line 102 formed on first main surface 10 a of silicon carbide substrate 10. The dicing line 102 is a position where cutting is planned when a plurality of semiconductor devices are formed on the silicon carbide substrate 10 and then separated into individual semiconductor devices in the dicing process. That is, the dicing lines 102, for example, the direction a 11 parallel to the direction in which the orientation flat extends, a plurality of dicing lines may be formed along the respective perpendicular direction a 12 in the direction a 11. A plurality of semiconductor device formation regions 101 may be formed so as to be surrounded by the dicing lines 102.
　図５および図６を参照して、第１のアライメントマーク１の第１の凸部１ａは、平面視したときに、たとえば長手方向と短手方向とを有する長方形状に形成されてもよい。第１の凸部１ａの長手方向は、ダイシングライン１０２が延びる方向と平行に形成されていてもよいし、交差するように形成されていてもよい。第１の凸部１ａの長手方向の長さＬ１はたとえば８０μｍであり、第１の凸部１ａの短手方向の長さはたとえば９μｍである。ダイシングライン１０２が延びる方向に対して垂直な方向におけるダイシングライン１０２の幅Ｌ３は、たとえば１２０μｍである。ここで、図６は図５の線分ＶＩ－ＶＩにおける断面図である。 5 and 6, the first convex portion 1a of the first alignment mark 1 may be formed in a rectangular shape having, for example, a longitudinal direction and a lateral direction when viewed in plan. The longitudinal direction of the 1st convex part 1a may be formed in parallel with the direction where the dicing line 102 is extended, and may be formed so that it may cross | intersect. The length L1 in the longitudinal direction of the first protrusion 1a is, for example, 80 μm, and the length in the short direction of the first protrusion 1a is, for example, 9 μm. The width L3 of the dicing line 102 in the direction perpendicular to the direction in which the dicing line 102 extends is, for example, 120 μm. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG.
　次に、炭化珪素基板１０に対して処理を行う（工程（Ｓ２５））。図７を参照して、具体的には、第１のアライメントマーク１を利用して、第１の主面１０ａ上にイオン注入マスク（図示しない）を形成し、該イオン注入マスクを介して第１の主面１０ａにイオン注入することにより、半導体装置の形成領域１０１内の第１のエピタキシャル層８１ａ上の所定の位置にイオン注入領域１１を形成する。イオン注入領域１１は、たとえば導電型がｐ型であって、不純物濃度が１×１０１７ｃｍ－３程度である。 Next, processing is performed on silicon carbide substrate 10 (step (S25)). Referring to FIG. 7, specifically, an ion implantation mask (not shown) is formed on first main surface 10a using first alignment mark 1, and the first alignment mark 1 is used to form the first alignment mark 1 through the ion implantation mask. By ion-implanting into one main surface 10a, the ion-implanted region 11 is formed at a predetermined position on the first epitaxial layer 81a in the formation region 101 of the semiconductor device. Ion implantation region 11 has, for example, a p-type conductivity and an impurity concentration of about 1 × 10 17 cm −3 .
　次に、第１のアライメントマーク１を保護する保護膜３０を形成する（工程（Ｓ３０）。具体的には、図８を参照して、まず、炭化珪素基板１０の第１の主面１０ａ上に保護膜３０を形成する。保護膜３０を構成する材料は、たとえば炭化タンタル（ＴａＣ）、または炭素材料である。炭素材料は、炭素原子を含む任意の材料とすればよく、たとえばグラファイトあるいはダイヤモンドなどである。保護膜３０の厚みｈ１（図９参照）は、この後の工程Ｓ４０において形成される第２のエピタキシャル層１２の厚みｈ２（図１０参照）に応じて決めればよい。保護膜３０の厚みｈ１は、第２のエピタキシャル層１２の厚みｈ２の０．５倍以上１．５倍以下となるように形成されるのが好ましい。本実施の形態においては、保護膜３０の厚みｈ１は、第２のエピタキシャル層１２の厚みｈ２と同等となるように設けられている。 Next, a protective film 30 is formed to protect the first alignment mark 1 (step (S30)) Specifically, referring to Fig. 8, first, on first main surface 10a of silicon carbide substrate 10. A protective film 30 is formed on the protective film 30. The material constituting the protective film 30 is, for example, tantalum carbide (TaC) or a carbon material, which may be any material containing carbon atoms, such as graphite or diamond. The thickness h1 (see FIG. 9) of the protective film 30 may be determined according to the thickness h2 (see FIG. 10) of the second epitaxial layer 12 to be formed in the subsequent step S40. The thickness h1 is preferably 0.5 times or more and 1.5 times or less than the thickness h2 of the second epitaxial layer 12. In the present embodiment, the thickness of the protective film 30 is set. 1 is provided so as to be equal to the thickness h2 of the second epitaxial layer 12.
　本工程（Ｓ３０）では、次に、図９を参照して、後の工程（Ｓ４０）において第２のエピタキシャル層１２を形成する領域上に形成された保護膜３０を除去する。具体的には、たとえばレジストマスク３５を保護膜３０上に形成し、レジストマスク３５をエッチングマスクとして保護膜３０をパターニングする。これにより、第１のアライメントマーク１上など、後の工程（Ｓ４０）においてエピタキシャル成長させる際にステップフロー成長を防止する必要のある領域は保護膜３０により保護されるとともに、第２のエピタキシャル層１２を形成する領域は第１の主面１０ａが露出する。その後、レジストマスク３５は任意の方法により除去される。 In this step (S30), next, referring to FIG. 9, the protective film 30 formed on the region for forming the second epitaxial layer 12 in the subsequent step (S40) is removed. Specifically, for example, a resist mask 35 is formed on the protective film 30, and the protective film 30 is patterned using the resist mask 35 as an etching mask. As a result, a region where step flow growth needs to be prevented when epitaxially growing in the subsequent step (S40), such as on the first alignment mark 1, is protected by the protective film 30, and the second epitaxial layer 12 is formed. In the region to be formed, the first main surface 10a is exposed. Thereafter, the resist mask 35 is removed by an arbitrary method.
　次に、第２のエピタキシャル層１２を形成する（工程（Ｓ４０））。具体的には、図１０を参照して、第２のエピタキシャル層１２は、第１のエピタキシャル層８１ａにイオン注入領域１１が形成された後、炭化珪素基板１０の第１の主面１０ａ上に形成される。第２のエピタキシャル層１２は、たとえば導電型がｎ型であって、不純物濃度が７×１０１５ｃｍ－３程度である。このとき、第２のエピタキシャル層１２は、ステップフロー成長することにより、オフ角を有する第１の主面１０ａ上に形成される。一方、保護膜３０上（保護膜３０により保護されている第１のアライメントマーク１上）ではステップフロー成長は起こらず、第２のエピタキシャル層１２は成長しない。そのため、第１のアライメントマーク１のパターン形状および該第１のアライメントマーク１のパターン形状を覆うように形成された保護膜３０のパターン形状は、ステップフロー成長による変形が抑制されている。 Next, the second epitaxial layer 12 is formed (step (S40)). Specifically, referring to FIG. 10, second epitaxial layer 12 is formed on first main surface 10 a of silicon carbide substrate 10 after ion implantation region 11 is formed in first epitaxial layer 81 a. It is formed. Second epitaxial layer 12 has an n-type conductivity, for example, and an impurity concentration of about 7 × 10 15 cm −3 . At this time, the second epitaxial layer 12 is formed on the first main surface 10a having an off angle by performing step flow growth. On the other hand, step flow growth does not occur on the protective film 30 (on the first alignment mark 1 protected by the protective film 30), and the second epitaxial layer 12 does not grow. Therefore, the pattern shape of the first alignment mark 1 and the pattern shape of the protective film 30 formed so as to cover the pattern shape of the first alignment mark 1 are suppressed from being deformed by step flow growth.
　第２のエピタキシャル層１２は、保護膜３０が形成されていない領域において、第２の主面１２ａと、第２の主面１２ａの反対側に位置して第１の主面１０ａと接する裏面１２ｂとを含む。本実施の形態において、第２のエピタキシャル層１２の厚みｈ２は、上述のように、保護膜３０の厚みｈ１と同等である。図１２は、本工程（Ｓ４０）において第２のエピタキシャル層１２を形成した後の、半導体装置の形成領域１０１の断面図である。本工程（Ｓ４０）によって、イオン注入領域１１は、炭化珪素基板１０（第１のエピタキシャル層８１ａ）と第２のエピタキシャル層１２とに埋め込まれる。本工程（Ｓ４０）において、第２のエピタキシャル層１２を形成した後、第１のアライメントマーク１を保護していた保護膜３０は、図１１に示すように除去されてもよい。 The second epitaxial layer 12 includes a second main surface 12a and a back surface 12b that is located opposite to the second main surface 12a and is in contact with the first main surface 10a in a region where the protective film 30 is not formed. Including. In the present embodiment, the thickness h2 of the second epitaxial layer 12 is equivalent to the thickness h1 of the protective film 30 as described above. FIG. 12 is a cross-sectional view of the formation region 101 of the semiconductor device after the second epitaxial layer 12 is formed in this step (S40). By this step (S40), ion implantation region 11 is embedded in silicon carbide substrate 10 (first epitaxial layer 81a) and second epitaxial layer 12. In this step (S40), after forming the second epitaxial layer 12, the protective film 30 protecting the first alignment mark 1 may be removed as shown in FIG.
　次に、第２のエピタキシャル層１２に対して処理を行う（工程（Ｓ５０））。具体的には、まず、図１３を参照して、第２の主面１２ａにイオン注入することにより、半導体装置の形成領域１０１内の第２のエピタキシャル層１２上に、ｐベース層８２およびｎ領域８３を形成する。次に、図１４を参照して、第１のアライメントマーク１を利用して第２の主面１２ａ上にイオン注入マスク（図示しない）を形成する。次に、該イオン注入マスクを介して第２の主面１２ａにイオン注入することにより、ｐベース層８２上にｐコンタクト領域８４を形成する。第１のアライメントマーク１の検出方法は、上述のように、ＬＳＡ方式とＦＩＡ方式のいずれであってもよい。ｐベース層８２およびｐコンタクト領域８４を形成するためのイオン注入においては、たとえばアルミニウム（Ａｌ）などの、ｐ型を付与するための不純物がイオン注入される。またｎ領域８３を形成するためのイオン注入においては、たとえばリン（Ｐ）などの、ｎ型を付与するための不純物をイオン注入する。 Next, the second epitaxial layer 12 is processed (step (S50)). Specifically, referring to FIG. 13, first, ions are implanted into second main surface 12a to form p base layer 82 and n on second epitaxial layer 12 in formation region 101 of the semiconductor device. Region 83 is formed. Next, referring to FIG. 14, an ion implantation mask (not shown) is formed on second main surface 12 a using first alignment mark 1. Next, the p contact region 84 is formed on the p base layer 82 by implanting ions into the second major surface 12a through the ion implantation mask. As described above, the detection method of the first alignment mark 1 may be either the LSA method or the FIA method. In ion implantation for forming p base layer 82 and p contact region 84, an impurity for imparting p-type, such as aluminum (Al), is implanted. In ion implantation for forming n region 83, an impurity such as phosphorus (P) for imparting n-type is ion-implanted.
　次に、不純物を活性化するための熱処理を行う。この熱処理の温度は、好ましくは１５００℃以上１９００℃以下であり、たとえば１７００℃程度である。熱処理の時間は、たとえば３０分程度である。熱処理の雰囲気は、好ましくは不活性ガス雰囲気であり、たとえばＡｒ雰囲気である。 Next, heat treatment is performed to activate the impurities. The temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The heat treatment time is, for example, about 30 minutes. The atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an Ar atmosphere.
　次に、第２の主面１２ａに開口部を有するトレンチを形成する。具体的には、まず、図１５を参照して、ｎ領域８３およびｐコンタクト領域８４からなる主面１２ａ上に、開口部を有するマスク層４０が形成される。マスク層４０として、たとえばシリコン酸化膜などを用いることができる。開口部はトレンチＴＲ（図１９参照）の位置に対応して形成される。当該マスク層４０は、第１のアライメントマーク１または第２のエピタキシャル層１２に形成された第１のアライメントマーク１と異なる第２のアライメントマークを利用して、上記開口部に対応する位置が露光されるようにアライメントされて形成されてもよい。 Next, a trench having an opening in the second main surface 12a is formed. Specifically, first, referring to FIG. 15, mask layer 40 having an opening is formed on main surface 12 a formed of n region 83 and p contact region 84. As mask layer 40, for example, a silicon oxide film or the like can be used. The opening is formed corresponding to the position of trench TR (see FIG. 19). The mask layer 40 uses a second alignment mark different from the first alignment mark 1 formed on the first alignment mark 1 or the second epitaxial layer 12, and the position corresponding to the opening is exposed. It may be formed in an aligned manner.
　次に、図１６を参照して、マスク層４０の開口部において、ｎ領域８３と、ｐベース層８２と、第２のエピタキシャル層１２の一部とをエッチングにより除去する。エッチングの方法としては、たとえば反応性イオンエッチング（ＲＩＥ）、特に誘導結合プラズマ（ＩＣＰ）ＲＩＥを用いることができる。具体的には、たとえば反応ガスとしてＳＦ6またはＳＦ6とＯ2との混合ガスを用いたＩＣＰ－ＲＩＥを用いることができる。このようなエッチングにより、トレンチＴＲ（図１９参照）が形成されるべき領域に、第２の主面１２ａに対してほぼ垂直な側壁を有する凹部ＴＱが形成される。 Next, referring to FIG. 16, n region 83, p base layer 82, and part of second epitaxial layer 12 are removed by etching in the opening of mask layer 40. As an etching method, for example, reactive ion etching (RIE), particularly inductively coupled plasma (ICP) RIE can be used. Specifically, for example, ICP-RIE using SF 6 or a mixed gas of SF 6 and O 2 as a reaction gas can be used. By such etching, a recess TQ having a side wall substantially perpendicular to the second main surface 12a is formed in a region where the trench TR (see FIG. 19) is to be formed.
　次に、凹部ＴＱにおいて熱エッチングを行う。熱エッチングは、たとえば、少なくとも１種類以上のハロゲン原子を有する反応性ガスを含む雰囲気中での加熱によって行い得る。少なくとも１種類以上のハロゲン原子は、塩素（Ｃｌ）原子およびフッ素（Ｆ）原子の少なくともいずれかを含む。この雰囲気は、たとえば、Ｃｌ2、ＢＣＬ3、ＳＦ6、またはＣＦ4である。たとえば、塩素ガスと酸素ガスとの混合ガスを反応ガスとして用い、熱処理温度を、たとえば７００℃以上１０００℃以下として、熱エッチングが行われる。 Next, thermal etching is performed in the recess TQ. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms. The at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. This atmosphere is, for example, Cl 2 , BCL 3 , SF 6 , or CF 4 . For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and a heat treatment temperature of, for example, 700 ° C. or more and 1000 ° C. or less.
　なお、反応ガスは、上述した塩素ガスと酸素ガスとに加えて、キャリアガスを含んでいてもよい。キャリアガスとしては、たとえば窒素（Ｎ2）ガス、アルゴンガス、ヘリウムガスなどを用いることができる。そして、上述のように熱処理温度を７００℃以上１０００℃以下とした場合、炭化珪素のエッチング速度はたとえば約７０μｍ／時になる。また、この場合に、酸化珪素から作られたマスク層４０は、炭化珪素に対する選択比が極めて大きいので、炭化珪素のエッチング中に実質的にエッチングされない。 Note that the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen (N 2 ) gas, argon gas, helium gas or the like can be used. When the heat treatment temperature is set to 700 ° C. or higher and 1000 ° C. or lower as described above, the etching rate of silicon carbide is about 70 μm / hour, for example. Further, in this case, the mask layer 40 made of silicon oxide has a very high selectivity with respect to silicon carbide, and therefore is not substantially etched during the etching of silicon carbide.
　次に、図１７に示すように、上記の熱エッチングにより、第１のエピタキシャル層８１ａおよび第２のエピタキシャル層１２の上面上にトレンチＴＲを形成する。トレンチＴＲは、ｎ領域８３およびｐベース層８２を貫通して第２のエピタキシャル層１２に至る側壁面ＳＷと、第２のエピタキシャル層１２上に位置する底面ＢＴとを有する。側壁面ＳＷおよび底面ＢＴの各々はイオン注入領域１１から離れている。次にマスク層４０がエッチングなど任意の方法により除去される。 Next, as shown in FIG. 17, a trench TR is formed on the upper surfaces of the first epitaxial layer 81a and the second epitaxial layer 12 by the thermal etching described above. Trench TR has side wall surface SW passing through n region 83 and p base layer 82 to second epitaxial layer 12, and bottom surface BT located on second epitaxial layer 12. Each of sidewall surface SW and bottom surface BT is separated from ion implantation region 11. Next, the mask layer 40 is removed by an arbitrary method such as etching.
　次に、図１８に示すように、トレンチＴＲの側壁面ＳＷおよび底面ＢＴの各々を覆うゲート酸化膜９１を形成する。ゲート酸化膜９１は、たとえば熱酸化により形成され得る。この後に、雰囲気ガスとして一酸化窒素（ＮＯ）ガスを用いるＮＯアニールが行われてもよい。温度プロファイルは、たとえば、温度１１００℃以上１３００℃以下、保持時間１時間程度の条件を有する。これにより、ゲート酸化膜９１とｐベース層８２との界面領域に窒素原子が導入される。その結果、界面領域における界面準位の形成が抑制されることで、チャネル移動度を向上させることができる。なお、このような窒素原子の導入が可能であれば、ＮＯガス以外のガスが雰囲気ガスとして用いられてもよい。このＮＯアニールの後にさらに、雰囲気ガスとしてアルゴン（Ａｒ）を用いるＡｒアニールが行われてもよい。Ａｒアニールの加熱温度は、上記ＮＯアニールの加熱温度よりも高く、ゲート酸化膜９１の融点よりも低いことが好ましい。この加熱温度が保持される時間は、たとえば１時間程度である。これにより、ゲート酸化膜９１とｐベース層８２との界面領域における界面準位の形成がさらに抑制される。なお、雰囲気ガスとして、Ａｒガスに代えて窒素ガスなどの他の不活性ガスが用いられてもよい。トレンチＴＲの側壁面ＳＷは、面方位｛０－３３－８｝を有し、好ましくは面方位（０－３３－８）を有する所定の面を含んでいてもよい。 Next, as shown in FIG. 18, a gate oxide film 91 covering each of the sidewall surface SW and the bottom surface BT of the trench TR is formed. Gate oxide film 91 can be formed, for example, by thermal oxidation. Thereafter, NO annealing using nitrogen monoxide (NO) gas as the atmospheric gas may be performed. The temperature profile has, for example, conditions of a temperature of 1100 ° C. to 1300 ° C. and a holding time of about 1 hour. Thereby, nitrogen atoms are introduced into the interface region between gate oxide film 91 and p base layer 82. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved. As long as such nitrogen atoms can be introduced, a gas other than NO gas may be used as the atmospheric gas. Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing. The heating temperature for Ar annealing is preferably higher than the heating temperature for NO annealing and lower than the melting point of the gate oxide film 91. The time during which this heating temperature is maintained is, for example, about 1 hour. Thereby, the formation of interface states in the interface region between gate oxide film 91 and p base layer 82 is further suppressed. Note that other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas. Sidewall surface SW of trench TR has a plane orientation {0-33-8}, and may preferably include a predetermined plane having a plane orientation (0-33-8).
　次に、図１９に示すように、ゲート酸化膜９１上にゲート電極９２を形成する。具体的には、トレンチＴＲの内部の領域をゲート酸化膜９１を介して埋めるように、ゲート酸化膜９１上にゲート電極９２が形成される。ゲート電極９２の形成方法は、たとえば、導体またはドープトポリシリコンの成膜とＣＭＰ（Chemical　Mechanical　Polishing）とによって行い得る。 Next, as shown in FIG. 19, a gate electrode 92 is formed on the gate oxide film 91. Specifically, gate electrode 92 is formed on gate oxide film 91 so as to fill the region inside trench TR with gate oxide film 91 interposed therebetween. The gate electrode 92 can be formed, for example, by film formation of conductor or doped polysilicon and CMP (Chemical Mechanical Polishing).
　次に、図２０を参照して、ゲート電極９２の露出面を覆うように、ゲート電極９２およびゲート酸化膜９１上に層間絶縁膜９３を形成する。その後、層間絶縁膜９３およびゲート酸化膜９１に開口部が形成されるようにエッチングが行われる。この開口部により上面Ｐ２上においてｎ領域８３およびｐコンタクト領域８４の各々が露出される。次に上面Ｐ２上においてｎ領域８３およびｎコンタクト領域８４の各々に接するソース電極９４を形成する。第１のエピタキシャル層８１ａからなる下面Ｐ１上に、炭化珪素単結晶基板８０を介して、ドレイン電極９８が形成される。 Next, referring to FIG. 20, an interlayer insulating film 93 is formed on gate electrode 92 and gate oxide film 91 so as to cover the exposed surface of gate electrode 92. Thereafter, etching is performed so that openings are formed in the interlayer insulating film 93 and the gate oxide film 91. Through this opening, each of n region 83 and p contact region 84 is exposed on upper surface P2. Next, source electrode 94 in contact with each of n region 83 and n contact region 84 is formed on upper surface P2. Drain electrode 98 is formed on lower surface P <b> 1 made of first epitaxial layer 81 a through silicon carbide single crystal substrate 80.
　図２１を参照して、ソース配線層９５を形成する。以上により、炭化珪素基板１０と、第２のエピタキシャル層１２と、ゲート酸化膜９１と、ゲート電極９２と、層間絶縁膜９３と、ソース電極９４と、ソース配線層９５と、ドレイン電極９８とを有する炭化珪素半導体装置としてのＭＯＳＦＥＴ１００が完成する。炭化珪素基板１０は、炭化珪素単結晶基板８０と、第１のエピタキシャル層８１ａと、イオン注入領域１１とを含む。第２のエピタキシャル層１２は、ｐベース層８２と、ｎ領域８３と、ｐコンタクト領域８４とを含む。 Referring to FIG. 21, a source wiring layer 95 is formed. As described above, the silicon carbide substrate 10, the second epitaxial layer 12, the gate oxide film 91, the gate electrode 92, the interlayer insulating film 93, the source electrode 94, the source wiring layer 95, and the drain electrode 98 are formed. MOSFET 100 as a silicon carbide semiconductor device is completed. Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 80, a first epitaxial layer 81 a, and an ion implantation region 11. Second epitaxial layer 12 includes a p base layer 82, an n region 83, and a p contact region 84.
　次に、実施の形態１に係るＭＯＳＦＥＴ１００の製造方法の作用効果について説明する。 Next, functions and effects of the method for manufacturing MOSFET 100 according to the first embodiment will be described.
　実施の形態１に係るＭＯＳＦＥＴ１００の製造方法によれば、｛０００１｝面に対してオフ角を有する第１の主面１０ａ上に形成された第１のアライメントマーク１は、第２のエピタキシャル層１２を形成する工程（Ｓ４０）において保護膜３０により保護されている。そのため、第２のエピタキシャル層１２を形成する工程（Ｓ４０）において、第１のアライメントマーク１に対しステップフロー成長が進行して、第１のアライメントマーク１の形状が変形することを抑制することができる。その結果、第２のエピタキシャル層１２を形成する工程（Ｓ４０）後において実施される第２のエピタキシャル層１２に対して処理を行う工程（Ｓ５０）においても、第１のアライメントマーク１を利用して、精密な位置合わせを行うことができる。 According to the method of manufacturing MOSFET 100 according to the first embodiment, first alignment mark 1 formed on first main surface 10a having an off angle with respect to the {0001} plane is formed by second epitaxial layer 12 It is protected by the protective film 30 in the step of forming (S40). For this reason, in the step of forming the second epitaxial layer 12 (S40), it is possible to prevent the first alignment mark 1 from undergoing step flow growth and the shape of the first alignment mark 1 from being deformed. it can. As a result, the first alignment mark 1 is used also in the step (S50) of processing the second epitaxial layer 12 performed after the step (S40) of forming the second epitaxial layer 12. Precise alignment can be performed.
　また、実施の形態１に係るＭＯＳＦＥＴ１００の製造方法によれば、第２のエピタキシャル層１２に対して処理を行う工程（Ｓ５０）は、保護膜３０を除去した後実施される。このため、第２のエピタキシャル層１２に対して処理を行う工程（Ｓ５０）では、第２のエピタキシャル層１２を形成する工程（Ｓ４０）において保護膜３０で保護されていたことにより、その上でステップフロー成長がされず、保護膜３０を形成する工程（Ｓ３０）時の形状を維持している第１のアライメントマーク１を利用して、位置合わせを行うことができる。その結果、第２のエピタキシャル層１２に対して処理を行う工程（Ｓ５０）では、たとえば保護膜３０を形成する工程（Ｓ３０）の前に第１のアライメントマーク１を利用して第１の主面１０ａ上に形成されたパターンに対して、精密な位置合わせを行うことができる。 In addition, according to the method for manufacturing MOSFET 100 according to the first embodiment, the step (S50) of processing the second epitaxial layer 12 is performed after removing the protective film 30. For this reason, in the process (S50) which processes with respect to the 2nd epitaxial layer 12, since it protected by the protective film 30 in the process (S40) of forming the 2nd epitaxial layer 12, it is a step on that Position alignment can be performed using the first alignment mark 1 that is not flow-grown and maintains the shape during the step of forming the protective film 30 (S30). As a result, in the step (S50) of processing the second epitaxial layer 12, the first main surface is used by using the first alignment mark 1 before the step (S30) of forming the protective film 30, for example. Precise alignment can be performed on the pattern formed on 10a.
　また、実施の形態１に係る炭化珪素半導体装置の製造方法によれば、第１のアライメントマーク１を保護する工程（Ｓ３０）の前に、第１のアライメントマーク１を利用して炭化珪素基板１０に対して処理を行う工程（Ｓ２５）を備えている。つまり、第２のエピタキシャル層１２を形成する工程（Ｓ４０）の前後に、いずれも第１のアライメントマーク１を利用する、炭化珪素基板１０に対して処理を行う工程（Ｓ２５）と第２のエピタキシャル層１２に対して処理を行う工程（Ｓ５０）とを備えていている。ここで、第１のアライメントマーク１は、工程（Ｓ４０）において保護膜３０により保護されているためステップフロー成長が防止されている。そのため、工程（Ｓ２５）および工程（Ｓ５０）において（つまり、工程（Ｓ４０）の前後で）、第１のアライメントマーク１を利用して精密な位置合わせを行うことができる。 In addition, according to the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment, silicon carbide substrate 10 is utilized using first alignment mark 1 before the step of protecting first alignment mark 1 (S30). The process (S25) which performs a process with respect to is provided. That is, before and after the step of forming the second epitaxial layer 12 (S40), the step of processing the silicon carbide substrate 10 using the first alignment mark 1 (S25) and the second epitaxial layer. And a step (S50) of processing the layer 12. Here, since the first alignment mark 1 is protected by the protective film 30 in the step (S40), step flow growth is prevented. Therefore, in the step (S25) and the step (S50) (that is, before and after the step (S40)), precise alignment can be performed using the first alignment mark 1.
　また、実施の形態１に係る炭化珪素半導体装置の製造方法によれば、保護膜３０を構成する材料は、ＴａＣを含んでいる。そのため、たとえば１５００℃以上１７００℃以下程度の温度条件下において行われる第２のエピタキシャル層１２を形成する工程（Ｓ４０）においても、保護膜３０は第１のアライメントマーク１を保護して、第１のアライメントマーク１上でエピタキシャル層がステップフロー成長することを抑制することができる。また、このようにすれば、炭化珪素は保護膜３０上に成長しない。そのため、第２のエピタキシャル層１２に対して処理を行う工程（Ｓ５０）が保護膜３０により第１のアライメントマーク１を保護した状態で行われる場合にも、炭化珪素基板の第２の主面１２ａを平面視したとき（第２の主面１２ａに垂直な方向に沿って上部から第２の主面１２ａを見たとき）に、第１のアライメントマーク１を容易に検出することができる。なお、本実施の形態において、保護膜３０を構成する材料は、たとえばダイヤモンドやグラファイトなどの炭素材料であってもよい。 Further, according to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, the material forming protective film 30 includes TaC. Therefore, also in the step (S40) of forming the second epitaxial layer 12 performed under a temperature condition of, for example, 1500 ° C. or more and 1700 ° C. or less, the protective film 30 protects the first alignment mark 1 and the first It is possible to suppress the epitaxial layer from growing in step flow on the alignment mark 1. Further, if this is done, silicon carbide does not grow on the protective film 30. Therefore, even when the process (S50) for processing the second epitaxial layer 12 is performed in a state where the first alignment mark 1 is protected by the protective film 30, the second main surface 12a of the silicon carbide substrate. When viewed in plan (when the second main surface 12a is viewed from above along the direction perpendicular to the second main surface 12a), the first alignment mark 1 can be easily detected. In the present embodiment, the material constituting protective film 30 may be a carbon material such as diamond or graphite.
　また、実施の形態１に係る炭化珪素半導体装置の製造方法では、保護膜３０を形成する工程（Ｓ３０）では、第２のエピタキシャル層１２を形成する工程（Ｓ４０）において形成される第２のエピタキシャル層１２の厚みと同等の厚みを有する保護膜３０が形成されている。このようにすれば、第２のエピタキシャル層１２のオーバーハングを防止することができるとともに、保護膜３０を容易に加工することができる。 In the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, in the step of forming protective film 30 (S30), the second epitaxial layer formed in the step of forming second epitaxial layer 12 (S40). A protective film 30 having a thickness equivalent to the thickness of the layer 12 is formed. In this way, overhang of the second epitaxial layer 12 can be prevented and the protective film 30 can be easily processed.
　なお、実施の形態１に係る炭化珪素半導体装置の製造方法において、第１のアライメントマーク１を利用する、炭化珪素基板１０に対して処理を行う工程（Ｓ２５）の後に、第１のアライメントマーク１を保護する保護膜３０を形成したが（工程（Ｓ３０））、これに限られるものではない。たとえば、第１のアライメントマーク１を保護する保護膜３０を形成した後、保護膜３０により保護された第１のアライメントマーク１を利用して、炭化珪素基板１０に対して処理を行ってもよい。このようにしても、本実施の形態に係る炭化珪素半導体装置の製造方法によれば、第２のエピタキシャル層１２を形成する工程（Ｓ４０）において保護膜３０により第１のアライメントマーク１を保護しておけば、工程（Ｓ４０）後において実施される第２のエピタキシャル層１２に対して処理を行う工程（Ｓ５０）においても、第１のアライメントマーク１を利用して、精密な位置合わせを行うことができる。 In the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, after the step (S25) of processing silicon carbide substrate 10 using first alignment mark 1, first alignment mark 1 is used. The protective film 30 for protecting the film is formed (step (S30)), but is not limited thereto. For example, after forming protective film 30 protecting first alignment mark 1, silicon carbide substrate 10 may be processed using first alignment mark 1 protected by protective film 30. . Even in this case, according to the method for manufacturing the silicon carbide semiconductor device in accordance with the present embodiment, first alignment mark 1 is protected by protective film 30 in the step of forming second epitaxial layer 12 (S40). In this case, in the step (S50) of processing the second epitaxial layer 12 performed after the step (S40), the first alignment mark 1 is used to perform precise alignment. Can do.
　また、この場合においても、工程（Ｓ５０）では、保護膜３０により覆われていない第１のアライメントマーク１を利用して、第２のエピタキシャル層１２に対して処理を行ってもよい。つまり、工程（Ｓ２５）においては保護膜３０により保護された第１のアライメントマーク１を利用して処理を行うとともに、工程（Ｓ５０）においては保護膜３０が除去された第１のアライメントマーク１を利用して処理を行ってもよい。第１のアライメントマーク１が保護膜３０で保護されているか否かは、第１のアライメントマーク１を利用した位置合わせ時に許容できない位置ズレを生じるものではない。そのため、工程（Ｓ４０）において保護膜３０により第１のアライメントマーク１が保護されている限りにおいて、工程（Ｓ２５）および工程（Ｓ５０）では保護膜３０の有無に関わらず、第１のアライメントマーク１を利用して精密な位置合わせを行うことができる。 Also in this case, in the step (S50), the second epitaxial layer 12 may be processed using the first alignment mark 1 that is not covered by the protective film 30. That is, in the step (S25), processing is performed using the first alignment mark 1 protected by the protective film 30, and in the step (S50), the first alignment mark 1 from which the protective film 30 has been removed is used. Processing may be performed using this. Whether or not the first alignment mark 1 is protected by the protective film 30 does not cause an unacceptable positional shift at the time of alignment using the first alignment mark 1. Therefore, as long as the first alignment mark 1 is protected by the protective film 30 in the step (S40), the first alignment mark 1 in the steps (S25) and (S50) regardless of the presence or absence of the protective film 30. Can be used for precise positioning.
　（実施の形態２）
　次に、本発明の実施の形態２に係る炭化珪素半導体装置の製造方法について説明する。本実施の形態に係る炭化珪素半導体装置の製造方法は、基本的には実施の形態１に係る炭化珪素半導体装置の製造方法と同様の構成を備えるが、炭化珪素基板１０に対して処理を行う工程（Ｓ２５）と、第２のエピタキシャル層１２に対して処理を行う工程（Ｓ５０）とにおいて、異なるアライメントマークを位置合わせに利用する点で異なる。具体的には、図２２を参照して、工程（Ｓ２５）においては、該工程（Ｓ２５）に先だって形成された第２のアライメントマーク２を利用するとともに、第２のエピタキシャル層１２を形成する工程（Ｓ４０）に先だって、第２のアライメントマーク２を形成する工程（Ｓ１５）をさらに備え、保護膜３０を形成する工程（Ｓ３０）では、少なくとも第１のアライメントマーク１を保護する。 (Embodiment 2)
Next, a method for manufacturing the silicon carbide semiconductor device according to the second embodiment of the present invention will be described. The method for manufacturing the silicon carbide semiconductor device according to the present embodiment basically has the same configuration as the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, but performs processing on silicon carbide substrate 10. The step (S25) is different from the step (S50) in which the second epitaxial layer 12 is processed in that different alignment marks are used for alignment. Specifically, referring to FIG. 22, in the step (S25), the second alignment mark 2 formed prior to the step (S25) is used and the second epitaxial layer 12 is formed. Prior to (S40), the method further includes a step (S15) of forming the second alignment mark 2, and in the step (S30) of forming the protective film 30, at least the first alignment mark 1 is protected.
　まず、｛０００１｝面に対してオフ角を有する第１の主面１０ａを含む炭化珪素基板１０を準備する（工程（Ｓ１０））。 First, silicon carbide substrate 10 including first main surface 10a having an off angle with respect to the {0001} plane is prepared (step (S10)).
　次に、図２３を参照して、第２のアライメントマーク２を形成する（工程（Ｓ１５））。第２のアライメントマーク２は、たとえば実施の形態１に係る炭化珪素半導体装置の製造方法における第１のアライメントマーク１を形成する工程（Ｓ２０）と同様に形成されてもよい。具体的には、たとえばレジストマスク（図示しない）を第１の主面１０ａ上に形成し、レジストマスクをエッチングマスクとして第２のアライメントマーク２を形成する。第２のアライメントマーク２は、たとえば反応性イオンエッチング（ＲＩＥ）法などのドライエッチング法により、レジストマスクの開口部に露出している炭化珪素基板１０の第１のエピタキシャル層８１ａがエッチングされて、第１の主面１０ａに対する段差部が形成されることにより設けられる。つまり、第２のアライメントマーク２は、たとえば第１の主面１０ａを含む第２の凸部２ａと、第１の主面１０ａに開口部を有する第２の凹部２ｂとを含むように形成される。 Next, referring to FIG. 23, the second alignment mark 2 is formed (step (S15)). Second alignment mark 2 may be formed in the same manner as the step (S20) of forming first alignment mark 1 in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, for example. Specifically, for example, a resist mask (not shown) is formed on the first main surface 10a, and the second alignment mark 2 is formed using the resist mask as an etching mask. Second alignment mark 2 is formed by etching first epitaxial layer 81a of silicon carbide substrate 10 exposed in the opening of the resist mask by a dry etching method such as a reactive ion etching (RIE) method, for example. It is provided by forming a step portion with respect to the first main surface 10a. That is, the second alignment mark 2 is formed so as to include, for example, a second convex portion 2a including the first main surface 10a and a second concave portion 2b having an opening in the first main surface 10a. The
　第１の主面１０ａに対する第２の凹部２ｂの深さは、たとえば０．５μｍ以上２μｍ以下程度であり、好ましくは、０．７μｍ以上１．５μｍ以下程度であり、さらに好ましくは０．７μｍ以上１．０μｍ以下程度である。レジストマスクは、第２のアライメントマーク２を形成後、任意の方法で除去される。第２のアライメントマーク２は、炭化珪素基板１０の第１の主面１０ａ上に形成されるダイシングライン１０２上に形成されてもよい。第２のアライメントマーク２の第２の凸部２ａは、平面視したときに、たとえば長手方向と短手方向とを有する長方形状に形成されてもよい。第２の凸部２ａの長手方向は、ダイシングライン１０２が延びる方向と平行に形成されていてもよいし、交差するように形成されていてもよい。 The depth of the second recess 2b with respect to the first main surface 10a is, for example, about 0.5 μm to 2 μm, preferably about 0.7 μm to 1.5 μm, and more preferably 0.7 μm or more. It is about 1.0 μm or less. The resist mask is removed by an arbitrary method after the second alignment mark 2 is formed. Second alignment mark 2 may be formed on dicing line 102 formed on first main surface 10a of silicon carbide substrate 10. The second protrusion 2a of the second alignment mark 2 may be formed in a rectangular shape having, for example, a longitudinal direction and a short direction when viewed in plan. The longitudinal direction of the 2nd convex part 2a may be formed in parallel with the direction where the dicing line 102 is extended, and may be formed so that it may cross | intersect.
　次に、炭化珪素基板１０に対して処理を行う（工程（Ｓ２５））。具体的には、図２４を参照して、第２のアライメントマーク２を利用して、第１の主面１０ａ上にイオン注入マスク（図示しない）を形成し、該イオン注入マスクを介して第１の主面１０ａにイオン注入することにより、半導体装置の形成領域１０１内の第１のエピタキシャル層８１ａ上の所定の位置にイオン注入領域１１を形成する。 Next, the silicon carbide substrate 10 is processed (step (S25)). Specifically, referring to FIG. 24, an ion implantation mask (not shown) is formed on first main surface 10a using second alignment mark 2, and the second alignment mark 2 is used to form the first implantation mask through the ion implantation mask. By ion-implanting into one main surface 10a, the ion-implanted region 11 is formed at a predetermined position on the first epitaxial layer 81a in the formation region 101 of the semiconductor device.
　次に、第１のアライメントマーク１を形成する（工程（Ｓ１０））。具体的には、図２５を参照して、第１のアライメントマーク１は、たとえばダイシングライン１０２において第２のアライメントマーク２が形成された領域以外の任意の領域に、第２のアライメントマーク２を利用して形成される。第１のアライメントマーク１は、たとえばたとえば第１の主面１０ａを含む第１の凸部１ａと、第１の主面１０ａに開口部を有する第１の凹部１ｂとを含むように形成される。 Next, the first alignment mark 1 is formed (step (S10)). Specifically, referring to FIG. 25, first alignment mark 1 may be formed in any region other than the region where second alignment mark 2 is formed in dicing line 102, for example. Formed using. The first alignment mark 1 is formed so as to include, for example, a first convex portion 1a including the first main surface 10a and a first concave portion 1b having an opening in the first main surface 10a. .
　次に、第１のアライメントマーク１を保護膜３０により保護する（工程（Ｓ３０））。具体的には、まず、炭化珪素基板１０の第１の主面１０ａ上に保護膜３０を形成する。保護膜３０を構成する材料は、たとえば炭化タンタル（ＴａＣ）、またはグラファイトあるいはダイヤモンドなどの炭素材料である。保護膜３０の厚みｈ１（図２６参照）は、この後の工程Ｓ４０において形成される第２のエピタキシャル層１２の厚みｈ２（図２７参照）に応じて決めればよい。保護膜３０の厚みｈ１は、第２のエピタキシャル層１２の厚みｈ２の０．５倍以上１．５倍以下となるように形成されるのが好ましい。本実施の形態においては、保護膜３０の厚みｈ１は、第２のエピタキシャル層１２の厚みｈ２と同等となるように設けられている。 Next, the first alignment mark 1 is protected by the protective film 30 (step (S30)). Specifically, first, protective film 30 is formed on first main surface 10a of silicon carbide substrate 10. The material constituting the protective film 30 is, for example, tantalum carbide (TaC), or a carbon material such as graphite or diamond. The thickness h1 (see FIG. 26) of the protective film 30 may be determined according to the thickness h2 (see FIG. 27) of the second epitaxial layer 12 formed in the subsequent step S40. The thickness h1 of the protective film 30 is preferably formed to be not less than 0.5 times and not more than 1.5 times the thickness h2 of the second epitaxial layer 12. In the present embodiment, the thickness h 1 of the protective film 30 is provided to be equal to the thickness h 2 of the second epitaxial layer 12.
　本工程（Ｓ３０）では、次に、後の工程（Ｓ４０）において第２のエピタキシャル層１２を形成する領域上に形成された保護膜３０を除去する。具体的には、たとえばレジストマスク３５を保護膜３０上に形成し、レジストマスク３５をエッチングマスクとして保護膜３０をパターニングする。これにより、第１のアライメントマーク１上など、後の工程（Ｓ４０）においてエピタキシャル成長させる際にステップフロー成長を防止する必要のある領域は保護膜３０により保護されるとともに、第２のエピタキシャル層１２が形成される領域は第１の主面１０ａが保護膜３０から露出する（図２６参照）。このとき、第２のアライメントマーク２上の保護膜３０は除去してもよい。その後、レジストマスク３５は任意の方法により除去される。 In this step (S30), next, the protective film 30 formed on the region for forming the second epitaxial layer 12 in the subsequent step (S40) is removed. Specifically, for example, a resist mask 35 is formed on the protective film 30, and the protective film 30 is patterned using the resist mask 35 as an etching mask. As a result, a region where it is necessary to prevent step flow growth when epitaxially growing in the subsequent step (S40), such as on the first alignment mark 1, is protected by the protective film 30, and the second epitaxial layer 12 is In the region to be formed, the first main surface 10a is exposed from the protective film 30 (see FIG. 26). At this time, the protective film 30 on the second alignment mark 2 may be removed. Thereafter, the resist mask 35 is removed by an arbitrary method.
　次に、第２のエピタキシャル層１２を形成する（工程（Ｓ４０））。具体的には、図２７を参照して、第２のエピタキシャル層１２は、第１のエピタキシャル層８１ａにイオン注入領域１１が形成された後、炭化珪素基板１０の第１の主面１０ａ上に形成される。第２のエピタキシャル層１２は、たとえば導電型がｎ型であって、不純物濃度が７×１０１５ｃｍ－３程度である。このとき、第２のエピタキシャル層１２は、ステップフロー成長することにより、オフ角を有する第１の主面１０ａ上に形成される。このとき、ステップフロー成長は、第２のアライメントマーク２上においても進行する。これにより、第２のアライメントマーク２の凸部２ａおよび凹部２ｂ上に形成された第２のエピタキシャル層１２の上部表面の形状が第２のアライメントマーク２の形状とは異なる形状に変形する。異なる観点から言えば、第２のアライメントマーク２上に形成された第２のエピタキシャル層１２の第２の主面１２ａは、六方晶炭化珪素のｃ軸を法線とする傾斜面を有している。 Next, the second epitaxial layer 12 is formed (step (S40)). Specifically, referring to FIG. 27, second epitaxial layer 12 is formed on first main surface 10a of silicon carbide substrate 10 after ion implantation region 11 is formed in first epitaxial layer 81a. It is formed. Second epitaxial layer 12 has an n-type conductivity, for example, and an impurity concentration of about 7 × 10 15 cm −3 . At this time, the second epitaxial layer 12 is formed on the first main surface 10a having an off angle by performing step flow growth. At this time, step flow growth also proceeds on the second alignment mark 2. As a result, the shape of the upper surface of the second epitaxial layer 12 formed on the convex portion 2 a and the concave portion 2 b of the second alignment mark 2 is deformed to a shape different from the shape of the second alignment mark 2. From a different point of view, the second main surface 12a of the second epitaxial layer 12 formed on the second alignment mark 2 has an inclined surface whose normal is the c-axis of hexagonal silicon carbide. Yes.
　一方、保護膜３０上および保護膜３０により保護されている第１のアライメントマーク１上ではステップフロー成長は起こらず、第２のエピタキシャル層１２は成長しない。そのため、第１のアライメントマーク１のパターン形状および該第１のアライメントマーク１のパターン形状を覆うように形成された保護膜３０のパターン形状は、ステップフロー成長による変形が抑制されている。第２のエピタキシャル層１２は、保護膜３０が形成されていない領域において、第２の主面１２ａと、第２の主面１２ａの反対側に位置して第１の主面１０ａと接する裏面１２ｂとを含む。本実施の形態において、第２のエピタキシャル層１２の厚みｈ２は、上述のように、保護膜３０の厚みｈ１と同等である。本工程（Ｓ４０）によって、イオン注入領域１１は、炭化珪素基板１０（第１のエピタキシャル層８１ａ）と第２のエピタキシャル層１２とに埋め込まれる。本工程（Ｓ４０）において、第２のエピタキシャル層１２を形成した後、第１のアライメントマーク１を保護していた保護膜３０は、除去されてもよい。 On the other hand, step flow growth does not occur on the protective film 30 and the first alignment mark 1 protected by the protective film 30, and the second epitaxial layer 12 does not grow. Therefore, the pattern shape of the first alignment mark 1 and the pattern shape of the protective film 30 formed so as to cover the pattern shape of the first alignment mark 1 are suppressed from being deformed by step flow growth. The second epitaxial layer 12 includes a second main surface 12a and a back surface 12b that is located opposite to the second main surface 12a and is in contact with the first main surface 10a in a region where the protective film 30 is not formed. Including. In the present embodiment, the thickness h2 of the second epitaxial layer 12 is equivalent to the thickness h1 of the protective film 30 as described above. By this step (S40), ion implantation region 11 is embedded in silicon carbide substrate 10 (first epitaxial layer 81a) and second epitaxial layer 12. In this step (S40), after forming the second epitaxial layer 12, the protective film 30 that has protected the first alignment mark 1 may be removed.
　次に、第２のエピタキシャル層１２に対して処理を行う（工程（Ｓ５０））。具体的には、実施の形態１に係る炭化珪素半導体装置の製造方法と同様に、まずイオン注入法によって、半導体装置の形成領域１０１内の第２のエピタキシャル層１２上に、ｐベース層８２、ｎ領域８３を形成する。次に、第１のアライメントマーク１を利用して第２の主面１２ａ上にイオン注入マスクを形成する。次に、該イオン注入マスクを介して第２の主面１２ａにイオン注入することにより、ｐベース層８２上にｐコンタクト領域８４を形成する。 Next, the second epitaxial layer 12 is processed (step (S50)). Specifically, similarly to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment, first, the p base layer 82 is formed on the second epitaxial layer 12 in the semiconductor device formation region 101 by ion implantation. An n region 83 is formed. Next, using the first alignment mark 1, an ion implantation mask is formed on the second main surface 12a. Next, the p contact region 84 is formed on the p base layer 82 by implanting ions into the second major surface 12a through the ion implantation mask.
　その後、実施の形態１に係る炭化珪素半導体装置の製造方法と同様に実施されることにより、実施の形態２に係る炭化珪素半導体装置としてのＭＯＳＦＥＴ１００が完成する。 Thereafter, the MOSFET 100 as the silicon carbide semiconductor device according to the second embodiment is completed by being carried out in the same manner as the method for manufacturing the silicon carbide semiconductor device according to the first embodiment.
　次に、実施の形態２に係る炭化珪素半導体装置の製造方法の作用効果について説明する。 Next, functions and effects of the method for manufacturing the silicon carbide semiconductor device according to the second embodiment will be described.
　実施の形態２に係る炭化珪素半導体装置の製造方法によれば、炭化珪素基板１０に対して処理を行う工程（Ｓ２５）と第２のエピタキシャル層１２に対して処理を行う工程（Ｓ５０）とで異なるアライメントマークを位置合わせに利用する。具体的には、工程（Ｓ２５）においては第２のアライメントマーク２を利用し、工程（Ｓ５０）においては第１のアライメントマーク１を位置合わせに利用する。このとき、たとえば第２のアライメントマーク２を形成する工程（Ｓ１５）の後であって第２のエピタキシャル層１２に対して処理を行う工程（Ｓ５０）の前に複数の工程が実施されると、これらの複数の工程において第２のアライメントマーク２に対しても処理が行われることになる。その結果、たとえば保護膜３０を形成する工程（Ｓ３０）によって第２のアライメントマーク２を保護し、工程（Ｓ４０）において第２のアライメントマーク２に対するステップフロー成長を抑制した場合でも、上記の複数の工程を施されることにより第２のアライメントマーク２は半導体製造装置において検出不良が生じるほど変形する場合がある。そのため、実施の形態２に係る炭化珪素半導体装置の製造方法のように、第２のアライメントマーク２が変形する前に第２のアライメントマーク２を利用して第１のアライメントマーク１を新たに形成することで、その後の工程（Ｓ５０）において第２のアライメントマーク２が変形している場合にも、第２のアライメントマーク２よりも処理された工程数が少なく変形量の少ない第１のアライメントマーク１を利用することができる。このとき、工程（Ｓ３０）においては、少なくとも第１のアライメントマーク１を保護膜３０により保護すればよい。その結果、工程（Ｓ５０）において、複数工程が実施されたことによる変形や、ステップフロー成長による変形を受けていない第１のアライメントマーク１を利用して位置合わせをすることができる。これにより、工程（Ｓ１７）と工程（Ｓ５０）とにおいて精密な位置合わせを行うことができる。 According to the method for manufacturing the silicon carbide semiconductor device in accordance with the second embodiment, the process for processing silicon carbide substrate 10 (S25) and the process for processing second epitaxial layer 12 (S50). Use different alignment marks for alignment. Specifically, in the step (S25), the second alignment mark 2 is used, and in the step (S50), the first alignment mark 1 is used for alignment. At this time, for example, after a step (S15) for forming the second alignment mark 2 and before a step (S50) for processing the second epitaxial layer 12, a plurality of steps are performed. In the plurality of processes, the second alignment mark 2 is also processed. As a result, for example, even when the second alignment mark 2 is protected by the step (S30) of forming the protective film 30 and the step flow growth with respect to the second alignment mark 2 is suppressed in the step (S40), By performing the process, the second alignment mark 2 may be deformed so as to cause a detection failure in the semiconductor manufacturing apparatus. Therefore, as in the method for manufacturing the silicon carbide semiconductor device according to the second embodiment, first alignment mark 1 is newly formed using second alignment mark 2 before second alignment mark 2 is deformed. Thus, even when the second alignment mark 2 is deformed in the subsequent step (S50), the number of processes processed is smaller than that of the second alignment mark 2, and the first alignment mark is less deformed. 1 can be used. At this time, in the step (S30), at least the first alignment mark 1 may be protected by the protective film 30. As a result, in the step (S50), alignment can be performed by using the first alignment mark 1 that has not undergone deformation due to the execution of multiple steps or deformation due to step flow growth. Thereby, precise alignment can be performed in the step (S17) and the step (S50).
　実施の形態２に係る炭化珪素半導体装置の製造方法において、保護膜３０を形成する工程（Ｓ３０）では、第１のアライメントマーク１を保護膜３０により保護しているが、第２のアライメントマーク２についても保護膜３０によって保護してもよい。 In the method for manufacturing the silicon carbide semiconductor device according to the second embodiment, in the step of forming protective film 30 (S30), first alignment mark 1 is protected by protective film 30, but second alignment mark 2 May be protected by the protective film 30.
　実施の形態２に係る炭化珪素半導体装置の製造方法では、炭化珪素基板１０に対して処理を行う工程（Ｓ２５）は、第２のアライメントマーク２を利用して１回のみ実施されているが、これに限られるものではない。たとえば、第２のアライメントマーク２を利用して炭化珪素基板１０に対して処理を行う工程（Ｓ２５）の後、第１のアライメントマーク１を形成する工程（Ｓ１０）の後であって第２のエピタキシャル層１２を形成する工程（Ｓ４０）の前に、第１のアライメントマーク１を利用して炭化珪素基板１０に対して処理を行う工程をさらに備えていてもよい。この場合、第１のアライメントマーク１を利用して炭化珪素基板１０に対して処理を行う工程は、第１のアライメントマーク１を保護膜３０により保護する工程（Ｓ３０）の前または後のいずれかにおいて実施されてもよいし、工程（Ｓ３０）の前および後のいずれにおいても実施されてもよい。このようにしても、第２のエピタキシャル層１２を形成する工程（Ｓ４０）において、第１のアライメントマーク１は保護膜３０により保護されているため、上述した実施の形態２に係る炭化珪素半導体装置の製造方法と同様の作用効果を奏することができる。 In the method for manufacturing the silicon carbide semiconductor device according to the second embodiment, the process (S25) of processing silicon carbide substrate 10 is performed only once using second alignment mark 2. It is not limited to this. For example, after the step (S25) of processing the silicon carbide substrate 10 using the second alignment mark 2 and after the step (S10) of forming the first alignment mark 1, Before the step of forming epitaxial layer 12 (S40), a step of processing silicon carbide substrate 10 using first alignment mark 1 may be further provided. In this case, the process of processing silicon carbide substrate 10 using first alignment mark 1 is either before or after the process of protecting first alignment mark 1 with protective film 30 (S30). It may be carried out at any time before or after the step (S30). Even in this case, since the first alignment mark 1 is protected by the protective film 30 in the step of forming the second epitaxial layer 12 (S40), the silicon carbide semiconductor device according to the second embodiment described above. The same operational effects as those of the manufacturing method can be obtained.
　実施の形態１および実施の形態２に係る炭化珪素半導体装置の製造方法における第１のアライメントマーク１および第２のアライメントマーク２は、平面視したときに第１の凸部１ａ，１ｂが長方形状に形成されているが、これに限られるものではない。第１のアライメントマーク１および第２のアライメントマーク２は、半導体製造装置において検出可能な任意の形状であればよい。たとえば、第１のアライメントマーク１および／または第２のアライメントマーク２は、平面視したときに十字型や円形状であってもよい。このようにしても、実施の形態１または実施の形態２と同様の効果を奏することができる。また、第１のアライメントマーク１および第２のアライメントマーク２は、第１の凸部１ａ，２ａの領域と第１の凹部１ｂ，２ｂの領域とが任意の構成比で構成されていてもよい。たとえば、第１のアライメントマーク１および／または第２のアライメントマーク２は、ダイシングライン１０２の広い領域に形成された第１の凹部１ｂ，２ｂにおいて、部分的に第１の凸部１ａ，２ａが形成されている構成であってもよい（凸型）。または、第１のアライメントマーク１および／または第２のアライメントマーク２は、ダイシングライン１０２の広い領域に形成された第１の凸部１ａ，２ａにおいて、部分的に第１の凹部１ｂ，２ｂが形成されている構成であってもよい（凹型）。 The first alignment mark 1 and the second alignment mark 2 in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment and the second embodiment are rectangular in shape when the first protrusions 1a and 1b are viewed in plan view. However, the present invention is not limited to this. The first alignment mark 1 and the second alignment mark 2 may be any shape that can be detected by the semiconductor manufacturing apparatus. For example, the first alignment mark 1 and / or the second alignment mark 2 may be cross-shaped or circular when viewed in plan. Even if it does in this way, there can exist an effect similar to Embodiment 1 or Embodiment 2. Further, the first alignment mark 1 and the second alignment mark 2 may be configured such that the first convex portions 1a and 2a and the first concave portions 1b and 2b have an arbitrary composition ratio. . For example, the first alignment mark 1 and / or the second alignment mark 2 is formed by the first protrusions 1a and 2a partially in the first recesses 1b and 2b formed in a wide area of the dicing line 102. The structure currently formed may be sufficient (convex type). Alternatively, the first alignment mark 1 and / or the second alignment mark 2 may be such that the first concave portions 1b and 2b are partially formed in the first convex portions 1a and 2a formed in a wide area of the dicing line 102. The structure currently formed may be sufficient (concave type).
　また、実施の形態１および実施の形態２に係る炭化珪素半導体装置の製造方法では、第２のエピタキシャル層１２を形成する工程（Ｓ４０）の後、第１のアライメントマーク１を保護していた保護膜３０を除去するが、これに限られるものではない。保護膜３０は、工程（Ｓ４０）後においても、第１のアライメントマーク１上に残しておいてもよい。上述のように、第１のアライメントマーク１が保護膜３０で保護されているか否かは、第１のアライメントマーク１を利用した位置合わせ時に許容できない位置ズレを生じるものではない。そのため、第２のエピタキシャル層１２に対して処理を行う工程（Ｓ５０）では、保護膜３０を形成する工程（Ｓ３０）の前に第１のアライメントマーク１を利用して第１の主面１０ａ上に形成されたパターンに対して、保護膜３０によって保護された第１のアライメントマーク１を利用して精密な位置合わせを行うことができる。 In the method for manufacturing the silicon carbide semiconductor device according to the first embodiment and the second embodiment, the first alignment mark 1 is protected after the step of forming the second epitaxial layer 12 (S40). Although the film | membrane 30 is removed, it is not restricted to this. The protective film 30 may be left on the first alignment mark 1 even after the step (S40). As described above, whether or not the first alignment mark 1 is protected by the protective film 30 does not cause an unacceptable positional shift at the time of alignment using the first alignment mark 1. Therefore, in the step (S50) of processing the second epitaxial layer 12, the first alignment mark 1 is used on the first main surface 10a before the step (S30) of forming the protective film 30. Precise alignment can be performed on the pattern formed by using the first alignment mark 1 protected by the protective film 30.
　また、実施の形態１および実施の形態２に係る炭化珪素半導体装置の製造方法において、保護膜３０は、第２のエピタキシャル層１２を形成する工程（Ｓ４０）の時点で、第２のエピタキシャル層１２の厚みに対して、０．５倍以上１．５倍以下の厚みを有するように形成されていてもよい（図２８参照）。このようにすれば、第２のエピタキシャル層１２のオーバーハングを防止することができるとともに、保護膜３０を容易に加工することができる。 In the method for manufacturing the silicon carbide semiconductor device according to the first and second embodiments, protective film 30 is formed at second epitaxial layer 12 at the time of the step of forming second epitaxial layer 12 (S40). The thickness may be 0.5 times or more and 1.5 times or less (see FIG. 28). In this way, overhang of the second epitaxial layer 12 can be prevented and the protective film 30 can be easily processed.
　また、実施の形態１および実施の形態２に係る炭化珪素半導体装置の製造方法では、第１のアライメントマーク１を利用して、第２のエピタキシャル層１２に対して処理する工程（Ｓ５０）は、イオン注入工程であったが、これに限られるものではない。第１のアライメントマーク１は、たとえば炭化珪素ドライエッチング工程、ゲート電極形成工程または層間絶縁膜のコンタクトホール形成工程などの工程に用いられてもよい。 In the method for manufacturing the silicon carbide semiconductor device according to the first embodiment and the second embodiment, the step (S50) of processing the second epitaxial layer 12 using the first alignment mark 1 includes Although it was an ion implantation process, it is not restricted to this. First alignment mark 1 may be used, for example, in a process such as a silicon carbide dry etching process, a gate electrode forming process, or an interlayer insulating film contact hole forming process.
　また、実施の形態１および実施の形態２に係る炭化珪素半導体装置の製造方法では、ｐベース層８２、ｎ領域８３、およびｐコンタクト領域８４はイオン注入により形成されているが、たとえば不純物の添加をともなうにエピタキシャル成長により形成されてもよい。この場合には、第２のエピタキシャル層１２に対して処理を行う工程（Ｓ５０）は、たとえば炭化珪素ドライエッチング工程等となる。 In the method for manufacturing the silicon carbide semiconductor device according to the first and second embodiments, p base layer 82, n region 83, and p contact region 84 are formed by ion implantation. In this case, it may be formed by epitaxial growth. In this case, the process (S50) for processing the second epitaxial layer 12 is, for example, a silicon carbide dry etching process.
　上記実施の形態１および実施の形態２において、炭化珪素半導体装置１００は、ＭＯＳＦＥＴであったが、たとえばショットキーバリアダイオードまたはＩＧＢＴ（Insulated　Gate　Bipolar　Transistor）などであってもよい。上記実施例において、第１導電型はｎ型であり、かつ第２導電型はｐ型であるとして説明したが、第１導電型はｐ型であり、かつ第２導電型はｎ型であってもよい。 In Embodiment 1 and Embodiment 2 described above, silicon carbide semiconductor device 100 is a MOSFET, but may be, for example, a Schottky barrier diode or an IGBT (Insulated Gate Bipolar Transistor). In the above embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type is p-type and the second conductivity type is n-type. May be.
　以上のように本発明の実施の形態について説明を行ったが、上述の実施の形態を様々に変形することも可能である。また、本発明の範囲は上述の実施の形態に限定されるものではない。本発明の範囲は、請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更を含むことが意図される。 Although the embodiments of the present invention have been described above, the above-described embodiments can be variously modified. The scope of the present invention is not limited to the above-described embodiment. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
　本発明は、｛０００１｝面に対してオフ角を有する主面を含む炭化珪素基板を用いる炭化珪素半導体装置の製造方法に特に有利に適用される。 The present invention is particularly advantageously applied to a method for manufacturing a silicon carbide semiconductor device using a silicon carbide substrate including a main surface having an off angle with respect to the {0001} plane.
１　第１のアライメントマーク、１ａ　第１の凸部、１ｂ　第１の凹部、２　第２のアライメントマーク、２ａ　第２の凸部、２ｂ　第２の凹部、１０　炭化珪素基板、１０ａ　第１の主面、１１　イオン注入領域、１２　第２のエピタキシャル層、１２ａ　第２の主面、１２ｂ　第２の裏面、２０　レジストマスク、３０　保護膜、４０　マスク層、８０　単結晶基板、８１ａ　第１のエピタキシャル層、８２　ｐベース層、８３　ｎ領域、８４　コンタクト領域、９１　ゲート酸化膜、９２　ゲート電極、９３　層間絶縁膜、９４　ソース電極、９５　ソース配線層、９８　ドレイン電極、１００　炭化珪素半導体装置、１０１　半導体装置形成領域、１０２　ダイシングライン。 1 1st alignment mark, 1a 1st convex part, 1b 1st concave part, 2nd 2nd alignment mark, 2a 2nd convex part, 2b 2nd concave part, 10 silicon carbide substrate, 10a 1st main Surface, 11 ion implantation region, 12 second epitaxial layer, 12a second main surface, 12b second back surface, 20 resist mask, 30 protective film, 40 mask layer, 80 single crystal substrate, 81a first epitaxial layer , 82 p base layer, 83 n region, 84 contact region, 91 gate oxide film, 92 gate electrode, 93 interlayer insulating film, 94 source electrode, 95 source wiring layer, 98 drain electrode, 100 silicon carbide semiconductor device, 101 semiconductor device Forming area, 102 dicing line.

Claims (7)

  1. 　｛０００１｝面に対してオフ角を有する主面を含む炭化珪素基板を準備する工程と、
    　前記主面上に第１のアライメントマークを形成する工程と、
    　前記第１のアライメントマークを保護する保護膜を形成する工程と、
    　前記保護膜が形成された状態で、前記主面上にエピタキシャル層を形成する工程と、
    　前記第１のアライメントマークを利用して、前記エピタキシャル層に対して処理を行う工程とを備える、炭化珪素半導体装置の製造方法。     Preparing a silicon carbide substrate including a main surface having an off angle with respect to the {0001} plane;
    Forming a first alignment mark on the main surface;
    Forming a protective film for protecting the first alignment mark;
    Forming an epitaxial layer on the main surface in a state where the protective film is formed;
    And a step of processing the epitaxial layer using the first alignment mark.
  2. 　前記エピタキシャル層に対して処理を行う工程は、前記保護膜を除去した後実施される、請求項１に記載の炭化珪素半導体装置の製造方法。 The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of processing the epitaxial layer is performed after removing the protective film.
  3. 　前記エピタキシャル層に対して処理を行う工程は、前記第１のアライメントマークが前記保護膜により保護された状態で実施される、請求項１に記載の炭化珪素半導体装置の製造方法。 The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of processing the epitaxial layer is performed in a state where the first alignment mark is protected by the protective film.
  4. 　前記保護膜を形成する工程の前に、前記第１のアライメントマークを利用して前記炭化珪素基板に対して処理を行う工程をさらに備える、請求項１～請求項３のいずれか１項に記載の炭化珪素半導体装置の製造方法。 The process according to any one of claims 1 to 3, further comprising a step of processing the silicon carbide substrate using the first alignment mark before the step of forming the protective film. A method for manufacturing a silicon carbide semiconductor device.
  5. 　前記第１のアライメントマークを形成する工程の前に、前記主面上に第２のアライメントマークを形成する工程と、前記第２のアライメントマークを利用して前記炭化珪素基板に対して処理を行う工程とをさらに備え、
    　前記第１のアライメントマークを形成する工程では、前記第２のアライメントマークを利用して前記第１のアライメントマークを形成し、
    　前記保護膜を形成する工程では、少なくとも前記第１のアライメントマークを保護する前記保護膜を形成する、請求項１～請求項４のいずれか１項に記載の炭化珪素半導体装置の製造方法。     Prior to the step of forming the first alignment mark, a step of forming a second alignment mark on the main surface, and processing the silicon carbide substrate using the second alignment mark A process,
    In the step of forming the first alignment mark, the first alignment mark is formed using the second alignment mark,
    5. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the step of forming the protective film, the protective film that protects at least the first alignment mark is formed.
  6. 　前記保護膜を構成する材料は、炭化タンタルまたは炭素材料を含む、請求項１～請求項５のいずれか１項に記載の炭化珪素半導体装置の製造方法。 6. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the material forming the protective film includes tantalum carbide or a carbon material.
  7. 　前記保護膜を形成する工程では、前記エピタキシャル層を形成する工程において形成される前記エピタキシャル層の厚みに対して、０．５倍以上１．５倍以下の厚みを有する前記保護膜が形成される、請求項１～請求項６のいずれか１項に記載の炭化珪素半導体装置の製造方法。 In the step of forming the protective film, the protective film having a thickness of 0.5 to 1.5 times the thickness of the epitaxial layer formed in the step of forming the epitaxial layer is formed. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 6.
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