JP7255343B2 - Silicon carbide semiconductor module and method for manufacturing silicon carbide semiconductor module - Google Patents

Description

The present disclosure relates to a silicon carbide semiconductor module and a method for manufacturing the silicon carbide semiconductor module.

International Publication No. 2017/203623 (Patent Document 1) describes a power module in which a plurality of silicon carbide switching elements are mounted on a substrate.

WO2017/203623

An object of the present disclosure is to improve the predictability of changes in characteristics of a silicon carbide semiconductor module as a whole.

A silicon carbide semiconductor module according to the present disclosure includes a circuit board and a plurality of silicon carbide semiconductor chips. The circuit board has a first major surface. A plurality of silicon carbide semiconductor chips are mounted on a circuit board and have a second main surface facing the first main surface. In each of the plurality of silicon carbide semiconductor chips, the distance between the center of the second main surface and the first main surface is 0.5 mm in the direction parallel to the first main surface toward the center from the outer peripheral edge of the second main surface. It is smaller than the distance between the separated inner periphery and the first major surface.

A method for manufacturing a silicon carbide semiconductor module according to the present disclosure includes a first step of preparing a circuit board having a first main surface and a plurality of silicon carbide semiconductor chips having a second main surface; and a second step of mounting each of the plurality of silicon carbide semiconductor chips on the circuit board so as to face one main surface. The second main surface has a first position 0.5 mm away from the outer peripheral edge of the second main surface toward the center of the second main surface in a direction parallel to the first main surface, and a first position relative to the center. and a second position located on the opposite side. In the first step, when the height of the second main surface is measured from the first position to the second position of the second main surface with the second main surface facing upward, the center of the second main surface is prepared a plurality of silicon carbide semiconductor chips positioned higher than a straight line passing through the first position and the second position.

According to the present disclosure, it is possible to improve the predictability of the characteristic change of the silicon carbide semiconductor module as a whole.

FIG. 1 is a schematic plan view showing the configuration of the silicon carbide semiconductor module according to the first embodiment. FIG. 2 is a schematic cross-sectional view taken along line II-II of FIGS. 1 and 7. FIG. FIG. 3 is a schematic cross-sectional view taken along line III-III of FIGS. 1 and 7. FIG. FIG. 4 is a schematic plan view showing the configuration of a silicon carbide semiconductor module according to the second embodiment. FIG. 5 is a schematic cross-sectional view taken along line VV of FIGS. 4 and 7. FIG. FIG. 6 is a schematic cross-sectional view taken along line VI-VI of FIGS. 4 and 7. FIG. FIG. 7 is a schematic plan view showing the configuration of a silicon carbide semiconductor module according to the third embodiment. FIG. 8 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device. FIG. 9 is a flow chart schematically showing a method of manufacturing a silicon carbide semiconductor module. FIG. 10 is a schematic plan view showing the first step of the method for manufacturing a silicon carbide semiconductor module. 11 is a schematic cross-sectional view taken along line XI-XI of FIG. 10. FIG. FIG. 12 is a schematic cross-sectional view showing a second step of the method for manufacturing a silicon carbide semiconductor module. FIG. 13 is a schematic cross-sectional view showing the third step of the method for manufacturing a silicon carbide semiconductor module. FIG. 14 is a schematic cross-sectional view showing a fourth step of the method for manufacturing a silicon carbide semiconductor module. FIG. 15 is a schematic cross-sectional view showing a fifth step of the method for manufacturing a silicon carbide semiconductor module. FIG. 16 is a schematic perspective view showing the configuration of a silicon carbide semiconductor chip. FIG. 17 is a schematic cross-sectional view showing a state in which the silicon carbide semiconductor chip is arranged on the stage. FIG. 18 is a height profile when the height of the second main surface is measured along the first straight line. FIG. 19 is a height profile when the height of the second main surface is measured along the second straight line. FIG. 20 is a modification of the height profile of the second main surface of the silicon carbide semiconductor chip. FIG. 21 shows the height of the second main surface measured from the first position on the upper side to the second position on the lower side along a straight line 0.5 mm away from the left side of the silicon carbide semiconductor chip toward the center. Profile. FIG. 22 is a height profile of the second main surface measured from a first position on the upper side to a second position on the lower side along a straight line 3 mm away from the right side of the silicon carbide semiconductor chip toward the center. . FIG. 23 shows the height profile of the second main surface measured from the first position on the upper side to the second position on the lower side along a straight line 0.5 mm away from the right side of the silicon carbide semiconductor chip toward the center. is. FIG. 24 is a height profile of the second main surface measured from the first position on the left side to the second position on the right side along a straight line 0.5 mm away from the upper side of the silicon carbide semiconductor chip toward the center. is. FIG. 25 is a height profile of the second main surface measured from the first position on the left side to the second position on the right side along a straight line 3 mm away from the upper side of the silicon carbide semiconductor chip toward the center. . FIG. 26 shows the height profile of the second main surface measured from the first position on the left side to the second position on the right side along a straight line 0.5 mm away from the bottom side of the silicon carbide semiconductor chip toward the center. is.

[Description of Embodiments of the Present Disclosure]
First, the embodiments of the present disclosure will be enumerated and described. In the crystallographic description of this specification, individual orientations are indicated by [ ], collective orientations by <>, individual planes by ( ), and collective planes by { }. Negative crystallographic exponents are usually expressed by placing a "-" (bar) above the number, but here the crystallographic index is expressed by prefixing the number with a negative sign. Represents a negative exponent above.

(1) Silicon carbide semiconductor module 400 according to the present disclosure includes circuit board 20 and a plurality of silicon carbide semiconductor chips 200 . The circuit board 20 has a first major surface 21 . A plurality of silicon carbide semiconductor chips 200 are mounted on circuit board 20 and have a second main surface 202 facing first main surface 21 . In each of the plurality of silicon carbide semiconductor chips 200 , the distance between the center 82 of the second main surface 202 and the first main surface 21 is the distance from the outer peripheral edge 204 of the second main surface 202 toward the center 82 of the first main surface 21 . is smaller than the distance between the inner peripheral portion 80 and the first main surface 21, which is 0.5 mm apart in a direction parallel to .

(2) According to silicon carbide semiconductor module 400 according to (1) above, each of silicon carbide semiconductor chips 200 is a rectangle having first side 211 and second side 212 shorter than first side 211. may be in the form of When the distance between the inner peripheral portion 80 and the first main surface 21 is defined as a first distance D1, and the distance between the center 82 and the first main surface 21 is defined as a second distance D2, the distance in the direction parallel to the first side 211 is The absolute value of the difference between the first distance D1 and the second distance D2 may be greater than the absolute value of the difference between the first distance D1 and the second distance D2 in the direction parallel to the second side 212 .

(3) According to silicon carbide semiconductor module 400 according to (1) above, each of silicon carbide semiconductor chips 200 may have a square shape.

(4) A method for manufacturing silicon carbide semiconductor module 400 according to the present disclosure is a first step of preparing circuit board 20 having first main surface 21 and a plurality of silicon carbide semiconductor chips 200 having second main surface 202 . and a second step of mounting each of the plurality of silicon carbide semiconductor chips 200 on the circuit board 20 such that the second main surface 202 faces the first main surface 21 . The second main surface 202 has a first position 81 0.5 mm away from the outer peripheral edge 204 of the second main surface 202 toward the center 82 of the second main surface 202 in a direction parallel to the first main surface 21 , and a center It has a first position 81 and a second position 84 opposite to 82 . In the first step, when the height of the second main surface 202 is measured from the first position 81 to the second position 84 with the second main surface 202 facing upward, the center 82 is located at the first position 81 and a plurality of silicon carbide semiconductor chips 200 positioned higher than a straight line passing through second position 84 are prepared.

(5) According to the method for manufacturing silicon carbide semiconductor module 400 according to (4) above, each of silicon carbide semiconductor chips 200 has first side 211 and second side 212 shorter than first side 211. may be rectangular. In the first step, the distance between the center 82 and the straight line when the height of the second main surface 202 is measured along the direction parallel to the first side 211 with the second main surface 202 facing upward Alternatively, a plurality of silicon carbide semiconductor chips 200 may be prepared that are larger than the distance between center 82 and a straight line when the height of second main surface 202 is measured along the direction parallel to second side 212 .

(6) According to the method for manufacturing silicon carbide semiconductor module 400 according to (4) above, each of silicon carbide semiconductor chips 200 may have a square shape.
[Details of the embodiment of the present disclosure]
Details of the embodiments of the present disclosure will be described below. In the following description, the same or corresponding elements are given the same reference numerals and the same descriptions thereof are not repeated.

(First embodiment)
First, the configuration of silicon carbide semiconductor module 400 according to the first embodiment will be described. FIG. 1 is a schematic plan view showing the configuration of a silicon carbide semiconductor module 400 according to the first embodiment.

As shown in FIG. 1 , silicon carbide semiconductor module 400 according to the first embodiment has circuit board 20 and a plurality of silicon carbide semiconductor chips 200 . Each of silicon carbide semiconductor chips 200 is provided on circuit board 20 . In a plan view, the circuit board 20 has, for example, a rectangular shape. A plurality of silicon carbide semiconductor chips 200 are arranged along each of the longitudinal direction and the lateral direction of circuit board 20 . The number of silicon carbide semiconductor chips 200 is not particularly limited, but is eight, for example. As shown in FIG. 1 , four silicon carbide semiconductor chips 200 are arranged along the longitudinal direction of circuit board 20 and two silicon carbide semiconductor chips 200 are arranged along the lateral direction of circuit board 20 . may have been

FIG. 2 is a schematic cross-sectional view taken along line II-II of FIG. As shown in FIG. 1, line II-II is a line that bisects the pair of second sides 212 . As shown in FIG. 2, the circuit board 20 has a substrate 24 and circuit patterns 23 . The circuit pattern 23 is provided on the base material 24 . Base material 24 is made of, for example, an insulating material. Circuit pattern 23 is made of, for example, a conductive material. The circuit board 20 has a first principal surface 21 and a third principal surface 22 . The third principal surface 22 is the surface opposite to the first principal surface 21 . The first main surface 21 is configured with a circuit pattern 23 . The third main surface 22 is made up of a base material 24 .

As shown in FIG. 2 , each of silicon carbide semiconductor chips 200 has a second main surface 202 , a fourth main surface 201 and an outer peripheral surface 203 . The fourth major surface 201 is the surface. The second major surface 202 is the back surface. The fourth major surface 201 is opposite the second major surface 202 . The outer peripheral surface 203 continues to each of the second main surface 202 and the fourth main surface 201 . As shown in FIG. 1 , each of silicon carbide semiconductor chips 200 has, for example, a rectangular shape when viewed in a direction perpendicular to first main surface 21 . Silicon carbide semiconductor chip 200 having a rectangular shape means that silicon carbide semiconductor chip 200 is arranged on a horizontal plane such that fourth main surface 201 of silicon carbide semiconductor chip 200 is in contact with the horizontal plane. The outer shape of silicon carbide semiconductor chip 200 is rectangular when viewed in a direction perpendicular to the horizontal plane.

As shown in FIG. 1 , each of silicon carbide semiconductor chips 200 has a first side 211 and a second side 212 . The second side 212 is shorter than the first side 211 . The first side 211 is the long side. The second side 212 is the short side. As shown in FIG. 1, the line that bisects the pair of second sides 212 is defined as a first straight line C1, and the line that bisects the pair of first sides 211 is defined as a second straight line C2. The third straight line C3 is a straight line perpendicular to each of the first straight line C1 and the second straight line C2. The third straight line C3 is perpendicular to the first major surface 21, for example.

As shown in FIG. 2 , each of a plurality of silicon carbide semiconductor chips 200 is mounted on circuit board 20 . When each of silicon carbide semiconductor chips 200 is mounted on circuit board 20 , second main surface 202 faces first main surface 21 . Second major surface 202 includes center 82 , outer perimeter edge 204 , and inner perimeter 80 . The center 82 is the point where the second main surface 202 and the third straight line C3 intersect. The inner perimeter 80 is annular and surrounded by an outer perimeter edge 204 . The inner peripheral portion 80 is located 0.5 mm away from the outer peripheral edge 204 of the second main surface 202 toward the center 82 in a direction parallel to the first main surface 21 . From another point of view, the inner peripheral portion 80 is a position spaced apart by a first width W from the outer peripheral surface 203 toward the center 82 in the direction perpendicular to the third straight line C3. The first width W is 0.5 mm.

As shown in FIG. 2, the distance between the center 82 and the first main surface 21 is defined as a second distance D2, and the distance between the inner peripheral portion 80 and the first main surface 21 is defined as a first distance D1. In each of silicon carbide semiconductor chips 200, second distance D2 is smaller than first distance D1. Note that the second distance D2 (that is, the distance between the center 82 and the first main surface 21) is smaller than the first distance D1 (that is, the distance between the inner peripheral portion 80 and the first main surface 21) means that the inner peripheral It means that the second distance D2 is smaller than the first distance D1 all around the portion 80 . Each of the first distance D1 and the second distance D2 is a distance in a direction perpendicular to the first major surface 21 . The first distance D1 may be, for example, 0.01 mm or longer, or may be 0.02 mm or longer. The first distance D1 may be, for example, 0.05 mm or less, or may be 0.03 mm or less. The second distance D2 may be, for example, 0.01 mm or longer, or may be 0.02 mm or longer. The second distance D2 may be, for example, 0.05 mm or less, or may be 0.03 mm or less. The absolute value of the difference between the first distance D1 and the second distance D2 may be, for example, 0.0001 mm or more and 0.002 mm or less.

FIG. 3 is a schematic cross-sectional view taken along line III-III of FIG. As shown in FIG. 1, line III-III is a line that bisects the pair of first sides 211 . As shown in FIG. 3, the distance between the inner peripheral portion 80 and the first main surface 21 is defined as a third distance D3. A third distance D3 is a distance in a direction perpendicular to the first major surface 21 . The third distance D3 may be, for example, 0.01 mm or longer, or may be 0.02 mm or longer. The third distance D3 may be, for example, 0.05 mm or less, or may be 0.03 mm or less. In each of silicon carbide semiconductor chips 200, second distance D2 is smaller than third distance D3. The third distance D3 may be smaller than the first distance D1 (see FIG. 2). From another point of view, the absolute value of the difference between the first distance D1 and the second distance D2 in the direction parallel to the first side 211 is the third distance D3 and the second distance D3 in the direction parallel to the second side 212. It may be larger than the absolute value of the difference from D2. The absolute value of the difference between the third distance D3 and the second distance D2 may be, for example, 0.0001 mm or more and 0.0015 mm or less.

As shown in FIGS. 2 and 3 , silicon carbide semiconductor module 400 has joining member 50 . Silicon carbide semiconductor chip 200 is mounted on circuit board 20 using bonding member 50 . Joining member 50 is positioned between silicon carbide semiconductor chip 200 and circuit board 20 . Joining member 50 is, for example, solder. The joining member 50 may be made of any conductive material, and is not limited to solder. The joining member 50 may be silver paste or the like, for example. As shown in FIGS. 2 and 3 , the joining member 50 is electrically connected to the circuit pattern 23 on the first main surface 21 . Joining member 50 is electrically connected to silicon carbide semiconductor chip 200 at second main surface 202 . Silicon carbide semiconductor chip 200 is electrically connected to circuit pattern 23 via joining member 50 .

(Second embodiment)
Next, the configuration of silicon carbide semiconductor module 400 according to the second embodiment will be described. Silicon carbide semiconductor module 400 according to the second embodiment differs from silicon carbide semiconductor module 400 according to the first embodiment mainly in the configuration in which silicon carbide semiconductor chip 200 is square. It is the same as the silicon carbide semiconductor module 400 according to the first embodiment. Hereinafter, the configuration different from silicon carbide semiconductor module 400 according to the first embodiment will be mainly described.

FIG. 4 is a schematic plan view showing the configuration of a silicon carbide semiconductor module 400 according to the second embodiment. As shown in FIG. 4, each of a plurality of silicon carbide semiconductor chips 200 included in silicon carbide semiconductor module 400 according to the second embodiment has a square shape. Silicon carbide semiconductor chip 200 having a square shape means that silicon carbide semiconductor chip 200 is arranged on a horizontal plane such that fourth main surface 201 of silicon carbide semiconductor chip 200 is in contact with the horizontal plane. The outer shape of silicon carbide semiconductor chip 200 is square when viewed in a direction perpendicular to the horizontal plane.

The number of silicon carbide semiconductor chips 200 is not particularly limited, but is twelve, for example. In a plan view, the circuit board 20 has, for example, a rectangular shape. A plurality of silicon carbide semiconductor chips 200 are arranged along each of the longitudinal direction and the lateral direction of circuit board 20 . As shown in FIG. 4 , four silicon carbide semiconductor chips 200 are arranged along the longitudinal direction of circuit board 20 and three silicon carbide semiconductor chips 200 are arranged along the lateral direction of circuit board 20 . may have been

As shown in FIG. 4 , each of silicon carbide semiconductor chips 200 has a first side 211 and a second side 212 . The length of the second side 212 is the same as the length of the first side 211 . As shown in FIG. 4, a line that bisects the pair of second sides 212 is defined as a first straight line C1, and a line that bisects the pair of first sides 211 is defined as a second straight line C2. The third straight line C3 is a straight line perpendicular to each of the first straight line C1 and the second straight line C2. The third straight line C3 is perpendicular to the first main surface 21, for example.

FIG. 5 is a schematic cross-sectional view taken along line VV of FIG. As shown in FIG. 4, the VV line is a line that bisects the pair of second sides 212 . As shown in FIG. 5 , each of a plurality of silicon carbide semiconductor chips 200 is mounted on circuit board 20 . When each of silicon carbide semiconductor chips 200 is mounted on circuit board 20 , second main surface 202 faces first main surface 21 . Second major surface 202 includes center 82 and inner perimeter 80 . The center 82 is the point where the second main surface 202 and the third straight line C3 intersect. The inner peripheral portion 80 is located 0.5 mm away from the outer peripheral edge 204 of the second main surface 202 toward the center 82 in a direction parallel to the first main surface 21 . From another point of view, the inner peripheral portion 80 is a position spaced apart by a first width W from the outer peripheral surface 203 toward the center 82 in the direction perpendicular to the third straight line C3. The first width W is 0.5 mm.

As shown in FIG. 5, the distance between the center 82 and the first main surface 21 is defined as a second distance D2, and the distance between the inner peripheral portion 80 and the first main surface 21 is defined as a first distance D1. In each of silicon carbide semiconductor chips 200, second distance D2 is smaller than first distance D1. Specifically, in the entire periphery of silicon carbide semiconductor chip 200, second distance D2 is smaller than first distance D1.

FIG. 6 is a schematic cross-sectional view taken along line VI-VI of FIG. As shown in FIG. 4, the VI-VI line is a line that bisects the pair of first sides 211 . As shown in FIG. 6, the distance between the inner peripheral portion 80 and the first main surface 21 is defined as a third distance D3. In each of silicon carbide semiconductor chips 200, third distance D3 is greater than second distance D2. The third distance D3 may be the same as or different from the first distance D1. From another point of view, the absolute value of the difference between the first distance D1 and the second distance D2 in the direction parallel to the first side 211 is the third distance D3 and the second distance D3 in the direction parallel to the second side 212. It may be the same as or different from the absolute value of the difference from D2.

(Third Embodiment)
Next, the configuration of silicon carbide semiconductor module 400 according to the third embodiment will be described. A silicon carbide semiconductor module 400 according to the third embodiment includes a silicon carbide semiconductor chip 200 included in the silicon carbide semiconductor module 400 according to the first embodiment and a silicon carbide semiconductor chip included in the silicon carbide semiconductor module 400 according to the second embodiment. 200 are mounted on a single circuit board 20 . Hereinafter, the configuration different from each of silicon carbide semiconductor module 400 according to the first embodiment and silicon carbide semiconductor module 400 according to the second embodiment will be mainly described.

FIG. 7 is a schematic plan view showing the configuration of a silicon carbide semiconductor module 400 according to the third embodiment. As shown in FIG. 7 , a silicon carbide semiconductor module 400 according to the third embodiment may have multiple first silicon carbide semiconductor chips 210 and multiple second silicon carbide semiconductor chips 220 . A plurality of first silicon carbide semiconductor chips 210 and a plurality of second silicon carbide semiconductor chips 220 are mounted on single circuit board 20 .

Circuit board 20 has, for example, a rectangular shape in a plan view (a field of view seen from a direction perpendicular to first main surface 21). The circuit board 20 has a first substrate area 25 and a second substrate area 26 . The second substrate region 26 is continuous with the first substrate region 25 . The first substrate area 25 is on one longitudinal side of the circuit board 20 . The second substrate area 26 is on the other longitudinal side of the circuit board 20 . A plurality of first silicon carbide semiconductor chips 210 are mounted on first substrate region 25 . A plurality of second silicon carbide semiconductor chips 220 are mounted on second substrate region 26 .

First silicon carbide semiconductor chip 210 includes a silicon carbide semiconductor element such as a transistor. Specifically, the transistor is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). Second silicon carbide semiconductor chip 220 includes a silicon carbide semiconductor element such as a diode. Specifically, the diode is, for example, a Schottky barrier diode or a PiN diode. The silicon carbide semiconductor element included in first silicon carbide semiconductor chip 210 has a function different from that of the silicon carbide semiconductor element included in second silicon carbide semiconductor chip 220 .

The number of first silicon carbide semiconductor chips 210 is not particularly limited, but is eight, for example. As shown in FIG. 7 , four first silicon carbide semiconductor chips 210 are arranged along the longitudinal direction of circuit board 20 , and two first silicon carbide semiconductor chips 210 are arranged along the lateral direction of circuit board 20 . A chip 210 may be placed. The number of second silicon carbide semiconductor chips 220 is not particularly limited, but is, for example, twelve. As shown in FIG. 7 , four second silicon carbide semiconductor chips 220 are arranged along the longitudinal direction of circuit board 20 and three second silicon carbide semiconductor chips 220 are arranged along the lateral direction of circuit board 20 . A chip 220 may be placed.

Next, the configuration of the silicon carbide semiconductor element included in silicon carbide semiconductor chip 200 will be described. FIG. 8 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor device.

As shown in FIG. 8, silicon carbide semiconductor device 150 is, for example, a MOSFET. MOSFET 150 mainly includes silicon carbide epitaxial substrate 100 , gate electrode 64 , gate insulating film 71 , isolation insulating film 72 (interlayer insulating film), source electrode 60 and drain electrode 63 . Silicon carbide epitaxial substrate 100 has a fifth main surface 1 and a sixth main surface 2 opposite to fifth main surface 1 . Silicon carbide epitaxial substrate 100 includes a silicon carbide single crystal substrate 4 and a silicon carbide epitaxial layer 3 provided on silicon carbide single crystal substrate 4 . Silicon carbide single-crystal substrate 4 forms sixth main surface 2 . Silicon carbide epitaxial layer 3 forms fifth main surface 1 .

Fifth main surface 1 is, for example, the {0001} plane or a plane that is off by 8° or less with respect to the {0001} plane. Specifically, the fifth main surface 1 is, for example, the (000-1) plane or a plane that is off by 8° or less with respect to the (000-1) plane. The fifth main surface 1 may be, for example, the (0001) plane or a plane that is off by 8° or less with respect to the (0001) plane. Silicon carbide single-crystal substrate 4 is made of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single-crystal substrate 4 has a thickness of, for example, 350 μm or more and 500 μm or less.

Silicon carbide epitaxial layer 3 mainly has drift region 10 , body region 30 , source region 40 and contact region 8 . Drift region 10 is provided on silicon carbide single crystal substrate 4 . Drift region 10 contains an n-type impurity such as nitrogen (N) and has an n-type conductivity (first conductivity type). The n-type impurity concentration of drift region 10 may be lower than the n-type impurity concentration of silicon carbide single crystal substrate 4 .

Body region 30 is provided on drift region 10 . Body region 30 contains a p-type impurity such as aluminum (Al), and has p-type conductivity (second conductivity type) different from n-type. The concentration of p-type impurities in body region 30 may be higher than the concentration of n-type impurities in drift region 10 . Body region 30 is separated from each of fifth main surface 1 and sixth main surface 2 .

Source region 40 is provided on body region 30 so as to be separated from drift region 10 by body region 30 . Source region 40 contains an n-type impurity such as nitrogen or phosphorus (P), and has n-type conductivity. Source region 40 forms part of fifth main surface 1 . The concentration of n-type impurities in source region 40 may be higher than the concentration of p-type impurities in body region 30 . The n-type impurity concentration of source region 40 is, for example, about 1×10 ¹⁹ cm ⁻³ .

Contact region 8 contains a p-type impurity such as aluminum and has p-type conductivity. The p-type impurity concentration of contact region 8 may be higher than the p-type impurity concentration of body region 30 . Contact region 8 may pass through source region 40 and contact body region 30 . Contact region 8 forms part of fifth main surface 1 . The p-type impurity concentration of contact region 8 is, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less.

As shown in FIG. 8, gate trenches 7 are provided in the fifth main surface 1 . Gate trench 7 has side surfaces 5 and a bottom surface 6 . The bottom surface 6 continues to the side surface 5 . The side surface 5 continues to the fifth main surface 1 . Side surface 5 is composed of drift region 10 , body region 30 and source region 40 . The bottom surface 6 is composed of a drift region.

Gate insulating film 71 contains, for example, silicon dioxide (SiO ₂ ). Gate insulating film 71 is in contact with each of side surface 5 and bottom surface 6 . Gate insulating film 71 is in contact with each of drift region 10 , body region 30 and source region 40 at side surface 5 . Gate insulating film 71 is in contact with drift region 10 at bottom surface 6 . A channel can be formed in the body region 30 in contact with the gate insulating film 71 . The thickness of gate insulating film 71 is, for example, 40 nm or more and 150 nm or less.

The gate electrode 64 is provided on the gate insulating film 71 . Gate electrode 64 is arranged in contact with gate insulating film 71 . The gate electrode 64 is provided so as to fill the trench formed by the gate insulating film 71 . Gate electrode 64 is made of a conductor such as polysilicon doped with an impurity.

The isolation insulating film 72 is provided on the gate electrode 64 . The isolation insulating film 72 electrically isolates the source electrode 60 and the gate electrode 64 . The isolation insulating film 72 is arranged between the source electrode 60 and the gate electrode 64 . The isolation insulating film 72 is provided so as to cover the gate electrode 64 . Isolation insulating film 72 is in contact with each of gate electrode 64 and gate insulating film 71 . Isolation insulating film 72 contains, for example, silicon nitride (SiN) or silicon oxynitride (SiON).

Source electrode 60 is provided on fifth main surface 1 . Source electrode 60 is in contact with source region 40 on fifth main surface 1 . Source electrode 60 may be in contact with contact region 8 on fifth main surface 1 . The source electrode 60 is provided on the isolation insulating film 72 .

The source electrode 60 has an electrode film 61 and a metal film 62 . The metal film 62 is provided on the electrode film 61 . Electrode film 61 contains nickel silicide (NiSi) or titanium aluminum silicide (TiAlSi), for example. Electrode film 61 is in contact with source region 40 on fifth main surface 1 . Electrode film 61 may be in contact with contact region 8 on fifth main surface 1 . The metal film 62 is the source wiring. Metal film 62 contains, for example, aluminum (Al).

The drain electrode 63 is provided on the sixth main surface 2 . Drain electrode 63 is in contact with silicon carbide single-crystal substrate 4 on sixth main surface 2 . Drain electrode 63 is electrically connected to drift region 10 on the sixth main surface 2 side. Drain electrode 63 is made of a material such as NiSi (nickel silicide) capable of forming ohmic contact with n-type silicon carbide single crystal substrate 4 . Drain electrode 63 is electrically connected to silicon carbide single crystal substrate 4 .

Next, the operation of the MOSFET 150 according to this embodiment will be described. In a state where the voltage applied to the gate electrode 64 is less than the threshold voltage, that is, in the OFF state, even if a voltage is applied between the source electrode 60 and the drain electrode 63, the pn between the body region 30 and the drift region 10 is maintained. The junction becomes reverse biased and non-conducting. On the other hand, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 64 , an inversion layer is formed in the channel region near the contact with the gate insulating film 71 of the body region 30 . As a result, body region 30 and drift region 10 are electrically connected, and current flows between source electrode 60 and drain electrode 63 . The MOSFET 150 operates as described above.

Next, a method for manufacturing silicon carbide semiconductor module 400 will be described.
As shown in FIG. 9, the method for manufacturing silicon carbide semiconductor module 400 mainly includes a preparation step S1 and a mounting step S2. First, in preparing step S1, a step of preparing a silicon carbide epitaxial substrate is performed. Silicon carbide single crystal substrate 4 is prepared by slicing a silicon carbide ingot (not shown) manufactured by, for example, a sublimation method. Silicon carbide single crystal substrate 4 has a maximum diameter of, for example, 100 mm or more, preferably 150 mm or more.

Next, a step of forming silicon carbide epitaxial layer 3 is performed. A silicon carbide single crystal substrate is formed by a CVD (Chemical Vapor Deposition) method using, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and hydrogen (H ₂ ) as a carrier gas. A silicon carbide epitaxial layer 3 is formed on 4 by epitaxial growth. During epitaxial growth, an n-type impurity such as nitrogen is introduced into silicon carbide epitaxial layer 3 . As described above, silicon carbide epitaxial substrate 100 is formed.

As shown in FIGS. 10 and 11 , silicon carbide epitaxial substrate 100 has silicon carbide single crystal substrate 4 and silicon carbide epitaxial layer 3 . Silicon carbide epitaxial layer 3 forms fifth main surface 1 . Silicon carbide epitaxial layer 3 forms sixth main surface 2 . The fifth main surface 1 extends two-dimensionally along each of the first direction 101 and the second direction 102 . Outer edge portion 13 of silicon carbide epitaxial substrate 100 surrounds fifth main surface 1 when viewed in a direction perpendicular to fifth main surface 1 . The outer edge 13 has, for example, an orientation flat 11 and an arcuate portion 12 . The orientation flat 11 extends along the first direction 101 . The arcuate portion 12 continues to the orientation flat 11 .

The second direction 102 is, for example, the <1-100> direction. The second direction may be, for example, the [1-100] direction. The first direction 101 is parallel to the fifth main surface 1 and perpendicular to the second direction 102 . The first direction 101 is, for example, a direction including a <11-20> direction component. From another point of view, the first direction is a direction obtained by projecting the <11-20> direction onto a plane parallel to the fifth main surface 1 . The first direction 101 may be a direction including a [11-20] direction component, for example.

The fifth main surface 1 is a {0001} plane or a plane inclined at an angle of 8° or less with respect to the {0001} plane. Specifically, the fifth main surface 1 is, for example, the (000-1) plane or a plane inclined at an angle of 8° or less with respect to the (000-1) plane. When fifth main surface 1 is inclined with respect to the {0001} plane, the inclination direction (off direction) is, for example, the <11-20> direction. The tilt angle (off angle) with respect to the {0001} plane may be 1° or more, or may be 2° or more. The off angle may be 7° or less, 6° or less, or 4° or less. The fifth main surface 1 may be the (0001) plane or a plane inclined at an angle of 8° or less with respect to the (0001) plane.

An ion implantation step is then performed. For example, a p-type impurity such as aluminum is ion-implanted into silicon carbide epitaxial layer 3 . Thereby, body region 30 is formed. Next, an n-type impurity such as phosphorus is ion-implanted into body region 30 . A source region 40 is thus formed. Next, a mask layer (not shown) having openings over the regions where the contact regions 8 are to be formed is formed. Next, a p-type impurity such as aluminum is implanted into source region 40 . Thereby, contact region 8 in contact with each of source region 40 and body region 30 is formed (see FIG. 12).

Next, activation annealing is performed to activate the impurity ions implanted into silicon carbide epitaxial substrate 100 . The temperature of the activation annealing is preferably 1500°C or higher and 1900°C or lower, for example about 1700°C. The activation annealing time is, for example, about 30 minutes. The atmosphere for the activation annealing is preferably an inert gas atmosphere such as an Ar atmosphere. Source region 40 and contact region 8 constitute fifth main surface 1 .

Next, a step of forming gate trenches 7 is performed. First, silicon carbide epitaxial substrate 100 is etched with mask layer 31 formed on fifth main surface 1 . Specifically, for example, part of source region 40 and part of body region 30 are removed by etching. As an etching method, for example, reactive ion etching, especially inductively coupled plasma reactive ion etching can be used. For example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF ₆ ) or a mixed gas of SF ₆ and oxygen (O ₂ ) as a reactive gas can be used. By etching, in the region where the gate trench 7 is to be formed, a side portion substantially perpendicular to the fifth main surface 1 and a bottom provided continuously with the side portion and substantially parallel to the fifth main surface 1 are formed. is formed.

A thermal etch is then performed in the recess. Thermal etching can be performed by heating in an atmosphere containing a reactive gas containing at least one type of halogen atom while mask layer 31 is formed on fifth main surface 1 . The at least one halogen atom includes at least one of chlorine (Cl) and fluorine (F) atoms. The atmosphere includes, for example, chlorine ( _Cl2 ), boron trichloride ( _BCl3 ), _SF6 or carbon tetrafluoride ( _CF4 ). For example, a mixed gas of chlorine gas and oxygen gas is used as a reaction gas, and thermal etching is performed at a heat treatment temperature of, for example, 800° C. or higher and 900° C. or lower. Note that the reaction gas may contain a carrier gas in addition to the chlorine gas and the oxygen gas described above. Nitrogen gas, argon gas, or helium gas, for example, can be used as the carrier gas. A gate trench 7 is formed in the fifth main surface 1 by thermal etching (see FIG. 13).

Side surface 5 extends through source region 40 and body region 30 to drift region 10 . From another point of view, the side surface 5 is composed of the source region 40 , the body region 30 and the drift region 10 . Bottom surface 6 is located in drift region 10 . From another point of view, the bottom surface 6 is composed of the drift region 10 . Bottom surface 6 is, for example, a plane parallel to sixth main surface 2 . As shown in FIG. 13 , in a cross section perpendicular to the longitudinal direction of gate trench 7 , the width of gate trench 7 increases from bottom surface 6 toward fifth main surface 1 .

Next, a step of forming gate insulating film 71 is performed. For example, by thermally oxidizing silicon carbide epitaxial substrate 100, gate insulating film 71 in contact with source region 40, body region 30, drift region 10, contact region 8 and fifth main surface 1 is formed. Specifically, silicon carbide epitaxial substrate 100 is heated, for example, at a temperature of 1300° C. or more and 1400° C. or less in an atmosphere containing oxygen. Thereby, a gate insulating film 71 in contact with the gate trench 7 is formed.

Next, heat treatment (NO annealing) may be performed on silicon carbide epitaxial substrate 100 in a nitrogen monoxide (NO) gas atmosphere. In the NO annealing, silicon carbide epitaxial substrate 100 is held under conditions of, for example, 1100° C. or more and 1400° C. or less for about 1 hour. Thereby, nitrogen atoms are introduced into the interface region between gate insulating film 71 and body region 30 . As a result, the channel mobility can be improved by suppressing the formation of interface states in the interface region.

After the NO anneal, Ar anneal using argon (Ar) as the ambient gas may be performed. The heating temperature for Ar annealing is, for example, higher than the heating temperature for NO annealing. The Ar annealing time is, for example, about one hour. This further suppresses the formation of an interface state in the interface region between gate insulating film 71 and body region 30 . As the atmosphere gas, other inert gas such as nitrogen gas may be used instead of Ar gas.

Next, a step of forming gate electrode 64 is performed. A gate electrode 64 is formed on the gate insulating film 71 . Gate electrode 64 is formed, for example, by LP-CVD (Low Pressure Chemical Vapor Deposition). The gate electrode 64 is formed to fill the groove formed by the gate insulating film 71 . Gate electrode 64 is formed to face each of source region 40, body region 30 and drift region 10 (see FIG. 14).

Next, a step of forming isolation insulating film 72 is performed. Specifically, an isolation insulating film 72 is formed in the gate trench 7 so as to cover the gate electrode 64 . Isolation insulating film 72 is formed by, for example, a CVD (Chemical Vapor Deposition) method. The isolation insulating film 72 may be formed by normal pressure CVD, plasma CVD, or low pressure CVD. Isolation insulating film 72 is, for example, a material containing silicon dioxide. Isolation insulating film 72 is in contact with each of gate electrode 64 and gate insulating film 71 .

Next, a step of forming the source electrode 60 is performed. For example, a portion of each of gate insulating film 71 and isolation insulating film 72 is removed by dry etching. As a result, a portion of fifth main surface 1 is exposed from gate insulating film 71 . Electrode film 61 is formed in contact with each of source region 40 and contact region 8 on fifth main surface 1 . Electrode film 61 is formed by sputtering, for example. Electrode film 61 is made of a material containing Ti, Al and Si, for example.

Next, the electrode film 61 is held at a temperature of, for example, 900° C. or more and 1100° C. or less for about 5 minutes. Thereby, at least part of electrode film 61 reacts with silicon contained in silicon carbide epitaxial substrate 100 to be silicided. As a result, the electrode film 61 that makes an ohmic contact with the source region 40 is formed. The electrode film 61 may be in ohmic contact with the contact region 8 . Next, a metal film 62 is formed. Metal film 62 is formed on each of electrode film 61 and isolation insulating film 72 . Metal film 62 contains, for example, aluminum. Thus, the source electrode 60 including the electrode film 61 and the metal film 62 is formed (see FIG. 15).

Next, sixth main surface 2 of silicon carbide epitaxial substrate 100 is subjected to back polishing. Thereby, the thickness of silicon carbide single crystal substrate 4 is reduced. Next, a step of forming the drain electrode 63 is performed. Drain electrode 63 in contact with sixth main surface 2 is formed by sputtering, for example. Drain electrode 63 is made of a material containing NiSi or TiAlSi, for example. Next, silicon carbide epitaxial substrate 100 is diced by, for example, a grindstone (not shown). Thereby, silicon carbide epitaxial substrate 100 is divided into a plurality of silicon carbide semiconductor chips 200 (see FIG. 16). Each of the plurality of silicon carbide semiconductor chips 200 includes a silicon carbide semiconductor element 150 such as a MOSFET.

As shown in FIG. 16 , each of silicon carbide semiconductor chips 200 has a second main surface 202 and a fourth main surface 201 . The fourth major surface 201 is opposite the second major surface 202 . The fourth major surface 201 is the surface. The source electrode 60 is exposed on the fourth main surface 201 . The second major surface 202 is the back surface. A drain electrode 63 is exposed on the second main surface 202 . The inner peripheral portion 80 of the second main surface 202 has a first position 81 , a second position 84 , a third position 83 and a fourth position 85 .

As shown in FIG. 16 , each of silicon carbide semiconductor chips 200 has a first side 211 and a second side 212 . The second side 212 is shorter than the first side 211 . The first side 211 is the long side. The second side 212 is the short side. As shown in FIG. 16, a line that bisects the pair of second sides 212 is defined as a first straight line C1, and a line that bisects the pair of first sides 211 is defined as a second straight line C2. The third straight line C3 is a straight line perpendicular to each of the first straight line C1 and the second straight line C2. The second major surface 202 has a center 82 . The center 82 is the point where the second main surface 202 and the third straight line C3 intersect. The first position 81 and the second position 84 are on one side and the other side of the first straight line C1, respectively. The third position 83 and the fourth position 85 are on one side and the other side of the second straight line C2, respectively.

Next, the surface shape of second main surface 202 of silicon carbide semiconductor chip 200 is measured. Specifically, the shape of the second principal surface 202 is measured using a surface shape measurement system (model number: DY-3000-008) manufactured by Kohzu Seiki Co., Ltd. FIG. 17 is a schematic cross-sectional view showing a state in which silicon carbide semiconductor chip 200 is arranged on stage 310 of the surface profile measurement system. As shown in FIG. 17, silicon carbide semiconductor chip 200 is placed on stage 310 of a profilometer system. The stage 310 has a flat surface 311 . The surface profile measurement system is a non-contact profile measurement system using a laser displacement meter.

As shown in FIG. 17 , silicon carbide semiconductor chip 200 is arranged on flat surface 311 such that fourth main surface 201 faces flat surface 311 . Silicon carbide semiconductor chip 200 is warped. Specifically, silicon carbide semiconductor chip 200 is warped such that fourth main surface 201 is recessed and second main surface 202 protrudes. In this state, the second main surface 202 is irradiated with laser light. The profilometer system measures the height of the second major surface 202 from the first location 81 to the second location 84 . The first position 81 is a position spaced apart by a first width W from the outer peripheral surface 203 toward the center 82 in the direction parallel to the flat surface 311 . The second position 84 is located on the opposite side of the center 82 from the first position 81 . A second position 84 is a position spaced apart by a first width W from the outer peripheral surface 203 toward the center 82 in the direction parallel to the flat surface 311 . The center 82 is located midway between the first position 81 and the second position 84 . The first width W is 0.5 mm.

FIG. 18 is a height profile of second main surface 202 of silicon carbide semiconductor chip 200 . As shown in FIG. 18, the height profile 302 of the second major surface 202 is upwardly convex. From another point of view, the second main surface 202 is curved so as to protrude in the opposite direction to the flat surface 311 of the stage. The height of the second main surface 202 at the first position 81 is the first height H1. The height of the second major surface 202 at the second position 84 is the second height H2. The height of the second major surface 202 at the center 82 is the third height H3. As shown in FIG. 18, the straight line passing through the first position 81 and the second position 84 is the fourth straight line C4.

In each of the plurality of silicon carbide semiconductor chips 200, when the height of second main surface 202 is measured from first position 81 to second position 84 with second main surface 202 facing upward, the second The center 82 of the main surface 202 is located higher than the straight line (fourth straight line C4) passing through the first position 81 and the second position 84 . Specifically, the height of the second main surface 202 at the center 82 (third height H3) is higher than the height of the fourth straight line C4 at the center 82 (fourth height H4). As shown in FIG. 18, the height profile 302 of the second major surface 202 has a monotonically increasing portion from the first position 81 to the center 82 and a monotonically decreasing portion from the center 82 to the second position 84 . You may have a part to do.

As described above, when the height of the second principal surface 202 is measured from the first position 81 to the second position 84 using, for example, a surface profile measurement system, the center 82 of the second principal surface 202 is the first Silicon carbide semiconductor chips 200 positioned higher than a straight line (fourth straight line C4) passing through position 81 and second position 84 are selected. In each of a plurality of selected silicon carbide semiconductor chips 200, when the height of second main surface 202 is measured from first position 81 to second position 84, center 82 of second main surface 202 is located at the first It is located higher than the straight line (fourth straight line C4) passing through the position 81 and the second position 84 .

Also, a circuit board 20 is prepared. The circuit board 20 has a base material 24 and a circuit pattern 23 . The circuit pattern 23 is provided on the base material 24 . The circuit board 20 has a first principal surface 21 and a third principal surface 22 . The third principal surface 22 is the surface opposite to the first principal surface 21 . The first main surface 21 is configured with a circuit pattern 23 . The third main surface 22 is made up of a base material 24 .

Next, the mounting step S2 is performed. In the mounting step, each of a plurality of silicon carbide semiconductor chips 200 is mounted on circuit board 20 such that second main surface 202 faces first main surface 21 . Specifically, as shown in FIGS. 2 and 3 , silicon carbide semiconductor chip 200 is mounted on circuit board 20 with bonding member 50 interposed therebetween. Joining member 50 is, for example, solder. The joining member 50 may be made of any conductive material, and is not limited to solder. The joining member 50 may be silver paste or the like, for example. As shown in FIGS. 2 and 3 , the joining member 50 is electrically connected to the circuit pattern 23 on the first main surface 21 . Joining member 50 is electrically connected to drain electrode 63 of silicon carbide semiconductor chip 200 at second main surface 202 . Drain electrode 63 of silicon carbide semiconductor chip 200 is electrically connected to circuit pattern 23 via joining member 50 .

As shown in FIG. 1, each of the plurality of silicon carbide semiconductor chips 200 may have a rectangular shape. Each of silicon carbide semiconductor chips 200 has a first side 211 and a second side 212 . When each of a plurality of silicon carbide semiconductor chips 200 has a rectangular shape, second side 212 is shorter than first side 211 . The first side 211 is the long side. The second side 212 is the short side.

FIG. 18 shows a height profile 302 when the height of the second main surface 202 is measured along the first straight line C1. As shown in FIGS. 16 and 18, the fourth straight line C4 is a straight line passing through the first position 81 and the second position 84. As shown in FIGS. The first position 81 is a position spaced apart by a first width W from the outer peripheral surface 203 toward the center 82 in the direction along the first straight line C1. The second position 84 is a position spaced apart by a first width W from the outer peripheral surface 203 toward the center 82 in the direction along the first straight line C1. The center 82 is located midway between the first position 81 and the second position 84 . The first width W is 0.5 mm.

FIG. 19 shows a height profile 302 when the height of the second main surface 202 is measured along the second straight line C2. As shown in FIGS. 16 and 19, the fifth straight line C5 is a straight line passing through the third position 83 and the fourth position 85. As shown in FIG. The third position 83 is a position spaced apart by the first width W from the outer peripheral surface 203 toward the center 82 in the direction along the second straight line C2. The fourth position 85 is located on the opposite side of the center 82 from the third position 83 . A fourth position 85 is a position spaced apart by a first width W from the outer peripheral surface 203 toward the center 82 in the direction along the second straight line C2. The center 82 is at an intermediate position between the third position 83 and the fourth position 85 . The first width W is 0.5 mm.

As shown in FIGS. 18 and 19, in the preparation step S1, with the second main surface 202 facing upward, the second main surface 202 extends along a direction (first straight line C1) parallel to the first side 211. The distance (fourth distance D4) between the center 82 and the fourth straight line C4 when the height of the surface 202 is measured is the second main surface 202 along the direction (second straight line C2) parallel to the second side 212. A plurality of silicon carbide semiconductor chips 200 that are larger than the distance (fifth distance D5) between center 82 and fifth straight line C5 when measuring the height of may be prepared. The fourth distance D4 may be, for example, 0.0001 mm or longer, or 0.0002 mm or longer. The fourth distance D4 may be, for example, 0.002 mm or less or 0.001 mm or less. The fifth distance D5 may be, for example, 0.0001 mm or longer, or 0.0002 mm or longer. The fifth distance D5 may be, for example, 0.002 mm or less or 0.001 mm or less. The absolute value of the difference between the fourth distance D4 and the fifth distance D5 may be, for example, 0.0001 mm or more and 0.001 mm or less.

As shown in FIG. 4, each of the plurality of silicon carbide semiconductor chips 200 may have a square shape. When each of a plurality of silicon carbide semiconductor chips 200 has a square shape, second side 212 has the same length as first side 211 . When each of a plurality of silicon carbide semiconductor chips 200 has a square shape, fourth distance D4 may be the same as or different from fifth distance D5.

FIG. 20 is a modification of height profile 302 of second main surface 202 of silicon carbide semiconductor chip 200 . As shown in FIG. 20, the height profile 302 of the second major surface 202 may have an upwardly convex portion and a downwardly convex portion. From another point of view, the second main surface 202 has a portion that is curved so as to protrude to the side opposite to the flat surface 311 of the stage, and a portion that is curved so as to protrude from the flat surface 311 . You may have a part.

Also in the height profile 302 shown in FIG. 20, the height of the second main surface 202 at the center 82 (third height H3) is higher than the height of the fourth straight line C4 at the center 82 (fourth height H4). in a high position. As shown in FIG. 20, the height profile 302 of the second major surface 202 exhibits a maximum value between the first position 81 and the center 82 and a minimum value between the center 82 and the second position 84. may indicate.

Next, functions and effects of silicon carbide semiconductor module 400 and its manufacturing method according to the above embodiment will be described.

Silicon carbide semiconductor module 400 generally has a plurality of silicon carbide semiconductor chips 200 mounted on circuit board 20 . Silicon carbide semiconductor chip 200 has a tendency to warp more easily than a silicon semiconductor chip. The distance between the center 82 of the back surface (second main surface 202) of silicon carbide semiconductor chip 200 and the front surface (first main surface 21) of circuit board 20 is equal to the inner peripheral portion 80 of the back surface of silicon carbide semiconductor chip 200 and the circuit board. 20 (in other words, the back surface is convex), the thickness of bonding member 50 at center 82 of the back surface is equal to the inner circumference of the back surface. It is smaller than the thickness of the joining member 50 at the portion 80 (see FIG. 2). Silicon carbide semiconductor chip 200 is provided with silicon carbide semiconductor element 150 in the center. Therefore, silicon carbide semiconductor chip 200 is more likely to generate heat in the central portion than in the outer peripheral portion.

When the thickness of the bonding member 50 at the center 82 of the back surface is smaller than the thickness of the bonding member 50 at the inner peripheral portion 80 of the back surface (in other words, when the back surface is convex), the thickness of the bonding member 50 at the center 82 of the back surface is reduced. Compared to the case where the thickness is greater than the thickness of the joining member 50 at the inner peripheral portion 80 of the back surface (in other words, when the back surface is concave), heat removal is facilitated. Therefore, it is considered that the temperature rise of silicon carbide semiconductor chip 200 can be reduced when the back surface is convex.

Silicon carbide semiconductor chip 200 deteriorates in characteristics (eg, on-resistance, threshold voltage, etc.) with environmental changes (eg, temperature change, aging change, etc.). Specifically, silicon carbide semiconductor chip 200 having a concave rear surface is more likely to have its characteristics deteriorated than silicon carbide semiconductor chip 200 having a convex rear surface. Therefore, in silicon carbide semiconductor module 400, when silicon carbide semiconductor chip 200 with a convex back surface and silicon carbide semiconductor chip 200 with a concave back surface are mixed, the characteristics of each silicon carbide semiconductor chip 200 are different. Since the deterioration rates are different, it is difficult to predict changes in the characteristics of silicon carbide semiconductor module 400 as a whole.

Therefore, in the silicon carbide semiconductor module 400 of the present embodiment, all the silicon carbide semiconductor chips 200 mounted on the silicon carbide semiconductor module 400 have the same convex back surface. Specifically, according to silicon carbide semiconductor module 400 of the present embodiment, in each of a plurality of silicon carbide semiconductor chips 200, the distance between center 82 of second main surface 202 and first main surface 21 is the second It is smaller than the distance between the inner peripheral portion 80 of the main surface 202 and the first main surface 21 . Further, according to the method for manufacturing silicon carbide semiconductor module 400 of the present embodiment, in each silicon carbide semiconductor chip 200, the height of second main surface 202 from first position 81 to second position 84 of second main surface 202 is , the center 82 of the second major surface 202 is located higher than a straight line passing through the first position 81 and the second position 84 . Thereby, the shape of the second main surface 202 (back surface) of all the silicon carbide semiconductor chips 200 becomes convex. Therefore, the rate of deterioration of the characteristics of all silicon carbide semiconductor chips 200 can be uniformed. As a result, the predictability of characteristic changes in silicon carbide semiconductor module 400 as a whole can be improved.

In silicon carbide semiconductor chip 200 removed from circuit board 20 , when measuring the height of second main surface 202 from first position 81 to second position 84 of second main surface 202 , When center 82 is at a position higher than a straight line passing through first position 81 and second position 84 , in the state of silicon carbide semiconductor module 400 , center 82 of second main surface 202 of silicon carbide semiconductor chip 200 and circuit It can be estimated that the distance between the substrate 20 and the first main surface 21 was smaller than the distance between the inner peripheral portion 80 of the second main surface 202 and the first main surface 21 .

Next, an example of height profile 302 of second main surface 202 of silicon carbide semiconductor chip 200 will be described. Silicon carbide semiconductor chip 200 has a square shape. Silicon carbide semiconductor chip 200 has a size of 6 mm×6 mm. A height profile 302 of the second main surface 202 was measured using a surface profile measurement system (model number: DY-3000-008) manufactured by Kozu Seiki Co., Ltd.

FIG. 21 shows the second principal measured from a first position 81 on the upper side to a second position 84 on the lower side along a straight line 0.5 mm away from the left side of silicon carbide semiconductor chip 200 toward center 82 . 3 is a height profile 302 of surface 202; A first position 81, which is the measurement start position of the height profile 302 of the second main surface 202, is a position 0.5 mm away from the upper side toward the lower side. As shown in FIG. 21, when the height of the second major surface 202 is measured from the first position 81 to the second position 84, the center 82 of the second major surface 202 is between the first position 81 and the second position 84. It was at a position higher than the straight line (fourth straight line C4) passing through. Height profile 302 had one maximum and one minimum.

FIG. 22 shows second main surface 202 measured from first position 81 on the upper side to second position 84 on the lower side along a straight line 3 mm away from the right side of silicon carbide semiconductor chip 200 toward center 82 . Height profile 302 . A first position 81, which is the measurement start position of the height profile 302 of the second main surface 202, is a position 0.5 mm away from the upper side toward the lower side. As shown in FIG. 22, when the height of the second principal surface 202 is measured from the first position 81 to the second position 84, the center 82 of the second principal surface 202 is the first position 81 and the second position 84. It was at a position higher than the straight line (fourth straight line C4) passing through. Height profile 302 had one maximum and one minimum.

FIG. 23 shows the second main surface measured from a first position 81 on the upper side to a second position 84 on the lower side along a straight line 0.5 mm away from the right side of silicon carbide semiconductor chip 200 toward center 82 . 202 is a height profile 302 . A first position 81, which is the measurement start position of the height profile 302 of the second main surface 202, is a position 0.5 mm away from the upper side toward the lower side. As shown in FIG. 23, when the height of the second major surface 202 is measured from the first position 81 to the second position 84, the center 82 of the second major surface 202 is between the first position 81 and the second position 84. It was at a position higher than the straight line (fourth straight line C4) passing through. Height profile 302 had two maxima and two minima.

FIG. 24 shows the second main surface measured from a first position 81 on the left side to a second position 84 on the right side along a straight line 0.5 mm away from the upper side of silicon carbide semiconductor chip 200 toward center 82 . 202 is a height profile 302 . A first position 81, which is the measurement start position of the height profile 302 of the second main surface 202, is a position 0.5 mm away from the left side toward the right side. As shown in FIG. 24, when the height of the second major surface 202 is measured from the first position 81 to the second position 84, the center 82 of the second major surface 202 is between the first position 81 and the second position 84. It was at a position higher than the straight line (fourth straight line C4) passing through. Height profile 302 had two maxima and one minima.

FIG. 25 shows second main surface 202 measured from first position 81 on the left side to second position 84 on the right side along a straight line 3 mm away from the upper side of silicon carbide semiconductor chip 200 toward center 82 . Height profile 302 . A first position 81, which is the measurement start position of the height profile 302 of the second main surface 202, is a position 0.5 mm away from the left side toward the right side. As shown in FIG. 25, when the height of the second principal surface 202 is measured from the first position 81 to the second position 84, the center 82 of the second principal surface 202 is the first position 81 and the second position 84. It was at a position higher than the straight line (fourth straight line C4) passing through. Height profile 302 had two maxima and one minima.

FIG. 26 shows the second main surface measured from a first position 81 on the left side to a second position 84 on the right side along a straight line 0.5 mm away from the lower side of silicon carbide semiconductor chip 200 toward center 82 . 202 is a height profile 302 . A first position 81, which is the measurement start position of the height profile 302 of the second main surface 202, is a position 0.5 mm away from the left side toward the right side. As shown in FIG. 25, when the height of the second principal surface 202 is measured from the first position 81 to the second position 84, the center 82 of the second principal surface 202 is the first position 81 and the second position 84. It was at a position higher than the straight line (fourth straight line C4) passing through. Height profile 302 had one maximum and two minimum values.

The embodiments and examples disclosed this time are illustrative in all respects and should not be considered restrictive. The scope of the present invention is indicated by the scope of the claims rather than the above description, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

1 fifth main surface 2 sixth main surface 3 silicon carbide epitaxial layer 4 silicon carbide single crystal substrate 5 side surface 6 bottom surface 7 gate trench 8 contact region 10 drift region 11 orientation flat 12 arc-shaped portion 13 outer edge portion 20 circuit board 21 first Main surface 22 Third main surface 23 Circuit pattern 24 Base material 25 First substrate region 26 Second substrate region 30 Body region 31 Mask layer 40 Source region 50 Junction member 60 Source electrode 61 Electrode film 62 Metal film 63 Drain electrode 64 Gate electrode 71 gate insulating film 72 isolation insulating film 80 inner peripheral portion 81 first position 82 center 83 third position 84 second position 85 fourth position 100 silicon carbide epitaxial substrate 101 first direction 102 second direction 150 silicon carbide semiconductor element (MOSFET )
200 silicon carbide semiconductor chip 201 fourth main surface 202 second main surface 203 outer peripheral surface 204 outer peripheral edge 210 first silicon carbide semiconductor chip 211 first side 212 second side 220 second silicon carbide semiconductor chip 302 height profile 310 stage 311 Flat surface 400 Silicon carbide semiconductor module C1 First straight line C2 Second straight line C3 Third straight line C4 Fourth straight line C5 Fifth straight line D1 First distance D2 Second distance D3 Third distance D4 Fourth distance D5 Fifth distance H1 First Height H2 Second height H3 Third height H4 Fourth height S1 Preparation process S2 Mounting process W First width

Claims (3)

a first step of preparing a circuit board having a first main surface and a plurality of silicon carbide semiconductor chips having a second main surface;
a second step of mounting each of the plurality of silicon carbide semiconductor chips on the circuit board such that the second main surface faces the first main surface;
The second principal surface has a first position 0.5 mm away from the outer peripheral edge of the second principal surface toward the center of the second principal surface in a direction parallel to the first principal surface, and and a second position opposite the first position,
In the first step, when the height of the second main surface is measured from the first position to the second position with the second main surface facing upward, the center is the second main surface. A method of manufacturing a silicon carbide semiconductor module, wherein the plurality of silicon carbide semiconductor chips are provided at positions higher than a straight line passing through the first position and the second position. each of the plurality of silicon carbide semiconductor chips has a rectangular shape having a first side and a second side shorter than the first side,
In the first step, with the second main surface facing upward, the center and the straight line when the height of the second main surface is measured along the direction parallel to the first side. is greater than the distance between the center and the straight line when the height of the second main surface is measured along the direction parallel to the second side, the plurality of silicon carbide semiconductor chips are prepared The method for manufacturing a silicon carbide semiconductor module according to claim 1 . 2. The method of manufacturing a silicon carbide semiconductor module according to claim 1 , wherein each of said plurality of silicon carbide semiconductor chips has a square shape.

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