JP2023182011A - Silicon carbide semiconductor device and manufacturing method of silicon carbide semiconductor device - Google Patents

Abstract

To provide a silicon carbide semiconductor device, in which leakage current flowing between a front surface and a rear surface via an edge surface can be reduced, and a manufacturing method of the silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device comprises a silicon carbide substrate that has a first principal surface and a second principal surface which is an opposite side of the first principal surface. The silicon carbide substrate has an edge surface that connects between the first principal surface and the second principal surface. The edge surface continues from a boundary of the second principal surface, and includes an inclined surface that is inclined to the second principal surface.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

Disclosed is a method for converting a semiconductor Si wafer into chips, in which steps are formed by performing anisotropic etching on the scribe line from the front surface of the semiconductor Si wafer, and then isotropic etching is performed on the entire back surface of the semiconductor Si wafer up to the steps. (For example, Patent Document 1).

JP2006-32486A

When a silicon carbide semiconductor device is manufactured according to the method described in Patent Document 1, a leakage current may flow between the front surface and the back surface via the end surface.

An object of the present disclosure is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can reduce leakage current flowing between the front surface and the back surface via an end surface.

A silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and the silicon carbide substrate has the first main surface and the second main surface opposite to the first main surface. It has an end surface that connects to the second main surface, and the end surface includes an inclined surface that is continuous from the boundary with the second main surface and is inclined with respect to the second main surface.

According to the present disclosure, leakage current flowing between the front surface and the back surface via the end surface can be reduced.

FIG. 1 is a plan view schematically showing a silicon carbide substrate included in a silicon carbide semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view schematically showing a silicon carbide substrate included in the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view showing a transistor included in the silicon carbide semiconductor device according to the first embodiment. FIG. 4 is a flowchart showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. FIG. 5 is a plan view (part 1) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 6 is a plan view (part 2) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 7 is a plan view (part 3) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 8 is a cross-sectional view (part 1) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 9 is a cross-sectional view (part 2) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 10 is a cross-sectional view (part 3) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 11 is a cross-sectional view (part 4) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 12 is a cross-sectional view (Part 5) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 13 is a cross-sectional view (part 6) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 14 is a cross-sectional view (part 7) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 15 is a cross-sectional view (Part 8) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 16 is a cross-sectional view (part 9) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 17 is a cross-sectional view (No. 10) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 18 is a cross-sectional view (No. 11) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 19 is a cross-sectional view (No. 12) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 20 is a cross-sectional view (No. 13) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 21 is a cross-sectional view (No. 14) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 22 is a cross-sectional view (No. 15) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 23 is a cross-sectional view (No. 16) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 24 is a cross-sectional view (No. 17) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 25 is a cross-sectional view (No. 18) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 26 is a cross-sectional view (No. 19) showing the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 27 is a plan view schematically showing a silicon carbide substrate included in the silicon carbide semiconductor device according to the second embodiment. FIG. 28 is a plan view (part 1) showing the method for manufacturing a silicon carbide semiconductor device according to the second embodiment. FIG. 29 is a plan view (part 2) showing the method for manufacturing the silicon carbide semiconductor device according to the second embodiment. FIG. 30 is a cross-sectional view schematically showing a silicon carbide substrate included in a silicon carbide semiconductor device according to a modification of the first embodiment.

The embodiment will be described below.

[Description of embodiments of the present disclosure]
First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are given the same reference numerals, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [], collective orientations are indicated by <>, individual planes are indicated by (), and collective planes are indicated by {}, respectively. Also, the fact that the crystallographic index is negative is usually expressed by putting a "-" (bar) above the number, but in this specification, a negative sign is shown in front of the number. There is.

[1] A silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and the silicon carbide substrate includes: It has an end surface that connects the first main surface and the second main surface, and the end surface includes an inclined surface that is continuous from the boundary with the second main surface and is inclined with respect to the second main surface.

Since silicon carbide can obtain a higher breakdown voltage than silicon, silicon carbide semiconductor devices can be made thinner than silicon-based semiconductor devices. On the other hand, in a thin silicon carbide semiconductor device, the distance between the two main surfaces is short, and a leakage current may flow between the two main surfaces. On the other hand, in the silicon carbide semiconductor device according to one aspect of the present disclosure, since the end face includes the inclined surface, the leakage current is lower than when the end face is perpendicular to the first main surface and the second main surface. The path through which the water flows can be lengthened. Therefore, the leakage current flowing between the first main surface and the second main surface using the end surface as a path can be reduced.

[2] In [1], the silicon carbide substrate may include a silicon carbide single crystal substrate including the second main surface and a silicon carbide epitaxial layer including the first main surface. In this case, the silicon carbide epitaxial layer has good crystallinity, making it easy to obtain excellent characteristics.

[3] In [1] or [2], the inclined surface may be inclined so as to become wider toward the second main surface. In this case, when the second main surface is connected to the conductive layer or the like using solder, the solder tends to rise up the slope, making it easy to obtain good bonding strength. Further, when sealing a silicon carbide semiconductor device by transfer molding, air bubbles can be easily discharged from the vicinity of the end face, and mounting defects due to residual air bubbles can be easily suppressed.

[4] In [1] or [2], the inclined surface may be inclined so as to become wider toward the first main surface. In this case as well, the effects of reducing leakage current and improving heat dissipation can be obtained.

[5] In [3] or [4], the angle between the inclined surface and the second main surface may be 50° or more and 65° or less. In this case, it is easy to obtain good crystallinity on the inclined surface.

[6] In [1] to [5], the inclined surface may include a {0-33-8} plane. In this case, it is easy to obtain good crystallinity on the inclined surface.

[7] In [1] to [6], the surface roughness within a square region of 100 nm on a side of the inclined surface may be 1.0 nm or less in RMS. In this case, chipping can be easily suppressed.

[8] In [1] to [7], when viewed in plan from a direction perpendicular to the first principal surface, the second principal surface has a planar shape of a rounded rectangle with at least one rounded corner. May have. In this case, stress concentration at corners of the planar shape can be easily alleviated.

[9] A method for manufacturing a silicon carbide semiconductor device according to another aspect of the present disclosure includes a first main surface and a third main surface opposite to the first main surface, the first main surface a step of preparing a silicon carbide wafer with dicing lines, a step of thermally etching the dicing lines in an atmosphere containing halogen gas to form grooves in the dicing lines, and and a step of dividing the silicon carbide wafer into pieces by thinning it from three main surfaces.

According to the method for manufacturing a silicon carbide semiconductor device according to another aspect of the present disclosure, the inclined surface according to claim 1 can be easily formed.

[10] In [9], the step of dividing the silicon carbide wafer into pieces may include the step of grinding the silicon carbide wafer from the third main surface side. In this case, since the grinding is performed after the grooves are formed, it is easy to disperse the pressure applied to the silicon carbide wafer.

[11] In [9] or [10], the step of preparing the silicon carbide wafer includes forming a silicon carbide epitaxial layer including the first main surface on a silicon carbide single crystal substrate including the third main surface. It may also include a step of forming. In this case, the silicon carbide epitaxial layer has good crystallinity, making it easy to obtain excellent properties.

[12] In [9] to [11], the step of thermally etching the dicing line includes forming a covering portion that covers a part of the first main surface and an opening that exposes the remainder of the first main surface. forming an etching mask on the first main surface, the covering part having at least one rounded corner when viewed in plan from a direction perpendicular to the first main surface. It may have a rectangular planar shape with rounded corners. In this case, stress concentration at corners of the planar shape can be easily alleviated.

[First embodiment]
A first embodiment of the present disclosure relates to a silicon carbide semiconductor device including a transistor. FIG. 1 is a plan view schematically showing a silicon carbide substrate included in a silicon carbide semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view schematically showing a silicon carbide substrate included in the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view showing a transistor included in the silicon carbide semiconductor device according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG.

As shown in FIGS. 1 and 2, a silicon carbide semiconductor device 100 according to the first embodiment includes a silicon carbide substrate 10, and the silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide single crystal substrate 50. an overlying silicon carbide epitaxial layer 40 . Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to first main surface 1 . Silicon carbide epitaxial layer 40 constitutes first principal surface 1 , and silicon carbide single crystal substrate 50 constitutes second principal surface 2 . Silicon carbide single crystal substrate 50 and silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen (N), and has n-type (first conductivity type). A semiconductor element is formed on a silicon carbide substrate 10. For example, distance L1 between first main surface 1 and second main surface 2, that is, the thickness of silicon carbide substrate 10, is about 50 μm or more and 200 μm or less.

The first main surface 1 is a {0001} plane or a {0001} plane inclined in the off direction by an off angle of 8° or less. Preferably, the first principal surface 1 is a (000-1) plane or a plane in which the (000-1) plane is inclined in the off direction by an off angle of 8° or less. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off-angle may be, for example, 1° or more, or 2° or more. The off angle may be 6° or less, or 4° or less.

As shown in FIG. 1, for example, silicon carbide substrate 10 has a rectangular planar shape. That is, the planar shape of silicon carbide substrate 10 includes two sides extending parallel to the first direction and two sides extending in the second direction perpendicular to the first direction. As shown in FIG. 2, silicon carbide substrate 10 has end surfaces 20 that connect first principal surface 1 and second principal surface 2 at positions corresponding to these four sides, respectively. The end surface 20 has an inclined surface 21 that is continuous from the boundary with the second main surface 2 and is inclined with respect to the second main surface 2. In this embodiment, the outline of the first main surface 1 is inside the outline of the second main surface 2 when viewed in plan from a direction perpendicular to the first main surface 1. The inclined surface 21 is inclined so as to become wider toward the second main surface 2 side. That is, the inclined surface 21 is inclined so as to enter inside the first main surface 1 as it approaches the first main surface 1 . The angle θ1 between the inclined surface 21 and the second main surface 2 is, for example, 50° or more and 65° or less. The angle θ1 may be, for example, 55° or more. The angle θ1 may be, for example, 60° or less. The inclined surface 21 preferably has a {0-33-8} plane. When the angle θ1 is 50° or more and 65° or less, it is easy to obtain good crystallinity in the inclined surface 21.

The angle θ1 may not be the same among the four inclined surfaces 21. For example, two inclined surfaces 21 provided at positions corresponding to sides parallel to the first direction have {0-33-8} planes, and two inclined surfaces 21 provided at positions corresponding to sides parallel to the second direction. The two inclined surfaces 21 may have a crystal plane different from the {0-33-8} plane. When the inclined surface 21 has a {0-33-8} plane, it is easy to obtain a good crystal plane on the inclined surface 21.

The end surface 20 may have a surface 23 that continues from the boundary with the first main surface 1 and a surface 22 that connects the inclined surface 21 and the surface 23. For example, the surface 23 may be substantially perpendicular to the first major surface 1 and the surface 22 may be substantially parallel to the first major surface 1 and the second major surface 2. For example, the distance L2 between the first principal surface 1 and the surface 22 is about 0.5 μm or more and 1.0 μm or less, which is extremely small compared to the distance L1.

In this embodiment, a MOSFET is formed on silicon carbide substrate 10 as an example of a semiconductor element. As shown in FIG. 3, silicon carbide epitaxial layer 40 mainly includes drift region 11, body region 12, source region 13, and contact region 18.

The drift region 11 has an n-type because it is doped with an n-type impurity such as nitrogen or phosphorus (P), for example. It is preferable that n-type impurities be added to the drift region 11 not by ion implantation but by impurity addition during epitaxial growth of the drift region 11.

Body region 12 is provided on drift region 11 . The body region 12 has a p-type (second conductivity type) because it is doped with a p-type impurity such as aluminum (Al), for example.

Source region 13 is provided on body region 12 so as to be separated from drift region 11 by body region 12 . The source region 13 has n-type because it is doped with an n-type impurity such as nitrogen or phosphorus. Source region 13 constitutes first main surface 1 .

The contact region 18 has p-type because it is doped with a p-type impurity such as aluminum. Contact region 18 constitutes first main surface 1 . Contact region 18 penetrates source region 13 and contacts body region 12 .

A plurality of gate trenches 5 are provided on the first main surface 1 . The gate trench 5 extends, for example, in a first direction parallel to the first main surface 1, and a plurality of gate trenches 5 are lined up in the second direction. Gate trench 5 has a bottom surface 4 made of drift region 11 . Gate trench 5 has a side surface 3 that extends through contact region 18 , source region 13 , and body region 12 and continues to bottom surface 4 . The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The angle of the side surface 3 with respect to the plane including the bottom surface 4 is, for example, 50° or more and 65° or less. This angle may be, for example, 55° or more. This angle may be, for example, 60° or less. The side surface 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.

A gate insulating film 81 is provided in contact with the side surfaces 3 and the bottom surface 4. The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of a material containing silicon dioxide, for example. Gate insulating film 81 contacts drift region 11 at bottom surface 4 . Gate insulating film 81 is in contact with each of source region 13 , body region 12 , and drift region 11 on side surface 3 . Gate insulating film 81 may be in contact with source region 13 on first main surface 1 .

A gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (polySi) containing conductive impurities. Gate electrode 82 is placed inside gate trench 5 .

An interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is made of a material containing silicon dioxide, for example. Interlayer insulating film 83 electrically insulates gate electrode 82 and source electrode 60.

Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the second direction. Contact holes 90 are provided such that gate trench 5 is located between adjacent contact holes 90 in the second direction. Contact hole 90 extends in the first direction. Source region 13 and contact region 18 are exposed from interlayer insulating film 83 and gate insulating film 81 through contact hole 90 .

A source electrode 60 in contact with the first main surface 1 is provided. The source electrode 60 has a contact electrode 61 provided in the contact hole 90 and a source wiring 62. Contact electrode 61 is in contact with source region 13 and contact region 18 on first main surface 1 . The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), Al, and Si. Contact electrode 61 is in ohmic contact with source region 13 and contact region 18 . The source wiring 62 is made of a material containing Al, for example.

A passivation film 85 is provided to cover the upper surface of the source wiring 62. Passivation film 85 is in contact with source wiring 62 . The passivation film 85 is made of a material containing polyimide, for example.

A drain electrode 70 in contact with the second main surface 2 is provided. Drain electrode 70 is in contact with silicon carbide single crystal substrate 50 at second main surface 2 . Drain electrode 70 is electrically connected to drift region 11 . The drain electrode 70 is made of a material containing NiSi, for example. The drain electrode 70 may be made of a material containing Ti, Al, and Si. Drain electrode 70 is in ohmic contact with silicon carbide single crystal substrate 50 .

In this embodiment, since the end surface 20 includes the inclined surface 21, the path through which the leakage current flows can be made longer than when the end surface 20 is perpendicular to the first main surface 1 and the second main surface 2. Therefore, the leakage current flowing between the first main surface 1 and the second main surface 2 using the end surface 20 as a path can be reduced. Moreover, since the area of the end surface 20 is larger than that in the case where the end surface 20 is perpendicular to the first main surface 1 and the second main surface 2, heat dissipation can be improved.

Further, silicon carbide substrate 10 includes silicon carbide single crystal substrate 50 including second main surface 2 and silicon carbide epitaxial layer 40 including first main surface 1 . In other words, silicon carbide substrate 10 is a so-called epitaxial substrate. Therefore, the crystallinity of the silicon carbide epitaxial layer is good and it is easy to obtain excellent characteristics.

Further, the inclined surface 21 is inclined so as to become wider toward the second main surface 2 side. Therefore, when the drain electrode 70 is connected to a conductive layer or the like formed on the surface of an insulating substrate via solder, the molten solder tends to rise up onto the inclined surface 21, causing a gap between the drain electrode 70 and the conductive layer, etc. It is easy to obtain good bonding strength. Further, when silicon carbide semiconductor device 100 is sealed by transfer molding, air bubbles can be easily discharged from the vicinity of end face 20, and mounting defects due to residual air bubbles can be easily suppressed.

The surface roughness of the inclined surface 21 is preferably 1.0 nm or less in RMS, more preferably 0.8 nm or less in a microscopic range such as calculated in a square area of 100 nm on a side. This is to suppress chipping in silicon carbide semiconductor device 100. Such microscopic surface roughness can be measured using, for example, an atomic force microscope (AFM).

Although inclined surface 21 preferably has a {0-33-8} plane, it may have a specific crystal plane of silicon carbide that is different from the {0-33-8} plane. Here, having a {0-33-8} plane means that the off-angle range is such that the plane orientation can be substantially considered to be {0-33-8}, taking into account the machining accuracy of the inclined surface 21, etc. This means that the surface orientation of the inclined surface 21 is included. The off-angle range in this case is, for example, a range of ±2° with respect to {0-33-8}.

For example, the angle formed between the off-direction of the inclined surface 21 and the <01-10> direction may be 5° or less. As a result, the off-direction becomes approximately the <01-10> direction, and as a result, the surface orientation of the inclined surface 21 becomes close to the {0-33-8} plane. The off angle of the inclined surface 21 with respect to the {0-33-8} plane in the <01-10> direction may be −3° or more and 5° or less.

"Off angle with respect to the {0-33-8} plane in the <01-10> direction" means the orthogonal projection of the normal of the inclined surface 21 onto a plane including the <01-10> direction and the <0001> direction, It is the angle formed with the normal line of the {0-33-8} plane. The sign of the angle is positive when the orthogonal projection approaches parallel to the <01-10> direction, and negative when the orthogonal projection approaches parallel to the <0001> direction.

Note that the gate trench 5 may be a vertical trench. That is, the angle of the side surface 3 with respect to the plane including the bottom surface 4 may be 90 degrees. Further, a transistor not including gate trench 5 may be formed in silicon carbide substrate 10. Further, the semiconductor element formed on silicon carbide substrate 10 is not limited to a transistor such as a MOSFET, and other semiconductor elements such as a Schottky barrier diode may be formed on silicon carbide substrate 10.

Next, a method for manufacturing silicon carbide semiconductor device 100 according to the first embodiment will be described. FIG. 4 is a flowchart showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. 5 to 7 are plan views showing a method for manufacturing a silicon carbide semiconductor device according to the first embodiment. 8 to 26 are cross-sectional views showing a method of manufacturing a silicon carbide semiconductor device according to the first embodiment. 17 to 26 show variations in the cross section shown in FIG. 3.

First, in step S1, as shown in FIGS. 8 and 17, silicon carbide single crystal substrate 50 is prepared. For example, silicon carbide single crystal substrate 50 is prepared by slicing a silicon carbide ingot (not shown) manufactured by a sublimation method. A buffer layer (not shown) may be formed on silicon carbide single crystal substrate 50. The buffer layer is formed by chemical vapor deposition (CVD) using, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and hydrogen (H ₂ ) as a carrier gas. ) method. For example, an n-type impurity such as nitrogen may be introduced into the buffer layer during epitaxial growth of the buffer layer.

Next, silicon carbide epitaxial layer 40 is formed on silicon carbide single crystal substrate 50. Silicon carbide epitaxial layer 40 is formed on silicon carbide single crystal substrate 50 by a CVD method using, for example, a mixed gas of silane and propane as a source gas and hydrogen as a carrier gas. During silicon carbide epitaxial layer 40 , an n-type impurity such as nitrogen is introduced into silicon carbide epitaxial layer 40 . Silicon carbide epitaxial layer 40 has an n-type conductivity type. In this way, silicon carbide wafer 51 including silicon carbide single crystal substrate 50 and silicon carbide epitaxial layer 40 is prepared. Silicon carbide wafer 51 has first main surface 1 and third main surface 55 opposite to first main surface 1 . For example, distance L3 between first main surface 1 and third main surface 55, that is, the thickness of silicon carbide wafer 51, is larger than the thickness of silicon carbide semiconductor device 100, for example, about 350 μm or more and 500 μm or less.

Next, in step S2, markers 91 are formed on the first main surface 1. In forming the marker 91, first, as shown in FIG. A separating dicing line 53 is set. For example, the dicing line 53 extends in the first direction and the second direction. Next, as shown in FIG. 8, silicon carbide epitaxial layer 40 is etched using, for example, a photoresist as an etching mask. As the etching method, for example, reactive ion etching (RIE), particularly inductive coupled plasma (ICP) RIE, can be used. Specifically, for example, ICP-RIE using SF ₆ or a mixed gas of SF ₆ and O ₂ as the reaction gas can be used. For example, the width of the marker 91 is about 10 μm, and the depth is equal to the distance L2, which is about 0.5 μm or more and 1.0 μm or less.

Next, in step S3, as shown in FIG. 18, ion implantation into silicon carbide epitaxial layer 40 is performed. For example, body region 12, source region 13, and contact region 18 are formed by ion implantation. The remainder of silicon carbide epitaxial layer 40 functions as drift region 11. In ion implantation for forming body region 12 or contact region 18, p-type impurity such as aluminum (Al) is ion-implanted. In the ion implantation for forming the source region 13, an n-type impurity such as phosphorus (P) is ion-implanted.

Next, in step S4, as shown in FIG. 9, an insulating film 92 is formed on the surface of silicon carbide epitaxial layer 40 by thermally oxidizing the surface of silicon carbide epitaxial layer 40. The insulating film 92 is made of a material containing silicon dioxide, for example.

Next, in step S5, as shown in FIGS. 6 and 10, an opening 92X is formed in the insulating film 92 to partially expose the bottom surface of the marker 91. In forming the opening 92X, the insulating film 92 is dry-etched using, for example, a photoresist as an etching mask. An etching mask 92Z is formed from the insulating film 92 and includes a covering portion 92Y that covers a part of the first main surface 1 and an opening 92X that exposes the remainder of the first main surface 1. The covering portion 92Y has a rectangular planar shape when viewed in plan from a direction perpendicular to the first main surface 1.

Next, in step S6, as shown in FIGS. 6 and 11, a dicing groove 95 is formed inside the marker 91 in plan view using an etching mask 92Z. In forming dicing grooves 95, first, a portion of silicon carbide wafer 51 is etched away in opening 92X by RIE such as ICP-RIE. Specifically, ICP-RIE can be used, for example, using SF ₆ or a mixed gas of SF ₆ and O ₂ as the reaction gas. By such etching, it is possible to form a recessed portion having an inner surface whose side surfaces are substantially perpendicular to the first main surface 1. Next, using etching mask 92Z, thermal etching is performed on silicon carbide wafer 51 on the inner surface of the recess. Thermal etching can be performed, for example, by heating silicon carbide wafer 51 in an atmosphere containing a halogen-based reactive gas containing at least one type of halogen atom. At least one type of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. This atmosphere is, for example, _Cl2 , _BCL3 , _SF6 , or _CF4 . For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas, and at a heat treatment temperature of, for example, 700° C. or higher and 1000° C. or lower. Note that the reaction gas may contain a carrier gas in addition to chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen (N ₂ ) gas, argon gas, helium gas, etc. can be used. When the heat treatment temperature is set to 700° C. or more and 1000° C. or less as described above, the etching rate of SiC is, for example, about 70 μm/hour. Insulating film 92 made of a material containing silicon dioxide and used as an etching mask has an extremely high selectivity to silicon carbide, so it is not substantially etched during etching of silicon carbide.

Dicing grooves 95 having side surfaces 93 and bottom surfaces 94 are formed in silicon carbide wafer 51 by the above thermal etching. When forming dicing grooves 95, silicon carbide wafer 51 is side-etched from openings 92X. Further, during thermal etching, the {0-33-8} plane, which is the crystal plane with the slowest etching rate, is self-formed as the side surface 93 of the dicing groove 95. For example, the distance L4 between the bottom surface 94 of the dicing groove 95 and the bottom surface of the marker 91 is, for example, about 50 μm or more and 200 μm or less. The distance between first main surface 1 and bottom surface 94 of dicing groove 95 is equal to the sum of distance L2 and distance L4, and first main surface 1 and second main surface 2 in silicon carbide semiconductor device 100 to be manufactured are and the distance L2 between the two.

Next, in step S7, the etching mask 92Z is removed from the first main surface 1, as shown in FIG.

Next, in step S8, activation heat treatment is performed to activate the impurities added by ion implantation. The temperature of this heat treatment is preferably 1500°C or more and 1900°C or less, for example about 1700°C. The heat treatment time is, for example, about 30 minutes. The atmosphere for the heat treatment is preferably an inert gas atmosphere, for example an Ar atmosphere.

Next, in step S9, gate trenches 5 are formed in silicon carbide wafer 51, as shown in FIG. Like the dicing groove 95, the gate trench 5 can be formed by RIE and thermal etching using an insulating film made of a material containing silicon dioxide in which an opening is formed as an etching mask. During thermal etching, the {0-33-8} plane is self-formed as the side surface 3.

Next, in step S10, as shown in FIG. 20, a gate insulating film 81 is formed. For example, by thermally oxidizing silicon carbide wafer 51, gate insulating film 81 in contact with source region 13, body region 12, drift region 11, and contact region 18 is formed. Specifically, silicon carbide wafer 51 is heated, for example, at a temperature of 1300° C. or more and 1400° C. or less in an atmosphere containing oxygen. As a result, a gate insulating film 81 in contact with the first main surface 1, side surfaces 3, and bottom surface 4 is formed. Note that when gate insulating film 81 is formed by thermal oxidation, strictly speaking, a part of silicon carbide wafer 51 is incorporated into gate insulating film 81. Therefore, in the subsequent processing, it is assumed that first main surface 1, side surface 3, and bottom surface 4 are slightly moved to the interface between gate insulating film 81 and silicon carbide wafer 51 after thermal oxidation.

Next, heat treatment (NO annealing) may be performed on silicon carbide wafer 51 in a nitrogen monoxide (NO) gas atmosphere. In the NO annealing, silicon carbide wafer 51 is held for about one hour under conditions of, for example, 1100° C. or higher and 1400° C. or lower. As a result, nitrogen atoms are introduced into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of interface states in the interface region is suppressed, thereby improving channel mobility.

Next, in step S11, a gate electrode 82 is formed as shown in FIG. Gate electrode 82 is formed on gate insulating film 81. The gate electrode 82 is formed by, for example, a low pressure chemical vapor deposition (LP-CVD) method. Gate electrode 82 is formed to face each of source region 13, body region 12, and drift region 11.

Next, in step S12, as shown in FIG. 22, an interlayer insulating film 83 is formed. Specifically, an interlayer insulating film 83 is formed to cover the gate electrode 82 and be in contact with the gate insulating film 81 . The interlayer insulating film 83 is formed by, for example, a CVD method. The interlayer insulating film 83 is made of a material containing silicon dioxide, for example. A portion of interlayer insulating film 83 may be formed inside gate trench 5 .

Next, in step S13, as shown in FIG. 23, the interlayer insulating film 83 and the gate insulating film 81 are etched to form a contact hole 90 in the interlayer insulating film 83 and the gate insulating film 81. As a result, source region 13 and contact region 18 are exposed from interlayer insulating film 83 and gate insulating film 81. Next, a metal film (not shown) for contact electrode 61 in contact with source region 13 and contact region 18 on first main surface 1 is formed. The metal film for the contact electrode 61 is formed by, for example, a sputtering method. The metal film for the contact electrode 61 is made of a material containing Ni, for example. Next, alloying annealing is performed. The metal film for the contact electrode 61 is held at a temperature of, for example, 900° C. or more and 1100° C. or less for about 5 minutes. As a result, at least a portion of the metal film for contact electrode 61 reacts with silicon contained in silicon carbide wafer 51 and becomes silicide. As a result, a contact electrode 61 that makes ohmic contact with the source region 13 and the contact region 18 is formed. The contact electrode 61 may be made of a material containing Ti, Al, and Si.

Next, in step S14, as shown in FIG. 24, source wiring 62 is formed. Specifically, source wiring 62 covering contact electrode 61 and interlayer insulating film 83 is formed. The source wiring 62 is formed by, for example, film formation using a sputtering method and RIE. The source wiring 62 is made of a material containing aluminum, for example. In this way, source electrode 60 having contact electrode 61 and source wiring 62 is formed.

Next, in step S15, a passivation film 85 is formed as shown in FIG. Specifically, a passivation film 85 covering the source wiring 62 is formed. The passivation film 85 is made of a material containing polyimide, for example. The passivation film 85 is formed, for example, by a coating method. The passivation film 85 may be formed by plasma CVD.

Next, in step S16, as shown in FIG. 13, an adhesive tape 96 is pasted on the passivation film 85. Note that in FIGS. 13 to 16, illustrations of the passivation film 85 and the like formed on the first main surface 1 of the silicon carbide wafer 51 are omitted.

Next, in step S17, back grinding of silicon carbide wafer 51 is performed. Specifically, silicon carbide wafer 51 is thinned by grinding from the third main surface 55 side. Polishing of silicon carbide wafer 51 is performed until the thickness of silicon carbide wafer 51 becomes equal to distance L2 between first main surface 1 and second main surface 2 in silicon carbide semiconductor device 100. Since the distance between the first main surface 1 and the bottom surface 94 of the dicing groove 95 is larger than the distance L2 between the first main surface 1 and the second main surface 2, as a result of polishing the third main surface 55, as shown in FIG. As shown in FIG. 7 and FIG. 14, silicon carbide wafer 51 is separated into individual pieces for each chip region 52. As shown in FIG. As a result, silicon carbide substrate 10 including first main surface 1 and second main surface 2 is formed for each chip region 52.

Next, in step S18, as shown in FIGS. 15 and 26, drain electrode 70 is formed in contact with silicon carbide single crystal substrate 50 on second main surface 2. In this way, silicon carbide semiconductor device 100 is formed in each chip region 52. The side surface 3 of the dicing groove 95 becomes the inclined surface 21, the side surface of the marker 91 becomes the surface 23, and the bottom surface of the marker 91 becomes the surface 22.

Next, in step S19, adhesive tape 96 is peeled off from silicon carbide semiconductor device 100, as shown in FIG.

In this way, silicon carbide semiconductor device 100 according to the first embodiment is completed.

In this manufacturing method, dicing lines 53 are thermally etched in an atmosphere containing halogen gas to form dicing grooves 95 in dicing lines 53, and silicon carbide wafer 51 is thinned from the third main surface 55 side to form silicon carbide. The wafer 51 is cut into pieces. Therefore, the side surface 93 of the dicing groove 95 can be made into an inclined surface inclined with respect to the third main surface 55, and this inclined surface becomes the inclined surface 21. Therefore, the end surface 20 having the inclined surface 21 can be easily formed.

Furthermore, since the inclined surface 21 is formed by thermal etching, mechanical damage is less likely to occur on the inclined surface 21 and its vicinity, and defects such as chipping are less likely to occur. Therefore, silicon carbide semiconductor device 100 has high mechanical strength and can improve reliability. For example, the surface roughness of the inclined surface 21 is easily set to 1.0 nm or less in RMS in a microscopic range such as calculated in a square area of 100 nm on a side.

Furthermore, as the grinding progresses from the third principal surface 55 side, silicon carbide wafer 51 is divided into individual pieces for each chip region 52 . Therefore, compared to the case where the wafer is diced using a dicer or the like after backgrinding, the pressure acting on silicon carbide substrate 10 can be dispersed, and cracks during machining can be reduced.

Note that the thermal etching may be stopped before the inclined surface 21 becomes a {0-33-8} plane. In other words, the inclined surface 21 does not have to be a {0-33-8} plane.

[Second embodiment]
Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the external shape. FIG. 27 is a plan view schematically showing a silicon carbide substrate included in the silicon carbide semiconductor device according to the second embodiment.

As shown in FIG. 27, in silicon carbide semiconductor device 200 according to the second embodiment, second main surface 2 has four rounded corners when viewed in plan from a direction perpendicular to first main surface 1. It has a rectangular planar shape with rounded corners. When viewed in plan from a direction perpendicular to the first main surface 1, the first main surface 1 may have a planar shape of a rounded rectangle with four rounded corners.

The other configurations are the same as in the first embodiment.

The second embodiment also provides the same effects as the first embodiment. Further, in the second embodiment, since the second main surface 2 has a planar shape of a rounded rectangle with four rounded corners, chipping at the four corners in the vicinity of the second main surface 2 can be further suppressed. Furthermore, if the first main surface 1 has a rounded rectangular planar shape with four rounded corners, chipping at the four corners in the vicinity of the first main surface 1 can be further suppressed. Furthermore, stress concentration at the four corners can be alleviated, and cracks due to stress concentration can be suppressed. Furthermore, when silicon carbide semiconductor device 100 is sealed by transfer molding, air bubbles can be more easily discharged from the vicinity of end face 20, and mounting defects due to residual air bubbles can be more easily suppressed.

Next, a method for manufacturing silicon carbide semiconductor device 200 according to the second embodiment will be described. 28 to 29 are plan views showing a method for manufacturing a silicon carbide semiconductor device according to the second embodiment.

First, in the same manner as in the first embodiment, processes from preparing silicon carbide wafer 51 (step S1) to forming insulating film 92 (step S4) are performed. Next, as shown in FIG. 28, an opening 292X is formed in the insulating film 92 to partially expose the bottom surface of the marker 91. In forming the opening 292X, the insulating film 292 is dry-etched using, for example, a photoresist as an etching mask. An etching mask 292Z is formed from the insulating film 92 and includes a covering portion 292Y that covers a part of the first main surface 1 and an opening 292X that exposes the remainder of the first main surface 1. The covering portion 292Y has a planar shape of a rounded rectangle with four rounded corners when viewed in plan from a direction perpendicular to the first main surface 1.

Next, a dicing groove 295 is formed inside the marker 91 in plan view using the etching mask 292Z. Like the dicing groove 95, the dicing groove 295 can be formed by RIE and thermal etching using the etching mask 292Z. Next, the etching mask 292Z is removed from the first main surface 1.

Thereafter, similar to the first embodiment, processes from activation heat treatment (step S8) to peeling of the adhesive tape 96 (step S19) are performed.

In this way, silicon carbide semiconductor device 200 according to the second embodiment is completed.

This manufacturing method also provides the same effects as the first embodiment. Furthermore, since the dicing grooves 295 are formed through thermal etching using an etching mask 292Z that includes a covering portion 292Y having a rounded rectangular planar shape with four rounded corners, the planar shape of the second main surface 2 is , it can be easily formed into a rounded rectangular planar shape with four rounded corners. Further, the planar shape of the first principal surface 1 can also be easily made into a rounded rectangular planar shape with four rounded corners.

Note that it is not necessary that all four corners have a rounded shape, and as long as only one corner has a rounded shape, the above effect can be obtained in that corner.

[Modified example]
Next, a modification of the first embodiment will be described. The modified example differs from the first embodiment mainly in the external shape. FIG. 30 is a cross-sectional view schematically showing a silicon carbide substrate included in a silicon carbide semiconductor device according to a modification of the first embodiment.

As shown in FIG. 30, in silicon carbide semiconductor device 100A according to the modification of the first embodiment, when viewed in plan from a direction perpendicular to first main surface 1, the outline of first main surface 1 is similar to that of second main surface 1. It is located outside the outline of the main surface 2. The inclined surface 21 is inclined so as to become wider toward the first main surface 1 side. That is, the inclined surface 21 is inclined so as to enter inside the second main surface 2 as it approaches the second main surface 2. The angle θ2 between the inclined surface 21 and the second main surface 2 is, for example, 50° or more and 65° or less. The angle θ2 may be, for example, 55° or more. The angle θ2 may be, for example, 60° or less. The inclined surface 21 preferably has a {0-33-8} surface.

The other configurations are the same as in the first embodiment.

Similarly to the first embodiment, the silicon carbide semiconductor device 100A according to the modification of the first embodiment reduces leakage current flowing between the first main surface 1 and the second main surface 2 using the end surface 20 as a path. It is possible to improve heat dissipation.

As a modification of the second embodiment, similarly to the modification of the first embodiment, the inclined surface 21 may be inclined so as to become wider toward the first main surface 1 side.

Although the embodiments have been described in detail above, they are not limited to specific embodiments, and various modifications and changes are possible within the scope of the claims.

1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift region 12 Body region 13 Source region 18 Contact region 20 End surface 21 Inclined surface 22, 23 Surface 40 Silicon carbide epitaxial layer 50 Silicon carbide Single crystal substrate 51 Silicon carbide wafer 52 Chip region 53 Dicing line 55 Third main surface 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Gate pad 85 Passivation film 90 Contact hole 91 marker 92, 292 insulating film 92X, 292X opening 92Y, 292Y covering section 92Z, 292Z etching mask 93 side surface 94 bottom surface 95, 295 dicing groove 96 adhesive tape 100, 100A, 200 silicon carbide semiconductor device

Claims (12)

comprising a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface,
The silicon carbide substrate has an end surface connecting the first main surface and the second main surface,
The end surface is a silicon carbide semiconductor device including an inclined surface continuous from a boundary with the second main surface and inclined with respect to the second main surface. The silicon carbide substrate is
a silicon carbide single crystal substrate including the second main surface;
a silicon carbide epitaxial layer including the first main surface;
The silicon carbide semiconductor device according to claim 1, comprising: The silicon carbide semiconductor device according to claim 1 or 2, wherein the inclined surface is inclined so as to become wider toward the second main surface. The silicon carbide semiconductor device according to claim 1 or 2, wherein the inclined surface is inclined so as to become wider toward the first main surface. The silicon carbide semiconductor device according to claim 3 or 4, wherein the angle between the inclined surface and the second main surface is 50° or more and 65° or less. The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein the inclined surface includes a {0-33-8} plane. The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the surface roughness in a square region of 100 nm on a side of the inclined surface is 1.0 nm or less in RMS. Any one of claims 1 to 7, wherein the second main surface has a rounded rectangular planar shape with at least one rounded corner when viewed in plan from a direction perpendicular to the first main surface. The silicon carbide semiconductor device described in . preparing a silicon carbide wafer having a first main surface and a third main surface opposite to the first main surface, and having a dicing line on the first main surface;
performing thermal etching on the dicing line in an atmosphere containing halogen gas to form a groove on the dicing line;
Thinning the silicon carbide wafer from the third main surface to separate the silicon carbide wafer into pieces;
A method for manufacturing a silicon carbide semiconductor device having the following. 10. The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein the step of dividing the silicon carbide wafer into pieces includes a step of grinding the silicon carbide wafer from the third main surface side. 11. The step of preparing the silicon carbide wafer includes the step of forming a silicon carbide epitaxial layer including the first main surface on a silicon carbide single crystal substrate including the third main surface. A method for manufacturing a silicon carbide semiconductor device according to . The step of thermally etching the dicing line includes etching the first main surface using an etching mask having a covering portion that covers a part of the first main surface and an opening that exposes the remainder of the first main surface. having a step of forming on a surface,
The covering portion has a rounded rectangular planar shape with at least one rounded corner when viewed in plan from a direction perpendicular to the first main surface. The method for manufacturing the silicon carbide semiconductor device described above.

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