WO2022097386A1 - Silicon carbide semiconductor device and method for producing silicon carbide semiconductor device - Google Patents

Silicon carbide semiconductor device and method for producing silicon carbide semiconductor device Download PDF

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Publication number
WO2022097386A1
WO2022097386A1 PCT/JP2021/035303 JP2021035303W WO2022097386A1 WO 2022097386 A1 WO2022097386 A1 WO 2022097386A1 JP 2021035303 W JP2021035303 W JP 2021035303W WO 2022097386 A1 WO2022097386 A1 WO 2022097386A1
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silicon carbide
main surface
semiconductor device
carbide semiconductor
wafer
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PCT/JP2021/035303
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French (fr)
Japanese (ja)
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拓 堀井
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住友電気工業株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.
  • an anisotropic etching is performed on a silicon wafer from the surface of the semiconductor Si wafer to form a step, and then isotropic etching is performed on the entire back surface of the semiconductor Si wafer up to the step.
  • the silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and the silicon carbide substrate is the first main surface and the above. It has an end face that connects to the second main surface, and the end face includes an inclined surface that is continuous from the boundary with the second main surface and is inclined with respect to the second main surface.
  • FIG. 1 is a plan view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing a transistor included in the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 4 is a flowchart showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 5 is a plan view (No. 1) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 6 is a plan view (No. 2) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 1 is a plan view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view showing an outline of a silicon carbide substrate included in the silicon
  • FIG. 7 is a plan view (No. 3) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 8 is a cross-sectional view (No. 1) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 9 is a cross-sectional view (No. 2) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 10 is a cross-sectional view (No. 3) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 11 is a cross-sectional view (No. 4) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 12 is a cross-sectional view (No.
  • FIG. 13 is a cross-sectional view (No. 6) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 14 is a cross-sectional view (No. 7) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 15 is a cross-sectional view (No. 8) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 16 is a cross-sectional view (No. 9) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 17 is a cross-sectional view (No. 10) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 18 is a cross-sectional view (No. 11) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 19 is a cross-sectional view (No. 12) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 20 is a cross-sectional view (No. 13) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 21 is a cross-sectional view (No. 14) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 22 is a cross-sectional view (No. 15) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 23 is a cross-sectional view (No.
  • FIG. 16 shows a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 24 is a cross-sectional view (No. 17) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 25 is a cross-sectional view (No. 18) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 26 is a cross-sectional view (No. 19) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 27 is a plan view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 28 is a plan view (No. 1) showing a method of manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 1 showing a method of manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 29 is a plan view (No. 2) showing a method of manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • FIG. 30 is a cross-sectional view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the modified example of the first embodiment.
  • An object of the present disclosure is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device capable of reducing a leakage current flowing between a front surface and a back surface via an end surface.
  • the leakage current flowing between the front surface and the back surface via the end surface can be reduced.
  • the silicon carbide semiconductor device includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and the silicon carbide substrate is a silicon carbide substrate. It has an end surface connecting the first main surface and the second main surface, and the end surface includes an inclined surface that is continuous from the boundary with the second main surface and is inclined with respect to the second main surface.
  • the silicon carbide semiconductor device can be made thinner than the silicon-based semiconductor device.
  • the distance between the two main surfaces is short, and a leak current may flow between the two main surfaces.
  • the silicon carbide semiconductor device according to one aspect of the present disclosure since the end face includes an inclined surface, the leakage current is higher than the case where the end face is perpendicular to the first main surface and the second main surface. Can lengthen the flow path. Therefore, it is possible to reduce the leakage current flowing between the first main surface and the second main surface using the end surface as a path.
  • the silicon carbide substrate may have a silicon carbide single crystal substrate including the second main surface and a silicon carbide epitaxial layer including the first main surface.
  • the crystallinity of the silicon carbide epitaxial layer is good, and it is easy to obtain excellent characteristics.
  • the internal angle of the angle formed by the inclined surface and the second main surface may be an acute angle in a cross-sectional view.
  • the solder easily rises to the inclined surface and good bonding strength can be easily obtained.
  • the silicon carbide semiconductor device is sealed by the transfer mold, bubbles are easily discharged from the vicinity of the end face, and mounting defects due to residual bubbles are easily suppressed.
  • the internal angle of the angle formed by the inclined surface and the second main surface may be an obtuse angle in a cross-sectional view. In this case as well, the effects of reducing the leakage current and improving the heat dissipation can be obtained.
  • the angle between the inclined surface and the second main surface may be 50 ° or more and 65 ° or less. In this case, it is easy to obtain good crystallinity on the inclined surface.
  • the inclined surface may include a ⁇ 0-33-8 ⁇ surface. In this case, it is easy to obtain good crystallinity on the inclined surface.
  • the surface roughness in the square region having a side of 100 nm on the inclined surface may be 1.0 nm or less in RMS. In this case, it is easy to suppress chipping.
  • the second main surface when viewed in a plan view from a direction perpendicular to the first main surface, has a rectangular planar shape with at least one rounded corner. You may have. In this case, it is easy to relax the stress concentration at the corners in the planar shape.
  • the method for manufacturing a silicon carbide semiconductor device has a first main surface and a third main surface opposite to the first main surface, and the first main surface.
  • the inclined surface according to [1] can be easily formed.
  • the step of individualizing the silicon carbide wafer may include a step of grinding the silicon carbide wafer from the third main surface side. In this case, since grinding is performed after the groove is formed, the pressure applied to the silicon carbide wafer can be easily dispersed.
  • the silicon carbide epitaxial layer containing the first main surface is placed on the silicon carbide single crystal substrate including the third main surface. It may have a step of forming. In this case, the crystallinity of the silicon carbide epitaxial layer is good, and it is easy to obtain excellent characteristics.
  • the step of performing thermal etching on the dicing line is an opening that exposes a covering portion that covers a part of the first main surface and an opening that exposes the rest of the first main surface.
  • the covering portion has at least one corner rounded when the etching mask including the portion is formed on the first main surface and is viewed in a plan view from a direction perpendicular to the first main surface. It may have a planar shape with rounded corners. In this case, it is easy to relax the stress concentration at the corners in the planar shape.
  • FIG. 1 is a plan view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 3 is a cross-sectional view showing a transistor included in the silicon carbide semiconductor device according to the first embodiment.
  • FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG.
  • the silicon carbide semiconductor device 100 includes a silicon carbide substrate 10, and the silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide single crystal substrate 50. Includes the silicon carbide epitaxial layer 40 above.
  • the silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1.
  • the silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2.
  • the silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, polytype 4H hexagonal silicon carbide.
  • the silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen (N) and has an n-type (first conductive type).
  • a semiconductor element is formed on the silicon carbide substrate 10.
  • the distance L1 between the first main surface 1 and the second main surface 2, that is, the thickness of the silicon carbide substrate 10 is about 50 ⁇ m or more and 200 ⁇ m or less.
  • the first main surface 1 is a surface on which the ⁇ 0001 ⁇ surface or the ⁇ 0001 ⁇ surface is inclined by an off angle of 8 ° or less in the off direction.
  • the first main surface 1 is a surface on which the (000-1) surface or the (000-1) surface is inclined by an off angle of 8 ° or less in the off direction.
  • the off direction may be, for example, the ⁇ 11-20> direction or the ⁇ 1-100> direction.
  • the off angle may be, for example, 1 ° or more, or 2 ° or more.
  • the off angle may be 6 ° or less, or 4 ° or less.
  • the silicon carbide substrate 10 has a rectangular planar shape. That is, the planar shape of the silicon carbide substrate 10 includes two sides extending parallel to the first direction and two sides extending in the second direction perpendicular to the first direction. As shown in FIG. 2, the silicon carbide substrate 10 has an end surface 20 connecting the first main surface 1 and the second main surface 2 at each of the positions corresponding to these four sides. The end surface 20 has an inclined surface 21 that is continuous from the boundary with the second main surface 2 and is inclined with respect to the second main surface 2. In the present embodiment, the contour of the first main surface 1 is inside the contour of the second main surface 2 when viewed in a plan view from a direction perpendicular to the first main surface 1.
  • the inclined surface 21 is inclined so as to expand toward the second main surface 2 side. That is, in the cross-sectional view, the internal angle of the angle formed by the inclined surface 21 and the second main surface 2 is an acute angle, and the inclined surface 21 enters the inside of the first main surface 1 as it approaches the first main surface 1. Is inclined to.
  • the angle ⁇ 1 formed by the inclined surface 21 and the second main surface 2 is, for example, 50 ° or more and 65 ° or less.
  • the angle ⁇ 1 may be, for example, 55 ° or more.
  • the angle ⁇ 1 may be, for example, 60 ° or less.
  • the inclined surface 21 preferably has a ⁇ 0-33-8 ⁇ surface. When the angle ⁇ 1 is 50 ° or more and 65 ° or less, good crystallinity can be easily obtained on the inclined surface 21.
  • the angle ⁇ 1 does not have to be common among the four inclined surfaces 21.
  • two inclined surfaces 21 provided at positions corresponding to sides parallel to the first direction have ⁇ 0-33-8 ⁇ planes and are provided at positions corresponding to sides parallel to the second direction.
  • the two inclined planes 21 may have a crystal plane different from the ⁇ 0-33-8 ⁇ plane.
  • the inclined surface 21 has a ⁇ 0-33-8 ⁇ surface, it is easy to obtain a good crystal plane on the inclined surface 21.
  • the end surface 20 may have a surface 23 continuous from the boundary with the first main surface 1 and a surface 22 connecting the inclined surface 21 and the surface 23.
  • the surface 23 may be substantially perpendicular to the first main surface 1 and the surface 22 may be substantially parallel to the first main surface 1 and the second main surface 2.
  • the distance L2 between the first main surface 1 and the surface 22 is about 0.5 ⁇ m or more and 1.0 ⁇ m or less, which is extremely small as compared with the distance L1.
  • a MOSFET is formed on the silicon carbide substrate 10 as an example of a semiconductor element.
  • the silicon carbide epitaxial layer 40 mainly has a drift region 11, a body region 12, a source region 13, and a contact region 18.
  • the drift region 11 has an n-type due to the addition of an n-type impurity such as nitrogen or phosphorus (P). It is preferable that the n-type impurities are added to the drift region 11 not by ion implantation but by adding impurities at the time of epitaxial growth of the drift region 11.
  • an n-type impurity such as nitrogen or phosphorus (P). It is preferable that the n-type impurities are added to the drift region 11 not by ion implantation but by adding impurities at the time of epitaxial growth of the drift region 11.
  • the body region 12 is provided on the drift region 11.
  • the body region 12 has a p-type (second conductive type) due to the addition of a p-type impurity such as aluminum (Al).
  • the source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12.
  • the source region 13 has an n-type due to the addition of an n-type impurity such as nitrogen or phosphorus.
  • the source region 13 constitutes the first main surface 1.
  • the contact region 18 has a p-type due to the addition of a p-type impurity such as aluminum.
  • the contact area 18 constitutes the first main surface 1.
  • the contact region 18 penetrates the source region 13 and touches the body region 12.
  • a plurality of gate trenches 5 are provided on the first main surface 1.
  • the gate trench 5 extends in the first direction parallel to, for example, the first main surface 1, and a plurality of gate trenches 5 are arranged in the second direction.
  • the gate trench 5 has a bottom surface 4 composed of a drift region 11.
  • the gate trench 5 has a side surface 3 that penetrates the source region 13 and the body region 12 and is connected to the bottom surface 4.
  • the bottom surface 4 is, for example, a plane parallel to the second main surface 2.
  • the angle of the side surface 3 with respect to the plane including the bottom surface 4 is, for example, 50 ° or more and 65 ° or less. This angle may be, for example, 55 ° or more. This angle may be, for example, 60 ° or less.
  • the side surface 3 preferably has a ⁇ 0-33-8 ⁇ surface.
  • the ⁇ 0-33-8 ⁇ plane is a crystal plane from which excellent mobility can be obtained.
  • a gate insulating film 81 in contact with the side surface 3 and the bottom surface 4 is provided.
  • the gate insulating film 81 is, for example, an oxide film.
  • the gate insulating film 81 is made of, for example, a material containing silicon dioxide.
  • the gate insulating film 81 is in contact with the drift region 11 on the bottom surface 4.
  • the gate insulating film 81 is in contact with each of the source region 13, the body region 12, and the drift region 11 on the side surface 3.
  • the gate insulating film 81 may be in contact with the source region 13 on the first main surface 1.
  • a gate electrode 82 is provided on the gate insulating film 81.
  • the gate electrode 82 is made of, for example, polysilicon (polySi) containing a conductive impurity.
  • the gate electrode 82 is arranged inside the gate trench 5.
  • the interlayer insulating film 83 in contact with the gate electrode 82 and the gate insulating film 81 is provided.
  • the interlayer insulating film 83 is made of a material containing, for example, silicon dioxide.
  • the interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60.
  • Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the second direction.
  • the contact hole 90 is provided so that the gate trench 5 is located between the contact holes 90 adjacent to each other in the second direction.
  • the contact hole 90 extends in the first direction. Through the contact hole 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.
  • a source electrode 60 in contact with the first main surface 1 is provided.
  • the source electrode 60 has a contact electrode 61 provided in the contact hole 90 and a source wiring 62.
  • the contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1.
  • the contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi).
  • the contact electrode 61 may be made of a material containing titanium (Ti), Al, and Si.
  • the contact electrode 61 is ohmic contacted with the source region 13 and the contact region 18.
  • the source wiring 62 is made of, for example, a material containing Al.
  • a passivation film 84 is provided to cover the upper surface of the source wiring 62.
  • the passivation film 84 is in contact with the source wiring 62.
  • the passivation film 84 is made of a material containing, for example, polyimide.
  • a drain electrode 70 in contact with the second main surface 2 is provided.
  • the drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 on the second main surface 2.
  • the drain electrode 70 is electrically connected to the drift region 11.
  • the drain electrode 70 is made of a material containing, for example, NiSi.
  • the drain electrode 70 may be made of a material containing Ti, Al, and Si.
  • the drain electrode 70 is ohmic-bonded to the silicon carbide single crystal substrate 50.
  • the end surface 20 since the end surface 20 includes the inclined surface 21, the path through which the leak current flows can be made longer than when the end surface 20 is perpendicular to the first main surface 1 and the second main surface 2. Therefore, it is possible to reduce the leakage current flowing between the first main surface 1 and the second main surface 2 with the end surface 20 as a path. Further, since the area of the end surface 20 is larger than that in the case where the end surface 20 is perpendicular to the first main surface 1 and the second main surface 2, heat dissipation can be improved.
  • the silicon carbide substrate 10 has a silicon carbide single crystal substrate 50 including the second main surface 2 and a silicon carbide epitaxial layer 40 including the first main surface 1. That is, the silicon carbide substrate 10 is a so-called epitaxial substrate. Therefore, the crystallinity of the silicon carbide epitaxial layer 40 is good, and it is easy to obtain excellent properties.
  • the internal angle of the angle formed by the inclined surface 21 and the second main surface 2 is an acute angle. Therefore, when the drain electrode 70 is connected to the conductive layer or the like formed on the surface of the insulating substrate via solder, the molten solder easily rises to the inclined surface 21 and is between the drain electrode 70 and the conductive layer or the like. It is easy to obtain good bonding strength. Further, when the silicon carbide semiconductor device 100 is sealed by the transfer mold, bubbles are easily discharged from the vicinity of the end face 20, and mounting defects due to residual bubbles are easily suppressed.
  • the surface roughness of the inclined surface 21 is preferably 1.0 nm or less in RMS, and more preferably 0.8 nm or less in a microscopic range such as that calculated in a square region having a side of 100 nm. This is to suppress chipping in the silicon carbide semiconductor device 100.
  • Such microscopic surface roughness can be measured using, for example, an atomic force microscope (AFM).
  • the inclined surface 21 preferably has a ⁇ 0-33-8 ⁇ plane, but may have a specific crystal plane of silicon carbide different from the ⁇ 0-33-8 ⁇ plane.
  • having a ⁇ 0-33-8 ⁇ plane means that the plane orientation is substantially within the range of an off angle that can be regarded as ⁇ 0-33-8 ⁇ in consideration of the machining accuracy of the inclined surface 21 and the like. It means that the plane orientation of the inclined surface 21 is included.
  • the off-angle range in this case is, for example, a range in which the off-angle is ⁇ 2 ° with respect to ⁇ 0-33-8 ⁇ .
  • the angle between the off-direction of the inclined surface 21 and the ⁇ 01-10> direction may be 5 ° or less.
  • the off-direction becomes substantially the ⁇ 01-10> direction, and as a result, the plane orientation of the inclined surface 21 becomes close to the ⁇ 0-33-8 ⁇ plane.
  • the off angle of the inclined surface 21 with respect to the ⁇ 0-33-8 ⁇ surface in the ⁇ 01-10> direction may be -3 ° or more and 5 ° or less.
  • the "off angle with respect to the ⁇ 0-33-8 ⁇ plane in the ⁇ 01-10> direction" is the orthogonal projection of the normal of the inclined surface 21 onto the plane including the ⁇ 01-10> direction and the ⁇ 0001> direction. This is the angle formed by the normal of the ⁇ 0-33-8 ⁇ plane. The sign of the angle is positive when the orthogonal projection approaches parallel to the ⁇ 01-10> direction, and negative when the orthogonal projection approaches parallel to the ⁇ 0001> direction.
  • the gate trench 5 may be a vertical trench. That is, the angle of the side surface 3 with respect to the plane including the bottom surface 4 may be 90 °. Further, a transistor that does not include the gate trench 5 may be formed on the silicon carbide substrate 10. Further, the semiconductor element formed on the silicon carbide substrate 10 is not limited to a transistor such as a MOSFET, and another semiconductor element such as a Schottky barrier diode may be formed on the silicon carbide substrate 10.
  • FIG. 4 is a flowchart showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • 5 to 7 are plan views showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment.
  • 8 to 26 are cross-sectional views showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 17 to 26 show changes in the cross section shown in FIG.
  • the silicon carbide single crystal substrate 50 is prepared as shown in FIGS. 8 and 17.
  • a silicon carbide single crystal substrate 50 is prepared by slicing a silicon carbide ingot (not shown) manufactured by a sublimation method.
  • a buffer layer (not shown) may be formed on the silicon carbide single crystal substrate 50.
  • the buffer layer uses, for example, a mixed gas of silane (SiH 4 ) and propane (C 3 H 8 ) as a raw material gas, and chemical vapor deposition (CVD: CVD) using, for example, hydrogen (H 2 ) as a carrier gas. ) Can be formed by the method.
  • n-type impurities such as nitrogen may be introduced into the buffer layer.
  • the silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50.
  • a silicon carbide epitaxial layer 40 is formed on a silicon carbide single crystal substrate 50 by a CVD method using a mixed gas of silane and propane as a raw material gas and, for example, hydrogen as a carrier gas.
  • n-type impurities such as nitrogen are introduced into the silicon carbide epitaxial layer 40.
  • the silicon carbide epitaxial layer 40 has an n-type conductive type. In this way, the silicon carbide wafer 51 provided with the silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 is prepared.
  • the silicon carbide wafer 51 has a first main surface 1 and a third main surface 55 opposite to the first main surface 1.
  • the distance L3 between the first main surface 1 and the third main surface 55, that is, the thickness of the silicon carbide wafer 51 is larger than the thickness of the silicon carbide semiconductor device 100, and is, for example, about 350 ⁇ m or more and 500 ⁇ m or less.
  • step S2 the marker 91 is formed on the first main surface 1.
  • a chip region 52 on which the silicon carbide semiconductor device 100 is to be formed and an adjacent chip region 52 are formed on the first main surface 1 of the silicon carbide wafer 51.
  • a dicing line 53 to be separated is set.
  • the silicon carbide epitaxial layer 40 is etched using, for example, a photoresist as an etching mask.
  • the etching method for example, reactive ion etching (RIE), particularly Inductive Coupled Plasma (ICP) RIE can be used.
  • ICP-RIE using SF 6 or a mixed gas of SF 6 and O 2 can be used as the reaction gas.
  • the width of the marker 91 is about 10 ⁇ m
  • the depth is equal to the distance L2, and is about 0.5 ⁇ m or more and 1.0 ⁇ m or less.
  • ion implantation into the silicon carbide epitaxial layer 40 is performed.
  • ion implantation forms a body region 12, a source region 13, and a contact region 18.
  • the rest of the silicon carbide epitaxial layer 40 functions as the drift region 11.
  • p-type impurities such as aluminum (Al) are ion-implanted.
  • n-type impurities such as phosphorus (P) are ion-implanted.
  • the insulating film 92 is formed on the surface of the silicon carbide epitaxial layer 40 by thermally oxidizing the surface of the silicon carbide epitaxial layer 40.
  • the insulating film 92 is made of a material containing, for example, silicon dioxide.
  • an opening 92X that partially exposes the bottom surface of the marker 91 is formed in the insulating film 92.
  • the opening 92X for example, dry etching of the insulating film 92 using a photoresist as an etching mask is performed.
  • an etching mask 92Z having a covering portion 92Y that covers a part of the first main surface 1 and an opening 92X that exposes the rest of the first main surface 1 is formed.
  • the covering portion 92Y has a rectangular planar shape when viewed in a plan view from a direction perpendicular to the first main surface 1.
  • a dicing groove 95 is formed inside the marker 91 in a plan view using the etching mask 92Z.
  • RIE such as ICP-RIE.
  • ICP-RIE using SF 6 or a mixed gas of SF 6 and O 2 can be used as the reaction gas.
  • the silicon carbide wafer 51 is thermally etched on the inner surface of the recess using the etching mask 92Z.
  • Thermal etching can be performed, for example, by heating the silicon carbide wafer 51 in an atmosphere containing a halogen-based reactive gas having at least one kind of halogen atom.
  • At least one kind of halogen atom contains at least one of a chlorine (Cl) atom and a fluorine (F) atom.
  • This atmosphere is, for example, Cl 2 , BCl 3 , SF 6 , or CF 4 .
  • heat etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and setting the heat treatment temperature to, for example, 700 ° C. or higher and 1000 ° C.
  • the reaction gas may contain a carrier gas in addition to the chlorine gas and the oxygen gas.
  • a carrier gas for example, nitrogen (N 2 ) gas, argon gas, helium gas and the like can be used.
  • the etching rate of SiC is, for example, about 70 ⁇ m / hour. Since the insulating film 92 made of a material containing silicon dioxide used as an etching mask has an extremely large selectivity with respect to silicon carbide, it is not substantially etched during etching of silicon carbide.
  • a dicing groove 95 having a side surface 93 and a bottom surface 94 is formed on the silicon carbide wafer 51.
  • the silicon carbide wafer 51 is etched so as to be side-etched from the opening 92X.
  • the ⁇ 0-33-8 ⁇ plane which is the crystal plane having the slowest etching rate, is self-formed as the side surface 93 of the dicing groove 95.
  • the distance L4 between the bottom surface 94 of the dicing groove 95 and the bottom surface of the marker 91 is, for example, about 50 ⁇ m or more and 200 ⁇ m or less.
  • the distance between the first main surface 1 and the bottom surface 94 of the dicing groove 95 is equal to the sum of the distance L2 and the distance L4, and the first main surface 1 and the second main surface 2 in the silicon carbide semiconductor device 100 to be manufactured are equal to each other.
  • step S7 the etching mask 92Z is removed from the first main surface 1 as shown in FIG.
  • step S8 an activation heat treatment for activating impurities added by ion implantation is performed.
  • the temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C.
  • the heat treatment time is, for example, about 30 minutes.
  • the atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an Ar atmosphere.
  • the gate trench 5 is formed on the silicon carbide wafer 51 as shown in FIG. Similar to the dicing groove 95, the gate trench 5 can be formed by RIE and thermal etching using an insulating film made of a material containing silicon dioxide having an opening formed as an etching mask. During thermal etching, the ⁇ 0-33-8 ⁇ surface is self-formed as the side surface 3.
  • step S10 the gate insulating film 81 is formed as shown in FIG.
  • a gate insulating film 81 in contact with the source region 13, the body region 12, the drift region 11, and the contact region 18 is formed.
  • the silicon carbide wafer 51 is heated at a temperature of, for example, 1300 ° C. or higher and 1400 ° C. or lower in an atmosphere containing oxygen.
  • the first main surface 1 and the gate insulating film 81 in contact with the side surface 3 and the bottom surface 4 are formed.
  • heat treatment may be performed on the silicon carbide wafer 51 in a nitric oxide (NO) gas atmosphere.
  • NO nitric oxide
  • the silicon carbide wafer 51 is held for about 1 hour under the condition of, for example, 1100 ° C. or higher and 1400 ° C. or lower.
  • nitrogen atoms are introduced into the interface region between the gate insulating film 81 and the body region 12.
  • the formation of the interface state in the interface region is suppressed, so that the channel mobility can be improved.
  • the gate electrode 82 is formed as shown in FIG.
  • the gate electrode 82 is formed on the gate insulating film 81.
  • the gate electrode 82 is formed by, for example, a reduced pressure CVD (Low Pressure-Chemical Vapor Deposition: LP-CVD) method.
  • the gate electrode 82 is formed so as to face each of the source region 13, the body region 12, and the drift region 11.
  • the interlayer insulating film 83 is formed as shown in FIG. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and contact the gate insulating film 81.
  • the interlayer insulating film 83 is formed by, for example, a CVD method.
  • the interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.
  • step S13 as shown in FIG. 23, the interlayer insulating film 83 and the gate insulating film 81 are etched to form the contact hole 90 in the interlayer insulating film 83 and the gate insulating film 81. As a result, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.
  • a metal film (not shown) for the contact electrode 61 in contact with the source region 13 and the contact region 18 is formed on the first main surface 1.
  • the metal film for the contact electrode 61 is formed by, for example, a sputtering method.
  • the metal film for the contact electrode 61 is made of, for example, a material containing Ni. Next, alloying annealing is performed.
  • the metal film for the contact electrode 61 is held at a temperature of, for example, 900 ° C. or higher and 1100 ° C. or lower for about 5 minutes. As a result, at least a part of the metal film for the contact electrode 61 reacts with the silicon contained in the silicon carbide wafer 51 to silicide. As a result, the contact electrode 61 that ohmic-bonds with the source region 13 and the contact region 18 is formed.
  • the contact electrode 61 may be made of a material containing Ti, Al, and Si.
  • the source wiring 62 is formed as shown in FIG. 24. Specifically, the source wiring 62 that covers the contact electrode 61 and the interlayer insulating film 83 is formed.
  • the source wiring 62 is formed by, for example, film formation by a sputtering method and RIE.
  • the source wiring 62 is made of a material containing, for example, aluminum. In this way, the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.
  • the passivation film 84 is formed as shown in FIG. 25. Specifically, a passivation film 84 that covers the source wiring 62 is formed.
  • the passivation film 84 is made of a material containing, for example, polyimide.
  • the passivation film 84 is formed, for example, by a coating method.
  • the passivation film 84 may be formed by a plasma CVD method.
  • step S16 as shown in FIG. 13, the adhesive tape 96 is attached onto the passivation film 85.
  • the passivation film 84 and the like formed on the first main surface 1 of the silicon carbide wafer 51 are not shown.
  • step S17 the back grind of the silicon carbide wafer 51 is performed. Specifically, the silicon carbide wafer 51 is thinned by grinding from the third main surface 55 side. The silicon carbide wafer 51 is polished until the thickness of the silicon carbide wafer 51 becomes equal to the distance L2 between the first main surface 1 and the second main surface 2 in the silicon carbide semiconductor device 100. Since the distance between the first main surface 1 and the bottom surface 94 of the dicing groove 95 is larger than the distance L2 between the first main surface 1 and the second main surface 2, the result of polishing the third main surface 55 is shown in FIG. As shown in 7 and 14, the silicon carbide wafer 51 is separated into individual pieces for each chip region 52. As a result, the silicon carbide substrate 10 having the first main surface 1 and the second main surface 2 is formed for each chip region 52.
  • step S18 as shown in FIGS. 15 and 26, a drain electrode 70 in contact with the silicon carbide single crystal substrate 50 is formed on the second main surface 2.
  • the silicon carbide semiconductor device 100 is formed in each chip region 52.
  • the side surface 3 of the dicing groove 95 is the inclined surface 21, the side surface of the marker 91 is the surface 23, and the bottom surface of the marker 91 is the surface 22.
  • step S19 as shown in FIG. 16, the adhesive tape 96 is peeled off from the silicon carbide semiconductor device 100.
  • the silicon carbide semiconductor device 100 according to the first embodiment is completed.
  • the dicing line 53 is thermally etched in an atmosphere containing halogen gas to form a dicing groove 95 in the dicing line 53, and the silicon carbide wafer 51 is thinned from the third main surface 55 side to form silicon carbide.
  • the wafer 51 is individualized. Therefore, the side surface 93 of the dicing groove 95 can be an inclined surface inclined with respect to the third main surface 55, and this inclined surface becomes the inclined surface 21. Therefore, the end surface 20 provided with the inclined surface 21 can be easily formed.
  • the inclined surface 21 is formed by thermal etching, mechanical damage is unlikely to occur in the inclined surface 21 and its vicinity, and defects such as chipping are unlikely to occur. Therefore, the mechanical strength of the silicon carbide semiconductor device 100 is high, and the reliability can be improved.
  • the surface roughness of the inclined surface 21 is likely to be 1.0 nm or less in RMS in a microscopic range such as that calculated in a square region having a side of 100 nm.
  • the silicon carbide wafer 51 is separated into individual pieces for each chip region 52. Therefore, as compared with the case where the wafer is fragmented by using a dicer or the like after back grinding, the pressure acting on the silicon carbide substrate 10 can be dispersed and cracks during machining can be reduced.
  • the thermal etching may be stopped before the inclined surface 21 becomes a ⁇ 0-33-8 ⁇ surface. That is, the inclined surface 21 does not have to be a ⁇ 0-33-8 ⁇ surface.
  • FIG. 27 is a plan view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the second embodiment.
  • the second main surface 2 has four corners rounded when viewed in a plan view from a direction perpendicular to the first main surface 1. It has a rectangular planar shape with rounded corners. When viewed in a plan view from a direction perpendicular to the first main surface 1, the first main surface 1 may have a planar shape with rounded corners having four rounded corners.
  • the second embodiment since the second main surface 2 has a rectangular planar shape with rounded corners, chipping at the four corners can be further suppressed in the vicinity of the second main surface 2. Further, if the first main surface 1 has a rectangular planar shape with rounded corners, chipping at the four corners can be further suppressed in the vicinity of the first main surface 1. In addition, stress concentration at the four corners can be relaxed and cracks due to stress concentration can be suppressed. Further, when the silicon carbide semiconductor device 100 is sealed by the transfer mold, it is easier to discharge bubbles from the vicinity of the end face 20, and it is easier to suppress mounting defects due to residual bubbles.
  • 28 to 29 are plan views showing a method of manufacturing the silicon carbide semiconductor device according to the second embodiment.
  • the processes from the preparation of the silicon carbide wafer 51 (step S1) to the formation of the insulating film 92 (step S4) are performed.
  • the insulating film 92 is formed with an opening 292X that partially exposes the bottom surface of the marker 91.
  • the opening 292X for example, dry etching of the insulating film 292 using a photoresist as an etching mask is performed.
  • an etching mask 292Z having a covering portion 292Y that covers a part of the first main surface 1 and an opening portion 292X that exposes the rest of the first main surface 1 is formed.
  • the covering portion 292Y has a rectangular planar shape with rounded corners when viewed in a plan view from a direction perpendicular to the first main surface 1.
  • a dicing groove 295 is formed inside the marker 91 in a plan view.
  • the dicing groove 295 can be formed by RIE and thermal etching using the etching mask 292Z, similarly to the dicing groove 95.
  • the etching mask 292Z is removed from the first main surface 1.
  • step S8 the treatment from the activation heat treatment (step S8) to the peeling of the adhesive tape 96 (step S19) is performed as in the first embodiment.
  • the silicon carbide semiconductor device 200 according to the second embodiment is completed.
  • the same effect as that of the first embodiment can be obtained by this manufacturing method.
  • the dicing groove 295 is formed through thermal etching using an etching mask 292Z including a covering portion 292Y having a rectangular planar shape with rounded corners
  • the planar shape of the second main surface 2 is formed.
  • the planar shape of the first main surface 1 can be easily changed to a rectangular planar shape with rounded corners.
  • FIG. 30 is a cross-sectional view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the modified example of the first embodiment.
  • the contour of the first main surface 1 is the second when viewed in a plan view from the direction perpendicular to the first main surface 1. It is outside the contour of the main surface 2.
  • the inclined surface 21 is inclined so as to expand toward the first main surface 1 side. That is, in the cross-sectional view, the internal angle of the angle formed by the inclined surface 21 and the second main surface 2 is an obtuse angle, and the inclined surface 21 enters the inside of the second main surface 2 as it approaches the second main surface 2. Is inclined to.
  • the angle ⁇ 2 formed by the inclined surface 21 and the second main surface 2 is, for example, 50 ° or more and 65 ° or less.
  • the angle ⁇ 2 may be, for example, 55 ° or more.
  • the angle ⁇ 2 may be, for example, 60 ° or less.
  • the inclined surface 21 preferably has a ⁇ 0-33-8 ⁇ surface.
  • the silicon carbide semiconductor device 100A according to the modified example of the first embodiment also reduces the leakage current flowing between the first main surface 1 and the second main surface 2 with the end surface 20 as a path. It can improve heat dissipation.
  • the inclined surface 21 may be inclined so as to expand toward the first main surface 1 side as in the modification of the first embodiment. That is, in the cross-sectional view, the internal angle of the angle formed by the inclined surface 21 and the second main surface 2 may be an obtuse angle.

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Abstract

This silicon carbide semiconductor device is provided with a silicon carbide substrate which has a first main surface and a second main surface that is on the reverse side of the first main surface. The silicon carbide substrate has an end face which connects the first main surface and the second main surface to each other; and the end face comprises an inclined surface which is inclined to the second main surface, while being continued from the boundary with the second main surface.

Description

炭化珪素半導体装置及び炭化珪素半導体装置の製造方法Silicon Carbide Semiconductor Device and Method for Manufacturing Silicon Carbide Semiconductor Device
　本開示は、炭化珪素半導体装置及び炭化珪素半導体装置の製造方法に関する。 The present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.
　本出願は、２０２０年１１月６日出願の日本出願第２０２０－１８５８４９号に基づく優先権を主張し、前記日本出願に記載された全ての記載内容を援用するものである。 This application claims priority based on Japanese Application No. 2020-185849 filed on November 6, 2020, and incorporates all the contents described in the Japanese application.
　半導体Ｓｉウェハの表面からスクライブラインに対し異方性エッチングを行って段差を形成し、その後に半導体Ｓｉウェハの裏面全体に対して段差まで等方性エッチングを行う半導体Ｓｉウェハのチップ化方法が開示されている（例えば、特許文献１）。 Disclosed is a method for forming a chip of a semiconductor Si wafer, in which an anisotropic etching is performed on a silicon wafer from the surface of the semiconductor Si wafer to form a step, and then isotropic etching is performed on the entire back surface of the semiconductor Si wafer up to the step. (For example, Patent Document 1).
日本国特開２００６－３２４８６号公報Japanese Patent Application Laid-Open No. 2006-32486
　本開示の炭化珪素半導体装置は、第１主面と、前記第１主面と反対側の第２主面とを有する炭化珪素基板を備え、前記炭化珪素基板は、前記第１主面と前記第２主面とをつなぐ端面を有し、前記端面は、前記第２主面との境界から連続し、前記第２主面に対して傾斜した傾斜面を含む。 The silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and the silicon carbide substrate is the first main surface and the above. It has an end face that connects to the second main surface, and the end face includes an inclined surface that is continuous from the boundary with the second main surface and is inclined with respect to the second main surface.
図１は、第１実施形態に係る炭化珪素半導体装置に含まれる炭化珪素基板の概要を示す平面図である。FIG. 1 is a plan view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the first embodiment. 図２は、第１実施形態に係る炭化珪素半導体装置に含まれる炭化珪素基板の概要を示す断面図である。FIG. 2 is a cross-sectional view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the first embodiment. 図３は、第１実施形態に係る炭化珪素半導体装置に含まれるトランジスタを示す断面図である。FIG. 3 is a cross-sectional view showing a transistor included in the silicon carbide semiconductor device according to the first embodiment. 図４は、第１実施形態に係る炭化珪素半導体装置の製造方法を示すフローチャートである。FIG. 4 is a flowchart showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図５は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す平面図（その１）である。FIG. 5 is a plan view (No. 1) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図６は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す平面図（その２）である。FIG. 6 is a plan view (No. 2) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図７は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す平面図（その３）である。FIG. 7 is a plan view (No. 3) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図８は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その１）である。FIG. 8 is a cross-sectional view (No. 1) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図９は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その２）である。FIG. 9 is a cross-sectional view (No. 2) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図１０は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その３）である。FIG. 10 is a cross-sectional view (No. 3) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図１１は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その４）である。FIG. 11 is a cross-sectional view (No. 4) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図１２は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その５）である。FIG. 12 is a cross-sectional view (No. 5) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図１３は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その６）である。FIG. 13 is a cross-sectional view (No. 6) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図１４は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その７）である。FIG. 14 is a cross-sectional view (No. 7) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図１５は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その８）である。FIG. 15 is a cross-sectional view (No. 8) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図１６は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その９）である。FIG. 16 is a cross-sectional view (No. 9) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図１７は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その１０）である。FIG. 17 is a cross-sectional view (No. 10) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図１８は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その１１）である。FIG. 18 is a cross-sectional view (No. 11) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図１９は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その１２）である。FIG. 19 is a cross-sectional view (No. 12) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図２０は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その１３）である。FIG. 20 is a cross-sectional view (No. 13) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図２１は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その１４）である。FIG. 21 is a cross-sectional view (No. 14) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図２２は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その１５）である。FIG. 22 is a cross-sectional view (No. 15) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図２３は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その１６）である。FIG. 23 is a cross-sectional view (No. 16) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図２４は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その１７）である。FIG. 24 is a cross-sectional view (No. 17) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図２５は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その１８）である。FIG. 25 is a cross-sectional view (No. 18) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図２６は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図（その１９）である。FIG. 26 is a cross-sectional view (No. 19) showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 図２７は、第２実施形態に係る炭化珪素半導体装置に含まれる炭化珪素基板の概要を示す平面図である。FIG. 27 is a plan view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the second embodiment. 図２８は、第２実施形態に係る炭化珪素半導体装置の製造方法を示す平面図（その１）である。FIG. 28 is a plan view (No. 1) showing a method of manufacturing the silicon carbide semiconductor device according to the second embodiment. 図２９は、第２実施形態に係る炭化珪素半導体装置の製造方法を示す平面図（その２）である。FIG. 29 is a plan view (No. 2) showing a method of manufacturing the silicon carbide semiconductor device according to the second embodiment. 図３０は、第１実施形態の変形例に係る炭化珪素半導体装置に含まれる炭化珪素基板の概要を示す断面図である。FIG. 30 is a cross-sectional view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the modified example of the first embodiment.
　［本開示が解決しようとする課題］
　特許文献１に記載の方法に準じて炭化珪素半導体装置を製造すると、端面を経由して表面と裏面との間をリーク電流が流れるおそれがある。 [Problems to be solved by this disclosure]
When a silicon carbide semiconductor device is manufactured according to the method described in Patent Document 1, a leakage current may flow between the front surface and the back surface via the end surface.
　本開示は、端面を経由して表面と裏面との間を流れるリーク電流を低減できる炭化珪素半導体装置及び炭化珪素半導体装置の製造方法を提供することを目的とする。 An object of the present disclosure is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device capable of reducing a leakage current flowing between a front surface and a back surface via an end surface.
　［本開示の効果］
　本開示によれば、端面を経由して表面と裏面との間を流れるリーク電流を低減できる。 [Effect of this disclosure]
According to the present disclosure, the leakage current flowing between the front surface and the back surface via the end surface can be reduced.
　実施するための形態について、以下に説明する。 The form for implementation will be explained below.
　［本開示の実施形態の説明］
　最初に本開示の実施態様を列記して説明する。以下の説明では、同一または対応する要素には同一の符号を付し、それらについて同じ説明は繰り返さない。本明細書中の結晶学的記載においては、個別方位を［］、集合方位を＜＞、個別面を（）、集合面を｛｝でそれぞれ示している。また結晶学上の指数が負であることは、通常、”－”（バー）を数字の上に付すことによって表現されるが、本明細書中では数字の前に負の符号を付している。 [Explanation of Embodiments of the present disclosure]
First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are designated by the same reference numerals, and the same description is not repeated for them. In the crystallographic description in the present specification, the individual orientation is indicated by [], the aggregate orientation is indicated by <>, the individual plane is indicated by (), and the aggregate plane is indicated by {}. Negative crystallographic exponents are usually expressed by adding a "-" (bar) above the number, but in the present specification, the number is preceded by a negative sign. There is.
　〔１〕　本開示の一態様に係る炭化珪素半導体装置は、第１主面と、前記第１主面と反対側の第２主面とを有する炭化珪素基板を備え、前記炭化珪素基板は、前記第１主面と前記第２主面とをつなぐ端面を有し、前記端面は、前記第２主面との境界から連続し、前記第２主面に対して傾斜した傾斜面を含む。 [1] The silicon carbide semiconductor device according to one aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and the silicon carbide substrate is a silicon carbide substrate. It has an end surface connecting the first main surface and the second main surface, and the end surface includes an inclined surface that is continuous from the boundary with the second main surface and is inclined with respect to the second main surface.
　炭化珪素はシリコンと比較して高い耐圧を得ることができるため、炭化珪素半導体装置はシリコン系半導体装置よりも薄くできる。その一方で、薄い炭化珪素半導体装置では２つの主面の間の距離が短く、２つの主面の間でリーク電流が流れるおそれがある。これに対し、本開示の一態様に係る炭化珪素半導体装置では、端面に傾斜面が含まれているため、端面が第１主面、第２主面に垂直になっている場合よりもリーク電流が流れる経路を長くできる。従って、端面を経路として第１主面と第２主面との間を流れるリーク電流を低減できる。 Since silicon carbide can obtain a higher withstand voltage than silicon, the silicon carbide semiconductor device can be made thinner than the silicon-based semiconductor device. On the other hand, in a thin silicon carbide semiconductor device, the distance between the two main surfaces is short, and a leak current may flow between the two main surfaces. On the other hand, in the silicon carbide semiconductor device according to one aspect of the present disclosure, since the end face includes an inclined surface, the leakage current is higher than the case where the end face is perpendicular to the first main surface and the second main surface. Can lengthen the flow path. Therefore, it is possible to reduce the leakage current flowing between the first main surface and the second main surface using the end surface as a path.
　〔２〕　〔１〕において、前記炭化珪素基板は、前記第２主面を含む炭化珪素単結晶基板と、前記第１主面を含む炭化珪素エピタキシャル層と、を有してもよい。この場合、炭化珪素エピタキシャル層の結晶性が良好であり、優れた特性を得やすい。 [2] In [1], the silicon carbide substrate may have a silicon carbide single crystal substrate including the second main surface and a silicon carbide epitaxial layer including the first main surface. In this case, the crystallinity of the silicon carbide epitaxial layer is good, and it is easy to obtain excellent characteristics.
　〔３〕　〔１〕又は〔２〕において、断面視において、前記傾斜面と前記第２主面とがなす角の内角は鋭角であってもよい。この場合、第２主面がはんだを用いて導電層等に接続されると、はんだが傾斜面にせり上がりやすく、良好な接合強度を得やすい。また、トランスファモールドにより炭化珪素半導体装置を封止する場合に、端面の近傍から気泡を排出させやすく、気泡の残留に伴う実装不良を抑制しやすい。 [3] In [1] or [2], the internal angle of the angle formed by the inclined surface and the second main surface may be an acute angle in a cross-sectional view. In this case, when the second main surface is connected to the conductive layer or the like by using solder, the solder easily rises to the inclined surface and good bonding strength can be easily obtained. Further, when the silicon carbide semiconductor device is sealed by the transfer mold, bubbles are easily discharged from the vicinity of the end face, and mounting defects due to residual bubbles are easily suppressed.
　〔４〕　〔１〕又は〔２〕において、断面視において、前記傾斜面と前記第２主面とがなす角の内角は鈍角であってもよい。この場合も、リーク電流の低減及び放熱性の向上の効果が得られる。 [4] In [1] or [2], the internal angle of the angle formed by the inclined surface and the second main surface may be an obtuse angle in a cross-sectional view. In this case as well, the effects of reducing the leakage current and improving the heat dissipation can be obtained.
　〔５〕　〔３〕又は〔４〕において、前記傾斜面と前記第２主面とのなす角度は、５０°以上６５°以下であってもよい。この場合、傾斜面に良好な結晶性を得やすい。 [5] In [3] or [4], the angle between the inclined surface and the second main surface may be 50 ° or more and 65 ° or less. In this case, it is easy to obtain good crystallinity on the inclined surface.
　〔６〕　〔１〕～〔５〕において、前記傾斜面は、｛０－３３－８｝面を含んでもよい。この場合、傾斜面に良好な結晶性を得やすい。 [6] In [1] to [5], the inclined surface may include a {0-33-8} surface. In this case, it is easy to obtain good crystallinity on the inclined surface.
　〔７〕　〔１〕～〔６〕において、前記傾斜面の一辺１００ｎｍの正方形領域内における表面粗さはＲＭＳで１．０ｎｍ以下であってもよい。この場合、チッピングを抑制しやすい。 [7] In [1] to [6], the surface roughness in the square region having a side of 100 nm on the inclined surface may be 1.0 nm or less in RMS. In this case, it is easy to suppress chipping.
　〔８〕　〔１〕～〔７〕において、前記第１主面に垂直な方向から平面視したときに、前記第２主面は、少なくとも１つの角が丸まった角丸長方形状の平面形状を有してもよい。この場合、平面形状における隅部での応力集中を緩和しやすい。 [8] In [1] to [7], when viewed in a plan view from a direction perpendicular to the first main surface, the second main surface has a rectangular planar shape with at least one rounded corner. You may have. In this case, it is easy to relax the stress concentration at the corners in the planar shape.
　〔９〕　本開示の他の一態様に係る炭化珪素半導体装置の製造方法は、第１主面と、前記第１主面と反対側の第３主面とを有し、前記第１主面にダイシングラインを備えた炭化珪素ウェハを準備する工程と、前記ダイシングラインに対してハロゲンガスを含む雰囲気で熱エッチングを行って前記ダイシングラインに溝を形成する工程と、前記炭化珪素ウェハを前記第３主面から薄化して前記炭化珪素ウェハを個片化する工程と、を有する。 [9] The method for manufacturing a silicon carbide semiconductor device according to another aspect of the present disclosure has a first main surface and a third main surface opposite to the first main surface, and the first main surface. A step of preparing a silicon carbide wafer provided with a dicing line, a step of performing thermal etching on the dicing line in an atmosphere containing halogen gas to form a groove in the dicing line, and a step of forming the silicon carbide wafer in the first step. 3. It has a step of thinning from the main surface to separate the silicon carbide wafer into individual pieces.
　本開示の他の一態様に係る炭化珪素半導体装置の製造方法によれば、〔１〕に記載の傾斜面を容易に形成できる。 According to the method for manufacturing a silicon carbide semiconductor device according to another aspect of the present disclosure, the inclined surface according to [1] can be easily formed.
　〔１０〕　〔９〕において、前記炭化珪素ウェハを個片化する工程は、前記炭化珪素ウェハを前記第３主面側から研削する工程を有してもよい。この場合、溝の形成後に研削が行われるため、炭化珪素ウェハにかかる圧力を分散しやすい。 In [10] and [9], the step of individualizing the silicon carbide wafer may include a step of grinding the silicon carbide wafer from the third main surface side. In this case, since grinding is performed after the groove is formed, the pressure applied to the silicon carbide wafer can be easily dispersed.
　〔１１〕　〔９〕又は〔１０〕において、前記炭化珪素ウェハを準備する工程は、前記第３主面を含む炭化珪素単結晶基板の上に、前記第１主面を含む炭化珪素エピタキシャル層を形成する工程を有してもよい。この場合、炭化珪素エピタキシャル層の結晶性が良好であり、優れた特性を得やすい。 [11] In the step of preparing the silicon carbide wafer in [9] or [10], the silicon carbide epitaxial layer containing the first main surface is placed on the silicon carbide single crystal substrate including the third main surface. It may have a step of forming. In this case, the crystallinity of the silicon carbide epitaxial layer is good, and it is easy to obtain excellent characteristics.
　〔１２〕　〔９〕～〔１１〕において、前記ダイシングラインに対して熱エッチングを行う工程は、前記第１主面の一部を覆う被覆部と、前記第１主面の残部を露出する開口部とを備えたエッチングマスクを前記第１主面の上に形成する工程を有し、前記第１主面に垂直な方向から平面視したときに、前記被覆部は、少なくとも１つの角が丸まった角丸長方形状の平面形状を有してもよい。この場合、平面形状における隅部での応力集中を緩和しやすい。 [12] In [9] to [11], the step of performing thermal etching on the dicing line is an opening that exposes a covering portion that covers a part of the first main surface and an opening that exposes the rest of the first main surface. The covering portion has at least one corner rounded when the etching mask including the portion is formed on the first main surface and is viewed in a plan view from a direction perpendicular to the first main surface. It may have a planar shape with rounded corners. In this case, it is easy to relax the stress concentration at the corners in the planar shape.
　［第１実施形態］
　本開示の第１実施形態は、トランジスタを含む炭化珪素半導体装置に関する。図１は、第１実施形態に係る炭化珪素半導体装置に含まれる炭化珪素基板の概要を示す平面図である。図２は、第１実施形態に係る炭化珪素半導体装置に含まれる炭化珪素基板の概要を示す断面図である。図３は、第１実施形態に係る炭化珪素半導体装置に含まれるトランジスタを示す断面図である。図２は、図１中のII-II線に沿った断面図に相当する。 [First Embodiment]
The first embodiment of the present disclosure relates to a silicon carbide semiconductor device including a transistor. FIG. 1 is a plan view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view showing a transistor included in the silicon carbide semiconductor device according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG.
　図１及び図２に示されるように、第１実施形態に係る炭化珪素半導体装置１００は炭化珪素基板１０を含み、炭化珪素基板１０は、炭化珪素単結晶基板５０と、炭化珪素単結晶基板５０上にある炭化珪素エピタキシャル層４０とを含む。炭化珪素基板１０は、第１主面１と、第１主面１と反対側の第２主面２とを有する。炭化珪素エピタキシャル層４０は第１主面１を構成し、炭化珪素単結晶基板５０は第２主面２を構成する。炭化珪素単結晶基板５０及び炭化珪素エピタキシャル層４０は、例えばポリタイプ４Ｈの六方晶炭化珪素から構成されている。炭化珪素単結晶基板５０は、例えば窒素（Ｎ）などのｎ型不純物を含みｎ型（第１導電型）を有する。炭化珪素基板１０に半導体素子が形成されている。例えば、第１主面１と第２主面２との間の距離Ｌ１、すなわち炭化珪素基板１０の厚さは、５０μｍ以上２００μｍ以下程度である。 As shown in FIGS. 1 and 2, the silicon carbide semiconductor device 100 according to the first embodiment includes a silicon carbide substrate 10, and the silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide single crystal substrate 50. Includes the silicon carbide epitaxial layer 40 above. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen (N) and has an n-type (first conductive type). A semiconductor element is formed on the silicon carbide substrate 10. For example, the distance L1 between the first main surface 1 and the second main surface 2, that is, the thickness of the silicon carbide substrate 10 is about 50 μm or more and 200 μm or less.
　第１主面１は、｛０００１｝面または｛０００１｝面がオフ方向に８°以下のオフ角だけ傾斜した面である。好ましくは、第１主面１は、（０００－１）面または（０００－１）面がオフ方向に８°以下のオフ角だけ傾斜した面である。オフ方向は、例えば＜１１－２０＞方向であってもよいし、＜１－１００＞方向であってもよい。オフ角は、例えば１°以上であってもよいし、２°以上であってもよい。オフ角は、６°以下であってもよいし、４°以下であってもよい。 The first main surface 1 is a surface on which the {0001} surface or the {0001} surface is inclined by an off angle of 8 ° or less in the off direction. Preferably, the first main surface 1 is a surface on which the (000-1) surface or the (000-1) surface is inclined by an off angle of 8 ° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1 ° or more, or 2 ° or more. The off angle may be 6 ° or less, or 4 ° or less.
　図１に示されるように、例えば、炭化珪素基板１０は矩形状の平面形状を有する。すなわち、炭化珪素基板１０の平面形状は、第１方向に平行に延びる２辺と、第１方向に垂直な第２方向に延びる２辺とを備える。図２に示されるように、炭化珪素基板１０は、これら４辺に相当する位置のそれぞれに第１主面１と第２主面２とをつなぐ端面２０を有する。端面２０は、第２主面２との境界から連続し、第２主面２に対して傾斜した傾斜面２１を有する。本実施形態では、第１主面１に垂直な方向から平面視したときに、第１主面１の輪郭が第２主面２の輪郭の内側にある。傾斜面２１は、第２主面２側ほど広がるように傾斜している。すなわち、断面視において、傾斜面２１と第２主面２とがなす角の内角は鋭角であり、傾斜面２１は、第１主面１に近づくほど、第１主面１の内側に入るように傾斜している。傾斜面２１と第２主面２とのなす角度θ１は、例えば５０°以上６５°以下である。角度θ１は、例えば５５°以上であってもよい。角度θ１は、例えば６０°以下であってもよい。傾斜面２１は、好ましくは、｛０－３３－８｝面を有する。角度θ１が５０°以上６５°以下であると、傾斜面２１に良好な結晶性を得やすい。 As shown in FIG. 1, for example, the silicon carbide substrate 10 has a rectangular planar shape. That is, the planar shape of the silicon carbide substrate 10 includes two sides extending parallel to the first direction and two sides extending in the second direction perpendicular to the first direction. As shown in FIG. 2, the silicon carbide substrate 10 has an end surface 20 connecting the first main surface 1 and the second main surface 2 at each of the positions corresponding to these four sides. The end surface 20 has an inclined surface 21 that is continuous from the boundary with the second main surface 2 and is inclined with respect to the second main surface 2. In the present embodiment, the contour of the first main surface 1 is inside the contour of the second main surface 2 when viewed in a plan view from a direction perpendicular to the first main surface 1. The inclined surface 21 is inclined so as to expand toward the second main surface 2 side. That is, in the cross-sectional view, the internal angle of the angle formed by the inclined surface 21 and the second main surface 2 is an acute angle, and the inclined surface 21 enters the inside of the first main surface 1 as it approaches the first main surface 1. Is inclined to. The angle θ1 formed by the inclined surface 21 and the second main surface 2 is, for example, 50 ° or more and 65 ° or less. The angle θ1 may be, for example, 55 ° or more. The angle θ1 may be, for example, 60 ° or less. The inclined surface 21 preferably has a {0-33-8} surface. When the angle θ1 is 50 ° or more and 65 ° or less, good crystallinity can be easily obtained on the inclined surface 21.
　４つの傾斜面２１の間で角度θ１が共通していなくてもよい。例えば、第１方向に平行な辺に相当する位置に設けられた２つの傾斜面２１が｛０－３３－８｝面を有し、第２方向に平行な辺に相当する位置に設けられた２つの傾斜面２１が｛０－３３－８｝面とは異なる結晶面を有してもよい。傾斜面２１が｛０－３３－８｝面を有していると、傾斜面２１に良好な結晶面を得やすい。 The angle θ1 does not have to be common among the four inclined surfaces 21. For example, two inclined surfaces 21 provided at positions corresponding to sides parallel to the first direction have {0-33-8} planes and are provided at positions corresponding to sides parallel to the second direction. The two inclined planes 21 may have a crystal plane different from the {0-33-8} plane. When the inclined surface 21 has a {0-33-8} surface, it is easy to obtain a good crystal plane on the inclined surface 21.
　端面２０が、第１主面１との境界から連続する面２３と、傾斜面２１と面２３とをつなぐ面２２とを有してもよい。例えば、面２３は、第１主面１に対して実質的に垂直であってもよく、面２２は、第１主面１及び第２主面２に実質的に平行であってもよい。例えば、第１主面１と面２２との間の距離Ｌ２は、０．５μｍ以上１．０μｍ以下程度であり、距離Ｌ１と比べると極めて小さい。 The end surface 20 may have a surface 23 continuous from the boundary with the first main surface 1 and a surface 22 connecting the inclined surface 21 and the surface 23. For example, the surface 23 may be substantially perpendicular to the first main surface 1 and the surface 22 may be substantially parallel to the first main surface 1 and the second main surface 2. For example, the distance L2 between the first main surface 1 and the surface 22 is about 0.5 μm or more and 1.0 μm or less, which is extremely small as compared with the distance L1.
　本実施形態では、炭化珪素基板１０に半導体素子の一例としてＭＯＳＦＥＴが形成されている。図３に示されるように、炭化珪素エピタキシャル層４０は、ドリフト領域１１と、ボディ領域１２と、ソース領域１３と、コンタクト領域１８とを主に有する。 In this embodiment, a MOSFET is formed on the silicon carbide substrate 10 as an example of a semiconductor element. As shown in FIG. 3, the silicon carbide epitaxial layer 40 mainly has a drift region 11, a body region 12, a source region 13, and a contact region 18.
　ドリフト領域１１は、例えば窒素またはリン（Ｐ）などのｎ型不純物が添加されていることでｎ型を有する。ドリフト領域１１へのｎ型不純物の添加は、イオン注入によってではなく、ドリフト領域１１のエピタキシャル成長時の不純物添加によって行われていることが好ましい。 The drift region 11 has an n-type due to the addition of an n-type impurity such as nitrogen or phosphorus (P). It is preferable that the n-type impurities are added to the drift region 11 not by ion implantation but by adding impurities at the time of epitaxial growth of the drift region 11.
　ボディ領域１２はドリフト領域１１上に設けられている。ボディ領域１２は、例えばアルミニウム（Ａｌ）などのｐ型不純物が添加されていることでｐ型（第２導電型）を有する。 The body region 12 is provided on the drift region 11. The body region 12 has a p-type (second conductive type) due to the addition of a p-type impurity such as aluminum (Al).
　ソース領域１３は、ボディ領域１２によってドリフト領域１１から隔てられるようにボディ領域１２上に設けられている。ソース領域１３は、例えば窒素またはリンなどのｎ型不純物が添加されていることでｎ型を有する。ソース領域１３は、第１主面１を構成している。 The source region 13 is provided on the body region 12 so as to be separated from the drift region 11 by the body region 12. The source region 13 has an n-type due to the addition of an n-type impurity such as nitrogen or phosphorus. The source region 13 constitutes the first main surface 1.
　コンタクト領域１８は、例えばアルミニウムなどのｐ型不純物が添加されていることでｐ型を有する。コンタクト領域１８は、第１主面１を構成する。コンタクト領域１８は、ソース領域１３を貫通し、ボディ領域１２に接する。 The contact region 18 has a p-type due to the addition of a p-type impurity such as aluminum. The contact area 18 constitutes the first main surface 1. The contact region 18 penetrates the source region 13 and touches the body region 12.
　第１主面１には、複数のゲートトレンチ５が設けられている。ゲートトレンチ５は、例えば第１主面１に平行な第１方向に延びており、複数のゲートトレンチ５が第２方向に並んでいる。ゲートトレンチ５は、ドリフト領域１１からなる底面４を有する。ゲートトレンチ５は、ソース領域１３及びボディ領域１２を貫通して底面４に連なる側面３を有する。底面４は、例えば第２主面２と平行な平面である。底面４を含む平面に対する側面３の角度は、例えば５０°以上６５°以下である。この角度は、例えば５５°以上であってもよい。この角度は、例えば６０°以下であってもよい。側面３は、好ましくは、｛０－３３－８｝面を有する。｛０－３３－８｝面は、優れた移動度が得られる結晶面である。 A plurality of gate trenches 5 are provided on the first main surface 1. The gate trench 5 extends in the first direction parallel to, for example, the first main surface 1, and a plurality of gate trenches 5 are arranged in the second direction. The gate trench 5 has a bottom surface 4 composed of a drift region 11. The gate trench 5 has a side surface 3 that penetrates the source region 13 and the body region 12 and is connected to the bottom surface 4. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The angle of the side surface 3 with respect to the plane including the bottom surface 4 is, for example, 50 ° or more and 65 ° or less. This angle may be, for example, 55 ° or more. This angle may be, for example, 60 ° or less. The side surface 3 preferably has a {0-33-8} surface. The {0-33-8} plane is a crystal plane from which excellent mobility can be obtained.
　側面３及び底面４に接するゲート絶縁膜８１が設けられている。ゲート絶縁膜８１は、例えば酸化膜である。ゲート絶縁膜８１は、例えば二酸化珪素を含む材料により構成されている。ゲート絶縁膜８１は、底面４においてドリフト領域１１と接する。ゲート絶縁膜８１は、側面３においてソース領域１３、ボディ領域１２及びドリフト領域１１の各々と接している。ゲート絶縁膜８１は、第１主面１においてソース領域１３と接していてもよい。 A gate insulating film 81 in contact with the side surface 3 and the bottom surface 4 is provided. The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 is in contact with the drift region 11 on the bottom surface 4. The gate insulating film 81 is in contact with each of the source region 13, the body region 12, and the drift region 11 on the side surface 3. The gate insulating film 81 may be in contact with the source region 13 on the first main surface 1.
　ゲート絶縁膜８１上にゲート電極８２が設けられている。ゲート電極８２は、例えば導電性不純物を含むポリシリコン（ポリＳｉ）から構成されている。ゲート電極８２は、ゲートトレンチ５の内部に配置されている。 A gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (polySi) containing a conductive impurity. The gate electrode 82 is arranged inside the gate trench 5.
　ゲート電極８２及びゲート絶縁膜８１に接する層間絶縁膜８３が設けられている。層間絶縁膜８３は、例えば二酸化珪素を含む材料から構成されている。層間絶縁膜８３は、ゲート電極８２とソース電極６０とを電気的に絶縁している。 An interlayer insulating film 83 in contact with the gate electrode 82 and the gate insulating film 81 is provided. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60.
　層間絶縁膜８３及びゲート絶縁膜８１には、第２方向に一定の間隔でコンタクトホール９０が形成されている。コンタクトホール９０は、第２方向で隣り合うコンタクトホール９０の間にゲートトレンチ５が位置するように設けられている。コンタクトホール９０は、第１方向に延びる。コンタクトホール９０を通じて、ソース領域１３及びコンタクト領域１８が層間絶縁膜８３及びゲート絶縁膜８１から露出している。 Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the second direction. The contact hole 90 is provided so that the gate trench 5 is located between the contact holes 90 adjacent to each other in the second direction. The contact hole 90 extends in the first direction. Through the contact hole 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.
　第１主面１に接するソース電極６０が設けられている。ソース電極６０は、コンタクトホール９０内に設けられたコンタクト電極６１と、ソース配線６２とを有する。コンタクト電極６１は、第１主面１において、ソース領域１３及びコンタクト領域１８に接している。コンタクト電極６１は、例えばニッケルシリサイド（ＮｉＳｉ）を含む材料から構成されている。コンタクト電極６１が、チタン（Ｔｉ）と、Ａｌと、Ｓｉとを含む材料から構成されていてもよい。コンタクト電極６１は、ソース領域１３及びコンタクト領域１８とオーミック接合している。ソース配線６２は、例えばＡｌを含む材料から構成されている。 A source electrode 60 in contact with the first main surface 1 is provided. The source electrode 60 has a contact electrode 61 provided in the contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13 and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), Al, and Si. The contact electrode 61 is ohmic contacted with the source region 13 and the contact region 18. The source wiring 62 is made of, for example, a material containing Al.
　ソース配線６２の上面を覆うパッシベーション膜８４が設けられている。パッシベーション膜８４は、ソース配線６２と接している。パッシベーション膜８４は、例えばポリイミドを含む材料から構成されている。 A passivation film 84 is provided to cover the upper surface of the source wiring 62. The passivation film 84 is in contact with the source wiring 62. The passivation film 84 is made of a material containing, for example, polyimide.
　第２主面２に接するドレイン電極７０が設けられている。ドレイン電極７０は、第２主面２において炭化珪素単結晶基板５０と接している。ドレイン電極７０は、ドリフト領域１１と電気的に接続されている。ドレイン電極７０は、例えばＮｉＳｉを含む材料から構成されている。ドレイン電極７０がＴｉと、Ａｌと、Ｓｉとを含む材料から構成されていてもよい。ドレイン電極７０は、炭化珪素単結晶基板５０とオーミック接合している。 A drain electrode 70 in contact with the second main surface 2 is provided. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 on the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing, for example, NiSi. The drain electrode 70 may be made of a material containing Ti, Al, and Si. The drain electrode 70 is ohmic-bonded to the silicon carbide single crystal substrate 50.
　本実施形態では、端面２０に傾斜面２１が含まれているため、端面２０が第１主面１及び第２主面２に垂直になっている場合よりもリーク電流が流れる経路を長くできる。従って、端面２０を経路として第１主面１と第２主面２との間を流れるリーク電流を低減できる。また、端面２０が第１主面１及び第２主面２に垂直になっている場合よりも端面２０の面積が大きくなるため、放熱性を向上できる。 In the present embodiment, since the end surface 20 includes the inclined surface 21, the path through which the leak current flows can be made longer than when the end surface 20 is perpendicular to the first main surface 1 and the second main surface 2. Therefore, it is possible to reduce the leakage current flowing between the first main surface 1 and the second main surface 2 with the end surface 20 as a path. Further, since the area of the end surface 20 is larger than that in the case where the end surface 20 is perpendicular to the first main surface 1 and the second main surface 2, heat dissipation can be improved.
　また、炭化珪素基板１０が、第２主面２を含む炭化珪素単結晶基板５０と、第１主面１を含む炭化珪素エピタキシャル層４０とを有する。つまり、炭化珪素基板１０は、いわゆるエピタキシャル基板である。このため、炭化珪素エピタキシャル層４０の結晶性が良好であり、優れた特性を得やすい。 Further, the silicon carbide substrate 10 has a silicon carbide single crystal substrate 50 including the second main surface 2 and a silicon carbide epitaxial layer 40 including the first main surface 1. That is, the silicon carbide substrate 10 is a so-called epitaxial substrate. Therefore, the crystallinity of the silicon carbide epitaxial layer 40 is good, and it is easy to obtain excellent properties.
　また、断面視において、傾斜面２１と第２主面２とがなす角の内角は鋭角である。このため、絶縁基板の表面に形成された導電層等にはんだを介してドレイン電極７０が接続される場合、溶融したはんだが傾斜面２１にせり上がりやすく、ドレイン電極７０と導電層等との間に良好な接合強度を得やすい。また、トランスファモールドにより炭化珪素半導体装置１００を封止する場合に、端面２０の近傍から気泡を排出させやすく、気泡の残留に伴う実装不良を抑制しやすい。 Further, in the cross-sectional view, the internal angle of the angle formed by the inclined surface 21 and the second main surface 2 is an acute angle. Therefore, when the drain electrode 70 is connected to the conductive layer or the like formed on the surface of the insulating substrate via solder, the molten solder easily rises to the inclined surface 21 and is between the drain electrode 70 and the conductive layer or the like. It is easy to obtain good bonding strength. Further, when the silicon carbide semiconductor device 100 is sealed by the transfer mold, bubbles are easily discharged from the vicinity of the end face 20, and mounting defects due to residual bubbles are easily suppressed.
　傾斜面２１の表面粗さは一辺１００ｎｍの正方形領域において算出するような微視的な範囲においてＲＭＳで１．０ｎｍ以下であることが好ましく、０．８ｎｍ以下であることがより好ましい。炭化珪素半導体装置１００におけるチッピングの抑制のためである。このような微視的な表面粗さは、例えば原子間力顕微鏡（Atomic Force Microscope：ＡＦＭ）を用いて測定することができる。 The surface roughness of the inclined surface 21 is preferably 1.0 nm or less in RMS, and more preferably 0.8 nm or less in a microscopic range such as that calculated in a square region having a side of 100 nm. This is to suppress chipping in the silicon carbide semiconductor device 100. Such microscopic surface roughness can be measured using, for example, an atomic force microscope (AFM).
　傾斜面２１は｛０－３３－８｝面を有していることが好ましいが、｛０－３３－８｝面とは異なる炭化珪素の特定の結晶面を有してもよい。ここで、｛０－３３－８｝面を有しているとは、傾斜面２１の加工精度などを考慮して実質的に面方位が｛０－３３－８｝とみなせるオフ角の範囲に傾斜面２１の面方位が含まれていることを意味する。この場合のオフ角の範囲は、例えば｛０－３３－８｝に対してオフ角が±２°の範囲である。 The inclined surface 21 preferably has a {0-33-8} plane, but may have a specific crystal plane of silicon carbide different from the {0-33-8} plane. Here, having a {0-33-8} plane means that the plane orientation is substantially within the range of an off angle that can be regarded as {0-33-8} in consideration of the machining accuracy of the inclined surface 21 and the like. It means that the plane orientation of the inclined surface 21 is included. The off-angle range in this case is, for example, a range in which the off-angle is ± 2 ° with respect to {0-33-8}.
　例えば、傾斜面２１のオフ方位と＜０１－１０＞方向とのなす角は５°以下となっていてもよい。これによりオフ方位がほぼ＜０１－１０＞方向となり、その結果、傾斜面２１の面方位が｛０－３３－８｝面に近くなる。傾斜面２１の、＜０１－１０＞方向における｛０－３３－８｝面に対するオフ角は－３°以上５°以下であってもよい。 For example, the angle between the off-direction of the inclined surface 21 and the <01-10> direction may be 5 ° or less. As a result, the off-direction becomes substantially the <01-10> direction, and as a result, the plane orientation of the inclined surface 21 becomes close to the {0-33-8} plane. The off angle of the inclined surface 21 with respect to the {0-33-8} surface in the <01-10> direction may be -3 ° or more and 5 ° or less.
　「＜０１－１０＞方向における｛０－３３－８｝面に対するオフ角」とは、＜０１－１０＞方向及び＜０００１＞方向を含む平面への傾斜面２１の法線の正射影と、｛０－３３－８｝面の法線とのなす角度である。当該角度の符号は、上記正射影が＜０１－１０＞方向に対して平行に近づく場合が正であり、上記正射影が＜０００１＞方向に対して平行に近づく場合が負である。 The "off angle with respect to the {0-33-8} plane in the <01-10> direction" is the orthogonal projection of the normal of the inclined surface 21 onto the plane including the <01-10> direction and the <0001> direction. This is the angle formed by the normal of the {0-33-8} plane. The sign of the angle is positive when the orthogonal projection approaches parallel to the <01-10> direction, and negative when the orthogonal projection approaches parallel to the <0001> direction.
　なお、ゲートトレンチ５が垂直トレンチであってもよい。つまり、底面４を含む平面に対する側面３の角度が９０°であってもよい。また、ゲートトレンチ５を含まないトランジスタが炭化珪素基板１０に形成されていてもよい。また、炭化珪素基板１０に形成される半導体素子はＭＯＳＦＥＴ等のトランジスタに限定されず、ショットキーバリアダイオード等の他の半導体素子が炭化珪素基板１０に形成されていてもよい。 The gate trench 5 may be a vertical trench. That is, the angle of the side surface 3 with respect to the plane including the bottom surface 4 may be 90 °. Further, a transistor that does not include the gate trench 5 may be formed on the silicon carbide substrate 10. Further, the semiconductor element formed on the silicon carbide substrate 10 is not limited to a transistor such as a MOSFET, and another semiconductor element such as a Schottky barrier diode may be formed on the silicon carbide substrate 10.
　次に、第１実施形態に係る炭化珪素半導体装置１００の製造方法について説明する。図４は、第１実施形態に係る炭化珪素半導体装置の製造方法を示すフローチャートである。図５～図７は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す平面図である。図８～図２６は、第１実施形態に係る炭化珪素半導体装置の製造方法を示す断面図である。図１７～図２６は、図３に示す断面の変化を示す。 Next, a method for manufacturing the silicon carbide semiconductor device 100 according to the first embodiment will be described. FIG. 4 is a flowchart showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 5 to 7 are plan views showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 8 to 26 are cross-sectional views showing a method of manufacturing the silicon carbide semiconductor device according to the first embodiment. 17 to 26 show changes in the cross section shown in FIG.
　まず、工程Ｓ１において、図８及び図１７に示されるように、炭化珪素単結晶基板５０が準備される。例えば昇華法によって製造された炭化珪素インゴット（図示せず）がスライスされることにより、炭化珪素単結晶基板５０が準備される。炭化珪素単結晶基板５０上にバッファ層（図示せず）が形成されてもよい。バッファ層は、例えば原料ガスとしてシラン（ＳｉＨ４）とプロパン（Ｃ３Ｈ８）との混合ガスを用い、キャリアガスとして例えば水素（Ｈ２）を用いた化学気相成長（Chemical Vapor Deposition：ＣＶＤ）法により形成することができる。バッファ層のエピタキシャル成長の際に、例えば窒素などのｎ型不純物がバッファ層に導入されてもよい。 First, in step S1, the silicon carbide single crystal substrate 50 is prepared as shown in FIGS. 8 and 17. For example, a silicon carbide single crystal substrate 50 is prepared by slicing a silicon carbide ingot (not shown) manufactured by a sublimation method. A buffer layer (not shown) may be formed on the silicon carbide single crystal substrate 50. The buffer layer uses, for example, a mixed gas of silane (SiH 4 ) and propane (C 3 H 8 ) as a raw material gas, and chemical vapor deposition (CVD: CVD) using, for example, hydrogen (H 2 ) as a carrier gas. ) Can be formed by the method. During the epitaxial growth of the buffer layer, n-type impurities such as nitrogen may be introduced into the buffer layer.
　次に、炭化珪素単結晶基板５０上に炭化珪素エピタキシャル層４０が形成される。例えば原料ガスとしてシランとプロパンとの混合ガスを用い、キャリアガスとして例えば水素を用いたＣＶＤ法により、炭化珪素単結晶基板５０上に炭化珪素エピタキシャル層４０が形成される。炭化珪素エピタキシャル層４０の形成の際、例えば窒素などのｎ型不純物が炭化珪素エピタキシャル層４０に導入される。炭化珪素エピタキシャル層４０は、ｎ型の導電型を有する。このようにして、炭化珪素単結晶基板５０及び炭化珪素エピタキシャル層４０を備えた炭化珪素ウェハ５１が準備される。炭化珪素ウェハ５１は、第１主面１と、第１主面１とは反対側の第３主面５５とを有する。例えば、第１主面１と第３主面５５との間の距離Ｌ３、すなわち炭化珪素ウェハ５１の厚さは、炭化珪素半導体装置１００の厚さよりも大きく、例えば３５０μｍ以上５００μｍ以下程度である。 Next, the silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, a silicon carbide epitaxial layer 40 is formed on a silicon carbide single crystal substrate 50 by a CVD method using a mixed gas of silane and propane as a raw material gas and, for example, hydrogen as a carrier gas. When forming the silicon carbide epitaxial layer 40, n-type impurities such as nitrogen are introduced into the silicon carbide epitaxial layer 40. The silicon carbide epitaxial layer 40 has an n-type conductive type. In this way, the silicon carbide wafer 51 provided with the silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 is prepared. The silicon carbide wafer 51 has a first main surface 1 and a third main surface 55 opposite to the first main surface 1. For example, the distance L3 between the first main surface 1 and the third main surface 55, that is, the thickness of the silicon carbide wafer 51 is larger than the thickness of the silicon carbide semiconductor device 100, and is, for example, about 350 μm or more and 500 μm or less.
　次に、工程Ｓ２において、第１主面１にマーカ９１が形成される。マーカ９１の形成では、まず、図５に示されるように、炭化珪素ウェハ５１の第１主面１に、炭化珪素半導体装置１００を形成する予定のチップ領域５２と、隣り合うチップ領域５２とを分離するダイシングライン５３とが設定される。例えば、ダイシングライン５３は、第１方向及び第２方向に延びる。次いで、図８に示されるように、例えばフォトレジストをエッチングマスクとして用い、炭化珪素エピタキシャル層４０のエッチングが行われる。エッチングの方法としては、例えば反応性イオンエッチング（Reactive Ion Etching：ＲＩＥ）、特に誘導結合プラズマ（Inductive Coupled Plasma：ＩＣＰ）ＲＩＥを用いることができる。具体的には、例えば反応ガスとしてＳＦ６またはＳＦ６とＯ２との混合ガスを用いたＩＣＰ－ＲＩＥを用いることができる。例えば、マーカ９１の幅は１０μｍ程度であり、深さは距離Ｌ２と等しく、０．５μｍ以上１．０μｍ以下程度である。 Next, in step S2, the marker 91 is formed on the first main surface 1. In the formation of the marker 91, first, as shown in FIG. 5, a chip region 52 on which the silicon carbide semiconductor device 100 is to be formed and an adjacent chip region 52 are formed on the first main surface 1 of the silicon carbide wafer 51. A dicing line 53 to be separated is set. For example, the dicing line 53 extends in the first direction and the second direction. Next, as shown in FIG. 8, the silicon carbide epitaxial layer 40 is etched using, for example, a photoresist as an etching mask. As the etching method, for example, reactive ion etching (RIE), particularly Inductive Coupled Plasma (ICP) RIE can be used. Specifically, for example, ICP-RIE using SF 6 or a mixed gas of SF 6 and O 2 can be used as the reaction gas. For example, the width of the marker 91 is about 10 μm, the depth is equal to the distance L2, and is about 0.5 μm or more and 1.0 μm or less.
　次に、工程Ｓ３において、図１８に示されるように、炭化珪素エピタキシャル層４０へのイオン注入が行われる。例えば、イオン注入により、ボディ領域１２、ソース領域１３及びコンタクト領域１８が形成される。炭化珪素エピタキシャル層４０の残部がドリフト領域１１として機能する。ボディ領域１２又はコンタクト領域１８を形成するためのイオン注入においては、例えばアルミニウム（Ａｌ）などのｐ型不純物がイオン注入される。ソース領域１３を形成するためのイオン注入においては、例えばリン（Ｐ）などのｎ型不純物がイオン注入される。 Next, in step S3, as shown in FIG. 18, ion implantation into the silicon carbide epitaxial layer 40 is performed. For example, ion implantation forms a body region 12, a source region 13, and a contact region 18. The rest of the silicon carbide epitaxial layer 40 functions as the drift region 11. In ion implantation for forming the body region 12 or the contact region 18, p-type impurities such as aluminum (Al) are ion-implanted. In the ion implantation for forming the source region 13, n-type impurities such as phosphorus (P) are ion-implanted.
　次に、工程Ｓ４において、図９に示されるように、炭化珪素エピタキシャル層４０の表面の熱酸化を行うことにより、炭化珪素エピタキシャル層４０の表面に絶縁膜９２を形成する。絶縁膜９２は、例えば二酸化珪素を含む材料から構成される。 Next, in step S4, as shown in FIG. 9, the insulating film 92 is formed on the surface of the silicon carbide epitaxial layer 40 by thermally oxidizing the surface of the silicon carbide epitaxial layer 40. The insulating film 92 is made of a material containing, for example, silicon dioxide.
　次に、工程Ｓ５において、図６及び図１０に示されるように、絶縁膜９２にマーカ９１の底面を部分的に露出する開口部９２Ｘを形成する。開口部９２Ｘの形成では、例えばフォトレジストをエッチングマスクとして用いた絶縁膜９２のドライエッチングを行う。絶縁膜９２から、第１主面１の一部を覆う被覆部９２Ｙと、第１主面１の残部を露出する開口部９２Ｘとを備えたエッチングマスク９２Ｚが形成される。被覆部９２Ｙは、第１主面１に垂直な方向から平面視したときに、長方形状の平面形状を有する。 Next, in step S5, as shown in FIGS. 6 and 10, an opening 92X that partially exposes the bottom surface of the marker 91 is formed in the insulating film 92. In the formation of the opening 92X, for example, dry etching of the insulating film 92 using a photoresist as an etching mask is performed. From the insulating film 92, an etching mask 92Z having a covering portion 92Y that covers a part of the first main surface 1 and an opening 92X that exposes the rest of the first main surface 1 is formed. The covering portion 92Y has a rectangular planar shape when viewed in a plan view from a direction perpendicular to the first main surface 1.
　次に、工程Ｓ６において、図６及び図１１に示されるように、エッチングマスク９２Ｚを用いて、平面視でマーカ９１の内側に、ダイシング溝９５が形成される。ダイシング溝９５の形成では、まず、開口部９２Ｘにおいて、ＩＣＰ－ＲＩＥ等のＲＩＥにより炭化珪素ウェハ５１の一部がエッチングにより除去される。具体的には、例えば反応ガスとしてＳＦ６またはＳＦ６とＯ２との混合ガスを用いたＩＣＰ－ＲＩＥを用いることができる。このようなエッチングにより、側面が第１主面１に対してほぼ垂直な内面を有する凹部を形成することができる。次いで、エッチングマスク９２Ｚを用いて、炭化珪素ウェハ５１に対して、凹部の内面において熱エッチングが行われる。熱エッチングは、例えば、少なくとも１種類以上のハロゲン原子を有するハロゲン系の反応性ガスを含む雰囲気中で、炭化珪素ウェハ５１を加熱することによって行い得る。少なくとも１種類以上のハロゲン原子は、塩素（Ｃｌ）原子及びフッ素（Ｆ）原子の少なくともいずれかを含む。この雰囲気は、例えば、Ｃｌ２、ＢＣｌ３、ＳＦ６、またはＣＦ４である。例えば、塩素ガスと酸素ガスとの混合ガスを反応ガスとして用い、熱処理温度を、例えば７００℃以上１０００℃以下として、熱エッチングが行われる。なお、反応ガスは、塩素ガスと酸素ガスとに加えてキャリアガスを含んでいてもよい。キャリアガスとしては、例えば窒素（Ｎ２）ガス、アルゴンガス、ヘリウムガスなどを用いることができる。そして、上述のように熱処理温度を７００℃以上１０００℃以下とした場合、ＳｉＣのエッチング速度は例えば約７０μｍ／時になる。エッチングマスクとして用いられる二酸化珪素を含む材料から構成される絶縁膜９２は、炭化珪素に対する選択比が極めて大きいため、炭化珪素のエッチング中に実質的にエッチングされない。 Next, in step S6, as shown in FIGS. 6 and 11, a dicing groove 95 is formed inside the marker 91 in a plan view using the etching mask 92Z. In the formation of the dicing groove 95, first, in the opening 92X, a part of the silicon carbide wafer 51 is removed by etching by RIE such as ICP-RIE. Specifically, for example, ICP-RIE using SF 6 or a mixed gas of SF 6 and O 2 can be used as the reaction gas. By such etching, it is possible to form a recess whose side surface has an inner surface substantially perpendicular to the first main surface 1. Next, the silicon carbide wafer 51 is thermally etched on the inner surface of the recess using the etching mask 92Z. Thermal etching can be performed, for example, by heating the silicon carbide wafer 51 in an atmosphere containing a halogen-based reactive gas having at least one kind of halogen atom. At least one kind of halogen atom contains at least one of a chlorine (Cl) atom and a fluorine (F) atom. This atmosphere is, for example, Cl 2 , BCl 3 , SF 6 , or CF 4 . For example, heat etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and setting the heat treatment temperature to, for example, 700 ° C. or higher and 1000 ° C. or lower. The reaction gas may contain a carrier gas in addition to the chlorine gas and the oxygen gas. As the carrier gas, for example, nitrogen (N 2 ) gas, argon gas, helium gas and the like can be used. When the heat treatment temperature is 700 ° C. or higher and 1000 ° C. or lower as described above, the etching rate of SiC is, for example, about 70 μm / hour. Since the insulating film 92 made of a material containing silicon dioxide used as an etching mask has an extremely large selectivity with respect to silicon carbide, it is not substantially etched during etching of silicon carbide.
　上記の熱エッチングにより炭化珪素ウェハ５１に、側面９３と、底面９４とを有するダイシング溝９５が形成される。ダイシング溝９５の形成の際、炭化珪素ウェハ５１は、開口部９２Ｘからサイドエッチングされるようにエッチングされる。また、熱エッチングの際、エッチング速度の最も遅い結晶面である｛０－３３－８｝面がダイシング溝９５の側面９３として自己形成される。例えば、ダイシング溝９５の底面９４とマーカ９１の底面との間の距離Ｌ４は、例えば５０μｍ以上２００μｍ以下程度である。第１主面１とダイシング溝９５の底面９４と間の距離は、距離Ｌ２と距離Ｌ４との和に等しく、製造しようとする炭化珪素半導体装置１００における第１主面１と第２主面２との間の距離Ｌ２よりも大きくする。 By the above thermal etching, a dicing groove 95 having a side surface 93 and a bottom surface 94 is formed on the silicon carbide wafer 51. During the formation of the dicing groove 95, the silicon carbide wafer 51 is etched so as to be side-etched from the opening 92X. Further, during thermal etching, the {0-33-8} plane, which is the crystal plane having the slowest etching rate, is self-formed as the side surface 93 of the dicing groove 95. For example, the distance L4 between the bottom surface 94 of the dicing groove 95 and the bottom surface of the marker 91 is, for example, about 50 μm or more and 200 μm or less. The distance between the first main surface 1 and the bottom surface 94 of the dicing groove 95 is equal to the sum of the distance L2 and the distance L4, and the first main surface 1 and the second main surface 2 in the silicon carbide semiconductor device 100 to be manufactured are equal to each other. The distance between and is greater than L2.
　次に、工程Ｓ７において、図１２に示されるように、エッチングマスク９２Ｚが第１主面１から除去される。 Next, in step S7, the etching mask 92Z is removed from the first main surface 1 as shown in FIG.
　次に、工程Ｓ８において、イオン注入により添加された不純物を活性化するための活性化熱処理が行われる。この熱処理の温度は、好ましくは１５００℃以上１９００℃以下であり、例えば１７００℃程度である。熱処理の時間は、例えば３０分程度である。熱処理の雰囲気は、好ましくは不活性ガス雰囲気であり、例えばＡｒ雰囲気である。 Next, in step S8, an activation heat treatment for activating impurities added by ion implantation is performed. The temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The heat treatment time is, for example, about 30 minutes. The atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an Ar atmosphere.
　次に、工程Ｓ９において、図１９に示されるように、炭化珪素ウェハ５１にゲートトレンチ５が形成される。ゲートトレンチ５は、ダイシング溝９５と同様に、開口部が形成された二酸化珪素を含む材料から構成される絶縁膜をエッチングマスクとした、ＲＩＥ及び熱エッチングにより形成できる。熱エッチングの際、｛０－３３－８｝面が側面３として自己形成される。 Next, in step S9, the gate trench 5 is formed on the silicon carbide wafer 51 as shown in FIG. Similar to the dicing groove 95, the gate trench 5 can be formed by RIE and thermal etching using an insulating film made of a material containing silicon dioxide having an opening formed as an etching mask. During thermal etching, the {0-33-8} surface is self-formed as the side surface 3.
　次に、工程Ｓ１０において、図２０に示されるように、ゲート絶縁膜８１が形成される。例えば炭化珪素ウェハ５１を熱酸化することにより、ソース領域１３と、ボディ領域１２と、ドリフト領域１１と、コンタクト領域１８とに接するゲート絶縁膜８１が形成される。具体的には、炭化珪素ウェハ５１が、酸素を含む雰囲気中において、例えば１３００℃以上１４００℃以下の温度で加熱される。これにより、第１主面１と、側面３及び底面４に接するゲート絶縁膜８１が形成される。なお、ゲート絶縁膜８１が熱酸化により形成された場合、厳密には、炭化珪素ウェハ５１の一部がゲート絶縁膜８１に取り込まれる。このため、以降の処理では、熱酸化後のゲート絶縁膜８１と炭化珪素ウェハ５１との間の界面に第１主面１、側面３及び底面４が若干移動したものとする。 Next, in step S10, the gate insulating film 81 is formed as shown in FIG. For example, by thermally oxidizing the silicon carbide wafer 51, a gate insulating film 81 in contact with the source region 13, the body region 12, the drift region 11, and the contact region 18 is formed. Specifically, the silicon carbide wafer 51 is heated at a temperature of, for example, 1300 ° C. or higher and 1400 ° C. or lower in an atmosphere containing oxygen. As a result, the first main surface 1 and the gate insulating film 81 in contact with the side surface 3 and the bottom surface 4 are formed. Strictly speaking, when the gate insulating film 81 is formed by thermal oxidation, a part of the silicon carbide wafer 51 is incorporated into the gate insulating film 81. Therefore, in the subsequent processing, it is assumed that the first main surface 1, the side surface 3 and the bottom surface 4 are slightly moved to the interface between the gate insulating film 81 after thermal oxidation and the silicon carbide wafer 51.
　次に、一酸化窒素（ＮＯ）ガス雰囲気中において炭化珪素ウェハ５１に対して熱処理（ＮＯアニール）が行われてもよい。ＮＯアニールにおいて、炭化珪素ウェハ５１が、例えば１１００℃以上１４００℃以下の条件下で１時間程度保持される。これにより、ゲート絶縁膜８１とボディ領域１２との界面領域に窒素原子が導入される。その結果、界面領域における界面準位の形成が抑制されることで、チャネル移動度を向上させることができる。 Next, heat treatment (NO annealing) may be performed on the silicon carbide wafer 51 in a nitric oxide (NO) gas atmosphere. In NO annealing, the silicon carbide wafer 51 is held for about 1 hour under the condition of, for example, 1100 ° C. or higher and 1400 ° C. or lower. As a result, nitrogen atoms are introduced into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of the interface state in the interface region is suppressed, so that the channel mobility can be improved.
　次に、工程Ｓ１１において、図２１に示されるように、ゲート電極８２が形成される。ゲート電極８２は、ゲート絶縁膜８１上に形成される。ゲート電極８２は、例えば減圧ＣＶＤ（Low Pressure - Chemical Vapor Deposition：ＬＰ－ＣＶＤ）法により形成される。ゲート電極８２は、ソース領域１３と、ボディ領域１２と、ドリフト領域１１との各々に対面するように形成される。 Next, in step S11, the gate electrode 82 is formed as shown in FIG. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed by, for example, a reduced pressure CVD (Low Pressure-Chemical Vapor Deposition: LP-CVD) method. The gate electrode 82 is formed so as to face each of the source region 13, the body region 12, and the drift region 11.
　次に、工程Ｓ１２において、図２２に示されるように、層間絶縁膜８３が形成される。具体的には、ゲート電極８２を覆い、かつゲート絶縁膜８１と接するように層間絶縁膜８３が形成される。層間絶縁膜８３は、例えば、ＣＶＤ法により形成される。層間絶縁膜８３は、例えば二酸化珪素を含む材料から構成される。層間絶縁膜８３の一部は、ゲートトレンチ５の内部に形成されてもよい。 Next, in step S12, the interlayer insulating film 83 is formed as shown in FIG. Specifically, the interlayer insulating film 83 is formed so as to cover the gate electrode 82 and contact the gate insulating film 81. The interlayer insulating film 83 is formed by, for example, a CVD method. The interlayer insulating film 83 is made of a material containing, for example, silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.
　次に、工程Ｓ１３において、図２３に示されるように、層間絶縁膜８３及びゲート絶縁膜８１のエッチングが行われることで、層間絶縁膜８３及びゲート絶縁膜８１にコンタクトホール９０が形成される。この結果、ソース領域１３及びコンタクト領域１８が層間絶縁膜８３及びゲート絶縁膜８１から露出する。次に、第１主面１においてソース領域１３及びコンタクト領域１８に接するコンタクト電極６１用の金属膜（図示せず）が形成される。コンタクト電極６１用の金属膜は、例えばスパッタリング法により形成される。コンタクト電極６１用の金属膜は、例えばＮｉを含む材料から構成される。次に、合金化アニールが実施される。コンタクト電極６１用の金属膜が、例えば９００℃以上１１００℃以下の温度で５分程度保持される。これにより、コンタクト電極６１用の金属膜の少なくとも一部が、炭化珪素ウェハ５１が含む珪素と反応してシリサイド化する。これにより、ソース領域１３及びコンタクト領域１８とオーミック接合するコンタクト電極６１が形成される。コンタクト電極６１が、Ｔｉと、Ａｌと、Ｓｉとを含む材料から構成されてもよい。 Next, in step S13, as shown in FIG. 23, the interlayer insulating film 83 and the gate insulating film 81 are etched to form the contact hole 90 in the interlayer insulating film 83 and the gate insulating film 81. As a result, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81. Next, a metal film (not shown) for the contact electrode 61 in contact with the source region 13 and the contact region 18 is formed on the first main surface 1. The metal film for the contact electrode 61 is formed by, for example, a sputtering method. The metal film for the contact electrode 61 is made of, for example, a material containing Ni. Next, alloying annealing is performed. The metal film for the contact electrode 61 is held at a temperature of, for example, 900 ° C. or higher and 1100 ° C. or lower for about 5 minutes. As a result, at least a part of the metal film for the contact electrode 61 reacts with the silicon contained in the silicon carbide wafer 51 to silicide. As a result, the contact electrode 61 that ohmic-bonds with the source region 13 and the contact region 18 is formed. The contact electrode 61 may be made of a material containing Ti, Al, and Si.
　次に、工程Ｓ１４において、図２４に示されるように、ソース配線６２が形成される。具体的には、コンタクト電極６１及び層間絶縁膜８３を覆うソース配線６２が形成される。ソース配線６２は、例えばスパッタリング法による成膜及びＲＩＥにより形成される。ソース配線６２は、例えばアルミニウムを含む材料から構成される。このようにして、コンタクト電極６１とソース配線６２とを有するソース電極６０が形成される。 Next, in step S14, the source wiring 62 is formed as shown in FIG. 24. Specifically, the source wiring 62 that covers the contact electrode 61 and the interlayer insulating film 83 is formed. The source wiring 62 is formed by, for example, film formation by a sputtering method and RIE. The source wiring 62 is made of a material containing, for example, aluminum. In this way, the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.
　次に、工程Ｓ１５において、図２５に示されるように、パッシベーション膜８４が形成される。具体的には、ソース配線６２を覆うパッシベーション膜８４が形成される。パッシベーション膜８４は、例えばポリイミドを含む材料から構成される。パッシベーション膜８４は、例えば塗布法により形成される。パッシベーション膜８４をプラズマＣＶＤ法により形成してもよい。 Next, in step S15, the passivation film 84 is formed as shown in FIG. 25. Specifically, a passivation film 84 that covers the source wiring 62 is formed. The passivation film 84 is made of a material containing, for example, polyimide. The passivation film 84 is formed, for example, by a coating method. The passivation film 84 may be formed by a plasma CVD method.
　次に、工程Ｓ１６において、図１３に示されるように、パッシベーション膜８５の上に接着テープ９６が貼り付けられる。なお、図１３～図１６では、炭化珪素ウェハ５１の第１主面１の上に形成されているパッシベーション膜８４等の図示を省略してある。 Next, in step S16, as shown in FIG. 13, the adhesive tape 96 is attached onto the passivation film 85. In FIGS. 13 to 16, the passivation film 84 and the like formed on the first main surface 1 of the silicon carbide wafer 51 are not shown.
　次に、工程Ｓ１７において、炭化珪素ウェハ５１のバックグラインドが行われる。具体的には、炭化珪素ウェハ５１が第３主面５５側から研削により薄化される。炭化珪素ウェハ５１の研磨は、炭化珪素ウェハ５１の厚さが、炭化珪素半導体装置１００における第１主面１と第２主面２との間の距離Ｌ２に等しくなるまで行う。第１主面１とダイシング溝９５の底面９４と間の距離が第１主面１と第２主面２との間の距離Ｌ２よりも大きいため、第３主面５５の研磨の結果、図７及び図１４に示されるように、炭化珪素ウェハ５１がチップ領域５２毎に個片化される。この結果、チップ領域５２毎に、第１主面１と第２主面２とを備えた炭化珪素基板１０が形成される。 Next, in step S17, the back grind of the silicon carbide wafer 51 is performed. Specifically, the silicon carbide wafer 51 is thinned by grinding from the third main surface 55 side. The silicon carbide wafer 51 is polished until the thickness of the silicon carbide wafer 51 becomes equal to the distance L2 between the first main surface 1 and the second main surface 2 in the silicon carbide semiconductor device 100. Since the distance between the first main surface 1 and the bottom surface 94 of the dicing groove 95 is larger than the distance L2 between the first main surface 1 and the second main surface 2, the result of polishing the third main surface 55 is shown in FIG. As shown in 7 and 14, the silicon carbide wafer 51 is separated into individual pieces for each chip region 52. As a result, the silicon carbide substrate 10 having the first main surface 1 and the second main surface 2 is formed for each chip region 52.
　次に、工程Ｓ１８において、図１５及び図２６に示されるように、第２主面２において炭化珪素単結晶基板５０に接するドレイン電極７０が形成される。このようにして、各チップ領域５２に炭化珪素半導体装置１００が形成される。ダイシング溝９５の側面３が傾斜面２１となり、マーカ９１の側面が面２３となり、マーカ９１の底面が面２２となる。 Next, in step S18, as shown in FIGS. 15 and 26, a drain electrode 70 in contact with the silicon carbide single crystal substrate 50 is formed on the second main surface 2. In this way, the silicon carbide semiconductor device 100 is formed in each chip region 52. The side surface 3 of the dicing groove 95 is the inclined surface 21, the side surface of the marker 91 is the surface 23, and the bottom surface of the marker 91 is the surface 22.
　次に、工程Ｓ１９において、図１６に示されるように、接着テープ９６が炭化珪素半導体装置１００から剥離される。 Next, in step S19, as shown in FIG. 16, the adhesive tape 96 is peeled off from the silicon carbide semiconductor device 100.
　このようにして、第１実施形態に係る炭化珪素半導体装置１００が完成する。 In this way, the silicon carbide semiconductor device 100 according to the first embodiment is completed.
　この製造方法では、ダイシングライン５３に対してハロゲンガスを含む雰囲気で熱エッチングを行ってダイシングライン５３にダイシング溝９５を形成し、炭化珪素ウェハ５１を第３主面５５側から薄化して炭化珪素ウェハ５１を個片化している。このため、ダイシング溝９５の側面９３を第３主面５５に対して傾斜した傾斜面とすることができ、この傾斜面が傾斜面２１となる。従って、傾斜面２１を備えた端面２０を容易に形成できる。 In this manufacturing method, the dicing line 53 is thermally etched in an atmosphere containing halogen gas to form a dicing groove 95 in the dicing line 53, and the silicon carbide wafer 51 is thinned from the third main surface 55 side to form silicon carbide. The wafer 51 is individualized. Therefore, the side surface 93 of the dicing groove 95 can be an inclined surface inclined with respect to the third main surface 55, and this inclined surface becomes the inclined surface 21. Therefore, the end surface 20 provided with the inclined surface 21 can be easily formed.
　また、傾斜面２１が熱エッチングにより形成されるため、傾斜面２１及びその近傍には機械的なダメージが生じにくく、チッピング等の欠陥が生じにくい。従って、炭化珪素半導体装置１００の機械的強度が高く、信頼性を向上できる。例えば、傾斜面２１の表面粗さを、一辺１００ｎｍの正方形領域において算出するような微視的な範囲においてＲＭＳで１．０ｎｍ以下としやすい。 Further, since the inclined surface 21 is formed by thermal etching, mechanical damage is unlikely to occur in the inclined surface 21 and its vicinity, and defects such as chipping are unlikely to occur. Therefore, the mechanical strength of the silicon carbide semiconductor device 100 is high, and the reliability can be improved. For example, the surface roughness of the inclined surface 21 is likely to be 1.0 nm or less in RMS in a microscopic range such as that calculated in a square region having a side of 100 nm.
　また、第３主面５５側からの研削の進行に伴って炭化珪素ウェハ５１がチップ領域５２毎に個片化される。このため、バックグラインドの後にダイサー等を用いてウェハを個片化する場合と比較して、炭化珪素基板１０に作用する圧力を分散でき、機械加工時の割れを低減できる。 Further, as the grinding progresses from the third main surface 55 side, the silicon carbide wafer 51 is separated into individual pieces for each chip region 52. Therefore, as compared with the case where the wafer is fragmented by using a dicer or the like after back grinding, the pressure acting on the silicon carbide substrate 10 can be dispersed and cracks during machining can be reduced.
　なお、熱エッチングは、傾斜面２１が｛０－３３－８｝面となる前に停止してもよい。つまり、傾斜面２１が｛０－３３－８｝面となっていなくてもよい。 Note that the thermal etching may be stopped before the inclined surface 21 becomes a {0-33-8} surface. That is, the inclined surface 21 does not have to be a {0-33-8} surface.
　［第２実施形態］
　次に、第２実施形態について説明する。第２実施形態は、主に外形の点で第１実施形態と相違する。図２７は、第２実施形態に係る炭化珪素半導体装置に含まれる炭化珪素基板の概要を示す平面図である。 [Second Embodiment]
Next, the second embodiment will be described. The second embodiment differs from the first embodiment mainly in terms of outer shape. FIG. 27 is a plan view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the second embodiment.
　図２７に示されるように、第２実施形態に係る炭化珪素半導体装置２００では、第１主面１に垂直な方向から平面視したときに、第２主面２が、４つの角が丸まった角丸長方形状の平面形状を有する。第１主面１に垂直な方向から平面視したときに、第１主面１が、４つの角が丸まった角丸長方形状の平面形状を有してもよい。 As shown in FIG. 27, in the silicon carbide semiconductor device 200 according to the second embodiment, the second main surface 2 has four corners rounded when viewed in a plan view from a direction perpendicular to the first main surface 1. It has a rectangular planar shape with rounded corners. When viewed in a plan view from a direction perpendicular to the first main surface 1, the first main surface 1 may have a planar shape with rounded corners having four rounded corners.
　他の構成は第１実施形態と同様である。 Other configurations are the same as in the first embodiment.
　第２実施形態によっても第１実施形態と同様の効果が得られる。また、第２実施形態では、第２主面２が４つの角が丸まった角丸長方形状の平面形状を有するため、第２主面２の近傍において４隅でのチッピングをより抑制できる。更に、第１主面１が４つの角が丸まった角丸長方形状の平面形状を有すれば、第１主面１の近傍において４隅でのチッピングをより抑制できる。また、４隅における応力の集中を緩和し、応力集中に伴うクラックを抑制できる。また、トランスファモールドにより炭化珪素半導体装置１００を封止する場合に、端面２０の近傍から気泡をより排出させやすく、気泡の残留に伴う実装不良をより抑制しやすい。 The same effect as that of the first embodiment can be obtained by the second embodiment. Further, in the second embodiment, since the second main surface 2 has a rectangular planar shape with rounded corners, chipping at the four corners can be further suppressed in the vicinity of the second main surface 2. Further, if the first main surface 1 has a rectangular planar shape with rounded corners, chipping at the four corners can be further suppressed in the vicinity of the first main surface 1. In addition, stress concentration at the four corners can be relaxed and cracks due to stress concentration can be suppressed. Further, when the silicon carbide semiconductor device 100 is sealed by the transfer mold, it is easier to discharge bubbles from the vicinity of the end face 20, and it is easier to suppress mounting defects due to residual bubbles.
　次に、第２実施形態に係る炭化珪素半導体装置２００の製造方法について説明する。図２８～図２９は、第２実施形態に係る炭化珪素半導体装置の製造方法を示す平面図である。 Next, a method for manufacturing the silicon carbide semiconductor device 200 according to the second embodiment will be described. 28 to 29 are plan views showing a method of manufacturing the silicon carbide semiconductor device according to the second embodiment.
　まず、第１実施形態と同様にして、炭化珪素ウェハ５１の準備（工程Ｓ１）から絶縁膜９２の形成（工程Ｓ４）までの処理が行われる。次いで、図２８に示されるように、絶縁膜９２にマーカ９１の底面を部分的に露出する開口部２９２Ｘを形成する。開口部２９２Ｘの形成では、例えばフォトレジストをエッチングマスクとして用いた絶縁膜２９２のドライエッチングを行う。絶縁膜９２から、第１主面１の一部を覆う被覆部２９２Ｙと、第１主面１の残部を露出する開口部２９２Ｘとを備えたエッチングマスク２９２Ｚが形成される。被覆部２９２Ｙは、第１主面１に垂直な方向から平面視したときに、４つの角が丸まった角丸長方形状の平面形状を有する。 First, in the same manner as in the first embodiment, the processes from the preparation of the silicon carbide wafer 51 (step S1) to the formation of the insulating film 92 (step S4) are performed. Then, as shown in FIG. 28, the insulating film 92 is formed with an opening 292X that partially exposes the bottom surface of the marker 91. In the formation of the opening 292X, for example, dry etching of the insulating film 292 using a photoresist as an etching mask is performed. From the insulating film 92, an etching mask 292Z having a covering portion 292Y that covers a part of the first main surface 1 and an opening portion 292X that exposes the rest of the first main surface 1 is formed. The covering portion 292Y has a rectangular planar shape with rounded corners when viewed in a plan view from a direction perpendicular to the first main surface 1.
　次に、エッチングマスク２９２Ｚを用いて、平面視でマーカ９１の内側に、ダイシング溝２９５が形成される。ダイシング溝２９５は、ダイシング溝９５と同様に、エッチングマスク２９２Ｚを用いたＲＩＥ及び熱エッチングにより形成できる。次に、図２９に示されるように、エッチングマスク２９２Ｚが第１主面１から除去される。 Next, using the etching mask 292Z, a dicing groove 295 is formed inside the marker 91 in a plan view. The dicing groove 295 can be formed by RIE and thermal etching using the etching mask 292Z, similarly to the dicing groove 95. Next, as shown in FIG. 29, the etching mask 292Z is removed from the first main surface 1.
　その後、第１実施形態と同様に、活性化熱処理（工程Ｓ８）から接着テープ９６の剥離（工程Ｓ１９）までの処理が行われる。 After that, the treatment from the activation heat treatment (step S8) to the peeling of the adhesive tape 96 (step S19) is performed as in the first embodiment.
　このようにして、第２実施形態に係る炭化珪素半導体装置２００が完成する。 In this way, the silicon carbide semiconductor device 200 according to the second embodiment is completed.
　この製造方法によっても、第１実施形態と同様の効果が得られる。また、４つの角が丸まった角丸長方形状の平面形状を有する被覆部２９２Ｙを含むエッチングマスク２９２Ｚを用いた熱エッチングを経てダイシング溝２９５が形成されるため、第２主面２の平面形状を、容易に４つの角が丸まった角丸長方形状の平面形状とすることができる。また、第１主面１の平面形状を、容易に４つの角が丸まった角丸長方形状の平面形状とすることもできる。 The same effect as that of the first embodiment can be obtained by this manufacturing method. Further, since the dicing groove 295 is formed through thermal etching using an etching mask 292Z including a covering portion 292Y having a rectangular planar shape with rounded corners, the planar shape of the second main surface 2 is formed. , It is possible to easily form a flat surface shape having a rounded rectangular shape with four rounded corners. Further, the planar shape of the first main surface 1 can be easily changed to a rectangular planar shape with rounded corners.
　なお、４隅のすべてが角丸形状となっている必要はなく、１隅だけでも角丸形状となっていれば、当該隅において上記の効果が得られる。 It is not necessary that all four corners have a rounded shape, and if only one corner has a rounded shape, the above effect can be obtained at that corner.
　［変形例］
　次に、第１実施形態の変形例について説明する。変形例は、主に外形の点で第１実施形態と相違する。図３０は、第１実施形態の変形例に係る炭化珪素半導体装置に含まれる炭化珪素基板の概要を示す断面図である。 [Modification example]
Next, a modification of the first embodiment will be described. The modified example differs from the first embodiment mainly in terms of the outer shape. FIG. 30 is a cross-sectional view showing an outline of a silicon carbide substrate included in the silicon carbide semiconductor device according to the modified example of the first embodiment.
　図３０に示されるように、第１実施形態の変形例に係る炭化珪素半導体装置１００Ａでは、第１主面１に垂直な方向から平面視したときに、第１主面１の輪郭が第２主面２の輪郭の外側にある。傾斜面２１は、第１主面１側ほど広がるように傾斜している。すなわち、断面視において、傾斜面２１と第２主面２とがなす角の内角は鈍角であり、傾斜面２１は、第２主面２に近づくほど、第２主面２の内側に入るように傾斜している。傾斜面２１と第２主面２とのなす角度θ２は、例えば５０°以上６５°以下である。角度θ２は、例えば５５°以上であってもよい。角度θ２は、例えば６０°以下であってもよい。傾斜面２１は、好ましくは、｛０－３３－８｝面を有する。 As shown in FIG. 30, in the silicon carbide semiconductor device 100A according to the modified example of the first embodiment, the contour of the first main surface 1 is the second when viewed in a plan view from the direction perpendicular to the first main surface 1. It is outside the contour of the main surface 2. The inclined surface 21 is inclined so as to expand toward the first main surface 1 side. That is, in the cross-sectional view, the internal angle of the angle formed by the inclined surface 21 and the second main surface 2 is an obtuse angle, and the inclined surface 21 enters the inside of the second main surface 2 as it approaches the second main surface 2. Is inclined to. The angle θ2 formed by the inclined surface 21 and the second main surface 2 is, for example, 50 ° or more and 65 ° or less. The angle θ2 may be, for example, 55 ° or more. The angle θ2 may be, for example, 60 ° or less. The inclined surface 21 preferably has a {0-33-8} surface.
　他の構成は第１実施形態と同様である。 Other configurations are the same as in the first embodiment.
　第１実施形態の変形例に係る炭化珪素半導体装置１００Ａによっても、第１実施形態と同様に、端面２０を経路として第１主面１と第２主面２との間を流れるリーク電流を低減でき、放熱性を向上できる。 Similarly to the first embodiment, the silicon carbide semiconductor device 100A according to the modified example of the first embodiment also reduces the leakage current flowing between the first main surface 1 and the second main surface 2 with the end surface 20 as a path. It can improve heat dissipation.
　第２実施形態の変形例として、第１実施形態の変形例と同様に、傾斜面２１が第１主面１側ほど広がるように傾斜していてもよい。すなわち、断面視において、傾斜面２１と第２主面２とがなす角の内角が鈍角であってもよい。 As a modification of the second embodiment, the inclined surface 21 may be inclined so as to expand toward the first main surface 1 side as in the modification of the first embodiment. That is, in the cross-sectional view, the internal angle of the angle formed by the inclined surface 21 and the second main surface 2 may be an obtuse angle.
　以上、実施形態について詳述したが、特定の実施形態に限定されるものではなく、請求の範囲に記載された範囲内において、種々の変形および変更が可能である。 Although the embodiments have been described in detail above, the embodiments are not limited to the specific embodiments, and various modifications and changes can be made within the scope of the claims.
　１　第１主面
　２　第２主面
　３　側面
　４　底面
　５　ゲートトレンチ
　１０　炭化珪素基板
　１１　ドリフト領域
　１２　ボディ領域
　１３　ソース領域
　１８　コンタクト領域
　２０　端面
　２１　傾斜面
　２２、２３　面
　４０　炭化珪素エピタキシャル層
　５０　炭化珪素単結晶基板
　５１　炭化珪素ウェハ
　５２　チップ領域
　５３　ダイシングライン
　５５　第３主面
　６０　ソース電極
　６１　コンタクト電極
　６２　ソース配線
　７０　ドレイン電極
　８１　ゲート絶縁膜
　８２　ゲート電極
　８３　層間絶縁膜
　８４　パッシベーション膜
　９０　コンタクトホール
　９１　マーカ
　９２、２９２　絶縁膜
　９２Ｘ、２９２Ｘ　開口部
　９２Ｙ、２９２Ｙ　被覆部
　９２Ｚ、２９２Ｚ　エッチングマスク
　９３　側面
　９４　底面
　９５、２９５　ダイシング溝
　９６　接着テープ
　１００、１００Ａ、２００　炭化珪素半導体装置 1 1st main surface 2 2nd main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift area 12 Body area 13 Source area 18 Contact area 20 End surface 21 Inclined surface 22, 23 surface 40 Silicon carbide epitaxial layer 50 Silicon carbide Single crystal substrate 51 Silicon carbide wafer 52 Chip area 53 Dicing line 55 Third main surface 60 Source electrode 61 Contact electrode 62 Source wiring 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Passion film 90 Contact hole 91 Marker 92 , 292 Insulating film 92X, 292X Opening 92Y, 292Y Coating part 92Z, 292Z Etching mask 93 Side surface 94 Bottom surface 95, 295 Dicing groove 96 Adhesive tape 100, 100A, 200 Silicon carbide semiconductor device

Claims (12)

  1. 　第１主面と、前記第１主面と反対側の第２主面とを有する炭化珪素基板を備え、
    　前記炭化珪素基板は、前記第１主面と前記第２主面とをつなぐ端面を有し、
    　前記端面は、前記第２主面との境界から連続し、前記第２主面に対して傾斜した傾斜面を含む炭化珪素半導体装置。     A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface is provided.
    The silicon carbide substrate has an end surface connecting the first main surface and the second main surface.
    A silicon carbide semiconductor device in which the end surface is continuous from a boundary with the second main surface and includes an inclined surface inclined with respect to the second main surface.
  2. 　前記炭化珪素基板は、
    　前記第２主面を含む炭化珪素単結晶基板と、
    　前記第１主面を含む炭化珪素エピタキシャル層と、
    　を有する請求項１に記載の炭化珪素半導体装置。     The silicon carbide substrate is
    The silicon carbide single crystal substrate including the second main surface and
    The silicon carbide epitaxial layer containing the first main surface and
    The silicon carbide semiconductor device according to claim 1.
  3. 　断面視において、前記傾斜面と前記第２主面とがなす角の内角は鋭角である請求項１または請求項２に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 1 or 2, wherein the internal angle of the angle formed by the inclined surface and the second main surface is an acute angle in a cross-sectional view.
  4. 　断面視において、前記傾斜面と前記第２主面とがなす角の内角は鈍角である請求項１または請求項２に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 1 or 2, wherein the internal angle of the angle formed by the inclined surface and the second main surface is an obtuse angle in a cross-sectional view.
  5. 　前記傾斜面と前記第２主面とのなす角度は、５０°以上６５°以下である請求項３または請求項４に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to claim 3 or 4, wherein the angle formed by the inclined surface and the second main surface is 50 ° or more and 65 ° or less.
  6. 　前記傾斜面は、｛０－３３－８｝面を含む請求項１から請求項５のいずれか１項に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein the inclined surface includes a {0-33-8} surface.
  7. 　前記傾斜面の一辺１００ｎｍの正方形領域内における表面粗さはＲＭＳで１．０ｎｍ以下である請求項１から請求項６のいずれか１項に記載の炭化珪素半導体装置。 The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein the surface roughness in a square region having a side of 100 nm on the inclined surface is 1.0 nm or less in RMS.
  8. 　前記第１主面に垂直な方向から平面視したときに、前記第２主面は、少なくとも１つの角が丸まった角丸長方形状の平面形状を有する請求項１から請求項７のいずれか１項に記載の炭化珪素半導体装置。 Any one of claims 1 to 7, wherein the second main surface has a rectangular planar shape with at least one rounded corner when viewed in a plan view from a direction perpendicular to the first main surface. The silicon carbide semiconductor device according to the section.
  9. 　第１主面と、前記第１主面と反対側の第３主面とを有し、前記第１主面にダイシングラインを備えた炭化珪素ウェハを準備する工程と、
    　前記ダイシングラインに対してハロゲンガスを含む雰囲気で熱エッチングを行って前記ダイシングラインに溝を形成する工程と、
    　前記炭化珪素ウェハを前記第３主面から薄化して前記炭化珪素ウェハを個片化する工程と、
    　を有する炭化珪素半導体装置の製造方法。     A step of preparing a silicon carbide wafer having a first main surface and a third main surface opposite to the first main surface and having a dicing line on the first main surface.
    A step of performing thermal etching on the dicing line in an atmosphere containing halogen gas to form a groove in the dicing line, and
    A step of thinning the silicon carbide wafer from the third main surface to separate the silicon carbide wafer into individual pieces.
    A method for manufacturing a silicon carbide semiconductor device having the above.
  10. 　前記炭化珪素ウェハを個片化する工程は、前記炭化珪素ウェハを前記第３主面側から研削する工程を有する請求項９に記載の炭化珪素半導体装置の製造方法。 The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein the step of fragmenting the silicon carbide wafer is a step of grinding the silicon carbide wafer from the third main surface side.
  11. 　前記炭化珪素ウェハを準備する工程は、前記第３主面を含む炭化珪素単結晶基板の上に、前記第１主面を含む炭化珪素エピタキシャル層を形成する工程を有する請求項９または請求項１０に記載の炭化珪素半導体装置の製造方法。 9. or 10. The step of preparing the silicon carbide wafer includes a step of forming a silicon carbide epitaxial layer including the first main surface on the silicon carbide single crystal substrate including the third main surface. The method for manufacturing a silicon carbide semiconductor device according to the above.
  12. 　前記ダイシングラインに対して熱エッチングを行う工程は、前記第１主面の一部を覆う被覆部と、前記第１主面の残部を露出する開口部とを備えたエッチングマスクを前記第１主面の上に形成する工程を有し、
    　前記第１主面に垂直な方向から平面視したときに、前記被覆部は、少なくとも１つの角が丸まった角丸長方形状の平面形状を有する請求項９から請求項１１のいずれか１項に記載の炭化珪素半導体装置の製造方法。     In the step of performing thermal etching on the dicing line, the first main surface is an etching mask provided with a covering portion that covers a part of the first main surface and an opening portion that exposes the rest of the first main surface. Has a process of forming on the surface,
    The aspect according to any one of claims 9 to 11, wherein the covering portion has a planar shape having a rounded rectangular shape having at least one rounded corner when viewed in a plan view from a direction perpendicular to the first main surface. The method for manufacturing a silicon carbide semiconductor device according to the description.
PCT/JP2021/035303 2020-11-06 2021-09-27 Silicon carbide semiconductor device and method for producing silicon carbide semiconductor device WO2022097386A1 (en)

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