JP7298294B2 - Silicon carbide epitaxial substrate, silicon carbide semiconductor chip and silicon carbide semiconductor module - Google Patents

Description

The present disclosure relates to silicon carbide epitaxial substrates, silicon carbide semiconductor chips and silicon carbide semiconductor modules.

International Publication No. 2017/203623 (Patent Document 1) describes a power module in which a plurality of silicon carbide switching elements are mounted on a substrate.

WO2017/203623

An object of the present disclosure is to improve reliability of a silicon carbide semiconductor module.

A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate and a silicon carbide epitaxial layer. A silicon carbide epitaxial layer overlies the silicon carbide substrate. In the direction parallel to the main surface of the silicon carbide epitaxial layer, the maximum lifetime is defined as the maximum carrier lifetime in the silicon carbide epitaxial layer, and the minimum lifetime is defined as the minimum carrier lifetime in the silicon carbide epitaxial layer. The value obtained by dividing the value obtained by subtracting by the maximum life is 0.05 or more and 0.2 or less.

A silicon carbide semiconductor chip according to the present disclosure includes a silicon carbide epitaxial substrate, a first electrode, and a second electrode. The silicon carbide epitaxial substrate includes a silicon carbide substrate having a first conductivity type and a silicon carbide epitaxial layer on the silicon carbide substrate. The silicon carbide epitaxial layer has a first conductivity type silicon carbide layer in contact with the silicon carbide substrate and a second conductivity type silicon carbide layer on the first conductivity type silicon carbide layer. The first electrode is in contact with the second conductivity type silicon carbide layer. The second electrode is in contact with the silicon carbide substrate. In the direction parallel to the main surface of the silicon carbide epitaxial substrate, the maximum carrier lifetime in the first conductivity type silicon carbide layer is defined as the maximum lifetime, and the minimum carrier lifetime in the first conductivity type silicon carbide layer is defined as the minimum lifetime. , the value obtained by dividing the value obtained by subtracting the minimum life from the maximum life by the maximum life is 0.05 or more and 0.2 or less.

A silicon carbide semiconductor module according to the present disclosure includes a circuit board and a plurality of silicon carbide semiconductor chips. A plurality of silicon carbide semiconductor chips are mounted on a circuit board. Each of the plurality of silicon carbide semiconductor chips includes a silicon carbide epitaxial substrate, a first electrode, and a second electrode. The silicon carbide epitaxial substrate has a silicon carbide substrate having a first conductivity type and a silicon carbide epitaxial layer on the silicon carbide substrate. The silicon carbide epitaxial layer has a first conductivity type silicon carbide layer in contact with the silicon carbide substrate and a second conductivity type silicon carbide layer on the first conductivity type silicon carbide layer. The first electrode is in contact with the second conductivity type silicon carbide layer. The second electrode is in contact with the silicon carbide substrate. In the plurality of silicon carbide semiconductor chips, when the maximum carrier lifetime in the first conductivity type silicon carbide layer is defined as the maximum lifetime and the minimum carrier lifetime in the first conductivity type silicon carbide layer is defined as the minimum lifetime, the maximum lifetime to the minimum The value obtained by dividing the value obtained by subtracting the service life by the maximum service life is 0.05 or more and 0.2 or less.

According to the present disclosure, reliability of a silicon carbide semiconductor module can be improved.

FIG. 1 is a schematic plan view showing the configuration of a silicon carbide epitaxial substrate according to this embodiment. FIG. 2 is a schematic cross-sectional view taken along line II-II of FIG. FIG. 3 is a schematic plan view showing the configuration of the silicon carbide semiconductor module according to the first embodiment. FIG. 4 is a schematic cross-sectional view taken along line IV-IV of FIG. FIG. 5 is a schematic plan view showing the configuration of the first silicon carbide semiconductor chip. FIG. 6 is a schematic cross-sectional view taken along line VI-VI of FIG. FIG. 7 is a schematic plan view showing the configuration of the second silicon carbide semiconductor chip. FIG. 8 is a schematic cross-sectional view taken along line VIII-VIII of FIG. FIG. 9 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor module according to the second embodiment. FIG. 10 is a schematic cross-sectional view showing the first step of the method for manufacturing a silicon carbide epitaxial substrate according to this embodiment. FIG. 11 is a schematic cross-sectional view showing the second step of the method for manufacturing a silicon carbide epitaxial substrate according to this embodiment. FIG. 12 is a schematic cross-sectional view showing the third step of the method for manufacturing a silicon carbide epitaxial substrate according to this embodiment. FIG. 13 is a schematic cross-sectional view showing the first step of the method for manufacturing a silicon carbide semiconductor chip according to this embodiment. FIG. 14 is a schematic cross-sectional view showing the second step of the method for manufacturing a silicon carbide semiconductor chip according to this embodiment. FIG. 15 is a schematic cross-sectional view showing the third step of the method for manufacturing a silicon carbide semiconductor chip according to this embodiment.

[Description of Embodiments of the Present Disclosure]
First, the embodiments of the present disclosure will be enumerated and described. In the crystallographic description of this specification, individual orientations are indicated by [ ], collective orientations by <>, individual planes by ( ), and collective planes by { }. Negative crystallographic exponents are usually expressed by placing a "-" (bar) above the number, but here the crystallographic index is expressed by prefixing the number with a negative sign. Represents a negative exponent above.

(1) Silicon carbide epitaxial substrate 100 according to the present disclosure includes silicon carbide substrate 4 and silicon carbide epitaxial layer 3 . Silicon carbide epitaxial layer 3 is on silicon carbide substrate 4 . In a direction parallel to main surface 1 of silicon carbide epitaxial layer 3, when the maximum carrier lifetime in silicon carbide epitaxial layer 3 is defined as the maximum lifetime and the minimum carrier lifetime in silicon carbide epitaxial layer 3 is defined as the minimum lifetime, the maximum The value obtained by dividing the value obtained by subtracting the minimum life from the life by the maximum life is 0.05 or more and 0.2 or less.

(2) In silicon carbide epitaxial substrate 100 according to (1) above, the minimum lifetime may be 0.5 μsec or more.

(3) In silicon carbide epitaxial substrate 100 according to (1) or (2) above, silicon carbide epitaxial layer 3 may have a thickness of 5 μm or more and 50 μm or less.

(4) Silicon carbide semiconductor chip 200 according to the present disclosure includes silicon carbide epitaxial substrate 100 , first electrode 60 , and second electrode 63 . Silicon carbide epitaxial substrate 100 includes silicon carbide substrate 4 having a first conductivity type and silicon carbide epitaxial layer 3 on silicon carbide substrate 4 . Silicon carbide epitaxial layer 3 has a first conductivity type silicon carbide layer 10 in contact with silicon carbide substrate 4 and a second conductivity type silicon carbide layer 8 on first conductivity type silicon carbide layer 10 . First electrode 60 is in contact with second conductivity type silicon carbide layer 8 . Second electrode 63 is in contact with silicon carbide substrate 4 . In the direction parallel to first main surface 1 of silicon carbide epitaxial substrate 100, the maximum value of carrier lifetime in first conductivity type silicon carbide layer 10 is defined as the maximum lifetime, and the minimum value of carrier lifetime in first conductivity type silicon carbide layer 10. is the minimum life, the value obtained by dividing the value obtained by subtracting the minimum life from the maximum life by the maximum life is 0.05 or more and 0.2 or less.

(5) Silicon carbide semiconductor module 300 according to the present disclosure includes circuit board 20 and a plurality of silicon carbide semiconductor chips 200 . A plurality of silicon carbide semiconductor chips 200 are mounted on circuit board 20 . Each of silicon carbide semiconductor chips 200 includes a silicon carbide epitaxial substrate 100 , a first electrode 60 and a second electrode 63 . Silicon carbide epitaxial substrate 100 has silicon carbide substrate 4 having a first conductivity type and silicon carbide epitaxial layer 3 on silicon carbide substrate 4 . Silicon carbide epitaxial layer 3 has a first conductivity type silicon carbide layer 10 in contact with silicon carbide substrate 4 and a second conductivity type silicon carbide layer 8 on first conductivity type silicon carbide layer 10 . First electrode 60 is in contact with second conductivity type silicon carbide layer 8 . Second electrode 63 is in contact with silicon carbide substrate 4 . Among the average carrier lifetimes of each of the plurality of silicon carbide semiconductor chips 200, the maximum value of the average carrier lifetime in the first conductivity type silicon carbide layer 10 is defined as the maximum lifetime, and the average carrier lifetime in the first conductivity type silicon carbide layer 10 is When the minimum value is defined as the minimum life, the value obtained by dividing the value obtained by subtracting the minimum life from the maximum life by the maximum life is 0.05 or more and 0.2 or less.

(6) In silicon carbide semiconductor module 300 according to (5) above, each of silicon carbide semiconductor chips 200 may include transistor 150 and diode 151 .

(7) In silicon carbide semiconductor module 300 according to (5) above, silicon carbide semiconductor chips 200 include first silicon carbide semiconductor chip 210 including transistor 150 and second silicon carbide semiconductor chip 220 including diode 151. may have
[Details of the embodiment of the present disclosure]
Details of the embodiments of the present disclosure will be described below. In the following description, the same or corresponding elements are given the same reference numerals and the same descriptions thereof are not repeated.

(Silicon carbide epitaxial substrate)
First, the configuration of silicon carbide epitaxial substrate 100 according to the present embodiment will be described. FIG. 1 is a schematic plan view showing the configuration of a silicon carbide epitaxial substrate 100 according to this embodiment. FIG. 2 is a schematic cross-sectional view taken along line II-II of FIG.

As shown in FIGS. 1 and 2 , silicon carbide epitaxial substrate 100 has silicon carbide substrate 4 and silicon carbide epitaxial layer 3 . Silicon carbide epitaxial layer 3 is on silicon carbide substrate 4 . Silicon carbide epitaxial substrate 100 has a first main surface 1 , a second main surface 2 and a peripheral edge 27 . The second major surface 2 is opposite the first major surface 1 . First main surface 1 is formed of silicon carbide epitaxial layer 3 . Second main surface 2 is formed of silicon carbide substrate 4 . Silicon carbide substrate 4 and silicon carbide epitaxial layer 3 are each made of, for example, hexagonal silicon carbide. Silicon carbide substrate 4 and silicon carbide epitaxial layer 3 each have a polytype of 4H, for example.

As shown in FIG. 1, the maximum diameter (diameter W1) of first main surface 1 is, for example, 150 mm. The diameter W1 may be 150 mm or more, 200 mm or more, or 250 mm or more. Although the upper limit of the diameter W1 is not particularly limited, it may be 300 mm or less, for example. The first main surface 1 is composed of a central region 11 and an outer peripheral region 12 . The outer peripheral region 12 is continuous with the central region 11 . Peripheral region 12 surrounds central region 11 . Peripheral region 12 is outside central region 11 . Peripheral region 12 is, for example, a region within 3 mm from peripheral edge 27 . In the radial direction of the first main surface 1, the width of the outer peripheral region 12 (the outer peripheral width W2) may be, for example, 3 mm or more and 5 mm or less.

As shown in FIG. 1 , the first main surface 1 extends along each of the first direction 101 and the second direction 102 . The first direction 101 is, for example, the <11-20> direction. The second direction 102 is, for example, the <1-100> direction. The first main surface 1 is the {0001} plane or a plane inclined with respect to the {0001} plane. Specifically, the first main surface 1 is, for example, the (0001) plane or a plane inclined by an angle of 8° or less with respect to the (0001) plane. The first main surface 1 may be the (000-1) plane or a plane inclined at an angle of 8° or less with respect to the (000-1) plane. When first main surface 1 is inclined with respect to the {0001} plane, the inclination direction (off direction) of first main surface 1 with respect to the {0001} plane is, for example, the <11-20> direction.

As shown in FIG. 1, the peripheral edge 27 is continuous with the outer peripheral region 12 . The peripheral edge 27 has an orientation flat portion 25 and an arcuate portion 26 . The arcuate portion 26 continues to the orientation flat portion 25 . As shown in FIG. 1 , orientation flat portion 25 extends along first direction 101 when viewed from a direction perpendicular to first main surface 1 .

As shown in FIG. 2, thickness T of silicon carbide epitaxial layer 3 is, for example, 50 μm or less. Thickness T of silicon carbide epitaxial layer 3 may be 40 μm or less, or may be 30 μm or less. Silicon carbide epitaxial layer 3 may have thickness T of, for example, 5 μm or more. Silicon carbide substrate 4 and silicon carbide epitaxial layer 3 each contain nitrogen (N) as an n-type impurity, for example. The conductivity type of each of silicon carbide substrate 4 and silicon carbide epitaxial layer 3 is, for example, n type (first conductivity type). The impurity concentration of silicon carbide substrate 4 may be higher than the impurity concentration of silicon carbide epitaxial layer 3 .

As shown in FIG. 2, silicon carbide substrate 4 includes basal plane dislocations 9 . In a plane parallel to the second main surface 2, the areal density of the basal plane dislocations 9 is, for example, higher than 100 cm ⁻² and lower than 1000 cm ⁻² . As shown in FIG. 2 , silicon carbide epitaxial substrate 100 has point defects 41 called Z _1/2 . Point defects 41 are caused by carbon vacancies. The energy level of Z _1/2 is Ec (the energy at the bottom of the conduction band) −0.65 eV. Higher Z1 _/2 densities lead to shorter carrier lifetimes.

In silicon carbide epitaxial substrate 100 according to the present embodiment, variations in Z _1/2 density are reduced in the direction parallel to first main surface 1 of silicon carbide epitaxial layer 3 . From another point of view, in-plane uniformity of Z _1/2 density is high in the direction parallel to first main surface 1 of silicon carbide epitaxial layer 3 . Specifically, in the direction parallel to first main surface 1 of silicon carbide epitaxial layer 3, the maximum value of Z _1/2 density in silicon carbide epitaxial layer 3 is the maximum density, and Z _{1/2 in silicon carbide epitaxial layer 3 is} When the minimum value of _{the two} densities is defined as the minimum density, the value obtained by dividing the value obtained by subtracting the minimum density from the maximum density by the maximum density is 0.05 or more and 0.2 or less.

A value obtained by dividing a value obtained by subtracting the minimum density from the maximum density by the maximum density may be, for example, 0.06 or more, or may be 0.07 or more. The value obtained by dividing the value obtained by subtracting the minimum density from the maximum density by the maximum density may be, for example, 0.19 or less, or may be 0.18 or less.

The maximum density is, for example, 2×10 ¹³ cm ⁻³ or less. The maximum density may be, for example, 1×10 ¹³ cm ⁻³ or less, or 9×10 ¹² cm ⁻³ or less. The minimum density is, for example, 1×10 ¹¹ cm ⁻³ or more. The minimum density may be, for example, 3×10 ¹¹ cm ⁻³ or more, or 5×10 ¹¹ cm ⁻³ or more.

Next, a method for measuring Z _1/2 density will be described.
The Z _1/2 density can be measured by a DLTS (Deep Level Transient Spectroscopy) method. According to the DLTS method, the Z _1/2 density is determined based on transient changes in junction capacitance. As a measuring device, for example, FT1230 manufactured by Phystech can be used. The measurement frequency is 1 MHz, and the measurement temperature is 150K or more and 500K or less. A Ni electrode with a diameter of 1 mm or the like can be used as the Schottky electrode.

First, a first measurement electrode (Schottky electrode) is formed on first main surface 1 of silicon carbide epitaxial substrate 100 . A second measurement electrode (ohmic electrode) is formed on the second main surface 2 . Z _1/2 density is determined based on transient changes in junction capacitance between a first measurement electrode (not shown) and a second measurement electrode (not shown). A first measurement electrode is formed in each of the plurality of measurement regions S shown in FIG. A first measurement electrode is formed in the central region 11 . Specifically, a plurality of first measurement electrodes are provided in a direction parallel to the first direction 101 passing through the center 13 of the first main surface 1 and in the second direction 102 passing through the center 13 of the first main surface 1 . A plurality of them are provided in parallel directions. A measurement pitch is, for example, 3 mm. For example, a total of 100 (50 along the first direction 101 and 50 along the second direction 102) first measuring electrodes are formed on the first major surface 1 . A second measurement electrode is formed on the entire surface of the second main surface 2 .

Next, the Z _1/2 density in each of the plurality of measurement regions S is determined. Among the Z _1/2 densities in each of the plurality of measurement regions S, the maximum Z _1/2 density is the maximum density, and the minimum Z _1/2 density is the minimum density.

Next, carrier lifetime of silicon carbide epitaxial substrate 100 will be described.
In silicon carbide epitaxial substrate 100 , variation in carrier lifetime is reduced in the direction parallel to first main surface 1 of silicon carbide epitaxial layer 3 . From another point of view, in-plane uniformity of carrier lifetime is high in the direction parallel to first main surface 1 of silicon carbide epitaxial layer 3 . Specifically, in the direction parallel to first main surface 1 of silicon carbide epitaxial layer 3, the maximum carrier lifetime in silicon carbide epitaxial layer 3 is defined as the maximum lifetime, and the minimum carrier lifetime in silicon carbide epitaxial layer 3 is defined as Assuming the minimum life, the value obtained by dividing the value obtained by subtracting the minimum life from the maximum life by the maximum life is 0.05 or more and 0.2 or less.

A value obtained by dividing a value obtained by subtracting the minimum life span from the maximum life span by the maximum life span may be, for example, 0.06 or more, or may be 0.07 or more. The value obtained by dividing the value obtained by subtracting the minimum life span from the maximum life span by the maximum life span may be, for example, 0.19 or less, or may be 0.18 or less.

A minimum lifetime is, for example, 0.5 μs or more. The minimum lifetime may be, for example, 0.7 μs or longer, or 0.9 μs or longer. The maximum lifetime is, for example, 40 μs or less. The maximum lifetime may be, for example, 30 μs or less, or 20 μs or less.

Next, a method for measuring carrier lifetime will be described.
The carrier lifetime can be measured by μ-PCD (Microwave Photo Conductivity Decay) method. According to the μ-PCD method, excess carriers are generated by irradiating the silicon carbide epitaxial layer 3 with an excitation laser, and the electrical conductivity, which decreases as the excess carriers recombine, is measured from the microwave reflectance. and the carrier lifetime is required. LTA-2200EP/F manufactured by Kobelco Research Institute can be used as a measuring device. The excitation laser is, for example, a YLF (Yttrium Lithium Fluoride) laser with a wavelength of 349 nm, and a microwave frequency of 26 GHz can be used. The time constant obtained from the region in which the attenuation of the intensity of the signal corresponding to the minority carrier excited and generated by laser irradiation can be regarded as an exponential function is defined as the lifetime of the minority carrier.

First, silicon carbide epitaxial substrate 100 is placed on the stage of the measuring apparatus. By moving the stage in the XY plane, carrier lifetimes can be measured in a plurality of measurement regions S on the first main surface 1 . Specifically, the carrier lifetime is measured in each of the plurality of measurement regions S shown in FIG. For example, by moving silicon carbide epitaxial substrate 100 along first direction 101 , carrier lifetimes are measured in a plurality of measurement regions S along first direction 101 . Next, by moving silicon carbide epitaxial substrate 100 along second direction 102 , carrier lifetimes are measured in a plurality of measurement regions S along second direction 102 . A measurement pitch is, for example, 3 mm. For example, the carrier lifetime is measured in a total of 100 measurement regions S (50 along the first direction 101 and 50 along the second direction 102). Among the carrier lifetimes in each of the plurality of measurement regions S, the maximum carrier lifetime is defined as the maximum lifetime, and the minimum carrier lifetime is defined as the minimum lifetime.

(Silicon carbide semiconductor module)
Next, the configuration of silicon carbide semiconductor module 300 according to the first embodiment will be described. FIG. 3 is a schematic plan view showing the configuration of a silicon carbide semiconductor module 300 according to the first embodiment.

As shown in FIG. 3 , silicon carbide semiconductor module 300 has circuit board 20 and a plurality of silicon carbide semiconductor chips 200 . Each of silicon carbide semiconductor chips 200 is mounted on circuit board 20 . In plan view, the circuit board 20 has, for example, a rectangular shape. The number of silicon carbide semiconductor chips 200 is not particularly limited, but is, for example, four. As shown in FIG. 3 , a total of two silicon carbide semiconductor chips 200 may be arranged in a two-row, two-column arrangement in plan view. The number of silicon carbide semiconductor chips 200 may be, for example, four or more, six or more, or eight or more.

FIG. 4 is a schematic cross-sectional view taken along line IV-IV of FIG. As shown in FIG. 4, the circuit board 20 has a substrate 24 and circuit patterns 23 . The circuit pattern 23 is provided on the base material 24 . Base material 24 is made of, for example, an insulating material. Circuit pattern 23 is made of, for example, a conductive material. The circuit board 20 has a third principal surface 21 and a fourth principal surface 22 . The fourth principal surface 22 is the surface opposite to the third principal surface 21 . The third principal surface 21 is configured with a circuit pattern 23 . The fourth major surface 22 is composed of a base material 24 .

As shown in FIG. 4 , silicon carbide semiconductor module 300 has joining member 50 . Silicon carbide semiconductor chip 200 is mounted on circuit board 20 using bonding member 50 . Joining member 50 is positioned between silicon carbide semiconductor chip 200 and circuit board 20 . Joining member 50 is, for example, solder. The joining member 50 may be made of any conductive material, and is not limited to solder. The joining member 50 may be silver paste or the like, for example. As shown in FIG. 4 , the joint member 50 is electrically connected to the circuit pattern 23 on the third main surface 21 . Joining member 50 is electrically connected to silicon carbide semiconductor chip 200 . Silicon carbide semiconductor chip 200 is electrically connected to circuit pattern 23 via joining member 50 .

As shown in FIG. 3 , in a silicon carbide semiconductor module 300 according to this embodiment, the plurality of silicon carbide semiconductor chips 200 has a first silicon carbide semiconductor chip 210 and a second silicon carbide semiconductor chip 220. may Silicon carbide semiconductor module 300 according to the present embodiment has, for example, two first silicon carbide semiconductor chips 210 and two second silicon carbide semiconductor chips 220 .

(Silicon carbide semiconductor chip)
Next, the configuration of first silicon carbide semiconductor chip 210 will be described. FIG. 5 is a schematic plan view showing the configuration of first silicon carbide semiconductor chip 210 . FIG. 6 is a schematic cross-sectional view taken along line VI-VI of FIG.

As shown in FIG. 6 , first silicon carbide semiconductor chip 210 includes transistor 150 . Transistor 150 mainly has silicon carbide epitaxial substrate 100 , first electrode 60 , second electrode 63 , gate electrode 64 , gate insulating film 71 and isolation insulating film 72 . Silicon carbide epitaxial substrate 100 has silicon carbide substrate 4 and silicon carbide epitaxial layer 3 on silicon carbide substrate 4 . Silicon carbide epitaxial layer 3 includes a first conductivity type silicon carbide layer 10 , a second conductivity type silicon carbide layer 8 , a body region 30 and a source region 40 . First conductivity type silicon carbide layer 10 is in contact with silicon carbide substrate 4 . Second conductivity type silicon carbide layer 8 is on first conductivity type silicon carbide layer 10 . Second conductivity type silicon carbide layer 8 continues to first conductivity type silicon carbide layer 10 . First conductivity type silicon carbide layer 10 is, for example, an n-type silicon carbide layer. The second conductivity type layer is, for example, a p-type silicon carbide layer.

As shown in FIG. 6 , silicon carbide epitaxial substrate 100 has first main surface 1 and second main surface 2 . The second major surface 2 is opposite the first major surface 1 . First conductivity type silicon carbide layer 10 is, for example, drift region 10 . First conductivity type silicon carbide layer 10 is provided on silicon carbide substrate 4 . Second conductivity type silicon carbide layer 8 is, for example, contact region 8 . Silicon carbide substrate 4 includes basal plane dislocations 9 . In a plane parallel to the second main surface 2, the areal density of the basal plane dislocations 9 is, for example, higher than 100 cm ⁻² and lower than 1000 cm ⁻² .

First electrode 60 is provided on second conductivity type silicon carbide layer 8 . From another point of view, first electrode 60 is in contact with second conductivity type silicon carbide layer 8 . First electrode 60 is in contact with second conductivity type silicon carbide layer 8 on first main surface 1 . The first electrode 60 is, for example, a source electrode. The second electrode 63 is located on the side opposite to the first electrode 60 . Second electrode 63 is in contact with silicon carbide substrate 4 . Second electrode 63 is in contact with silicon carbide substrate 4 on second main surface 2 . The second electrode 63 is, for example, a drain electrode.

The first main surface 1 is, for example, the {0001} plane or a plane that is off by 8° or less with respect to the {0001} plane. Specifically, the first main surface 1 is, for example, the (000-1) plane or a plane that is off by 8° or less with respect to the (000-1) plane. The first main surface 1 may be, for example, the (0001) plane or a plane that is off by 8° or less with respect to the (0001) plane. Silicon carbide substrate 4 is made of, for example, hexagonal silicon carbide of polytype 4H.

Silicon carbide epitaxial layer 3 mainly has drift region 10 , body region 30 , source region 40 and contact region 8 . Drift region 10 is provided on silicon carbide substrate 4 . Drift region 10 contains an n-type impurity such as nitrogen (N) and has an n-type conductivity (first conductivity type). The concentration of n-type impurities in drift region 10 may be lower than the concentration of n-type impurities in silicon carbide substrate 4 .

Body region 30 is provided on drift region 10 . Body region 30 contains a p-type impurity such as aluminum (Al), and has p-type conductivity (second conductivity type) different from n-type. The concentration of p-type impurities in body region 30 may be higher than the concentration of n-type impurities in drift region 10 .

Source region 40 is provided on body region 30 so as to be separated from drift region 10 by body region 30 . Source region 40 contains an n-type impurity such as nitrogen or phosphorus (P), and has n-type conductivity. Source region 40 forms part of first main surface 1 . The concentration of n-type impurities in source region 40 may be higher than the concentration of p-type impurities in body region 30 .

Contact region 8 contains a p-type impurity such as aluminum and has p-type conductivity. The p-type impurity concentration of contact region 8 may be higher than the p-type impurity concentration of body region 30 . Contact region 8 penetrates each of source region 40 and body region 30 and is in contact with drift region 10 . Contact region 8 forms part of first main surface 1 .

As shown in FIG. 6, a gate trench 7 is provided in the first main surface 1 . Gate trench 7 has side surfaces 5 and a bottom surface 6 . The bottom surface 6 continues to the side surface 5 . The side surface 5 is continuous with the first main surface 1 . Side surface 5 is composed of drift region 10 , body region 30 and source region 40 . The bottom surface 6 is composed of a drift region 10 .

Gate insulating film 71 contains, for example, silicon dioxide (SiO ₂ ). Gate insulating film 71 is in contact with each of side surface 5 and bottom surface 6 . Gate insulating film 71 is in contact with each of drift region 10 , body region 30 and source region 40 at side surface 5 . Gate insulating film 71 is in contact with drift region 10 at bottom surface 6 . A channel can be formed in the body region 30 in contact with the gate insulating film 71 .

The gate electrode 64 is provided on the gate insulating film 71 . Gate electrode 64 is arranged in contact with gate insulating film 71 . The gate electrode 64 is provided so as to fill the trench formed by the gate insulating film 71 . Gate electrode 64 is made of a conductor such as polysilicon doped with an impurity.

The isolation insulating film 72 is provided on the gate electrode 64 . The isolation insulating film 72 electrically isolates the source electrode 60 and the gate electrode 64 . The isolation insulating film 72 is arranged between the source electrode 60 and the gate electrode 64 . The isolation insulating film 72 is provided so as to cover the gate electrode 64 . Isolation insulating film 72 is in contact with each of gate electrode 64 and gate insulating film 71 . Isolation insulating film 72 contains, for example, silicon nitride (SiN) or silicon oxynitride (SiON).

Source electrode 60 is provided on first main surface 1 . Source electrode 60 may be in contact with each of source region 40 and contact region 8 on first main surface 1 . The source electrode 60 is provided on the isolation insulating film 72 .

The source electrode 60 has an electrode film 61 and a metal film 62 . The metal film 62 is provided on the electrode film 61 . Electrode film 61 contains nickel silicide (NiSi) or titanium aluminum silicide (TiAlSi), for example. Electrode film 61 is in contact with each of source region 40 and contact region 8 . The metal film 62 is the source wiring. Metal film 62 contains, for example, aluminum (Al).

Drain electrode 63 is provided on second main surface 2 . Drain electrode 63 is in contact with silicon carbide substrate 4 on second main surface 2 . Drain electrode 63 is electrically connected to drift region 10 on the second main surface 2 side. Drain electrode 63 is made of a material such as NiSi (nickel silicide) capable of forming ohmic contact with n-type silicon carbide substrate 4 . Drain electrode 63 is electrically connected to silicon carbide substrate 4 .

In first silicon carbide semiconductor chip 210, in the direction parallel to first main surface 1 of silicon carbide epitaxial substrate 100, the maximum value of Z _1/2 density in first conductivity type silicon carbide layer 10 is defined as the maximum density. When the minimum value of Z _1/2 density in one-conductivity type silicon carbide layer 10 is defined as the minimum density, the value obtained by dividing the value obtained by subtracting the minimum density from the maximum density by the maximum density is 0.05 or more and 0.2 or less. be.

A value obtained by dividing a value obtained by subtracting the minimum density from the maximum density by the maximum density may be, for example, 0.06 or more, or may be 0.07 or more. The value obtained by dividing the value obtained by subtracting the minimum density from the maximum density by the maximum density may be, for example, 0.19 or less, or may be 0.18 or less.

As mentioned above, the Z _1/2 density can be measured by the DLTS method. The Z _1/2 density is measured in each of the plurality of measurement regions S shown in FIG. As shown in FIG. 5, the measurement areas S are positioned on two intersecting diagonal lines. For example, first electrode 60 , isolation insulating film 72 , gate electrode 64 , gate insulating film 71 and the like are first removed from silicon carbide semiconductor chip 200 using a chemical solution. Next, body region 30, source region 40 and contact region 8 are removed so that first conductivity type silicon carbide layer 10 is exposed. Specifically, silicon carbide epitaxial substrate 100 is ground. Next, silicon carbide epitaxial substrate 100 is mechanically polished. Next, chemical mechanical polishing is performed on silicon carbide epitaxial substrate 100 . Thereby, first conductivity type silicon carbide layer 10 is exposed. Next, silicon carbide epitaxial substrate 100 is cleaned.

In order to measure the Z _1/2 density while suppressing the influence of the silicon carbide substrate 4, the silicon carbide epitaxial layer 3 is polished below the bottom surface 6 of the gate trench 7, and the drift region 10 has a thickness of It is desirable to be 5 μm or more. A first measurement electrode is formed in each of a plurality of measurement regions S on the surface of first conductivity type silicon carbide layer 10 to measure Z _1/2 density of first conductivity type silicon carbide layer 10 . The first measurement electrode is arranged in a region without the gate trench 7 and the ion-implanted regions (specifically, the body region 30, the source region 40 and the contact region 8, etc.). Z _1/2 density is measured in five measurement regions S on the surface of first conductivity type silicon carbide layer 10 . Among the Z _1/2 densities in each of the plurality of measurement regions S, the maximum Z _1/2 density is the maximum density, and the minimum Z _1/2 density is the minimum density.

In first silicon carbide semiconductor chip 210, in the direction parallel to first main surface 1 of silicon carbide epitaxial substrate 100, the maximum carrier lifetime in first conductivity type silicon carbide layer 10 is defined as the maximum lifetime, and the first conductivity type Assuming that the minimum carrier lifetime in silicon carbide layer 10 is the minimum lifetime, the value obtained by dividing the value obtained by subtracting the minimum lifetime from the maximum lifetime by the maximum lifetime is 0.05 or more and 0.2 or less.

A value obtained by dividing a value obtained by subtracting the minimum density from the maximum density by the maximum density may be, for example, 0.06 or more, or may be 0.07 or more. The value obtained by dividing the value obtained by subtracting the minimum density from the maximum density by the maximum density may be, for example, 0.19 or less, or may be 0.18 or less.

As described above, carrier lifetime can be measured by the μ-PCD method. Carrier lifetimes are measured in each of a plurality of measurement regions S shown in FIG. As shown in FIG. 5, the measurement areas S are positioned on two intersecting diagonal lines. For example, first electrode 60 , isolation insulating film 72 , gate electrode 64 , gate insulating film 71 and the like are first removed from silicon carbide semiconductor chip 200 using a chemical solution. Next, body region 30, source region 40 and contact region 8 are removed so that first conductivity type silicon carbide layer 10 is exposed. Specifically, silicon carbide epitaxial substrate 100 is ground. Next, silicon carbide epitaxial substrate 100 is mechanically polished. Next, chemical mechanical polishing is performed on silicon carbide epitaxial substrate 100 . Thereby, first conductivity type silicon carbide layer 10 is exposed. Next, silicon carbide epitaxial substrate 100 is cleaned.

In order to measure the carrier lifetime while suppressing the influence of silicon carbide substrate 4, silicon carbide epitaxial layer 3 should be polished below bottom surface 6 of gate trench 7, and drift region 10 should have a thickness of 5 μm or more. It is desirable to have A first measurement electrode is formed in each of a plurality of measurement regions S on the surface of first conductivity type silicon carbide layer 10 to measure the carrier lifetime of first conductivity type silicon carbide layer 10 . The first measurement electrode is arranged in a region without the gate trench 7 and the ion-implanted regions (specifically, the body region 30, the source region 40 and the contact region 8, etc.). Carrier lifetimes are measured in five measurement regions S on the surface of first conductivity type silicon carbide layer 10 . Among the carrier lifetimes in each of the plurality of measurement regions S, the maximum carrier lifetime is defined as the maximum lifetime, and the minimum carrier lifetime is defined as the minimum lifetime.

Next, the configuration of second silicon carbide semiconductor chip 220 will be described. FIG. 7 is a schematic plan view showing the configuration of second silicon carbide semiconductor chip 220 . FIG. 8 is a schematic cross-sectional view taken along line VIII-VIII of FIG.

As shown in FIG. 8 , second silicon carbide semiconductor chip 220 includes diode 151 . Silicon carbide semiconductor chip 200 mainly has silicon carbide epitaxial substrate 100 , first electrode 60 , and second electrode 63 . Silicon carbide epitaxial substrate 100 has silicon carbide substrate 4 and silicon carbide epitaxial layer 3 on silicon carbide substrate 4 . Silicon carbide epitaxial layer 3 includes a first conductivity type silicon carbide layer 10 and a second conductivity type silicon carbide layer 8 . First conductivity type silicon carbide layer 10 is in contact with silicon carbide substrate 4 . Second conductivity type silicon carbide layer 8 is on first conductivity type silicon carbide layer 10 . Second conductivity type silicon carbide layer 8 continues to first conductivity type silicon carbide layer 10 . First conductivity type silicon carbide layer 10 is, for example, an n-type silicon carbide layer. The second conductivity type layer is, for example, a p-type silicon carbide layer.

As shown in FIG. 8, first conductivity type silicon carbide layer 10 is, for example, n-type epitaxial layer 10 . N-type epitaxial layer 10 is provided on silicon carbide substrate 4 . Each of n-type epitaxial layer 10 and silicon carbide substrate 4 has an n-type impurity such as nitrogen. The impurity concentration of silicon carbide substrate 4 may be higher than the impurity concentration of n-type epitaxial layer 10 . Second conductivity type silicon carbide layer 8 is, for example, a p-type epitaxial layer. Silicon carbide substrate 4 includes basal plane dislocations 9 . In a plane parallel to the second main surface 2, the areal density of the basal plane dislocations 9 is, for example, higher than 100 cm ⁻² and lower than 1000 cm ⁻² .

First electrode 60 is provided on second conductivity type silicon carbide layer 8 . From another point of view, first electrode 60 is in contact with second conductivity type silicon carbide layer 8 . First electrode 60 is in contact with second conductivity type silicon carbide layer 8 on first main surface 1 . The second electrode 63 is located on the side opposite to the first electrode 60 . Second electrode 63 is in contact with silicon carbide substrate 4 . Second electrode 63 is in contact with silicon carbide substrate 4 on second main surface 2 .

In second silicon carbide semiconductor chip 220, the maximum value of Z _1/2 density in first conductivity type silicon carbide layer 10 in the direction parallel to first main surface 1 of silicon carbide epitaxial substrate 100 is defined as the maximum density. When the minimum value of Z _1/2 density in one-conductivity type silicon carbide layer 10 is defined as the minimum density, the value obtained by dividing the value obtained by subtracting the minimum density from the maximum density by the maximum density is 0.05 or more and 0.2 or less. be.

A value obtained by dividing a value obtained by subtracting the minimum density from the maximum density by the maximum density may be, for example, 0.06 or more, or may be 0.07 or more. The value obtained by dividing the value obtained by subtracting the minimum density from the maximum density by the maximum density may be, for example, 0.19 or less, or may be 0.18 or less. The method for measuring Z _1/2 density in second silicon carbide semiconductor chip 220 is the same as the method for measuring Z _1/2 density in first silicon carbide semiconductor chip 210 .

In second silicon carbide semiconductor chip 220, the maximum carrier lifetime in first conductivity type silicon carbide layer 10 in the direction parallel to first main surface 1 of silicon carbide epitaxial substrate 100 is defined as the maximum lifetime, and the first conductivity type Assuming that the minimum carrier lifetime in silicon carbide layer 10 is the minimum lifetime, the value obtained by dividing the value obtained by subtracting the minimum lifetime from the maximum lifetime by the maximum lifetime is 0.05 or more and 0.2 or less.

A value obtained by dividing a value obtained by subtracting the minimum density from the maximum density by the maximum density may be, for example, 0.06 or more, or may be 0.07 or more. The value obtained by dividing the value obtained by subtracting the minimum density from the maximum density by the maximum density may be, for example, 0.19 or less, or may be 0.18 or less. The method of measuring the carrier lifetime in second silicon carbide semiconductor chip 220 is the same as the method of measuring the carrier lifetime in first silicon carbide semiconductor chip 210 .

As described above, a plurality of silicon carbide semiconductor chips 200 may have first silicon carbide semiconductor chips 210 and second silicon carbide semiconductor chips 220 . First silicon carbide semiconductor chip 210 includes a first silicon carbide semiconductor element. The first silicon carbide semiconductor device is transistor 150, for example. Second silicon carbide semiconductor chip 220 includes a second silicon carbide semiconductor element different from the first silicon carbide semiconductor element. Second silicon carbide semiconductor element is diode 151, for example.

Each of a plurality of silicon carbide semiconductor chips 200 includes silicon carbide substrate 4 , silicon carbide epitaxial substrate 100 including silicon carbide epitaxial layer 3 on silicon carbide substrate 4 , and first electrode in contact with second conductivity type silicon carbide layer 8 . 60 and a second electrode 63 in contact with silicon carbide substrate 4 . Silicon carbide epitaxial layer 3 includes a first conductivity type silicon carbide layer 10 and a second conductivity type silicon carbide layer 8 on first conductivity type silicon carbide layer 10 . First conductivity type silicon carbide layer 10 is in contact with silicon carbide substrate 4 .

As shown in FIG. 3 , first silicon carbide semiconductor chip 210 has first chip 201 and second chip 202 . As shown in FIG. 5, carrier lifetimes are obtained in a plurality of measurement regions S of each of the first chip 201 and the second chip 202. FIG. A maximum lifetime, a minimum lifetime and an average lifetime are obtained for each of the first tip 201 and the second tip 202 .

As shown in FIG. 3 , second silicon carbide semiconductor chip 220 has third chip 203 and fourth chip 204 . As shown in FIG. 7, carrier lifetimes are obtained in a plurality of measurement regions S of each of the third chip 203 and the fourth chip 204. FIG. A maximum lifetime, a minimum lifetime and an average lifetime are obtained for each of the third tip 203 and the fourth tip 204 . Note that the average lifetime is the average value of carrier lifetimes in a plurality of measurement regions S (eg, five locations).

Table 1 shows the maximum lifetime, minimum lifetime and average lifetime of each of a plurality of silicon carbide semiconductor chips 200. Specifically, the maximum lifetime, minimum lifetime and average lifetime of the first chip 201 are T11, T12 and T13, respectively. The maximum lifetime, minimum lifetime and average lifetime of the second chip 202 are T21, T22 and T23 respectively. The maximum lifetime, minimum lifetime and average lifetime of the third chip 203 are T31, T32 and T33 respectively. The maximum lifetime, minimum lifetime and average lifetime for the fourth chip 204 are T41, T42 and T43 respectively.

Among the average carrier lifetimes of each of the plurality of silicon carbide semiconductor chips 200, the maximum value of the average carrier lifetime in the first conductivity type silicon carbide layer 10 is defined as the maximum lifetime, and the average carrier lifetime in the first conductivity type silicon carbide layer 10 is When the minimum value is defined as the minimum life, the value obtained by dividing the value obtained by subtracting the minimum life from the maximum life by the maximum life is 0.05 or more and 0.2 or less.

Specifically, among the average lifetimes of the first chip 201, the second chip 202, the third chip 203, and the fourth chip 204, the longest average lifetime is the maximum lifetime. Similarly, among the average life spans of the first chip 201, the second chip 202, the third chip 203 and the fourth chip 204, the smallest average life span is the minimum life span. For example, assume that T13 is the largest value among T13, T23, T33 and T43, and T43 is the smallest value. In this case, in a plurality of silicon carbide semiconductor chips 200, the value obtained by dividing the value obtained by subtracting the minimum lifetime from the maximum lifetime by the maximum lifetime is (T13-T43)/T13.

Table 2 shows the maximum density, minimum density and average density in each of the plurality of silicon carbide semiconductor chips 200. Specifically, the maximum density, minimum density and average density in the first chip 201 are Z11, Z12 and Z13 respectively. The maximum, minimum and average densities in the second chip 202 are Z21, Z22 and Z23 respectively. The maximum, minimum and average densities in the third chip 203 are Z31, Z32 and Z33 respectively. The maximum, minimum and average densities in the fourth chip 204 are Z41, Z42 and Z43 respectively.

In a plurality of silicon carbide semiconductor chips 200, the maximum value of Z _1/2 density in first conductivity type silicon carbide layer 10 is the maximum density, and the minimum value of Z _1/2 density in first conductivity type silicon carbide layer 10 is the minimum value. In terms of density, the value obtained by dividing the value obtained by subtracting the minimum density from the maximum density by the maximum density is 0.05 or more and 0.2 or less.

Specifically, among the average densities of the first chip 201, the second chip 202, the third chip 203 and the fourth chip 204, the highest average density is the maximum density. Similarly, among the average densities of the first chip 201, the second chip 202, the third chip 203 and the fourth chip 204, the smallest average density is the minimum density. For example, assume that Z13 is the largest value among Z13, Z23, Z33 and Z43, and Z43 is the smallest value. In this case, in the plurality of silicon carbide semiconductor chips 200, the value obtained by dividing the value obtained by subtracting the minimum density from the maximum density by the maximum density is (Z13-Z43)/Z13.

Next, the configuration of silicon carbide semiconductor module 300 according to the second embodiment will be described. FIG. 9 is a schematic cross-sectional view showing the configuration of a silicon carbide semiconductor module 300 according to the second embodiment.

As shown in FIG. 9 , each of silicon carbide semiconductor chips 200 may include transistor 150 and diode 151 . From another point of view, each of the plurality of silicon carbide semiconductor chips 200 has a built-in diode.

As shown in FIG. 9, each of a plurality of silicon carbide semiconductor chips 200 may include transistor 150 shown in FIG. 6 and diode 151 shown in FIG. A first electrode 60 of the transistor 150 is electrically connected to a first electrode 60 of the diode 151 . A second electrode 63 of the transistor 150 is electrically connected to a second electrode 63 of the diode 151 . The configuration of transistor 150 is similar to the configuration shown in FIG. The configuration of diode 151 is similar to that shown in FIG.

In silicon carbide semiconductor module 300 according to each of the first and second embodiments, transistor 150 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). Diode 151 is, for example, a PiN diode. Further, in the above description, the first conductivity type is the n-type and the second conductivity type is the p-type, but the first conductivity type may be the p-type and the second conductivity type may be the n-type. .

(Manufacturing method of silicon carbide epitaxial substrate)
Next, a method for manufacturing silicon carbide epitaxial substrate 100 will be described.

First, silicon carbide substrate 4 is prepared, for example, by slicing a silicon carbide single crystal ingot. A polytype of silicon carbide is, for example, 4H. Silicon carbide substrate 4 contains an impurity capable of imparting n-type conductivity, such as nitrogen. Silicon carbide substrate 4 includes basal plane dislocations 9 .

Silicon carbide epitaxial layer 3 is then formed on silicon carbide substrate 4 . For example, silicon carbide epitaxial layer 3 is epitaxially grown by a CVD (Chemical Vapor Deposition) method. In epitaxial growth, for example, silane (SiH ₄ ) and propane (C ₃ H ₈ ) are used as raw material gases, and hydrogen (H ₂ ) is used as carrier gas. The temperature of silicon carbide substrate 4 during epitaxial growth is about 1400° C. or more and 1700° C. or less. During epitaxial growth, an n-type impurity such as nitrogen is introduced. Silicon carbide epitaxial layer 3 has a thickness of, for example, 30 μm.

As shown in FIG. 10 , silicon carbide epitaxial substrate 100 has first main surface 1 and second main surface 2 . First main surface 1 is formed of silicon carbide epitaxial layer 3 . Second main surface 2 is formed of silicon carbide substrate 4 . Silicon carbide epitaxial layer 3 includes point defects 41 called Z _1/2 .

Next, a step of modifying the first main surface 1 is performed. Specifically, silicon carbide epitaxial substrate 100 is processed in an atmosphere of oxygen (O ₂ ) plasma or carbon dioxide (CO ₂ ) plasma. Thereby, the first main surface 1 is modified. From another point of view, the first main surface 1 is oxidized by plasma treatment. The plasma processing conditions are, for example, a gas flow rate of 0.05 L/min or more and 0.5 L/min or less, room temperature, and a processing time of 30 minutes. As a result, silicon dioxide film 43 is formed on first main surface 1 . As shown in FIG. 11 , carbon atoms 42 are left near first main surface 1 by forming silicon dioxide film 43 on first main surface 1 .

Next, a step of implanting carbon ions is performed. As shown in FIG. 12 , carbon ions 44 are implanted into silicon carbide epitaxial layer 3 while silicon dioxide film 43 is formed on first main surface 1 . Carbon ions 44 are implanted into silicon carbide epitaxial layer 3 through silicon dioxide film 43 . The implantation depth of carbon ions 44 is, for example, about 200 nm. The implantation conditions for the carbon ions 44 are, for example, a temperature of 600° C., an implantation energy of 10 keV to 150 keV, and a carbon density of about 5×10 ²⁰ cm ⁻³ in the implanted region.

Next, a step of annealing silicon carbide epitaxial substrate 100 is performed. For example, silicon carbide epitaxial substrate 100 is annealed at a temperature of 1600° C. or higher. Annealing time is, for example, 30 minutes or more. Thereby, carbon atoms 42 existing in the vicinity of first main surface 1 are diffused into a deep layer (that is, on the second main surface 2 side) of silicon carbide epitaxial substrate 100 . The diffused carbon atoms 42 recombine with the point defects 41 present in the deep layer of the silicon carbide epitaxial layer 3 , so that the point defects 41 present in the deep layer disappear. The step of annealing silicon carbide epitaxial substrate 100 is performed with silicon dioxide film 43 formed on first main surface 1 . After the step of annealing silicon carbide epitaxial substrate 100, silicon dioxide film 43 is removed.

As described above, first, carbon atoms 42 are formed near the first main surface 1 in the oxygen plasma treatment step. After that, in a carbon ion implantation step, carbon ions 44 are implanted at a position deeper than the carbon atoms 42 formed in the oxygen plasma treatment step. After that, silicon carbide epitaxial substrate 100 is annealed. This reduces point defects 41 called Z _1/2 uniformly in the direction parallel to the first main surface 1 . As a result, silicon carbide epitaxial substrate 100 according to the present embodiment is manufactured.

(Manufacturing method of silicon carbide semiconductor chip)
First, silicon carbide epitaxial substrate 100 having high in-plane uniformity of point defects 41 called Z _1/2 is manufactured by the method described above. An ion implantation step is then performed. Specifically, a p-type impurity such as aluminum is ion-implanted into silicon carbide epitaxial layer 3 . Thereby, body region 30 is formed. Next, an n-type impurity such as phosphorus is ion-implanted into body region 30 . A source region 40 is thus formed. Next, a mask layer (not shown) having openings over the regions where the contact regions 8 are to be formed is formed. Next, a p-type impurity such as aluminum is implanted into source region 40 . Thereby, contact region 8 penetrating through source region 40 and body region 30 and in contact with drift region 10 is formed (see FIG. 13).

Next, activation annealing is performed to activate the impurity ions implanted into silicon carbide epitaxial substrate 100 . The temperature of the activation annealing is preferably 1500°C or higher and 1900°C or lower, for example about 1700°C. The activation annealing time is, for example, about 30 minutes. The atmosphere for the activation annealing is preferably an inert gas atmosphere such as an Ar atmosphere.

Next, a step of forming gate trenches 7 is performed. First, silicon carbide epitaxial substrate 100 is etched with mask layer 33 formed on first main surface 1 . Specifically, for example, part of source region 40 and part of body region 30 are removed by etching. As an etching method, for example, reactive ion etching, especially inductively coupled plasma reactive ion etching can be used. For example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF ₆ ) or a mixed gas of SF ₆ and oxygen (O ₂ ) as a reactive gas can be used. By etching, in the region where the gate trench 7 is to be formed, a side portion substantially perpendicular to the first main surface 1 and a bottom provided continuously with the side portion and substantially parallel to the first main surface 1 are formed. is formed.

A thermal etch is then performed in the recess. Thermal etching can be performed by heating in an atmosphere containing a reactive gas containing at least one type of halogen atom while mask layer 33 is formed on first main surface 1 . The at least one halogen atom includes at least one of chlorine (Cl) and fluorine (F) atoms. The atmosphere includes, for example, chlorine ( _Cl2 ), boron trichloride ( _BCl3 ), _SF6 or carbon tetrafluoride ( _CF4 ). For example, a mixed gas of chlorine gas and oxygen gas is used as a reaction gas, and thermal etching is performed at a heat treatment temperature of, for example, 800° C. or higher and 900° C. or lower. Note that the reaction gas may contain a carrier gas in addition to the chlorine gas and the oxygen gas described above. Nitrogen gas, argon gas, or helium gas, for example, can be used as the carrier gas. A gate trench 7 is formed in the first main surface 1 by thermal etching (see FIG. 14).

Side surface 5 extends through source region 40 and body region 30 to drift region 10 . From another point of view, the side surface 5 is composed of the source region 40 , the body region 30 and the drift region 10 . Bottom surface 6 is located in drift region 10 . From another point of view, the bottom surface 6 is composed of the drift region 10 . Bottom surface 6 is, for example, a plane parallel to second main surface 2 . As shown in FIG. 14 , the width of gate trench 7 increases from bottom surface 6 toward first main surface 1 in a cross-sectional view.

Next, a step of forming gate insulating film 71 is performed. For example, by thermally oxidizing silicon carbide epitaxial substrate 100, gate insulating film 71 in contact with source region 40, body region 30, drift region 10, contact region 8 and first main surface 1 is formed. Specifically, silicon carbide epitaxial substrate 100 is heated, for example, at a temperature of 1300° C. or more and 1400° C. or less in an atmosphere containing oxygen. Thereby, a gate insulating film 71 in contact with the gate trench 7 is formed.

Next, heat treatment (NO annealing) may be performed on silicon carbide epitaxial substrate 100 in a nitrogen monoxide (NO) gas atmosphere. In the NO annealing, silicon carbide epitaxial substrate 100 is held under conditions of, for example, 1100° C. or more and 1400° C. or less for about 1 hour. Thereby, nitrogen atoms are introduced into the interface region between gate insulating film 71 and body region 30 . As a result, the channel mobility can be improved by suppressing the formation of interface states in the interface region.

After the NO anneal, Ar anneal using argon (Ar) as the ambient gas may be performed. The heating temperature for Ar annealing is, for example, higher than the heating temperature for NO annealing. The Ar annealing time is, for example, about one hour. This further suppresses the formation of an interface state in the interface region between gate insulating film 71 and body region 30 . As the atmosphere gas, other inert gas such as nitrogen gas may be used instead of Ar gas.

Next, a step of forming gate electrode 64 is performed. A gate electrode 64 is formed on the gate insulating film 71 . Gate electrode 64 is formed, for example, by LP-CVD (Low Pressure Chemical Vapor Deposition). The gate electrode 64 is formed to fill the groove formed by the gate insulating film 71 . Gate electrode 64 is formed to face each of source region 40, body region 30 and drift region 10 (see FIG. 15).

Next, a step of forming isolation insulating film 72 is performed. Specifically, an isolation insulating film 72 is formed in the gate trench 7 so as to cover the gate electrode 64 . Isolation insulating film 72 is formed by, for example, the CVD method. The isolation insulating film 72 may be formed by normal pressure CVD, plasma CVD, or low pressure CVD. Isolation insulating film 72 is, for example, a material containing silicon dioxide. Isolation insulating film 72 is in contact with each of gate electrode 64 and gate insulating film 71 .

Next, a step of forming the source electrode 60 is performed. For example, a portion of each of gate insulating film 71 and isolation insulating film 72 is removed by dry etching. As a result, a portion of first main surface 1 is exposed from gate insulating film 71 . An electrode film 61 is formed in contact with each of source region 40 and contact region 8 on first main surface 1 . Electrode film 61 is formed by sputtering, for example. Electrode film 61 is made of a material containing Ti, Al and Si, for example.

Next, the electrode film 61 is held at a temperature of, for example, 900° C. or more and 1100° C. or less for about 5 minutes. Thereby, at least part of electrode film 61 reacts with silicon contained in silicon carbide epitaxial substrate 100 to be silicided. As a result, the electrode film 61 that makes an ohmic contact with the source region 40 is formed. The electrode film 61 may be in ohmic contact with the contact region 8 . Next, a metal film 62 is formed. Metal film 62 is formed on each of electrode film 61 and isolation insulating film 72 . Metal film 62 contains, for example, aluminum. Through the above steps, the source electrode 60 including the electrode film 61 and the metal film 62 is formed.

Next, second main surface 2 of silicon carbide epitaxial substrate 100 is subjected to back polishing. Thereby, the thickness of silicon carbide substrate 4 is reduced. Next, a step of forming the drain electrode 63 is performed. Drain electrode 63 in contact with second main surface 2 is formed by sputtering, for example. Drain electrode 63 is made of a material containing NiSi or TiAlSi, for example. Next, silicon carbide epitaxial substrate 100 is diced by, for example, a grindstone (not shown). Thereby, silicon carbide epitaxial substrate 100 is divided into a plurality of silicon carbide semiconductor chips 200 . As described above, silicon carbide semiconductor chip 200 according to the present embodiment is manufactured.

(Manufacturing method of silicon carbide semiconductor module)
First, the circuit board 20 is prepared. As shown in FIG. 4, the circuit board 20 has a substrate 24 and circuit patterns 23 . The circuit pattern 23 is provided on the base material 24 . The circuit board 20 has a third principal surface 21 and a fourth principal surface 22 . The fourth principal surface 22 is the surface opposite to the third principal surface 21 . The third principal surface 21 is configured with a circuit pattern 23 . The fourth major surface 22 is composed of a base material 24 .

Next, each of a plurality of silicon carbide semiconductor chips 200 is mounted on circuit board 20 . Specifically, as shown in FIG. 4 , silicon carbide semiconductor chip 200 is mounted on circuit board 20 with bonding member 50 interposed therebetween. Joining member 50 is, for example, solder. The joining member 50 may be made of any conductive material, and is not limited to solder. The joining member 50 may be silver paste or the like, for example. As shown in FIG. 4 , the joint member 50 is electrically connected to the circuit pattern 23 on the third main surface 21 . Joining member 50 is electrically connected to silicon carbide semiconductor chip 200 on the second main surface 2 side. Drain electrode 63 of silicon carbide semiconductor chip 200 is electrically connected to circuit pattern 23 via joining member 50 .

In the mounting process, in the plurality of silicon carbide semiconductor chips 200, the maximum value of carrier lifetime in first conductivity type silicon carbide layer 10 is defined as the maximum lifetime, and the minimum value of carrier lifetime in first conductivity type silicon carbide layer 10 is defined as the minimum lifetime. , a plurality of silicon carbide semiconductor chips 200 are selected such that the value obtained by dividing the maximum lifetime minus the minimum lifetime by the maximum lifetime is 0.05 or more and 0.2 or less.

In the mounting step, in the plurality of silicon carbide semiconductor chips 200, the maximum value of the Z _1/2 density in the first conductivity type silicon carbide layer 10 is set as the maximum density, and the Z _1/2 density in the first conductivity type silicon carbide layer 10 is set as the maximum density. is the minimum density, the plurality of silicon carbide semiconductor chips 200 are selected such that the value obtained by dividing the maximum density minus the minimum density by the maximum density is 0.05 or more and 0.2 or less. may

Next, functions and effects of silicon carbide epitaxial substrate 100, silicon carbide semiconductor chip 200 and silicon carbide semiconductor module 300 according to the above embodiment will be described.

In silicon carbide semiconductor module 300 , a plurality of silicon carbide semiconductor chips 200 are mounted on circuit board 20 . In order to improve the reliability of silicon carbide semiconductor module 300 , it is required that each of silicon carbide semiconductor chips 200 have the same characteristics.

Silicon carbide substrate 4 usually contains basal plane dislocations 9 . A portion of basal plane dislocations 9 contained in silicon carbide substrate 4 is inherited by silicon carbide epitaxial layer 3 . When bipolar diode 151 is used in silicon carbide semiconductor chip 200, a phenomenon of forward deterioration occurs as basal plane dislocations 9 expand. Therefore, when bipolar diode 151 is used, it is more difficult to match the characteristics of each of silicon carbide semiconductor chips 200 than when bipolar diode 151 is not used.

Forward degradation occurs because basal plane dislocations 9 expand due to energy generated when carriers (electrons, holes) injected into silicon carbide epitaxial layer 3 recombine. When the carrier lifetime is long, the number of carriers reaching the basal plane dislocation 9 increases. In this case, the probability of forward degradation occurring increases. When forward degradation occurs, the on-resistance increases.

According to the silicon carbide semiconductor module 300 according to the present embodiment, in the plurality of silicon carbide semiconductor chips 200, the maximum value of the carrier lifetime in the first conductivity type silicon carbide layer 10 is set as the maximum lifetime, and the first conductivity type silicon carbide layer 10 When the minimum value of the carrier lifetime in is defined as the minimum lifetime, the value obtained by dividing the value obtained by subtracting the minimum lifetime from the maximum lifetime by the maximum lifetime is 0.05 or more and 0.2 or less. Thus, in a plurality of silicon carbide semiconductor chips 200, the variation in forward deterioration can be reduced by reducing the variation in carrier lifetime. Therefore, variation in on-resistance can be reduced in a plurality of silicon carbide semiconductor chips 200 . As a result, reliability of silicon carbide semiconductor module 300 can be improved.

According to silicon carbide epitaxial substrate 100 according to the present embodiment, in the direction parallel to the main surface of silicon carbide epitaxial layer 3 , the maximum value of the carrier lifetime in silicon carbide epitaxial substrate 100 is set as the maximum lifetime, and in silicon carbide epitaxial substrate 100 When the minimum value of the carrier lifetime is defined as the minimum lifetime, the value obtained by dividing the value obtained by subtracting the minimum lifetime from the maximum lifetime by the maximum lifetime is 0.05 or more and 0.2 or less. A plurality of silicon carbide semiconductor chips 200 are usually manufactured from one silicon carbide epitaxial substrate 100 . By reducing variation in carrier lifetime in silicon carbide epitaxial substrate 100 , variation in carrier lifetime can be reduced in a plurality of silicon carbide semiconductor chips 200 . As a result, reliability of silicon carbide semiconductor module 300 can be improved.

According to silicon carbide semiconductor chip 200 according to the present embodiment, in the direction parallel to the main surface of the silicon carbide epitaxial substrate, the maximum carrier lifetime in first conductivity type silicon carbide layer 10 is set as the maximum lifetime, and the first conductivity type Assuming that the minimum carrier lifetime in silicon carbide layer 10 is the minimum lifetime, the value obtained by dividing the value obtained by subtracting the minimum lifetime from the maximum lifetime by the maximum lifetime is 0.05 or more and 0.2 or less. Thereby, variation in carrier lifetime can be reduced in the plane of silicon carbide semiconductor chip 200 .

The embodiments disclosed this time are illustrative in all respects and should be considered not restrictive. The scope of the present invention is indicated by the scope of the claims rather than the above description, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

1 main surface (first main surface)
2 second main surface 3 silicon carbide epitaxial layer 4 silicon carbide substrate 5 side surface 6 bottom surface 7 gate trench 8 contact region (second conductivity type silicon carbide layer)
9 basal plane dislocation 10 drift region, n-type epitaxial layer (first conductivity type silicon carbide layer)
11 Central region 12 Peripheral region 13 Center 20 Circuit board 21 Third principal surface 22 Fourth principal surface 23 Circuit pattern 24 Base material 25 Orientation flat portion 26 Circular portion 27 Peripheral edge 30 Body region 33 Mask layer 40 Source region 41 Point defect 42 Carbon atom 43 Silicon dioxide film 44 Carbon ion 50 Joining member 60 First electrode (source electrode)
61 electrode film 62 metal film 63 second electrode (drain electrode)
64 gate electrode 71 gate insulating film 72 isolation insulating film 100 silicon carbide epitaxial substrate 101 first direction 102 second direction 150 transistor 151 diode 200 silicon carbide semiconductor chip 201 first chip 202 second chip 203 third chip 204 fourth chip 210 First silicon carbide semiconductor chip 220 Second silicon carbide semiconductor chip 300 Silicon carbide semiconductor module S Measurement region T Thickness W1 Diameter W2 Peripheral width

Claims (7)

a silicon carbide substrate;
A silicon carbide epitaxial substrate comprising a silicon carbide epitaxial layer on the silicon carbide substrate,
In the direction parallel to the main surface of the silicon carbide epitaxial layer, the maximum value of the carrier lifetime in the silicon carbide epitaxial layer is defined as the maximum lifetime, and the minimum value of the carrier lifetime in the silicon carbide epitaxial layer is defined as the minimum lifetime. A silicon carbide epitaxial substrate, wherein a value obtained by dividing a value obtained by subtracting the minimum lifetime from the lifetime by the maximum lifetime is 0.05 or more and 0.2 or less. 2. The silicon carbide epitaxial substrate according to claim 1, wherein said minimum lifetime is 0.5 microseconds or more. 3. The silicon carbide epitaxial substrate according to claim 1, wherein said silicon carbide epitaxial layer has a thickness of 5 μm or more and 50 μm or less. a silicon carbide epitaxial substrate including a silicon carbide substrate having a first conductivity type and a silicon carbide epitaxial layer on the silicon carbide substrate;
The silicon carbide epitaxial layer has a first conductivity type silicon carbide layer in contact with the silicon carbide substrate and a second conductivity type silicon carbide layer on the first conductivity type silicon carbide layer, and
a first electrode in contact with the second conductivity type silicon carbide layer;
a second electrode in contact with the silicon carbide substrate;
In a direction parallel to the main surface of the silicon carbide epitaxial substrate, the maximum carrier lifetime in the first conductivity type silicon carbide layer is defined as the maximum lifetime, and the minimum carrier lifetime in the first conductivity type silicon carbide layer is defined as the minimum lifetime. , a value obtained by dividing a value obtained by subtracting the minimum life from the maximum life by the maximum life is 0.05 or more and 0.2 or less. a circuit board;
a plurality of silicon carbide semiconductor chips mounted on the circuit board,
Each of the plurality of silicon carbide semiconductor chips,
a silicon carbide epitaxial substrate including a silicon carbide substrate having a first conductivity type and a silicon carbide epitaxial layer on the silicon carbide substrate;
The silicon carbide epitaxial layer has a first conductivity type silicon carbide layer in contact with the silicon carbide substrate and a second conductivity type silicon carbide layer on the first conductivity type silicon carbide layer, and
a first electrode in contact with the second conductivity type silicon carbide layer;
a second electrode in contact with the silicon carbide substrate,
Among the average carrier lifetimes of each of the plurality of silicon carbide semiconductor chips, the maximum value of the average carrier lifetime in the first conductivity type silicon carbide layer is defined as the maximum lifetime, and the average carrier lifetime in the first conductivity type silicon carbide layer is A silicon carbide semiconductor module, wherein a value obtained by dividing a value obtained by subtracting the minimum life from the maximum life by the maximum life is 0.05 or more and 0.2 or less, where the minimum value is the minimum life. 6. The silicon carbide semiconductor module according to claim 5, wherein each of said plurality of silicon carbide semiconductor chips includes a transistor and a diode. 6. The silicon carbide semiconductor module according to claim 5, wherein said plurality of silicon carbide semiconductor chips have a first silicon carbide semiconductor chip including a transistor and a second silicon carbide semiconductor chip including a diode.

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