JP2012094648A - Method for manufacturing silicon carbide semiconductor element, and wafer with silicon carbide layer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a yield by reducing variations of element characteristics in a surface parallel to the main surface of a silicon carbide wafer.SOLUTION: A method for manufacturing a silicon carbide semiconductor element comprises the steps of: (A) providing a wafer 1 with a silicon carbon layer, the wafer 1 comprising a silicon carbide wafer 101 and a first silicon carbide layer 110 which is placed on a main surface of the silicon carbide wafer 101 and has a plurality of first conductive type impurity regions 105 including first conductive type impurity; and (B) forming a second silicon carbide layer 115 by epitaxially growing silicon carbide on a surface of the first silicon carbide layer 110. In the step (B), conditions for epitaxial growth are controlled such that thickness of the second silicon carbide layer 115 and/or impurity concentration have a certain distribution in a surface parallel to the main surface of th silicon carbide wafer 101, based on a concentration distribution of the first conductive type impurity on the surface of the first conductive type impurity regions 105.

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor element and a wafer having a silicon carbide layer.

  Silicon carbide (silicon carbide: SiC) has excellent physical properties such as a larger band gap and higher dielectric breakdown electric field strength than silicon (Si), so it is applied to next-generation low-loss power devices and the like. It is an expected semiconductor material. Silicon carbide has many polytypes such as cubic 3C—SiC and hexagonal 6H—SiC and 4H—SiC. Among these, 4H-SiC is a polytype generally used for producing a practical silicon carbide semiconductor element.

  A silicon carbide semiconductor element such as a metal-insulator-semiconductor field effect transistor (MISFET) includes a silicon carbide wafer and a silicon carbide epitaxial layer formed on the main surface of the silicon carbide wafer. Formed using. The silicon carbide epitaxial layer becomes an active region of the silicon carbide semiconductor element. As the silicon carbide wafer, for example, a 4H—SiC wafer having a main surface substantially coincident with the (0001) Si plane perpendicular to the c-axis crystal axis is preferably used. In general, a plurality of silicon carbide semiconductor elements are formed using one silicon carbide wafer.

  In this specification, a “silicon carbide wafer” refers to a substrate obtained by cutting and polishing single crystal SiC produced by a modified Lely method or a sublimation method to a predetermined size. In addition, a substrate in which a silicon carbide layer such as a silicon carbide epitaxial layer is formed on a silicon carbide wafer is referred to as “a wafer with a silicon carbide layer”. “Wafer with a silicon carbide layer” also includes a substrate in which a plurality of silicon carbide semiconductor elements or parts thereof are formed on a silicon carbide wafer on which a silicon carbide layer is formed. The silicon carbide layer provided wafer on which the plurality of silicon carbide semiconductor elements are formed is then cut (diced) into a predetermined chip size, whereby the plurality of silicon carbide semiconductor elements are separated from each other.

When producing a silicon carbide semiconductor element, the conductivity type and carrier concentration are controlled in a selected region of the silicon carbide epitaxial layer formed on the silicon carbide wafer according to the type of semiconductor element to be produced. An impurity doped layer is formed. For example, in the MISFET, the impurity doped layer functions as a p-type body region or an n ⁺ source region.

  In general, the impurity doped layer is formed by performing heat treatment (activation annealing) after implanting impurity ions into the silicon carbide epitaxial layer. By performing activation annealing, the implanted impurity ions can be activated and the crystallinity disorder of the silicon carbide epitaxial layer generated by the ion implantation can be recovered.

  In order to recover the disorder of crystallinity generated by ion implantation, that is, to recover the Si—C bond, activation annealing is performed at a temperature higher than the activation annealing temperature for the silicon semiconductor layer. Since the Si—C bond of silicon carbide has a higher covalent bond energy than the Si—Si bond of silicon, when the Si—C bond is broken, the Si—C bond has a higher energy than the Si—Si bond to bond again. It is necessary. Therefore, the temperature of activation annealing (hereinafter simply referred to as “annealing temperature”) when forming the impurity doped layer in the silicon carbide epitaxial layer is set to, for example, 1600 ° C. or higher.

  However, for example, if activation annealing is performed at a high temperature of 1600 ° C. or higher, the following problems specific to silicon carbide semiconductor elements may occur.

  During the activation annealing, silicon is selectively sublimated from the surface of the silicon carbide epitaxial layer, and as a result, carbon remains on the surface of the silicon carbide epitaxial layer. The remaining carbon constitutes a carbon nanotube structure or a graphene structure, and becomes a carbon layer. The carbon layer is removed as necessary. Thus, the surface portion of the silicon carbide epitaxial layer disappears due to the activation annealing.

  Non-Patent Document 1 discloses that activation annealing is performed with the annealing temperature set to a low temperature of 1200 ° C. or lower, for example, as a method for suppressing silicon sublimation due to activation annealing.

  In Patent Document 1, in order to suppress surface roughness of the silicon carbide epitaxial layer due to activation annealing, a cap layer mainly made of carbon is provided on the surface of the silicon carbide epitaxial layer and activated in that state. Annealing is disclosed. However, as a result of investigations by the present inventors, it is possible to suppress surface roughness of the silicon carbide epitaxial layer even if the activation annealing is performed after forming the cap layer, but selective sublimation of silicon from the surface of the silicon carbide epitaxial layer can be suppressed. It is difficult to prevent.

JP 2005-260267 A J. et al. A. Cooper et al. , Mat. Res. Soc. Symp. Proc. 572, 3 (1999)

  According to the method disclosed in Non-Patent Document 1, since activation annealing is performed in a low temperature range of 1200 ° C. or lower, there is a possibility that crystals disturbed by ion implantation cannot be sufficiently recovered. For this reason, in the silicon carbide semiconductor element, there is a possibility that element characteristics such as an increase in leakage current and an increase in on-resistance when reverse bias is applied may be deteriorated.

  On the other hand, as a result of the study by the present inventors, the following problems due to activation annealing were newly found.

  As an activation annealing apparatus, an apparatus using induction heating, resistance heating, electron impact heating or the like is generally used. For example, when activation annealing is performed at a temperature of 1600 ° C. or higher, it is very difficult to uniformly heat the silicon carbide layer-attached wafer using any of the above annealing apparatuses. For this reason, the temperature of the silicon carbide layer-attached wafer is not uniform in a plane parallel to the main surface of the silicon carbide wafer (hereinafter, abbreviated as “in-plane of the silicon carbide-layer wafer” or simply “in-plane”). Distribution. When the above temperature distribution occurs in the silicon carbide epitaxial layer during activation annealing, the disappearance amount of the silicon carbide epitaxial layer also has a non-uniform distribution in the plane corresponding to this temperature distribution. Such in-plane distribution of the disappearance amount becomes a factor in which the characteristics vary among a plurality of silicon carbide semiconductor elements formed from one silicon carbide layer-attached wafer.

  For example, when a plurality of MISFETs are formed on a wafer with a silicon carbide layer, the above in-plane distribution occurs in the impurity concentration (dopant concentration) on the surface of the body region which is an impurity doped layer. Since the impurity concentration in the body region greatly affects the threshold voltage of the MISFET, it is extremely difficult to make the threshold voltage of the MISFET uniform in the plane. For this reason, the threshold voltage varies among a plurality of MISFETs formed using one silicon carbide wafer, resulting in a problem that the yield decreases. This problem will be described later in detail with reference to the drawings.

  The present invention has been made in view of the above circumstances, and its object is to produce device characteristics in a plane parallel to the main surface of a silicon carbide wafer when a plurality of silicon carbide semiconductor devices are manufactured on a silicon carbide wafer. It is to improve the yield by suppressing the variation of the above.

  A method for manufacturing a silicon carbide semiconductor device of the present invention includes (A) a silicon carbide wafer and a plurality of first conductivity type impurity regions that are disposed on a main surface of the silicon carbide wafer and that include impurities of a first conductivity type. A step of preparing a wafer with a silicon carbide layer comprising a first silicon carbide layer, and (B) epitaxially growing silicon carbide on the surface of the first silicon carbide layer, thereby providing the plurality of first conductivity type impurity regions; Forming a second silicon carbide layer to be in contact with each other, and in the step (B), based on the concentration distribution of the first conductivity type impurity on the surface of the plurality of first conductivity type impurity regions, Conditions for epitaxial growth are controlled so that the thickness, impurity concentration, or both of the second silicon carbide layer have a distribution in a plane parallel to the main surface of the silicon carbide wafer.

  Thereby, variation in element characteristics in a plane parallel to the main surface of the silicon carbide wafer, which is caused by the impurity concentration distribution on the surface of the first conductivity type impurity region, can be suppressed, so that the yield of silicon carbide semiconductor elements is improved. it can.

  According to the present invention, in the wafer with a silicon carbide layer in which the first silicon carbide layer is formed, the variation in device characteristics due to the impurity concentration distribution on the surface of the first silicon carbide layer is epitaxially grown on the first silicon carbide layer. This can be suppressed by controlling the growth conditions of the second silicon carbide layer. For this reason, the yield of a silicon carbide semiconductor element can be improved and manufacturing cost can be reduced.

(A)-(g) is typical process sectional drawing explaining the manufacturing method of the silicon carbide semiconductor element of 1st Embodiment by this invention, respectively. It is a top view for demonstrating the manufacturing method of the silicon carbide semiconductor element of 1st Embodiment by this invention, and is a figure corresponding to the process shown in FIG.1 (b). (A) is a graph illustrating the impurity concentration distribution on the surface of the body region in the first embodiment according to the present invention, and (b) is a graph on the body region derived according to the concentration distribution shown in (a). It is a graph which shows the in-plane distribution of the impurity concentration of the 2nd silicon carbide layer to form, (c) is a graph which shows the in-plane distribution of the threshold voltage obtained by the concentration distribution shown to (a) and (b). . (A) is a graph which shows the correlation with the supply amount of the source gas at the time of forming a 2nd silicon carbide layer, and the magnitude | size of the in-plane dispersion | variation in the impurity concentration and thickness of a 2nd silicon carbide layer, b) is a graph showing the distribution of the thickness and impurity concentration of the second silicon carbide layer in the plane of the wafer 1 with silicon carbide layer when the supply amount of the source gas (SiH ₄ ) is 10 sccm. (A) And (b) is a graph which shows the in-plane distribution of the thickness of the 2nd silicon carbide layer 115 when a growth pressure is set to 200 mbar and 100 mbar, respectively. It is typical sectional drawing for demonstrating the epitaxial growth process of a 2nd silicon carbide layer in the manufacturing method of 1st Embodiment by this invention. It is sectional drawing of the wafer with a silicon carbide layer of 1st Embodiment by this invention. It is sectional drawing which illustrates the unit cell of the other silicon carbide semiconductor element in 1st Embodiment by this invention. (A) is a top view of the conventional wafer with a silicon carbide layer, (b) is for demonstrating the structure of the unit cell of the silicon carbide semiconductor element formed in the wafer with a silicon carbide layer shown to (a). FIG. (A) And (b) is a schematic diagram for demonstrating the subject of the conventional silicon carbide semiconductor element, (a) is an example of the impurity concentration profile of the depth direction of p-type impurity implantation area | region 305 '. FIG. 6B is a cross-sectional view for explaining the impurity concentration on the surface of the body region 305 obtained by performing activation annealing on the p-type impurity implantation region 305 ′.

  First, the problems found by the present inventors will be described in more detail with reference to the drawings.

  FIG. 9A is a plan view illustrating a conventional wafer 401 with a silicon carbide layer in which the silicon carbide semiconductor element 400 is formed. Silicon carbide semiconductor element 400 is, for example, a MISFET having a planar structure. FIG. 9B is a cross-sectional view for explaining the configuration of the unit cell 300 included in the MISFET.

  The silicon carbide layer-equipped wafer 401 includes, for example, a silicon carbide wafer 301 having a diameter of 3 inches or more and a plurality of silicon carbide semiconductor elements 400 formed on the silicon carbide wafer 301. Each silicon carbide semiconductor element 400 is composed of a plurality of unit cells 300 arranged two-dimensionally.

  Each unit cell 300 includes, for example, an n-type silicon carbide wafer 301 and a first silicon carbide layer 310 formed by epitaxial growth on the silicon carbide wafer 301 as shown in FIG. 9B.

In the first silicon carbide layer 310, a p-type body region 305 and an n ⁺ -type source region 308 which is disposed so as to be in contact with the body region 305 and contains an n-type impurity at a high concentration are formed. A p ⁺ -type contact region 309 containing p-type impurities at a higher concentration than the body region 305 is formed inside the body region 305. Further, regions other than body region 305 and source region 308 in first silicon carbide layer 310 become n ⁻ type drift region 302 containing n-type impurities at a low concentration. An n-type second silicon carbide layer (channel layer) 307 is formed on first silicon carbide layer 310 so as to be in contact with the surface of body region 305. Second silicon carbide layer 307 is formed by epitaxial growth. A gate insulating film 311 is formed on the second silicon carbide layer 307 by, for example, thermal oxidation, and a gate electrode 313 is provided on the gate insulating film 311. A source electrode 312 is provided so as to be in contact with the source region 308 and the contact region 309. A drain electrode 314 is provided on the back surface of the silicon carbide wafer 301.

  In unit cell 300, body region 305, source region 308, and contact region 309 are impurity doped layers formed by implanting impurity ions into first silicon carbide layer 310 and then performing activation annealing.

  The activation annealing is usually performed by placing the silicon carbide layer-attached wafer 401 after implanting impurity ions into the first silicon carbide layer 310 in a chamber of an annealing apparatus and heating it to a predetermined temperature. At this time, in particular, when a silicon carbide wafer 301 of 3 inches or more is used, a temperature difference is likely to occur within the surface of the silicon carbide layer-attached wafer 401. For example, the temperature of the silicon carbide layer-attached wafer 401 tends to be higher at the central portion than the peripheral portion, or lower at the central portion than the peripheral portion. For this reason, the temperature distribution in the surface of wafer 401 with a silicon carbide layer (hereinafter simply referred to as “in-plane temperature distribution”) increases in temperature from the center of wafer 401 with a silicon carbide layer toward the periphery. In many cases, the distribution becomes lower (concentric distribution).

  For example, when activation annealing is performed using a self-revolving annealing apparatus, the in-plane temperature distribution tends to be a concentric distribution. In the chamber of the self-revolving type annealing apparatus, for example, a plurality of silicon carbide layer-attached wafers 401 are fixed to a disc-shaped holder, the holders are rotated, and the silicon carbide layer-attached wafers 401 are each rotated while being carbonized. The wafer 401 with silicon layer is heated. In such an annealing apparatus, the peripheral portion of the silicon carbide layer-attached wafer 401 is closer to the heat source than the central portion, and therefore tends to be at a high temperature. However, depending on the arrangement of the heat source and the temperature gradient with respect to the distance from the heat source, the central portion of the silicon carbide layer-attached wafer 401 may be hotter than the peripheral portion.

  As described above, when activation annealing is performed, silicon is selectively sublimated from the surface of the first silicon carbide layer 310, and a part of the surface layer disappears. The amount of disappearance of first silicon carbide layer 310 increases as the annealing temperature increases. Therefore, when the in-plane temperature distribution as described above occurs in the silicon carbide layer-attached wafer 401 during the activation annealing, the disappearance amount of the first silicon carbide layer 310 is also distributed in-plane corresponding to this in-plane temperature distribution. Arise.

  Depending on the structure of the annealing apparatus and the annealing method, the in-plane temperature distribution of the silicon carbide layer-attached wafer 401 may not be a concentric distribution. For example, when heating the silicon carbide layer-coated wafer 401 without rotating or revolving in the chamber of the annealing apparatus, the in-plane temperature distribution of the silicon carbide layer-coated wafer 401 is unlikely to be concentric. Even in such a case, there is a high possibility that the in-plane temperature distribution will not be uniform, and a non-uniform in-plane distribution may occur in the disappearance amount of the first silicon carbide layer 310.

  When the disappearance amount of first silicon carbide layer 310 is distributed in the plane, there is a possibility that the impurity concentration on the surface of first silicon carbide layer 310 may vary. Hereinafter, this reason will be described with reference to the drawings.

  FIG. 10A is a diagram illustrating an impurity concentration profile in the depth direction of a p-type impurity implantation region 305 ′ obtained by implanting a p-type impurity into the first silicon carbide layer 310. FIG. ) Is a cross-sectional view schematically showing a body region 305 obtained by performing activation annealing on a p-type impurity implantation region 305 ′. In practice, a plurality of body regions 305 are formed at intervals in the surface region of wafer 401 with a silicon carbide layer. Here, for simplicity, body region 305 is formed on the entire silicon carbide layer-containing wafer 401. FIG.

  As shown in FIG. 10A, the impurity concentration profile P of the p-type impurity implantation region 305 ′ is not uniform in the depth direction of the first silicon carbide layer 310. In the surface region of the p-type impurity implantation region 305 ′, the impurity concentration profile P is low on the surface of the first silicon carbide layer 310 and gradually increases as the depth D from the surface increases.

  When activation annealing is performed on the p-type impurity implantation region 305 ', a body region 305 is obtained as shown in FIG. In the activation annealing, as described above, the surface portion of the first silicon carbide layer 310 disappears. The impurity concentration profile P shown in FIG. 10A is maintained even after annealing.

  In the example shown in FIG. 10B, the disappearance amount of the silicon carbide layer 310 increases from the central portion toward the peripheral portion in the plane of the silicon carbide layer-attached wafer 401. For this reason, the body region 305 is thinner at the periphery than at the center.

  Since the impurity concentration profile of p-type impurity implantation region 305 after annealing is not uniform, impurities on the surface of first silicon carbide layer 310 (that is, the surface of body region 305) according to the disappearance amount of first silicon carbide layer 310. Concentration is different. In this example, at the periphery of the body region 305, the layer from the surface to the depth d1 disappears, resulting in an impurity concentration of c1. On the other hand, in the central portion, the layer from the surface to the depth d2 (d2 <d1) disappears, and as a result, the impurity concentration c2 becomes lower than the impurity concentration c1 in the peripheral portion.

  As described above, the amount of disappearance of first silicon carbide layer 310 is not uniform in the plane of the wafer with the silicon carbide layer due to the in-plane temperature distribution generated during the activation annealing, and therefore the first silicon carbide layer after the activation annealing is not uniform. The impurity concentration on the surface of 310 is also unevenly distributed. This becomes a factor that the characteristics vary among the plurality of silicon carbide semiconductor elements 400 formed on one silicon carbide wafer 301.

  In particular, the impurity concentration on the surface of the body region 305 greatly affects the threshold voltage of the MISFET. When the above distribution occurs in the impurity concentration on the surface of body region 305, a threshold voltage is generated between a plurality of silicon carbide semiconductor elements (MISFETs) 400 formed on silicon carbide wafer 301 corresponding to the concentration distribution. It varies.

  Thus, in the conventional manufacturing process of silicon carbide semiconductor element 400, due to the in-plane temperature distribution during activation annealing, the threshold voltage varies within the plane of silicon carbide wafer 301, and the reliability decreases. There was a risk of lowering the yield.

  In the course of studying the method for solving the above problem, the inventor forms the second silicon carbide layer 307 by epitaxial growth on the first silicon carbide layer 310 and the impurity concentration and thickness of the second silicon carbide layer 307. It was found that the in-plane distribution can be controlled. Further, by controlling the in-plane distribution of the impurity concentration and thickness of the second silicon carbide layer 307, the variation of the impurity concentration on the surface of the body region 305 formed in the first silicon carbide layer 310 is compensated, and the threshold voltage is increased. We obtained the knowledge that in-plane variation can be suppressed.

  The present invention has been made on the basis of the above knowledge, and according to the impurity concentration distribution on the surface of first silicon carbide layer 310 (for example, the surface of body region 305), second silicon carbide layer 307 is formed thereon. A predetermined in-plane distribution is deliberately produced in the thickness and concentration. This makes it possible to suppress variations in threshold voltage caused by the in-plane temperature distribution during activation annealing.

(First embodiment)
Hereinafter, a first embodiment of a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described with reference to the drawings. Here, a MISFET having a p-type conductivity as the first conductivity type and an n-type conductivity type as the second conductivity type will be described as an example. However, the silicon carbide semiconductor element of the present embodiment has an n-type, A MISFET having a p-type conductivity as the two-conductivity type may be used.

  1A to 1G are process cross-sectional views for illustrating a method for manufacturing a silicon carbide semiconductor element of this embodiment. FIG. 1 shows an element formation portion R1 where a silicon carbide semiconductor element is formed in the silicon carbide layer-attached wafer 1 and a part of a measurement portion R2 provided in a region other than the element formation portion. For the sake of simplicity, a process of forming one unit cell in the element forming unit R1 and one parameter check region in the measuring unit R2 is illustrated, but the element forming unit R1 includes a plurality of unit cells, A plurality of parameter check areas may be formed in the measurement unit R2.

  First, as shown in FIG. 1 (a), a second conductivity type (n-type) first silicon carbide layer 110 is grown on the main surface of a silicon carbide wafer 101 by epitaxial growth, and the silicon carbide layer provided wafer 1 is obtained. Get.

As the silicon carbide wafer 101, for example, a 4H—SiC wafer having a diameter of 75 mm and having an off angle of about 4 degrees in the <11-20> (112 bar 0) direction from the (0001) Si surface is used. preferable. By using this wafer, a silicon carbide semiconductor element having higher carrier mobility than a 6H—SiC wafer or the like can be manufactured. Silicon carbide wafer 101 is n-type, and the carrier concentration in silicon carbide wafer 101 is, for example, about 8 × 10 ¹⁸ cm ⁻³ .

In the step of forming first silicon carbide layer 110, first, the temperature of silicon carbide wafer 101 is raised before epitaxial growth. In this temperature raising process, the silicon carbide wafer 101 is heated in an atmosphere containing at least hydrogen without supplying the source gas. When the temperature of the silicon carbide wafer 101 (wafer temperature) reaches a predetermined growth temperature (here, 1600 ° C.), supply of the raw material gas and nitrogen as the dopant gas is started. In this way, on the main surface of silicon carbide wafer 101, for example, first silicon carbide layer 110 having an n-type carrier concentration of about 5 × 10 ¹⁶ cm ⁻³ and a thickness of about 10 μm is formed.

  Subsequently, as shown in FIG. 1B, p-type impurity implantation regions 105 ′ and 109 ′ are implanted by implanting p-type or n-type impurity ions into selected regions of the first silicon carbide layer 110. , And an n-type impurity implantation region 108 '.

  At this time, p-type impurity ions are also implanted into a part of measurement part R2 of wafer 1 with silicon carbide layer. As a result, a p-type impurity implantation region 116 'serving as a parameter check region is formed in the measurement unit R2.

  Specifically, a mask is formed on first silicon carbide layer 110, and p-type impurity (for example, aluminum) ions are implanted into a region where the mask is not formed, so that p-type impurity implantation region 105 ′ serving as a body region is formed. Then, a p-type impurity implantation region 116 ′ serving as a parameter check region is formed. The p-type impurity implantation regions 105 ′ and 116 ′ are simultaneously formed under the same implantation conditions. Further, n-type impurity (for example, nitrogen) ions are implanted into a region of the first silicon carbide layer 110 adjacent to the p-type impurity implantation region 105 ′ to form an n-type impurity implantation region 108 ′ serving as a source region. Further, p-type impurity (for example, aluminum) ions are implanted into the p-type impurity region 105 ′ to form a high-concentration p-type impurity implanted region 109 ′ to be a contact region.

  FIG. 2 is a plan view corresponding to the process cross-sectional view of FIG. As shown in FIG. 2, here, p-type impurity implantation region 116 'is formed along the center of silicon carbide layer-attached wafer 1 and two diameters extending in the X and Y directions orthogonal to each other. Here, three p-type impurity implantation regions 116 ′ are arranged at a pitch of 10 mm between the center and the periphery. Each p-type impurity implantation region 116 ′ is, for example, a circle having a diameter of 1 mm when viewed from the direction perpendicular to the main surface of silicon carbide wafer 101.

  The number and arrangement of the p-type impurity implantation regions 116 ′ are not limited to the illustrated example, but a plurality of p-type impurity implantation regions 116 ′ are preferably arranged from the center portion to the peripheral portion of the wafer 1 with silicon carbide layer. Alternatively, one p-type impurity implantation region 116 ′ extending from the central portion to the peripheral portion may be formed.

  In this example, p-type impurity region 105 ′ and p-type impurity region 116 ′ are formed in the surface region of first silicon carbide layer 110, but these regions may not be formed in the surface region. However, it is preferable that at least a part of p-type impurity region 105 ′ and at least a part of p-type impurity region 116 ′ are arranged to be exposed on the surface of first silicon carbide layer 110.

  Subsequently, a carbon cap layer 117 is formed on the surface of the first silicon carbide layer 110, and activation annealing is performed in this state. The annealing temperature is set to 1700 ° C., for example. Thereby, as shown in FIG. 1C, the impurity implantation regions 105 ′, 109 ′, and 108 ′ become the body region 105, the contact region 109, and the source region 108, respectively. Further, the p-type impurity implantation region 116 ′ becomes a parameter check region 116. In the first silicon carbide layer 110, a region where none of the body region 105, the contact region 109, the source region 108, and the parameter check region 116 is formed becomes an n-type drift region 102. Thereafter, the carbon cap layer 117 is removed. It should be noted that Si in the surface of the first silicon carbide layer 110 is sublimated by the activation annealing, and the portion remaining as a carbon layer is removed from the silicon carbide layer-attached wafer 1 together with the carbon cap layer 117.

  Next, a distribution of impurity concentration on the surface of the body region 105 (hereinafter abbreviated as “surface concentration distribution”) is obtained. The surface concentration distribution of the body region 105 may be obtained by measuring the impurity concentration on the surface of the parameter check region 116. The concentration is measured by, for example, capacitance-voltage (hereinafter abbreviated as CV) measurement. According to the CV measurement, the impurity concentration on the surface of the first silicon carbide layer 110 can be evaluated nondestructively.

  In this embodiment, as shown in FIG. 1D, the mercury probe CV measurement device is used, and the impurity concentration on the surface of each parameter check region 116 is evaluated by CV measurement. Based on this result, the surface concentration distribution of the body region 105 is calculated.

  The measurement procedure using the mercury probe CV measurement device will be described below. Silicon carbide wafer 101 is placed on the stage of the CV measuring apparatus. Mercury is brought into contact with the parameter check region 116 from a cylinder placed on the parameter check region 116, and a high frequency bias voltage is applied between the back surface of the silicon carbide wafer 101. The frequency in this case is 100 kHz, for example. By applying a bias voltage, the capacitance generated by the depletion layer formed in the parameter check region 116 is measured. Since the width of the depletion layer changes by sweeping the bias voltage, it is possible to derive a profile in the depth direction of the dopant concentration in the parameter check region 116 by measuring the capacitance at each bias voltage. .

  Subsequently, as shown in FIG. 1E, an n-type second silicon carbide layer 115 is formed on the surface of the first silicon carbide layer 110 by epitaxial growth. Here, second silicon carbide layer 115 is arranged in contact with body region 105 and functions as a channel layer.

  At this time, the surface concentration distribution of the body region 105 obtained in the above process is fed forward to the growth conditions of the second silicon carbide layer 115 so that the threshold voltage of the MISFET becomes uniform in the plane of the wafer 1 with the silicon carbide layer. . As described later, by adjusting the growth conditions of the second silicon carbide layer 115, the in-plane distribution of the impurity concentration and thickness of the second silicon carbide layer 115 in the plane of the silicon carbide layer-attached wafer 1 is arbitrarily controlled. it can.

In the present embodiment, the second silicon carbide layer (channel layer) 115 is formed by supplying nitrogen as a dopant gas. The average concentration of the second silicon carbide layer 115 is, for example, about 1 × 10 ¹⁷ cm ⁻³ and the average thickness is, for example, 100 nm. In addition, as will be described later, by controlling parameters such as the supply amount of the source gas and the growth pressure, the in-plane distribution corresponding to the surface concentration distribution of the body region 105 is adjusted to the thickness and concentration of the second silicon carbide layer 115. Is deliberately generated.

  In-plane distribution may be generated in both the concentration and thickness of second silicon carbide layer 115, or in-plane distribution may be generated in only one of them.

Thereafter, as shown in FIG. 1F, a gate insulating film 111 is formed. The gate insulating film 111 may be an oxide film, an oxynitride film, or a stacked film of these films. Here, as the gate insulating film 111, for example, a thermal oxidation (SiO ₂ ) film is formed by thermally oxidizing the surface of the first silicon carbide layer 110 at a temperature of about 1100 ° C. The thickness of the gate insulating film 111 is, for example, about 50 nm. Instead of the thermal oxide film, a SiO ₂ film may be formed on the first silicon carbide layer 110 by a CVD method.

  Finally, as shown in FIG. 1G, a gate electrode 113, a source electrode 112, and a drain electrode 114 are formed. For the source electrode 112 and the drain electrode 114, Ni is vapor-deposited on the back surface of the source region 108 and the silicon carbide wafer 101, respectively, using an electron beam (EB) vapor deposition apparatus, and then, for example, about 1000 ° C. using a heating furnace. It is formed by heating with. Source electrode 112 forms an ohmic junction with source region 108 and contact region 109, and drain electrode 114 forms an ohmic junction with silicon carbide wafer 101. The gate electrode 113 can be formed, for example, by depositing phosphorus-doped polysilicon (poly-Si film) on the gate insulating film 111 using an LPCVD (Low Pressure Chemical Vapor Deposition) apparatus.

  Through the above steps, a plurality of silicon carbide semiconductor elements are formed on wafer 1 with silicon carbide layer. Although not shown, the element forming portion R1 of the silicon carbide layer-equipped wafer 1 is thereafter cut for each element. Thereby, a plurality of silicon carbide semiconductor elements (chips) are obtained.

<Method for evaluating surface concentration distribution of body region 105>
In the above method, CV measurement using a mercury probe is performed as a method for evaluating the surface concentration distribution of the body region 105, but secondary ion mass spectrometry (SIMS) can also be performed instead. In SIMS, the concentration of impurities in the SiC crystal is measured by mass spectrometry while removing the surface of the first silicon carbide layer 110 by sputtering of Ar ions.

  However, when SIMS is used, the surface of the first silicon carbide layer 110 is destroyed in order to measure the impurity concentration while removing the surface of the first silicon carbide layer 110. Therefore, when this method is used, it is preferable to previously prepare a measurement region (pad) by SIMS in the measurement part R2 of the wafer 1 with silicon carbide layer. The measurement area may have the same structure as the parameter check area 116.

  Thus, the surface concentration distribution of body region 105 can be evaluated without breaking the portion of first silicon carbide layer 110 located at element formation region R1.

  As another evaluation method, there is a method of measuring the specific resistance of the surface of the body region 105. In this method, the specific resistance of the surface of the body region 105 or the parameter check region 116 is measured without directly measuring the impurity concentration (surface concentration) of the surface of the body region 105 or the parameter check region 116. Next, based on the correlation between the surface concentration and the specific resistance obtained in advance, the surface concentration of the region can be derived from the measurement result of the specific resistance.

  When performing nondestructive measurement as in the method of measuring specific resistance, the surface of body region 105 can be directly measured, so that parameter check region 116 is not formed on wafer 1 with silicon carbide layer. May be.

  Further, a correlation between the activation annealing condition and the surface concentration distribution of the body region 105 may be obtained in advance by a preliminary experiment. In this case, the surface concentration distribution can be derived based on the activation annealing conditions and the correlation obtained in advance without performing concentration measurement.

<Derivation of in-plane distribution of concentration and thickness of second silicon carbide layer 115>
Next, a procedure for determining the epitaxial growth conditions of the second silicon carbide layer 115 will be described with reference to FIG.

  FIG. 3A is a diagram illustrating the surface concentration distribution of the body region 105 derived from the measurement result of the impurity concentration of the surface of the parameter check region 116 by the mercury probe C-V measurement device in the above method. The surface concentration of the body region 105 has a concentric distribution due to, for example, an in-plane temperature distribution during annealing. In this example, it can be seen that the surface concentration of the body region 105 has a distribution that increases from the central portion toward the peripheral portion of the wafer 1 with silicon carbide layer.

  From the surface concentration distribution shown in FIG. 3 (a), the in-plane of the concentration and / or thickness of the second silicon carbide layer 115 for suppressing the variation in the threshold voltage of the MISFET in the in-plane of the wafer 1 with silicon carbide layer. Deriving the distribution.

  The higher the concentration of the second silicon carbide layer 115, the lower the resistance of the second silicon carbide layer 115, and thus the lower the threshold voltage. The lower the concentration of the second silicon carbide layer 115, the higher the threshold voltage. Further, as the second silicon carbide layer 115 is thicker, the depletion layer is less likely to spread in the second silicon carbide layer 115, so that the threshold voltage is lowered, and the thinner the second silicon carbide layer 115 is, the higher the threshold voltage is.

  Therefore, when body region 105 has the surface concentration distribution shown in FIG. 3A, if the thickness of second silicon carbide layer 115 is substantially constant in the plane, the impurity concentration of second silicon carbide layer 115 is the center. What is necessary is just to have in-plane distribution which becomes high toward a peripheral part from a part. FIG. 3B illustrates an in-plane distribution of the concentration of second silicon carbide layer 115 derived from the surface concentration distribution of body region 105. When the second silicon carbide layer 115 having the concentration distribution as shown is formed, the threshold voltage of the MISFET can be made substantially uniform in the plane as shown in FIG.

  On the other hand, the impurity concentration of second silicon carbide layer 115 may be substantially constant in the plane, and the thickness of second silicon carbide layer 115 may have an in-plane distribution that suppresses variations in threshold voltage. In that case, the thickness of second silicon carbide layer 115 only needs to have an in-plane distribution that increases from the central portion toward the peripheral portion (not shown). Furthermore, it is possible to suppress variations in threshold voltage by providing a distribution in both impurity concentration and thickness of second silicon carbide layer 115.

  Which of the thickness, impurity concentration, and both in-plane distributions of the second silicon carbide layer 115 is controlled may be appropriately selected according to the surface concentration distribution of the body region 105. For example, when the impurity concentration on the surface of body region 105 differs by 10 times or more between the central portion and the peripheral portion, the in-plane distribution of both the concentration and thickness of second silicon carbide layer 115 can be controlled. preferable.

When only one of the concentration and thickness of second silicon carbide layer 115 is controlled, normally, the in-plane distribution of the threshold voltage is made uniform by controlling the in-plane distribution of the concentration of second silicon carbide layer 115. It is effective. However, when the concentration difference in the surface concentration distribution of the body region 105 is small (for example, 3% or less), it is possible to control more strictly by controlling the in-plane distribution of the thickness of the second silicon carbide layer 115. It may be preferable.

<Feedforward Method for Growth Conditions of Second Silicon Carbide Layer 115>
Next, referring to FIG. 1 again, the procedure for feedforward to the growth conditions of the second silicon carbide layer 115 will be described below.

  First, in the step shown in FIG. 1D, after measuring the impurity concentration on the surface of the 13 parameter check regions 116, the extent of the surface concentration distribution of the body region 105 is calculated based on the result. To do.

  Next, whether to control the concentration or thickness of second silicon carbide layer 115 is determined according to the degree of surface concentration distribution of body region 105. When the surface concentration distribution of body region 105 is large (for example, concentration variation with respect to the average impurity concentration of body region 105: ± 50% or more), both the concentration and thickness of second silicon carbide layer 115 may be controlled. it can.

  Subsequently, an in-plane distribution of the impurity concentration and / or thickness of the second silicon carbide layer 115 is derived so that the threshold voltage of the MISFET satisfies the reference value and the reference range in the plane. Then, growth parameters and growth conditions are determined so that the derived in-plane distribution can be obtained.

  Thereafter, in the step shown in FIG. 1E, the second silicon carbide layer 115 is formed by applying feed-forward growth conditions.

  Note that the calculated surface concentration distribution of the body region 105 may be substantially uniform. In that case, a growth condition is selected such that the impurity concentration and thickness of the first silicon carbide layer 115 are substantially uniform in the plane.

  By feeding forward the growth conditions of the second silicon carbide layer 115, it becomes possible to give the thickness and impurity concentration of the second silicon carbide layer 115 a predetermined in-plane distribution based on the surface concentration distribution of the body region 105. . Therefore, the threshold voltages of a plurality of silicon carbide semiconductor elements (MISFETs) formed on the silicon carbide layer-attached wafer 1 can be controlled within a predetermined range. Here, “within a predetermined range” means that the variation of the threshold voltage of the MISFET with respect to the designed value (reference value) is within the reference range (for example, within ± 5%).

  Thus, when a silicon carbide semiconductor element is manufactured by the method of this embodiment, the variation in threshold voltage can be greatly reduced, and the in-plane distribution of the threshold voltage can be suppressed within the reference range. Therefore, a silicon carbide semiconductor element having excellent electrical characteristics expected from the excellent physical properties of silicon carbide can be manufactured with a high yield.

<Method for controlling in-plane distribution of impurity concentration and thickness of second silicon carbide layer 115>
Hereinafter, a correlation between conditions (growth conditions) for forming second silicon carbide layer 115 by epitaxial growth, impurity concentration (here, n-type impurity concentration) and thickness of second silicon carbide layer 115 will be described. . The correlation described below is summarized in Table 1.

(Control of raw material gas supply)
The inventor formed the second silicon carbide layer 115 under different growth conditions, and examined the in-plane distribution of the impurity concentration and thickness. From this result, by controlling the supply amount of the source gas, a desired in-plane distribution is obtained in the impurity concentration of the second silicon carbide layer 115 while keeping the thickness of the second silicon carbide layer 115 in-plane uniform. I found out that I can have it.

FIG. 4A is a graph showing the correlation between the supply amount of the source gas when forming the second silicon carbide layer 115 and the in-plane variation in the impurity concentration and thickness of the second silicon carbide layer 115. . The horizontal axis represents the supply amount of the source gas Si source gas (SiH ₄ ), and the vertical axis represents the in-plane variation in the impurity concentration and thickness of the second silicon carbide layer 115 and the growth rate of the second silicon carbide layer 115. Represents.

  As is apparent from this graph, when the supply amount of the source gas is decreased, the in-plane variation in the impurity concentration of the second silicon carbide layer 115 increases. On the other hand, the in-plane variation of the thickness of the second silicon carbide layer 115 is substantially constant (for example, in-plane variation: ± 5% or less) without largely depending on the supply amount of the source gas.

FIG. 4B shows the thickness and impurity concentration of the second silicon carbide layer at a distance from the center of the silicon carbide layer-attached wafer 1 when the supply amount of the Si source gas (SiH ₄ ) is 10 sccm. It is a graph. In this example, it can be seen that the impurity concentration (nitrogen concentration) of the second silicon carbide layer 115 is low at the center of the silicon carbide layer-attached wafer 1 and increases toward the periphery.

  From the results shown in FIGS. 4A and 4B, the following growth mechanism can be considered.

  When the supply amount of the Si source gas is increased, the Si source gas that decomposes at a low temperature (about 600 ° C.) easily reaches the center of the wafer 1 with silicon carbide layer. On the other hand, the C source gas is supplied substantially uniformly in the plane of the silicon carbide layer-coated wafer 1. For this reason, the ratio of the amount of the Si source gas to the amount of the C source gas is increased not only in the peripheral portion but also in the central portion of the wafer 1 with silicon carbide layer. As a result, the in-plane distribution of the supply amount ratio (C / Si ratio) of the source gas reaching the surface of the first silicon carbide layer 110 is reduced. During the epitaxial growth of SiC, nitrogen, which is an impurity, is taken into the C site. If the feed gas ratio (C / Si ratio) is substantially constant in the plane, the nitrogen concentration distribution is also substantially constant in the plane. Become.

  On the other hand, when the supply amount of the source gas is small, the Si source gas hardly reaches the center of the wafer 1 with silicon carbide layer. For this reason, in the center part of wafer 1 with a silicon carbide layer, the supply amount ratio (C / Si ratio) of source gas becomes larger than a peripheral part. When the supply ratio of the source gas has such an in-plane distribution, the concentration of nitrogen taken into the C site also has an in-plane distribution. For this reason, as shown in FIG.4 (b), the density | concentration (impurity density | concentration) of nitrogen of the 2nd silicon carbide layer 115 becomes higher than a peripheral part in the center part of the wafer 1 with a silicon carbide layer.

  Note that the supply ratio of the source gas in the plane of the silicon carbide layer-coated wafer 1 is adjusted by adjusting the supply amount of the C source gas instead of or in addition to the supply amount of the Si source gas. May be controlled.

  In this way, by controlling the supply amount of the source gas, the in-plane distribution of the impurity concentration of the second silicon carbide layer 115 can be independently controlled while keeping the thickness of the second silicon carbide layer 115 constant. .

  The impurity concentration of the second silicon carbide layer 115 has a greater influence on the threshold voltage of the MISFET than the thickness of the second silicon carbide layer 115. Therefore, when the surface concentration distribution of body region 105 is large (for example, in-plane variation in concentration: ± 3% or more), it is preferable to control the in-plane distribution of the concentration of second silicon carbide layer 115.

(Pressure during epitaxial growth)
The inventor has further found that the in-plane distribution of the thickness of the second silicon carbide layer 115 can be controlled by the pressure in the growth chamber (growth pressure) during epitaxial growth.

  FIGS. 5A and 5B are graphs showing the in-plane distribution of the thickness of the second silicon carbide layer 115 when the growth pressure is set to 200 mbar and 100 mbar, respectively. The vertical axis of the graph represents the thickness of the second silicon carbide layer 115, and the horizontal axis represents the distance from the center of the wafer 1 with the silicon carbide layer. The formation conditions of the second silicon carbide layer 115 other than the growth pressure are all the same.

  From this graph, it can be seen that the in-plane distribution of the concentration and thickness of the second silicon carbide layer 115 can be controlled by changing the growth pressure. The reason for this will be described below.

FIG. 6 is a schematic cross-sectional view for explaining the epitaxial growth step. As shown in FIG. 6, in the epitaxial growth step, a silicon carbide layer-attached wafer 1 is fixed on a holder 501 installed in a chamber (growth chamber), and a silicon carbide layer-attached wafer 1 (first silicon carbide layer 110). The source gas is supplied to the surface of At this time, a gas phase reaction layer 502 in which a gas phase reaction of a source gas (for example, SiH ₄ , C ₃ H ₈ ) occurs is formed above the surface of the silicon carbide layer-attached wafer 1. Further, a stagnation layer (diffusion layer) 504 is formed at the interface between the silicon carbide layer-attached wafer 1 and the gas phase reaction layer 502. The reactive species including Si and C diffuse from the gas phase reaction layer 502 through the stagnation layer 504 and reach the surface of the wafer 1 with silicon carbide layer.

  In the epitaxial growth process, the thickness of the stagnation layer 504 changes depending on the growth pressure. Specifically, when the growth pressure is high (for example, 200 mbar or more), the stagnation layer 504 is thicker at the periphery than the center of the wafer 1 with silicon carbide layer. When the growth pressure is low (for example, 50 mbar or less), the stagnation layer 504 is thicker at the center than the peripheral edge of the silicon carbide layer-attached wafer 1. The reason for this will be described below.

  In this embodiment, since the source gas is supplied from the central portion of the epitaxial growth chamber, the flow rate of the source gas differs between the central portion and the peripheral portion in the growth chamber. When the growth pressure is low, the flow rate of the gas is large at the center of the growth chamber and decreases toward the periphery, so that the stagnation layer 504 is thick at the center and thin at the periphery. When viewed from the silicon carbide layer-attached wafer 1 that rotates in the growth chamber, the flow rate of the source gas is higher in the central portion of the silicon carbide layer-attached wafer 1 than the peripheral portion, so that the stagnation layer 504 is the silicon carbide layer-attached wafer 1. It becomes thicker than the peripheral edge at the center. On the other hand, when the growth pressure is high, the difference in the gas flow rate between the growth chamber central portion and the peripheral portion becomes small, and when viewed from the rotating silicon carbide layer-attached wafer 1, the flow rate of the source gas is silicon carbide. The peripheral edge of the layered wafer 1 is higher than the central portion. For this reason, the stagnation layer 504 is thicker at the periphery than the center of the wafer 1 with silicon carbide layer.

  When the thickness of the stagnation layer 504 has the above distribution, the thickness and impurity concentration of the formed epitaxial film (second silicon carbide layer 115) are also distributed. In the region where the stagnation layer 504 is thick, the amount of raw material supplied to the surface of the first silicon carbide layer 110 therebelow is larger than in the thin region. For this reason, the thickness of the epitaxial film is increased. Also, in the thick region of the stagnation layer 504, the growth rate of the epitaxial film is high, so that the impurity concentration is low.

  Thus, by controlling the growth pressure, an in-plane distribution is generated in the thickness of the stagnation layer 504, and as a result, the in-plane distribution of the thickness and impurity concentration of the second silicon carbide layer 115 can be controlled. It becomes possible.

(Speed during epitaxial growth)
If the supply amount of a gas containing impurities (for example, nitrogen gas) is constant during epitaxial growth, the amount of impurities taken into the SiC crystal decreases as the epitaxial growth rate (growth rate) increases. The impurity concentration of the epitaxial film that becomes the silicon layer (channel layer) is lowered. Conversely, when the growth rate is low, nitrogen is easily taken into the SiC crystal, so that the impurity concentration of the epitaxial film becomes high.

  Therefore, if the epitaxial growth conditions are controlled so that the growth rate has a non-uniform distribution in the plane of the silicon carbide layer-attached wafer 1, the impurity concentration of the second silicon carbide layer 115 can be varied in the plane. Become.

(Other growth conditions)
Growth parameters other than the supply amount of raw material gas and the growth pressure can be controlled. For example, as shown in Table 1, even if the in-plane distribution of the thickness and impurity concentration of the second silicon carbide layer 115 is controlled by controlling the growth temperature and the feed gas ratio (C / Si ratio). Good.

  In the epitaxial growth step, the silicon carbide layer provided wafer 1 may be heated so that the temperature (growth temperature) at the time of epitaxial growth has a gradient in the plane of the silicon carbide layer provided wafer 1. For example, when the growth temperature is set high (for example, 1700 ° C. or higher) and the wafer 1 with silicon carbide layer 1 is heated while revolving, the temperature at the peripheral portion of the wafer 401 with silicon carbide layer becomes higher than that at the center. Since the growth rate of the epitaxial film can be increased at a portion where the growth temperature is high in the silicon carbide layer-attached wafer 1 as compared with a low portion, the growth rate can have a desired in-plane distribution. As described above, the higher the growth rate, the larger the thickness of the second silicon carbide layer 115 and the lower the impurity concentration.

  Even when the surface concentration distribution of body region 105 is not concentric, a surface in accordance with the surface concentration distribution of body region 105 can be obtained by controlling the growth parameters so that the thickness and impurity concentration of second silicon carbide layer 115 are adjusted. An internal distribution may be generated. For example, when the impurity concentration on the surface of body region 105 has such a distribution that increases from one end A of silicon carbide layer-attached wafer 401 to the other end B toward end B, second silicon carbide layer 115 has an end. The growth parameter may be controlled so that the portion B is thicker than the end A.

<Structure of wafer with silicon carbide layer on which silicon carbide semiconductor element is formed>
An example of the structure of wafer 1 with a silicon carbide layer in which a silicon carbide semiconductor element is formed using the method of this embodiment is shown in FIG.

  As shown in FIG. 7, the silicon carbide layer-equipped wafer 1 of the present embodiment includes an element forming portion R1 and a measuring portion R2 provided in a region other than the element forming portion R1. A plurality of unit cells 100 are formed in the element formation portion R1, and a plurality of parameter check regions 116 are formed in the measurement portion R2. In FIG. 7, one unit cell 100 and one parameter check area 116 are shown.

  Each unit cell 100 includes a silicon carbide wafer 101, a first silicon carbide layer 110 formed on silicon carbide wafer 101 and having a first conductivity type impurity region containing a first conductivity type impurity, and a first silicon carbide layer. 110 and a second silicon carbide layer 115 made of silicon carbide. First silicon carbide layer 110 and second silicon carbide layer 115 are formed by epitaxial growth. Second silicon carbide layer 115 contains a second conductivity type impurity.

  A plurality of body regions 105 are formed in first silicon carbide layer 110 as first conductivity type impurity regions. Second silicon carbide layer 115 is formed in contact with the surface of each body region 105.

  Source region 108 containing a second conductivity type impurity is formed in first silicon carbide layer 110 so as to be adjacent to body region 105. Here, source region 108 is surrounded by body region 105 on the surface of first silicon carbide layer 110. In each body region 105, a contact region 109 that is in contact with the body region 105 and contains a first conductivity type impurity at a higher concentration than the body region 105 is formed.

  Second silicon carbide layer 115 is disposed in contact with part of body region 105 and in contact with source region 108 and drift region 102 across part of body region 105.

  A gate electrode 113 is provided on the second silicon carbide layer 115 through a gate insulating film 111. On the first silicon carbide layer 110, a source electrode 112 in contact with the source region 108 and the contact region 109 is provided. The source electrode 112 is connected to the electrode wiring layer 118 in a contact hole formed in the interlayer insulating film 117. Furthermore, a drain electrode 114 is provided on the back surface (surface opposite to the main surface) of silicon carbide wafer 101.

  On the other hand, a parameter check region 116 is arranged in a portion (measurement unit R2) in which the silicon carbide semiconductor element is not formed in wafer 1 with a silicon carbide layer. The parameter check region 116 is formed by the same implantation step and activation annealing step as the body region 105 and contains the same impurities. If the disappearance amount of silicon carbide by activation annealing is substantially equal, the impurity concentration profiles in the depth direction of these regions are substantially the same.

  In this example, the concentration (surface concentration) of the first conductivity type impurity in the portion in contact with the second silicon carbide layer 115 in the surface of the body region 105 is higher in the peripheral portion than in the central portion of the wafer 1 with silicon carbide layer. . Further, the concentration of the second conductivity type impurity in the second silicon carbide layer 115 is higher at the peripheral portion than at the central portion of the wafer 1 with silicon carbide layer. Alternatively or in addition, the second silicon carbide layer 115 may be thicker at the periphery than the center of the wafer 1 with silicon carbide layer. Thereby, the in-plane variation in element characteristics due to the distribution of the surface concentration of body region 105 can be suppressed by the in-plane distribution of the thickness or impurity concentration of second silicon carbide layer 115.

  In the present embodiment, the surface concentration of body region 105 located at the peripheral edge of wafer 1 with silicon carbide layer is different from the surface concentration of body region 105 located at the center of wafer 1 with silicon carbide layer. For example, the surface concentration of the body region 105 in the present embodiment may have a concentric distribution.

  When the surface concentration of body region 105 located at the center of silicon carbide layer-provided wafer 1 is higher than the surface concentration of body region 105 located at the peripheral portion of wafer 1 with silicon carbide layer, in second silicon carbide layer 115 The concentration of the second conductivity type impurity has a distribution that is higher in the central portion than in the peripheral portion of the wafer 1 with silicon carbide layer. Alternatively or in addition, the second silicon carbide layer 115 may be thicker at the center than the peripheral edge of the silicon carbide layer-attached wafer 1. Even with such a configuration, the same effect as described above can be obtained.

  Thus, when the surface concentration of body region 105 located at the peripheral portion of wafer 1 with the silicon carbide layer is different from the surface concentration of body region 105 located at the central portion of wafer 1 with the silicon carbide layer. The portion of the second silicon carbide layer 115 that contacts the body region 105 having the higher surface concentration may be thicker than the portion that contacts the body region 105 having the lower surface concentration. Alternatively, the impurity concentration of the portion of the second silicon carbide layer 115 in contact with the body region 105 having the higher surface concentration may be set higher than the impurity concentration of the portion in contact with the body region 105 having the lower surface concentration. If at least one of the thickness and impurity concentration of the second silicon carbide layer 115 has the above distribution, the effect of the present invention can be obtained.

  A first conductivity type parameter check region 116 including the same impurity as that of body region 105 may be formed in a portion (measurement unit R <b> 2) in which silicon carbide semiconductor element is not formed in wafer 1 with silicon carbide layer. The impurity concentration on the surface of the parameter check region 116 is a portion located on the side where the body region 105 having a high surface concentration is disposed in the central portion and the peripheral portion of the wafer 1 with silicon carbide layer, and the body region 105 having a low surface concentration. It becomes higher than the part located in the direction where is arranged. Therefore, by measuring the impurity concentration on the surface of the parameter check region 116, the surface concentration distribution of the body region 105 can be obtained without damaging the surface of the body region 105 by measurement.

  In the present embodiment, a plurality of parameter check regions 116 are arranged in a region where the plurality of body regions 105 are not formed in the surface region of the first silicon carbide layer 110. Parameter check region 116 is preferably arranged at least in the central portion and the peripheral portion of silicon carbide layer-attached wafer 1. The surface concentration of the parameter check region 116 has the same distribution as the surface concentration of the body region 105.

  In the manufacturing method described above with reference to FIG. 1, a storage channel type MISFET having a planar structure is manufactured as a silicon carbide semiconductor element, but a MISFET having a trench structure may be manufactured.

  FIG. 8 is a cross-sectional view illustrating a storage channel type MISFET unit cell 200 having a trench structure. For simplicity, the same components as those in FIG.

  In the MISFET having the trench structure, the source region 108 of the second conductivity type is disposed in the surface region of the first silicon carbide layer 110, and the body region 105 is formed below the source region 108 and in contact with the source region 108. Has been. Contact region 109 is disposed in body region 105 and is electrically connected to body region 105. Drift region 102 is arranged between body region 105 and silicon carbide wafer 101.

  In addition, trench 120 is formed in first silicon carbide layer 110 so as to penetrate through source region 108 and body region 105 and reach drift region 102. A second silicon carbide layer 115 is formed in trench 120 so as to be in contact with drift region 102, body region 105, and source region 108. On the second silicon carbide layer 115, a gate insulating film 111 and a gate electrode 113 are provided in this order. Other configurations are the same as those shown in FIG.

  Even when a MISFET having a trench structure is manufactured using the silicon carbide wafer 101, the second region of the surface of the body region 105 is in contact with the second silicon carbide layer 115, that is, according to the concentration distribution of the sidewall portion of the trench 120. The in-plane distribution of the thickness or impurity concentration of silicon carbide layer 115 is controlled. Thereby, the effect similar to the method shown in FIG. 1 is acquired. Although not shown, a parameter check region may be formed in a portion of the wafer with a silicon carbide layer where no silicon carbide semiconductor element is formed, as in the configuration shown in FIG.

  In the present embodiment, a silicon carbide semiconductor device including a first silicon carbide layer including a first conductivity type impurity region and a second silicon carbide layer including a second conductivity type impurity formed on the surface thereof by epitaxial growth. It can be widely applied to the manufacturing method. As a result, the in-plane distribution of the thickness and / or impurity concentration of the second silicon carbide layer can be controlled based on the impurity concentration distribution on the surface of the first conductivity type impurity region, thereby suppressing in-plane variations in element characteristics. This can improve the yield.

  The manufacturing method of the silicon carbide semiconductor element of this embodiment is not limited to the said method. In the above method, the first conductivity type impurity region is formed by ion implantation and activation annealing, but another method (for example, a solid phase diffusion method using SOG (Spin on Glass)) may be used instead. The present embodiment can also be applied to the case where the surface concentration distribution of the first conductivity type impurity region becomes non-uniform by a method other than activation annealing. Further, in the above method, an epitaxial layer having a conductivity type different from that of the first conductivity type impurity region is formed as the second silicon carbide layer, but the conductivity types of the second silicon carbide layer and the first conductivity type impurity region are the same. It may be.

  The silicon carbide semiconductor element in the present embodiment is not limited to a vertical MISFET having a planar structure or a trench structure. For example, a lateral MISFET in which a source electrode and a drain electrode are disposed on the main surface of a silicon carbide wafer may be used. Or a diode, a junction field effect transistor (Junction Field Effect Transistor: JFET), etc. may be sufficient. Further, an insulated gate bipolar transistor (IGBT) can be manufactured using a silicon carbide wafer having a conductivity type different from that of the first silicon carbide layer 110.

  According to the present invention, in a method for manufacturing a silicon carbide semiconductor element using a silicon carbide wafer, variations in element characteristics in a plane parallel to the main surface of the wafer with a silicon carbide layer can be suppressed. Thereby, a silicon carbide semiconductor element can be manufactured with a high yield.

  The present invention is advantageous when applied to a power semiconductor device that requires low loss. In particular, the present invention is suitably applied to the manufacture of silicon carbide semiconductor elements such as MISFETs, IGBTs, JFETs, and diodes using a silicon carbide wafer having a diameter of 3 inches or more.

101, 301 Silicon carbide wafer 110, 310 First silicon carbide layer 102, 302 Drift region 105, 305 Body region 108, 308 Source region 109, 309 Contact region 111, 311 Gate insulating film 112, 312 Source electrode 113, 313 Gate electrode 114, 314 Drain electrode 115, 307 Second silicon carbide layer (channel layer)
100, 200, 300 MISFET unit cell 400 Silicon carbide semiconductor element (MISFET)

Claims (18)

(A) A silicon carbide layer comprising a silicon carbide wafer and a first silicon carbide layer that is disposed on the main surface of the silicon carbide wafer and has a plurality of first conductivity type impurity regions containing impurities of the first conductivity type. Preparing a wafer with a wafer,
(B) forming a second silicon carbide layer in contact with the plurality of first conductivity type impurity regions by epitaxially growing silicon carbide on the surface of the first silicon carbide layer;
In the step (B), the second carbonization is performed in a plane parallel to the main surface of the silicon carbide wafer based on the concentration distribution of the first conductivity type impurities on the surfaces of the plurality of first conductivity type impurity regions. A method for manufacturing a silicon carbide semiconductor device, wherein conditions for epitaxial growth are controlled so that the thickness of the silicon layer, the impurity concentration, or both are distributed. The step (A)
Ion-implanting a first conductivity type impurity into the first silicon carbide layer;
The plurality of first conductivity type impurity regions are formed by activating the first conductivity type impurity ion-implanted into the first silicon carbide layer by annealing the silicon carbide layer-attached wafer. The manufacturing method of the silicon carbide semiconductor element of Claim 1 including the process to do.   After the step (A) and before the step (B), by measuring the concentration of the first conductivity type impurity on the surface of the first silicon carbide layer, the plurality of first conductivity type impurity regions The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a step (C) of deriving a concentration distribution of the first conductivity type impurity on the surface. The first silicon carbide layer further includes a first conductivity type parameter check region disposed in a portion of the surface region of the first silicon carbide layer where the plurality of first conductivity type impurity regions are not disposed. And
In the step (C), the concentration of the first conductivity type impurity on the surface of the parameter check region is measured, and based on this, the concentration of the first conductivity type impurity on the surface of the plurality of first conductivity type impurity regions is measured. The method for manufacturing a silicon carbide semiconductor element according to claim 3, wherein a concentration distribution is derived. The step (A)
Ion-implanting a first conductivity type impurity into the first silicon carbide layer;
An annealing process is performed on the silicon carbide layer-attached wafer to activate the first conductivity type impurities ion-implanted into the first silicon carbide layer, whereby the plurality of first conductivity type impurity regions and The method for manufacturing a silicon carbide semiconductor device according to claim 4, further comprising a step of forming a parameter check region.   In the step (C), the concentration of the first conductivity type impurity on the surface of the plurality of first conductivity type impurity regions is measured, and based on this, the first concentration on the surface of the plurality of first conductivity type impurity regions is measured. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein a concentration distribution of the conductivity type impurity is derived.   The method for manufacturing a silicon carbide semiconductor element according to claim 1, wherein in the step (B), the second silicon carbide layer includes a second conductivity type impurity.   Among the plurality of first conductivity type impurity regions, the concentration of the first conductivity type impurity at the surface of the first conductivity type impurity region disposed in the center of the wafer with the silicon carbide layer is a value of the wafer with the silicon carbide layer. The method for manufacturing a silicon carbide semiconductor element according to claim 1, wherein the concentration of the first conductivity type impurity on the surface of the first conductivity type impurity region disposed in the peripheral portion is different from that of the first conductivity type impurity region. In the step (B),
The thickness of the second silicon carbide layer is such that the first conductivity type impurity region disposed at the center portion of the wafer with the silicon carbide layer and the first conductivity type disposed at the peripheral portion of the wafer with the silicon carbide layer. The epitaxial growth conditions are set so that the portion of the impurity region in contact with the higher concentration of the first conductivity type impurity on the surface is larger than the portion of the surface in contact with the lower concentration of the first conductivity type impurity. The manufacturing method of the silicon carbide semiconductor element of Claim 8 controlled. In the step (B),
The impurity concentration of the second silicon carbide layer is the first conductivity type disposed in the first conductivity type impurity region disposed in the center of the wafer with the silicon carbide layer and the peripheral portion of the wafer with the silicon carbide layer. The epitaxial growth conditions are set so that the portion of the impurity region in contact with the higher concentration of the first conductivity type impurity on the surface is higher than the portion of the surface in contact with the lower concentration of the first conductivity type impurity. The manufacturing method of the silicon carbide semiconductor element of Claim 8 or 9 to control.   In the step (B), the conditions for the epitaxial growth include the flow rate of the source gas supplied to the silicon carbide layer-attached wafer, the ratio of the amount of carbon and silicon supplied to the silicon carbide layer-attached wafer, and the growth during epitaxial growth. The method for manufacturing a silicon carbide semiconductor element according to any one of claims 1 to 10, including at least one of an indoor pressure and a temperature of the silicon carbide layer-attached wafer during epitaxial growth.   The silicon carbide according to claim 3, wherein in the step (C), the concentration of the first conductivity type impurity is measured by capacitance-voltage measurement, secondary ion mass spectrometry measurement, or specific resistance measurement. A method for manufacturing a semiconductor device.   The method for manufacturing a silicon carbide semiconductor element according to any one of claims 1 to 12, wherein the silicon carbide wafer is a 4H-SiC wafer having a (0001) Si surface having an off angle of 2 degrees to 10 degrees as a main surface. .   The method for manufacturing a silicon carbide semiconductor element according to claim 1, wherein the first conductivity type impurity region is a body region, and the second silicon carbide layer is a channel layer. The step (A)
The first silicon carbide layer includes the body region, a second conductivity type source region adjacent to the body region, and a first conductivity type impurity disposed in the body region at a higher concentration than the body region. And a step of forming a first conductivity type contact region including a region of the first silicon carbide layer in which neither the body region nor the source region is disposed becomes a second conductivity type drift region,
After the step (B),
Forming a gate insulating film in contact with the second silicon carbide layer;
Forming a gate electrode on the gate insulating film;
Forming a source electrode in contact with the source region;
The method for manufacturing a silicon carbide semiconductor device according to claim 14, further comprising: forming a drain electrode on a surface opposite to the main surface of the silicon carbide wafer. A silicon carbide wafer;
A first silicon carbide layer disposed on the silicon carbide wafer;
A plurality of first conductivity type impurity regions disposed in the first silicon carbide layer and containing a first conductivity type impurity;
A silicon carbide layer provided wafer comprising a second silicon carbide layer disposed on and in contact with each of the plurality of first conductivity type impurity regions on the first silicon carbide layer,
The second silicon carbide layer contains impurities of a second conductivity type;
The concentration α of the first conductivity type impurity in the portion in contact with the second silicon carbide layer among the surfaces of the plurality of first conductivity type impurity regions is the same as that with the silicon carbide layer in the plurality of first conductivity type impurity regions. The first conductivity type impurity region disposed in the center of the wafer is different from the first conductivity type impurity region disposed in the peripheral portion of the wafer with the silicon carbide layer,
The thickness of the second silicon carbide layer is such that the first conductivity type impurity region disposed at the center of the wafer with the silicon carbide layer and the first conductivity type disposed at the peripheral portion of the wafer with the silicon carbide layer. Of the impurity region, the portion in contact with the higher concentration α and larger than the portion in contact with the lower concentration α, and / or
The wafer with a silicon carbide layer, wherein the impurity concentration of the second silicon carbide layer is higher at the portion in contact with the higher concentration α and higher than the portion in contact with the lower concentration α. A parameter check region including the same impurity as the first conductivity type impurity region in a portion of the surface region of the first silicon carbide layer where the first conductivity type impurity region is not disposed;
The concentration of the first conductivity type impurity on the surface of the parameter check region is the one in which the first conductivity type impurity region having the higher concentration α is disposed in the central portion and the peripheral portion of the wafer with the silicon carbide layer. 17. The wafer with a silicon carbide layer according to claim 16, which is higher in a portion located at a position higher than a portion located at a position where the first conductivity type impurity region having a lower concentration α is disposed. The first conductivity type impurity region is a body region;
The first silicon carbide layer includes a second conductivity type source region disposed adjacent to the body region, and a first conductivity type impurity disposed in the body region at a higher concentration than the body region. And a second conductivity type drift region located in a region of the first silicon carbide layer in which neither the body region nor the source region is disposed,
A gate insulating film in contact with the second silicon carbide layer;
A gate electrode provided on the gate insulating film;
A source electrode disposed in contact with the source region;
The wafer with a silicon carbide layer according to claim 16 or 17, further comprising a drain electrode provided on a surface opposite to the main surface of the silicon carbide wafer.

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