JP6508369B2 - Silicon carbide semiconductor device and method of manufacturing the same - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device and a method of manufacturing the same, and more particularly to a silicon carbide semiconductor device having a trench formed on a main surface and a method of manufacturing the same.

  BACKGROUND In recent years, in order to enable use of a semiconductor device with high breakdown voltage, low loss, high temperature environment, etc., adoption of silicon carbide as a material of the semiconductor device is being promoted. Silicon carbide is a wide band gap semiconductor having a large band gap as compared to silicon which has conventionally been widely used as a material for constituting a semiconductor device. Therefore, by adopting silicon carbide as a material forming the semiconductor device, it is possible to achieve high breakdown voltage of the semiconductor device, reduction of on-resistance, and the like. In addition, a semiconductor device employing silicon carbide as a material also has an advantage in that the decrease in characteristics when used under a high temperature environment is smaller than a semiconductor device employing silicon as a material.

  For example, Japanese Unexamined Patent Publication No. 2008-147232 (Patent Document 1) describes a trench type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) made of silicon carbide. According to the MOSFET, the thickness of the channel layer is made equal to or more than the length obtained by a predetermined formula so that punch-through due to the short channel effect does not occur, and the lower end of the base layer is closer to the drain electrode than the lower end It is provided to be located on the side.

Also, Y. Nakano et al., “690 V, 1.00 mΩ cm ² 4 H—SiC Double-Trench MOSFETs”, Materials Science Forum Vols. 717-720 (2012) page 1069-1072 (non-patent document 1) for switching A MOSFET is described in which a trench for holding a breakdown voltage is formed adjacent to the trench and the bottom of the trench for holding a breakdown voltage is provided closer to the drain electrode than the bottom of the switching trench. A p-type base layer is provided in the lower part of the withstand voltage holding trench.

  Furthermore, according to the trench MOSFET described in WO 2013/157259 (Patent Document 2), the p-type region is provided in contact with the bottom of the gate trench.

JP, 2008-147232, A International Publication No. 2013/157259

Y. Nakano et al., "690 V, 1.00 mΩ cm 24 H-SiC Double-Trench MOSFETs", Materials Science Forum Vols. 717-720 (2012) page 1069-1072

  The vertical power transistor realizes high breakdown voltage at the pn junction between the base layer and the drift layer. The breakdown voltage is designed by controlling the electric field in the semiconductor to a predetermined value by adjusting the concentration and thickness of the drift layer. In the case of switching at the interface between the semiconductor and the insulating film, the insulating film is also exposed to a high electric field. In particular, since silicon carbide has a high dielectric breakdown electric field, a design capable of achieving a high breakdown voltage by increasing the electric field in the semiconductor can be realized, but the switching portion needs a structure for alleviating the high electric field. Since the trench type transistor can reduce the cell pitch, the degree of integration of the cell can be increased and the on-resistance can be reduced. However, since the electric field strength in the region where the trench portion protrudes becomes high, the withstand voltage is lowered compared to the planar transistor.

According to the MOSFET described in JP2008-147232A, the bottom of the trench is provided closer to the source electrode than the end of the p-type base layer on the drain electrode side, so that the electric field is not concentrated in the trench. A depletion layer spreading under the p-type base layer prevents an electric field from being applied to the bottom of the trench. Also, according to the MOSFET described in Y. Nakano et al., "690 V, 1.00 mΩ cm ² 4 H-SiC Double-Trench MOSFETs", Materials Science Forum Vols. 717-720 (2012) page 1069-1072, the above structure is fabricated. For this purpose, a breakdown voltage holding trench is created adjacent to the switching trench, a p-type base layer is provided below the breakdown voltage holding trench, and a depletion layer is formed at a deep position to form a trench for the current control portion. Protecting the structure.

  However, in each of the above-described structures, the current flowing out of the current control unit at the time of on interferes with the effect of spreading to the drift layer, so the on-resistance increases. For example, in a high breakdown voltage device of 1200 V or more, particularly a high breakdown voltage device of 3300 V or more, the impurity concentration of the drift layer decreases. Therefore, the depletion layer of the p-type base layer spreads, and the current emitted from the channel does not effectively spread to the drift layer, resulting in an increase in on-resistance. Further, if the distance between the trench and the p-type base layer is increased, the electric field in the trench can not be sufficiently relaxed, and the breakdown voltage of the MOSFET is degraded. On the other hand, shortening the distance between the gate trench and the p-type base layer increases the on-resistance of the MOSFET. That is, the on-resistance and the breakdown voltage are in a trade-off relationship.

  Furthermore, according to the MOSFET described in WO 2013/157259, the electric field at the bottom of the trench is relaxed by forming a p-type region at the bottom of the trench. However, since the electric field is concentrated on the side of the trench, it is difficult to maintain the withstand voltage high enough.

  An object of one aspect of the present invention is to provide a silicon carbide semiconductor device capable of reducing on-resistance and improving withstand voltage, and a method of manufacturing the same.

  A method of manufacturing a silicon carbide semiconductor device according to an aspect of the present invention includes the following steps. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface is formed. The step of forming the silicon carbide substrate includes the step of forming a first impurity region having a first conductivity type by epitaxial growth, and performing ion implantation to the first impurity region to form a second conductive type different from the first conductivity type. A step of forming a buried region having a conductivity type and arranged periodically, and an impurity having a second conductivity type in contact with the first impurity region and the buried region and lower than the buried region Forming a second impurity region having a concentration by epitaxial growth; and forming a third impurity region having a first conductivity type and separated from the first impurity region by the second impurity region. A trench is formed which has a side portion extending through the second impurity region and the third impurity region to the first impurity region, and a bottom portion connected to the side portion, and arranged at the same cycle as the buried region. Ru. A gate insulating film in contact with the first impurity region, the second impurity region, and the third impurity region is formed on the side portion of the trench.

  A silicon carbide semiconductor device according to an aspect of the present invention includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate has a first impurity region having a first conductivity type, a second impurity region in contact with the first impurity region and a second conductivity type different from the first conductivity type, and a first conductivity type. A third impurity region separated from the first impurity region by the second impurity region and a second conductivity type, having an impurity concentration higher than that of the second impurity region, and on the side of the second main surface And a buried region extending from a part of the end of the second impurity region toward the second main surface. A trench having a side portion connected to the first main surface and a bottom portion connected to the side portion is formed on the first main surface of the silicon carbide substrate. The gate insulating film is in contact with the first impurity region, the second impurity region, and the third impurity region on the side portion of the trench, and in contact with the first impurity region at the bottom of the trench. A third position from the position closest to the third impurity region to the boundary portion between the third impurity region and the embedded region among the positions in the embedded region having an impurity concentration four times the impurity concentration of the third impurity region The distance along the normal direction of the main surface of 1 is 0.3 μm or less.

  According to one aspect of the present invention, it is possible to provide a silicon carbide semiconductor device capable of reducing on-resistance and improving withstand voltage, and a method of manufacturing the same.

It is a cross-sectional schematic diagram for demonstrating schematically the structure of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating schematically the surface orientation of the silicon carbide substrate of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. FIG. 3 is a schematic plan view for schematically illustrating the structure of the trench in the silicon carbide semiconductor device in accordance with the first embodiment of the present invention. FIG. 5 is a schematic plan view for schematically illustrating the positional relationship between the trench and the embedded region in the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 7 is a diagram schematically illustrating impurity concentrations in the second impurity region and the buried region of the silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 6 is a flow diagram schematically illustrating a method of manufacturing a silicon carbide semiconductor device according to the first embodiment of the present invention. FIG. 5 is a schematic cross sectional view for schematically illustrating the first step of the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment of the present invention. It is a cross-sectional schematic diagram for demonstrating schematically the 2nd process of the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. FIG. 7 is a schematic cross sectional view for schematically illustrating the third step of the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment of the present invention. It is a cross-sectional schematic diagram for demonstrating schematically the 4th process of the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. FIG. 14 is a schematic cross sectional view for schematically illustrating the fifth step of the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment of the present invention. It is a cross-sectional schematic diagram for demonstrating schematically the 6th process of the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. FIG. 14 is a schematic cross sectional view for schematically illustrating the seventh step of the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment of the present invention. FIG. 16 is a schematic cross sectional view for schematically illustrating the eighth step of the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment of the present invention. FIG. 16 is a schematic cross sectional view for schematically illustrating a ninth step of the method for manufacturing the silicon carbide semiconductor device in accordance with the first embodiment of the present invention. It is a cross-sectional schematic diagram for demonstrating schematically the structure of the silicon carbide semiconductor device which concerns on Embodiment 2 of this invention. FIG. 13 is a schematic cross sectional view for schematically illustrating the first step of the method for manufacturing the silicon carbide semiconductor device in accordance with the second embodiment of the present invention. FIG. 13 is a schematic cross sectional view for schematically illustrating the second step of the method for manufacturing the silicon carbide semiconductor device in accordance with the second embodiment of the present invention. FIG. 16 is a schematic cross sectional view for schematically illustrating the third step of the method for manufacturing the silicon carbide semiconductor device in accordance with the second embodiment of the present invention. It is a cross-sectional schematic diagram for demonstrating schematically the structure of the silicon carbide semiconductor device which concerns on Embodiment 3 of this invention. FIG. 13 is a schematic cross sectional view for schematically illustrating the method for manufacturing the silicon carbide semiconductor device in accordance with the third embodiment of the present invention. It is a cross-sectional schematic diagram for demonstrating schematically the structure of the silicon carbide semiconductor device which concerns on Embodiment 4 of this invention.

Description of the embodiment of the present invention
First, the embodiments of the present invention will be listed and described.

  (1) A method of manufacturing a silicon carbide semiconductor device 1 according to an aspect of the present invention includes the following steps. A silicon carbide substrate 10 having a first main surface 10a and a second main surface 10b opposite to the first main surface 10a is formed. In the step of forming silicon carbide substrate 10, the step of forming first impurity region 12 having the first conductivity type by epitaxial growth, and the step of performing ion implantation on first impurity region 12 A step of forming a buried region 17 having a different second conductivity type and arranged periodically, and in contact with the first impurity region 12 and the buried region 17 and having a second conductivity type, and being buried Forming a second impurity region 13 having an impurity concentration lower than that of the buried region 17 by epitaxial growth, and a third impurity region having a first conductivity type and separated from the first impurity region 12 by the second impurity region 13 And b. It has a side portion SW penetrating through the second impurity region 13 and the third impurity region 14 to the first impurity region 12 and a bottom portion BT connected to the side portion SW, and at the same period as the embedded region 17 Arranged trenches TR are formed. A gate insulating film 15 in contact with the first impurity region 12, the second impurity region 13, and the third impurity region 14 is formed on the side portion SW of the trench TR.

  According to the method of manufacturing silicon carbide semiconductor device 1 according to the above (1), after buried region 17 is formed by performing ion implantation to first impurity region 12, first impurity region 12 and the buried region 17 are buried. In contact with the region 17, a second impurity region 13 having an impurity concentration lower than that of the buried region 17 is formed by epitaxial growth. Therefore, the ion implantation energy can be reduced as compared to the case where the embedded region 17 is formed by ion implantation from the surface of the second impurity region 13 after the second impurity region 13 is formed. As a result, channeling and multiple scattering of ions occur due to the high ion implantation energy, and it is possible to suppress the diffusion of ion-implanted impurities from obstructing the current flow. Further, since the pn junction formed of first impurity region 12 and buried region 17 is formed at a position deep away from first main surface 10a of silicon carbide substrate 10, the electric field in trench TR is effectively cut off can do. Furthermore, since the second impurity region 13 to be a channel is formed by epitaxial growth, a high quality channel can be realized.

  (2) In the method of manufacturing silicon carbide semiconductor device 1 according to (1), preferably, in the step of forming trench TR, side portion SW of trench TR is separated from buried region 17 by first impurity region 12. As a result, the trench TR is formed. The distance between the side portion SW of the trench TR and the side surface of the embedded region 17 opposite to the side portion SW in the direction parallel to the first major surface 10a is 0.2 μm or more and 5 μm or less. When the distance D between the side portion SW of the trench TR and the side surface of the buried region 17 is smaller than 0.2 μm, the spread of the current from the channel is prevented and the on-resistance is increased. When the distance D between the side portion SW of trench TR and the side surface of buried region 17 is larger than 5 μm, buried region 17 reduces the effect of shielding the electric field at bottom portion BT of trench TR. Therefore, distance D between side portion SW of trench TR and the side surface of buried region 17 opposite to side portion SW in the direction parallel to first main surface 10a of silicon carbide substrate 10 is 0.2 μm or more and 5 μm. It is preferable that it is the following.

  (3) In the method of manufacturing silicon carbide semiconductor device 1 according to (1), preferably, in the step of forming trench TR, trench TR is formed such that embedded region 17 is exposed at bottom portion BT of trench TR. . As a result, the bottom portion BT of the trench TR is effectively shielded from the high electric field, whereby the breakdown voltage can be improved.

  (4) In the method of manufacturing silicon carbide semiconductor device 1 according to (3), preferably, the width of bottom portion BT of trench TR in the direction parallel to first main surface 10 a is larger than the width of buried region 17. large. Thereby, it is possible to suppress that the flow of current is interrupted by the depletion layer spreading from the side surface of the embedded region 17. As a result, the on-resistance can be reduced.

  (5) In the method for manufacturing silicon carbide semiconductor device 1 according to any one of (1) to (4), preferably, depth H1 of trench TR in the normal direction of first main surface 10a is 0.3 μm. The width is not less than 3 μm and smaller than the width of the trench TR in the direction parallel to the first major surface 10 a. If the depth H1 of the trench TR is smaller than 0.3 μm, formation of a channel becomes difficult. When the depth H1 of the trench TR is larger than 3 μm, it becomes difficult to control the shape of the trench. Therefore, the depth H1 of the trench TR is preferably 0.3 μm or more and 3 μm or less.

  (6) In the method of manufacturing silicon carbide semiconductor device 1 according to any one of (1) to (5), preferably, the first main surface of the silicon carbide substrate is a surface turned off in the off direction from the {0001} plane. It is. Side portion SW of trench TR includes a surface SW1 perpendicular to the off direction and having a plane orientation perpendicular to the normal direction of first main surface 10a. By making the plane having the normal to the off direction and the direction perpendicular to the side walls as the side walls of the main trench, it is possible to minimize the deviation of the plane orientation of the side walls. In addition, when the off direction is, for example, the <11-20> direction, it is possible to form the flatter silicon carbide epitaxial layer 5.

  (7) In the method of manufacturing silicon carbide semiconductor device 1 according to any one of the above (1) to (6), preferably, the step of forming embedded region 17 is performed from the normal direction of first main surface 10a. Ion implantation is performed in a direction perpendicular to the off direction and inclined by 2 ° or more and 10 ° or less with respect to the direction parallel to the first major surface 10 a. Channeling can be effectively suppressed by performing ion implantation in a direction perpendicular to the off direction and inclined by 2 ° or more and 10 ° or less with respect to the direction parallel to the first major surface 10a. Further, when the embedded region 17 is formed at the corner portion CR of the bottom portion BT of the trench TR in which deterioration of the withstand voltage easily occurs, occurrence of positional deviation of the embedded region 17 can be effectively suppressed.

  (8) In the method of manufacturing silicon carbide semiconductor device 1 according to any one of (1) to (7), preferably, in the step of forming trench TR, viewed from the normal direction of first main surface 10a, Trench TR is formed such that corner CR of bottom BT of trench TR overlaps buried region 17. Thereby, it is possible to shield the electric field at the corner CR of the bottom BT of the trench TR in which the breakdown voltage tends to deteriorate.

  (9) In the method for manufacturing silicon carbide semiconductor device 1 according to any one of (1) to (8), preferably, the step of forming silicon carbide substrate 10 includes the first impurity region from the second main surface 10b side. 12 further includes the step of forming a periodically arranged carrier injection region 28 having the second conductivity type by performing ion implantation to 12. As a result, by promoting the injection of carriers from the carrier injection region 28, the on-resistance can be reduced.

  (10) A silicon carbide semiconductor device 1 according to an aspect of the present invention includes a silicon carbide substrate 10 and a gate insulating film 15. Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b opposite to first main surface 10a. Silicon carbide substrate 10 includes a first impurity region 12 having a first conductivity type, a second impurity region 13 in contact with the first impurity region 12 and a second conductivity type different from the first conductivity type, and a first A third impurity region 14 having a conductivity type, separated from the first impurity region 12 by a second impurity region 13, and having a second conductivity type, having an impurity concentration higher than that of the second impurity region 13; And, it includes a buried region 17 extending from a part of the end 13a of the second impurity region 13 on the side of the second major surface 10b toward the second major surface 10b. In first main surface 10a of silicon carbide substrate 10, a trench TR is formed having a side portion SW connected to first main surface 10a and a bottom portion BT connected to side portion SW. Gate insulating film 15 is in contact with first impurity region 12, second impurity region 13 and third impurity region 14 at side portion SW of trench TR, and at the bottom portion BT of trench TR with first impurity region 12 Contact. The boundary between the second impurity region 13 and the buried region 17 from the position closest to the second impurity region 13 among the positions in the buried region 17 having an impurity concentration four times the impurity concentration of the second impurity region 13 The distance to the portion along the normal direction of the first major surface 10a is 0.3 μm or less. Thus, the electric field is sufficiently shielded in the embedded region 17 to reduce the capacitance of the source portion.

  (11) Preferably, in silicon carbide semiconductor device 1 according to (10), corner portion CR of bottom portion BT of trench TR overlaps with buried region 17 when viewed in the normal direction of first main surface 10a. Is located in Thereby, it is possible to shield the electric field at the corner CR of the bottom BT of the trench TR in which the breakdown voltage tends to deteriorate.

  (12) In silicon carbide semiconductor device 1 according to (10) or (11), preferably, first impurity region 12 is in contact with first region 12 a in contact with second impurity region 13 and with first region 12 a, The second region 12b is located opposite to the second impurity region 13 as viewed from the first region 12a and has an impurity concentration higher than that of the first region 12a, and in contact with the second region 12b as viewed from the second region 12b. And a third region 12c opposite to the first region 12a and having an impurity concentration lower than that of the second region 12b. As a result, at the time of off, the depletion layer spreads in the first region 12a having a low impurity concentration, whereby the electric field in the trench TR is relaxed, whereby a high breakdown voltage can be maintained. At the on time, the voltage applied to gate electrode 27 allows carriers to be collected around trench TR from second region 12 b having a high impurity concentration. As a result, since high conductivity can be realized, the on-resistance can be reduced. That is, the on-resistance can be reduced and the withstand voltage can be improved.

(13) Preferably, in silicon carbide semiconductor device 1 according to any one of (10) to (12), silicon carbide substrate 10 has a second conductivity type, and forms second main surface 10b, and A second conductivity type epitaxial layer 29 provided in contact with the first impurity region 12 and a second conductivity type, and in contact with the second conductivity type epitaxial layer 29 and the first impurity region 12, a second conductivity type epitaxial It further includes carrier injection regions 28 having a higher impurity concentration than layer 29 and provided periodically. As a result, by promoting the injection of carriers from the carrier injection region 28, the on-resistance can be reduced.
Details of the Embodiment of the Present Invention
Hereinafter, embodiments of the present invention will be described based on the drawings. In the following drawings, the same or corresponding parts have the same reference characters allotted and description thereof will not be repeated. In the crystallographic description in the present specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. Also, as for the negative index, in crystallographic terms, "-" (bar) is to be added above the numbers, but in the present specification, the numbers are attached with a negative sign.

Embodiment 1
First, the configuration of a MOSFET as a silicon carbide semiconductor device according to the first embodiment of the present invention will be described.

  Referring to FIG. 1, MOSFET 1 according to the first embodiment includes silicon carbide substrate 10, gate electrode 27, gate insulating film 15, interlayer insulating film 21, source electrode 16, source interconnection 19, and drain. The electrode 20 and the protective film 24 are mainly included. Silicon carbide substrate 10 has a first main surface 10 a and a second main surface 10 b opposite to first main surface 10 a, and is on silicon carbide single crystal substrate 11 and silicon carbide single crystal substrate 11. And the silicon carbide epitaxial layer 5 provided in FIG.

  Silicon carbide single crystal substrate 11 is made of, for example, hexagonal silicon carbide single crystal of polytype 4H. The maximum diameter of first main surface 10a of silicon carbide substrate 10 is, for example, 150 mm, preferably 150 mm or more. First main surface 10a of silicon carbide substrate 10 is, for example, a surface which is off by 8 ° or less from the {0001} plane or the {0001} plane. The thickness of silicon carbide single crystal substrate 11 is, for example, 400 μm. The resistivity of silicon carbide single crystal substrate 11 is, for example, 0.017 Ωcm.

  Silicon carbide epitaxial layer 5 includes first impurity region 12, base region 13 (second impurity region 13), source region 14 (third impurity region 14), contact region 18, buried region 17, and buffer. The layer 22 is mainly included. Buffer layer 22 is provided on silicon carbide single crystal substrate 11. The first impurity region 12 is provided on the buffer layer 22. Each of first impurity region 12 and buffer layer 22 is an n-type (first conductivity type) region including an n-type impurity (donor) for giving n-type such as nitrogen. The first impurity region 12 is in contact with the base region 13 and the buried region 17.

The concentration of the n-type impurity such as nitrogen contained in the first impurity region 12 and the thickness of the first impurity region 12 change depending on the withstand voltage. When the withstand voltage is 1200 V, the thickness of first impurity region 12 is, for example, about 10 μm, and the nitrogen concentration contained in first impurity region 12 is about 1 × 10 ¹⁶ cm ⁻³ . When the breakdown voltage is 1700 V, the thickness of the first impurity region 12 is, for example, about 20 μm, and the nitrogen concentration contained in the first impurity region 12 is about 5 × 10 ¹⁵ cm ⁻³ . Further, when the withstand voltage is 3300 V, the thickness of the first impurity region 12 is, for example, about 30 μm, and the nitrogen concentration contained in the first impurity region 12 is about 3 × 10 ¹⁵ cm ⁻³ .

Preferably, the concentration of n-type impurities such as nitrogen contained in buffer layer 22 is lower than the concentration of n-type impurities such as nitrogen contained in silicon carbide single crystal substrate 11. The concentration of an n-type impurity such as nitrogen contained in silicon carbide single crystal substrate 11 is, for example, 5 × 10 ¹⁸ cm ⁻³ or more and 9 × 10 ¹⁸ cm ⁻³ or less. The concentration of n-type impurities such as nitrogen contained in buffer layer 22 is, for example, not less than 1 × 10 ¹⁸ cm ^{−3 and not} more than 2 × 10 ¹⁸ cm ⁻³ . Preferably, the concentration of the n-type impurity such as nitrogen contained in the first impurity region 12 is lower than the concentration of the n-type impurity such as nitrogen contained in the buffer layer 22.

Base region 13 (second impurity region 13) is provided on each of first impurity region 12 and buried region 17 so as to be in contact with first impurity region 12. The base region 13 is a region having p-type (second conductivity type) different from n-type. Base region 13 includes a p-type impurity (acceptor) for imparting p-type such as Al (aluminum) or B (boron), for example. The concentration of p-type impurities such as aluminum in base region 13 is, for example, 7 × 10 ¹⁵ cm ⁻³ . Base region 13 is an epitaxial layer formed by, for example, epitaxial growth. The thickness of base region 13 is, for example, 0.5 μm.

Source region 14 (third impurity region 14) is provided on base region 13 so as to be separated from first impurity region 12 by base region 13. Source region 14 includes an n-type impurity such as phosphorus for giving n-type, and has n-type. The concentration of the n-type impurity contained in the source region 14 is higher than the concentration of the n-type impurity contained in the first impurity region 12. The concentration of n-type impurities such as phosphorus contained in source region 14 is, for example, 1 × 10 ²⁰ cm ⁻³ .

Contact region 18 is a p-type region containing a p-type impurity such as aluminum or boron, for example. The contact region 18 is provided to penetrate through each of the source region 14 and the base region 13 to reach the buried region 17 so as to be sandwiched between each of the source region 14 and the base region 13. In other words, contact region 18 is formed to connect first main surface 10 a of silicon carbide substrate 10 to embedded region 17. The concentration of the p-type impurity contained in the contact region 18 is higher than the concentration of the p-type impurity contained in the base region 13. The concentration of the p-type impurity such as aluminum contained in contact region 18 is, for example, 1 × 10 ²⁰ cm ⁻³ .

Buried region 17 includes p-type impurities such as aluminum or boron, for example, and has p-type. Buried region 17 has a higher impurity concentration than base region 13. The concentration of the p-type impurity such as aluminum contained in the embedded region 17 is, for example, 5 × 10 ¹⁷ cm ⁻³ or more and 8 × 10 ¹⁸ cm ⁻³ or less. The element and concentration of impurities contained in each of the above-mentioned regions can be measured, for example, by SCM (Scanning Capacitance Microscope) or SIMS (Secondary Ion Mass Spectrometry).

  Buried region 17 is in contact with each of contact region 18 and base region 13. It is provided to extend from a part of end 13a of base region 13 on the second main surface 10b side of silicon carbide substrate 10 toward second main surface 10b. In other words, the buried region 17 is located on the opposite side of the source region 14 as viewed from the base region 13 and located on the opposite side of the source electrode 16 as viewed from the contact region 18. The width of the buried region 17 in the direction parallel to the first major surface 10 a may be larger than the width of the contact region 18.

  The end of the embedded region 17 on the side of the second main surface 10b and the side portion of the embedded region 17 are cross-sectional views (views along a direction parallel to the first main surface 10a of the silicon carbide substrate 10) In 1), a part of the first impurity region 12 is formed so as to be sandwiched between two buried regions 17.

  In first main surface 10a of silicon carbide substrate 10, a trench TR is formed having a side portion SW connected to first main surface 10a and a bottom portion BT connected to side portion SW. The side portion SW of the trench TR penetrates each of the source region 14 and the base region 13 to reach the first impurity region 12, and the bottom portion BT of the trench TR is located in the first impurity region 12. That is, the first impurity region 12, the base region 13, and the source region 14 are in contact with the side portion SW of the trench, and the first impurity region 12 is in contact with the bottom portion BT of the trench TR. Side portion SW of trench TR extends along a direction substantially parallel to the normal direction of first main surface 10 a of silicon carbide substrate 10, and bottom portion BT of trench TR is a portion of silicon carbide substrate 10. It is substantially parallel to the first major surface 10a. The boundary between the side portion SW and the bottom portion BT of the trench TR may be formed to have a curvature. Buried region 17 is provided opposite to a corner where side portion SW of trench TR and bottom portion BT meet. Bottom portion BT of trench TR is located on the second main surface 10b side with respect to the surface along the end of embedded region 17 on the first main surface 10a side, and the buried region on the second main surface 10b side It is located closer to the first major surface 10 a than the surface along the end portion of 17.

  If the depth H1 of the trench TR is smaller than 0.3 μm, formation of a channel becomes difficult. When the depth H1 of the trench TR is larger than 3 μm, it becomes difficult to control the shape of the trench. Therefore, the depth H1 of the trench TR is preferably 0.3 μm or more and 3 μm or less. More preferably, depth H1 of trench TR is 0.3 μm or more and 2 μm or less, and further preferably 0.8 μm or more and 1.5 μm or less. The depth H1 of the trench TR is preferably smaller than the width of the trench TR. When the depth H1 of the trench TR is smaller than the width of the trench TR, the gate insulating film 15 having a uniform thickness can be easily formed in contact with the side portion SW and the bottom portion BT of the trench TR.

  When the distance D between the side portion SW of the trench TR and the side surface of the buried region 17 is smaller than 0.2 μm, the spread of the current from the channel is prevented and the on-resistance is increased. When the distance D between the side portion SW of trench TR and the side surface of buried region 17 is larger than 5 μm, buried region 17 reduces the effect of shielding the electric field at bottom portion BT of trench TR. Therefore, distance D between side portion SW of trench TR and the side surface of buried region 17 opposite to side portion SW in the direction parallel to first main surface 10a of silicon carbide substrate 10 is 0.2 μm or more and 5 μm. It is preferable that it is the following. More preferably, the distance D between the side portion SW of the trench TR and the side surface of the buried region 17 opposite to the side portion SW is 1 μm or more and 2 μm or less.

  As described above, in the JFET region sandwiched by the pn junction of the first impurity region 12 having the n-type region and the buried region 17 having the p-type, a withstand voltage securing channel is formed. A current control channel is formed in base region 13 in contact with side portion SW of trench TR. By setting the current flowing in the current control channel and the direction of the current flowing in the JFET region to be substantially the same, the current is controlled by the gate electrode 27 in contact with the gate insulating film 15, and the breakdown voltage is secured in the JFET region.

  Gate insulating film 15 is made of, for example, silicon dioxide, and is provided in contact with side portion SW of trench TR and bottom portion BT. Gate insulating film 15 is in contact with first impurity region 12, base region 13 and source region 14 at side portion SW of trench TR, and is in contact with first impurity region 12 at bottom portion BT of trench TR. A channel region CH can be formed in the base region 13 in contact with the gate insulating film 15.

  The gate electrode 27 is disposed in contact with the gate insulating film 15 and is provided to fill the groove formed by the gate insulating film 15. The gate electrode 27 may be provided exposed from the source region 14. Gate electrode 27 is made of, for example, a conductor such as polysilicon doped with an impurity.

  Source electrode 16 is made of, for example, a material containing Ni and Ti. Source electrode 16 is in contact with each of source region 14 and contact region 18 at first main surface 10 a of silicon carbide substrate 10. Source electrode 16 includes an alloy layer in ohmic contact with source region 14. The alloy layer is, for example, a silicide with a metal contained in source electrode 16. Preferably, the source electrode 16 is made of a material containing Ti, Al and Si.

  Interlayer insulating film 21 is provided at a position facing first main surface 10 a of silicon carbide substrate 10. Specifically, interlayer insulating film 21 is provided in contact with each of gate electrode 27 and gate insulating film 15 so as to cover gate electrode 27. Interlayer insulating film 21 includes, for example, a TEOS (Tetra Ethyl Ortho Silicate) oxide film and PSG (Phosphorus Silicon Glass). The interlayer insulating film 21 electrically insulates the gate electrode 27 and the source electrode 16. Source interconnection 19 covers interlayer insulating film 21 and is provided in contact with source electrode 16. Source interconnection 19 is electrically connected to source region 14 via source electrode 16. Source interconnection 19 is made of, for example, a material containing AlSiCu. The protective film 24 is provided on the source wiring 19 so as to cover the source wiring 19. Protective film 24 includes, for example, a nitride film and polyimide.

  Drain electrode 20 is provided in contact with second main surface 10 b of silicon carbide substrate 10. The drain electrode 20 is made of, for example, a material capable of ohmic junction with the n-type silicon carbide single crystal substrate 11 such as NiSi (nickel silicide). Thus, drain electrode 20 is electrically connected to silicon carbide single crystal substrate 11.

  The plane orientation of silicon carbide substrate 10 will be described with reference to FIG. First main surface 10a of silicon carbide substrate 10 is a surface turned off in the off direction a1 by, for example, the off angle θ from the {0001} plane (the surface shown by the broken line). The off direction is a direction in which the normal vector z of the first major surface 10a is inclined from the [0001] direction. In FIG. 2, the direction c is the [0001] direction (that is, the c-axis of hexagonal silicon carbide), and the off direction a1 is, for example, the <11-20> direction. The off angle θ is preferably an angle of 8 ° or less. The in-plane off direction is a direction obtained by projecting the off direction onto the first major surface 10 a. In the case of FIG. 2, the in-plane off direction is the a11 direction. The angle formed by the off direction a1 and the in-plane off direction a11 is equal to the off angle θ. The off direction a1 is not limited to, for example, the <11-20> direction. The off direction a1 may be, for example, a <1-100> direction.

  The planar structure of the trench TR formed in the semiconductor chip 40 will be described with reference to FIG. FIG. 1 is a cross-sectional view of region I-I in FIG. That is, the depth direction in FIG. 1 corresponds to the in-plane off direction a11. In a plan view (a view along the normal direction of first main surface 10a of silicon carbide substrate 10), bottom portion BT of trench TR has, for example, a rectangular shape. The longitudinal direction of the rectangle is, for example, the same direction as the in-plane off direction a11. The in-plane off direction a11 is, for example, a direction obtained by projecting the <11-20> direction onto the first major surface 10a, and is a direction including a component in the <11-20> direction. The short side direction of the rectangle is a direction parallel to the first major surface 10a and a direction a21 perpendicular to the in-plane off direction a11. The direction a21 is, for example, a <1-100> direction. The semiconductor chip 40 may include a plurality of trenches TR arranged side by side in the lateral direction of the trenches TR and a guard ring 41 surrounding the plurality of trenches TR. Trenches TR are periodically arranged, for example, along the <1-100> direction.

  FIG. 4 is an enlarged view of a region IV in FIG. As shown in FIG. 4, the side SW of the trench TR includes a first side SW1 and a second side SW2. The first side portion SW1 of the trench TR is a surface which is perpendicular to the off direction a1 and has a plane orientation of a direction a21 perpendicular to the normal direction of the first major surface 10a. The first side portion SW1 is, for example, a (1-100) plane having a normal in the <1-100> direction. The second side portion SW2 of the trench TR is a surface having a surface orientation in the in-plane off direction a11. The second side SW2 is a surface having a normal including, for example, a component in the <11-20> direction.

  Referring to FIG. 4, embedded region 17 may include a first embedded region 17 a and a second embedded region 17 b. In a plan view, the first embedded region 17a is formed to surround the entire side portion SW of the trench TR. The second embedded region 17 b is arranged to overlap the four corners CR of the bottom portion BT of the trench TR in a plan view. In other words, when viewed in the normal direction of first main surface 10a, embedded region 17 is arranged to overlap corner CR of bottom BT of trench TR, and is sandwiched between two adjacent corners CR. It is arranged outside the bottom BT so that it does not overlap the bottom BT in the region.

  The distribution of the impurity concentration in base region 13 and buried region 17 will be described with reference to FIG. Each of base region 13 and buried region 17 contains a p-type impurity such as aluminum, for example. The impurity concentration d1 of the p-type impurity in the base region 13 is lower than the maximum value of the impurity concentration of the p-type impurity in the buried region 17. Since base region 13 is an impurity region formed by epitaxial growth, the impurity concentration in base region 13 is substantially constant in the normal direction of first main surface 10a (that is, the direction of arrow X in FIG. 1). . Since the embedded region 17 is an impurity region formed by multistage ion implantation, it has a plurality of maximum values in the direction along the normal direction of the first major surface 10a. Among the positions c1, c2, c3 and c4 having an impurity concentration d2 (= d1 × 4) four times the impurity concentration d1 of the base region 13 in the buried region 17, the base from the position c1 closest to the base region 13 The distance A along the normal direction of the first major surface 10a to the boundary b1 between the region 13 and the embedded region 17 is 0.3 μm or less.

  Next, the operation of the MOSFET 1 according to the first embodiment will be described. Referring to FIG. 1, in the state where the voltage applied to gate electrode 27 is less than the threshold voltage, that is, in the off state, base region 13 and the first region 13 are selected even if a voltage is applied between source electrode 16 and drain electrode 20. The pn junction formed between the first impurity region 12 and the first impurity region 12 is reverse biased and becomes nonconductive. On the other hand, when a voltage higher than the threshold voltage is applied to gate electrode 27, an inversion layer is formed in the channel region which is the vicinity of contact with gate insulating film 15 of base region 13. As a result, source region 14 and first impurity region 12 are electrically connected, and a current flows between source electrode 16 and drain electrode 20. As described above, the MOSFET 1 operates.

  Next, a method of manufacturing MOSFET 1 as the silicon carbide semiconductor device according to the first embodiment will be described.

  Referring to FIG. 7, silicon carbide single crystal substrate 11 is prepared, for example, by slicing a silicon carbide single crystal ingot grown by the modified Lely method, cutting out the substrate, and mirror polishing the surface of the substrate. Ru. Silicon carbide single crystal substrate 11 is, for example, hexagonal silicon carbide of polytype 4H. The diameter of the main surface of silicon carbide single crystal substrate 11 is, for example, 150 mm, and the thickness is, for example, 400 μm. The main surface of silicon carbide single crystal substrate 11 is, for example, a surface which is off by about 8 ° or less from the {0001} plane or the {0001} plane.

Next, an n-type epitaxial layer forming step (S10: FIG. 6) is performed. For example, a carrier gas containing hydrogen, a raw material gas containing silane and propane, and a dopant gas containing nitrogen are supplied onto silicon carbide single crystal substrate 11, and silicon carbide single crystal substrate 11 is supplied under a pressure of 100 mbar (10 kPa). Is heated to, for example, about 1550.degree. Thereby, as shown in FIG. 8, n-type silicon carbide epitaxial layer 5 is formed on silicon carbide single crystal substrate 11. Silicon carbide epitaxial layer 5 has a buffer layer 22 formed on silicon carbide single crystal substrate 11 and a first impurity region 12 formed on buffer layer 22. The first impurity region 12 is doped with nitrogen, and the concentration of nitrogen is, for example, 1.0 × 10 ¹⁶ cm ⁻² . The thickness of first impurity region 12 is, for example, 10 μm. As described above, the n-type first impurity region 12 is formed by epitaxial growth.

Next, a p-type buried region forming step (S20: FIG. 6) is performed. Specifically, referring to FIG. 9, ion implantation mask 31 is formed on first impurity region 12 of silicon carbide epitaxial layer 5. The ion implantation mask is made of a material including a TEOS oxide film, and the thickness of the ion implantation mask 31 is, for example, 1.6 μm. Next, RF (Radio Frequency) etching is performed on the ion implantation mask 31 using CHF ₃ and O ₂ . Thereby, a through film of, for example, about 80 nm is left on a portion where ion implantation is to be performed. Next, ion implantation is performed on first impurity region 12 of silicon carbide epitaxial layer 5 using ion implantation mask 31 having a through film. For example, Al (aluminum) ions are implanted in the direction of the arrow into silicon carbide epitaxial layer 5 through the through film, to thereby have p type conductivity and a higher impurity concentration than base region 13. Region 17 is formed (see FIG. 10). In a cross-sectional view, the buried region 17 has portions of the plurality of buried regions 17 spaced apart. Specifically, embedded region 17 is periodically arranged in the direction parallel to first main surface 10a of silicon carbide substrate 10 and in the direction a21 (see FIG. 3).

  Conditions for ion implantation such as acceleration voltage and dose so that the impurity concentration of the embedded region 17 on the second main surface 10b side is higher than the impurity concentration of the embedded region 17 on the first main surface 10a side Is adjusted. Preferably, in the step of forming buried region 17, the normal direction of first main surface 10a is perpendicular to off direction a1 and at least 2 ° with the direction parallel to first main surface 10a. For example, aluminum ions are implanted in a direction inclined by 10 ° or less. The direction perpendicular to the off direction a1 and parallel to the first major surface 10a is, for example, the <1-100> direction. As described above, by implanting ions into the first impurity region 12, buried regions 17 having p-type different from n-type and periodically arranged are formed.

Next, a p-type epitaxial layer forming step (S40: FIG. 6) is performed. Specifically, for example, base region 13 having p-type doped with aluminum at a concentration of 7 × 10 ¹⁵ cm ⁻³ is formed by epitaxial growth. The base region is formed by epitaxial growth so as to be in contact with the buried region 17 and the first impurity region 12 (see FIG. 11). The thickness of base region 13 is, for example, 0.5 μm. As described above, base region 13 having p-type conductivity and having an impurity concentration lower than that of buried region 17 is formed by epitaxial growth in contact with first impurity region 12 and buried region 17.

Next, an n-type source region forming step (S50: FIG. 6) is performed. Referring to FIG. 12, ion implantation mask 33 is formed on base region 13. The ion implantation mask is made of, for example, a material including a TEOS oxide film, and the thickness of the ion implantation mask 31 is, for example, 1.6 μm. Next, RF etching is performed on the ion implantation mask 33 using CHF ₃ and O ₂ . Thereby, a through film of, for example, about 80 nm is left on the region where the source region 14 is formed. Next, ion implantation is performed on base region 13 of silicon carbide epitaxial layer 5 using ion implantation mask 33 having a through film. For example, P (phosphorus) ions are ion-implanted into the base region 13 of the silicon carbide epitaxial layer 5 through the through film in the direction of the arrow to form the n-type source region 14 (see FIG. 12). Preferably, in the step of forming source region 14, from the normal direction of first main surface 10a, perpendicular to off direction a1, and at least 2 ° to the direction parallel to first main surface 10a. For example, phosphorus ions are implanted in a direction inclined at an angle less than or equal to °. The direction perpendicular to the off direction a1 and parallel to the first major surface 10a is, for example, the <1-100> direction. As described above, source region 14 which has n-type and is separated from first impurity region 12 by base region 13 is formed.

Next, a p-type contact region formation step (S60: FIG. 6) is performed. Referring to FIG. 13, ion implantation mask 34 is formed on base region 13 and source region 14. The ion implantation mask is made of, for example, a material including a TEOS oxide film, and the thickness of the ion implantation mask 31 is, for example, 1.6 μm. Next, RF etching is performed on the ion implantation mask 34 using CHF ₃ and O ₂ . Thereby, a through film of, for example, about 80 nm is left on the region where the contact region 18 is to be formed. Next, ion implantation is performed on base region 13 of silicon carbide epitaxial layer 5 using ion implantation mask 34 having a through film. For example, aluminum ions are implanted into base region 13 to a depth reaching buried region 17. Thereby, source region 14 and base region 13 are formed so as to connect first main surface 10a of silicon carbide substrate 10 with buried region 17, and are each formed to connect p type contact region 18 of a conductivity type. Are formed (see FIG. 13). Preferably, in the step of forming contact region 18, the direction normal to first main surface 10a is perpendicular to off direction a1 and at least 2 ° with the direction parallel to first main surface 10a. For example, aluminum ions are implanted in a direction inclined at an angle of not more than °. The direction perpendicular to the off direction a1 and parallel to the first major surface 10a is, for example, the <1-100> direction.

  Next, an activation annealing step is performed. After ion implantation mask 34 is removed from first main surface 10a of silicon carbide substrate 10, first main surface 10a of silicon carbide substrate 10 is covered with a protective film. Next, silicon carbide substrate 10 is heated, for example, at a temperature of 1650 ° C. or more and 1750 ° C. or less for about 30 minutes in an argon atmosphere. Thereby, the p-type impurity such as aluminum contained in base region 13, the n-type impurity such as phosphorus contained in source region 14 and the p-type impurity such as aluminum contained in contact region 18 are activated. .

Next, a trench formation step (S70: FIG. 6) is performed. Referring to FIG. 14, an etching mask 35 is formed on source region 14 and contact region 18. The etching mask 35 is made of, for example, a material including a TEOS oxide film, and the thickness of the etching mask 35 is, for example, 1.6 μm. Next, RF etching is performed on the etching mask 35 on the region where the trench TR is to be formed using CHF ₃ and O ₂ to form an opening in the etching mask 35. Next, etching is performed on silicon carbide substrate 10 using etching mask 35 in which an opening is formed on the region where trench TR is to be formed. For example, ECR (Electron Cyclotron Resonance) plasma etching is performed on silicon carbide substrate 10 using SF ₆ and O ₂ . Thereby, trench TR having side portion SW connected to first main surface 10a of silicon carbide substrate 10 and bottom portion BT connected to side portion SW is formed. Source region 14, base region 13 and first impurity region 12 are exposed at side portion SW of trench TR, and first impurity region 12 is exposed at bottom portion BT of trench TR.

  Referring to FIGS. 3 and 14, the period of trench TR along the direction a21 is the same as the period of buried region 17 along the direction a2. That the period of the trench TR is the same as the period of the buried region 17 means that the distance between the two adjacent trenches TR is almost the same as the distance between the two adjacent buried regions 17 and there is an alignment error or the like. It does not matter. In other words, one embedded region 17 may be provided corresponding to one trench TR. As described above, it has side portion SW extending through base region 13 and source region 14 to first impurity region 12 and bottom portion BT connected to side portion SW, and has the same cycle as embedded region 17. Trenches TR are formed in the

  Preferably, in the step of forming trench TR, trench TR is formed such that side portion SW of trench TR is separated from buried region 17 by first impurity region 12. Distance D (see FIG. 1) between side portion SW of trench TR and the side surface of buried region 17 opposite to side portion SW in the direction parallel to first main surface 10a of silicon carbide substrate 10 is 0.2 μm It is 5 μm or less. Preferably, depth H of trench TR in a direction normal to first main surface 10a of silicon carbide substrate 10 is 0.3 μm or more and 3 μm or less, and parallel to first main surface 10a of silicon carbide substrate 10 Smaller than the width of the trench TR in one direction.

  Preferably, first main surface 10a of silicon carbide substrate 10 is a surface turned off in the off direction a1 from the {0001} plane. As shown in FIG. 4, the side SW of the trench TR includes a first side SW1 and a second side SW2. The first side portion SW1 of the trench TR is a surface which is perpendicular to the off direction a1 and has a plane orientation of a direction a21 perpendicular to the normal direction of the first major surface 10a. The second side portion SW2 of the trench TR is a surface having a surface orientation in the in-plane off direction a11.

  Preferably, in the step of forming trench TR, trench TR is formed such that corner CR of bottom portion BT of trench TR overlaps buried region 17 as viewed in the normal direction of first main surface 10a. Referring to FIG. 4, embedded region 17 may include a first embedded region 17 a and a second embedded region 17 b. In a plan view, the first embedded region 17a is formed to surround the entire side portion SW of the trench TR. The second embedded region 17 b is formed to overlap the four corner portions CR of the bottom portion BT of the trench TR in a plan view. In other words, when viewed in the normal direction of first main surface 10a, buried region 17 is arranged to overlap corner CR of bottom BT of trench TR, and is sandwiched between two adjacent corners CR. Trench TR is formed to be disposed outside of bottom portion BT so as not to overlap with bottom portion BT in the region.

  Next, a gate oxide film formation step (S80: FIG. 6) is performed. Specifically, silicon carbide substrate 10 having trench TR formed in first main surface 10a is arranged in the heating furnace. By introducing oxygen into the heating furnace and dry oxidizing silicon carbide substrate 10 at a temperature of, for example, 1100 ° C. or more and 1200 ° C. or less, gate insulating film 15 in contact with side portion SW and bottom portion BT of trench TR is formed. . Gate insulating film 15 is in contact with first impurity region 12, base region 13 and source region 14 at side portion SW of trench TR, and is in contact with first impurity region 12 at the bottom portion BT of trench TR (FIG. 15). reference). The thickness of gate insulating film 15 is, for example, about 90 nm.

  Next, a NO annealing step is performed. Specifically, silicon carbide substrate 10 having gate insulating film 15 formed on first main surface 10a in a nitrogen-containing atmosphere is heat-treated at a temperature of, for example, 1250 ° C. or more and 1350 ° C. The gas containing nitrogen is, for example, dinitrogen monoxide diluted 10% with nitrogen or the like. Preferably, silicon carbide substrate 10 on which gate insulating film 15 is formed is held, for example, for about 60 minutes in a gas containing nitrogen.

  Next, gate electrode 27 is formed to fill the groove formed by gate insulating film 15. Gate electrode 27 is made of, for example, a material containing polysilicon containing an impurity. Next, interlayer insulating film 21 is formed to cover gate electrode 27 and to be in contact with contact region 18 and source region 14. Interlayer insulating film 21 includes, for example, a TEOS oxide film and PSG.

  Next, interlayer insulating film 21 is removed in a region where source electrode 16 is to be formed, whereby each of source region 14 and contact region 18 is exposed from interlayer insulating film 21. Next, source electrode 16 is formed, for example, by sputtering on first main surface 10a of silicon carbide substrate 10 to be in contact with both source region 14 and contact region 18. Source electrode 16 includes, for example, Ni and Ti. Preferably, source electrode 16 is made of a material containing TiAlSi. Next, silicon carbide substrate 10 on which source electrode 16 provided in contact with source region 14 and contact region 18 is formed on first main surface 10a of silicon carbide substrate 10 is, for example, 900 ° C. or higher An RTA (Rapid Thermal Anneal) of 1100 ° C. or less is performed for about 2 minutes. Thereby, at least a part of source electrode 16 reacts with silicon contained in the silicon carbide substrate to be silicided. Thus, the source electrode 16 in ohmic contact with the source region 14 is formed. Preferably, source electrode 16 is in ohmic contact with each of source region 14 and contact region 18.

  Referring to FIG. 1, source interconnection 19 is formed in contact with source electrode 16 and covering interlayer insulating film 21. Source interconnection 19 is preferably made of a material containing Al, for example, a material containing AlSiCu. Next, a protective film 24 is formed to cover the source wiring 19. The protective film 24 is made of, for example, a material including a nitride film and a polyimide. Next, drain electrode 20 made of, for example, NiSi is formed in contact with second main surface 10 b of silicon carbide substrate 10. The drain electrode 20 may be, for example, TiAlSi. The drain electrode 20 is preferably formed by sputtering, but may be formed by vapor deposition. After the drain electrode 20 is formed, the drain electrode 20 is heated, for example, by laser annealing. Thereby, at least a part of the drain electrode 20 is silicided, and the drain electrode 20 in ohmic junction with the silicon carbide single crystal substrate 11 is formed. As described above, the MOSFET 1 shown in FIG. 1 is manufactured.

  Next, functions and effects of MOSFET 1 as a silicon carbide semiconductor device according to the first embodiment and a method of manufacturing the same will be described.

  According to the method of manufacturing MOSFET 1 in accordance with the first embodiment, after buried region 17 is formed by performing ion implantation to first impurity region 12, first impurity region 12 and buried region 17 are formed. At the same time, base region 13 having an impurity concentration lower than that of buried region 17 is formed by epitaxial growth. Therefore, the ion implantation energy can be reduced as compared to the case where the embedded region 17 is formed by implanting ions from the surface of the base region 13 after the base region 13 is formed. As a result, channeling and multiple scattering of ions occur due to the high ion implantation energy, and it is possible to suppress the diffusion of ion-implanted impurities from obstructing the current flow. Further, since the pn junction formed of first impurity region 12 and buried region 17 is formed at a position deep away from first main surface 10a of silicon carbide substrate 10, the electric field in trench TR is effectively cut off can do. Furthermore, since the second impurity region 13 to be a channel is formed by epitaxial growth, a high quality channel can be realized.

  Further, according to the method of manufacturing MOSFET 1 in accordance with the first embodiment, in the step of forming trench TR, trench TR is formed such that side portion SW of trench TR is separated from buried region 17 by first impurity region 12. Be done. The distance between the side portion SW of the trench TR and the side surface of the embedded region 17 opposite to the side portion SW in the direction parallel to the first major surface 10a is 0.2 μm or more and 5 μm or less. When the distance D between the side portion SW of the trench TR and the side surface of the buried region 17 is smaller than 0.2 μm, the spread of the current from the channel is prevented and the on-resistance is increased. When the distance D between the side portion SW of trench TR and the side surface of buried region 17 is larger than 5 μm, buried region 17 reduces the effect of shielding the electric field at bottom portion BT of trench TR.

  Further, according to the method of manufacturing MOSFET 1 in accordance with the first embodiment, depth H1 of trench TR in the normal direction of first main surface 10a is 0.3 μm or more and 3 μm or less, and first main surface 10a Smaller than the width of the trench TR in a direction parallel to If the depth H1 of the trench TR is smaller than 0.3 μm, formation of a channel becomes difficult. When the depth H1 of the trench TR is larger than 3 μm, it becomes difficult to control the shape of the trench.

  Furthermore, according to the method of manufacturing MOSFET 1 in accordance with the first embodiment, first main surface 10a of silicon carbide substrate 10 is a surface turned off in the off direction from the {0001} plane. Side portion SW of trench TR includes a surface SW1 perpendicular to the off direction and having a plane orientation perpendicular to the normal direction of first main surface 10a. By making the plane having the normal to the off direction and the direction perpendicular to the side walls as the side walls of the main trench, it is possible to minimize the deviation of the plane orientation of the side walls. In addition, when the off direction is, for example, the <11-20> direction, it is possible to form the flatter silicon carbide epitaxial layer 5.

  Furthermore, according to the method of manufacturing MOSFET 1 in accordance with the first embodiment, the step of forming embedded region 17 is perpendicular to the off direction from the normal direction of first main surface 10a, and is the first main surface Ion implantation is performed in a direction inclined by 2 ° to 10 ° with respect to the direction parallel to 10 a. Channeling can be effectively suppressed by performing ion implantation in a direction perpendicular to the off direction and inclined by 2 ° or more and 10 ° or less with respect to the direction parallel to the first major surface 10a. Further, when the embedded region 17 is formed at the corner portion CR of the bottom portion BT of the trench TR in which deterioration of the withstand voltage easily occurs, occurrence of positional deviation of the embedded region 17 can be effectively suppressed.

  Further, according to the method of manufacturing MOSFET 1 in accordance with the first embodiment, in the step of forming trench TR, corner portion CR of bottom portion BT of trench TR is a buried region as viewed from the normal direction of first main surface 10a. Trench TR is formed to overlap 17. Thereby, it is possible to shield the electric field at the corner CR of the bottom BT of the trench TR in which the breakdown voltage tends to deteriorate.

  According to MOSFET 1 in accordance with the first embodiment, base region 13 and the buried region are buried at the position closest to base region 13 among the locations in buried region 17 having the impurity concentration four times the impurity concentration of base region 13. The distance along the normal direction of the first major surface 10a to the boundary with the region 17 is 0.3 μm or less. Thus, the electric field is sufficiently shielded in the embedded region 17 to reduce the capacitance of the source portion.

  Further, according to MOSFET 1 in accordance with the first embodiment, corner portion CR of bottom portion BT of trench TR is arranged to overlap with buried region 17 when viewed in the normal direction of first main surface 10a. Thereby, it is possible to shield the electric field at the corner CR of the bottom BT of the trench TR in which the breakdown voltage tends to deteriorate.

Second Embodiment
Next, the configuration of a MOSFET as a silicon carbide semiconductor device according to the second embodiment of the present invention will be described. The MOSFET according to the second embodiment is different from the MOSFET according to the first embodiment in that the buried region 17 is in contact with the bottom portion BT of the trench TR, and the other configuration is the same as the MOSFET according to the first embodiment. It is similar. Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

  Referring to FIG. 16, buried region 17 is provided to extend from bottom portion BT of trench TR toward second major surface 10b. Each of the side portion and the lower end portion of the buried region 17 is in contact with the first impurity region 12. Buried region 17 has p type and has a higher impurity concentration than base region 13. Buried region 17 is short-circuited (connected) to contact region 18 in a partial region in silicon carbide substrate 10. Gate insulating film 15 is in contact with both buried region 17 and first impurity region 12 at bottom portion BT of trench TR. The contact region 18 does not penetrate through the base region 13, and the lower end portion of the contact region 18 is located closer to the first major surface 10 a than the lower end portion of the base region 13.

  Preferably, width W1 of embedded region 17 in the direction parallel to first main surface 10a is smaller than width W2 of bottom portion BT of trench TR. A value obtained by subtracting the width W1 of the buried region 17 from the width W2 of the bottom portion BT of the trench TR is, for example, 0.1 μm or more and 0.4 μm or less. When viewed in the normal direction of the first major surface 10a, the buried region 17 is preferably formed so as not to protrude from the bottom portion BT of the trench. By making the width W2 of the bottom portion BT of the trench TR larger than the width W1 of the buried region 17 by 0.1 μm or more, the current flowing from the channel is spread without being blocked by the depletion layer from the side of the buried region 17 The on-resistance can be reduced. By making the width W2 of the bottom portion BT of the trench TR smaller than the width W1 of the buried region 17 by 0.4 μm or less, concentration of the electric field at the corner where the side SW of the trench TR and the bottom portion BT are connected is suppressed can do.

  16, in a cross sectional view (field of view along a direction parallel to first main surface 10a of silicon carbide substrate 10, ie, the field of view of FIG. 16), trench TR has the same symmetry axis as embedded region 17. It is preferable that they have line symmetry (line symmetry) with respect to the symmetry axis. The symmetrical shape of trench TR can suppress local concentration of the electric field.

  Next, a method of manufacturing MOSFET 1 as a silicon carbide semiconductor device according to the second embodiment will be described. The method of manufacturing the MOSFET according to the second embodiment is different from the method of manufacturing the MOSFET according to the first embodiment in that the trench is formed such that the embedded region is exposed at the bottom of the trench in the step of forming the trench. The other configuration is the same as the method of manufacturing the MOSFET according to the first embodiment. Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

Referring to FIGS. 7 and 8, the n-type epitaxial layer forming step (S10: FIG. 6) is performed by the same method as the method described in the first embodiment. Next, a p-type buried region forming step (S20: FIG. 6) is performed. Specifically, referring to FIG. 17, ion implantation mask 31 is formed on first impurity region 12 of silicon carbide epitaxial layer 5. The ion implantation mask is made of a material including a TEOS oxide film, and the thickness of the ion implantation mask 31 is, for example, 1.6 μm. Next, RF etching is performed on the ion implantation mask 31 using CHF ₃ and O ₂ . Thereby, a through film of, for example, about 80 nm is left on a portion where ion implantation is to be performed. Next, ion implantation is performed on first impurity region 12 of silicon carbide epitaxial layer 5 using ion implantation mask 31 having a through film. For example, Al (aluminum) ions are implanted in the direction of the arrow into silicon carbide epitaxial layer 5 through the through film, to thereby have p type conductivity and a higher impurity concentration than base region 13. Region 17 is formed (see FIG. 17). In a cross-sectional view, the buried region 17 has portions of the plurality of buried regions 17 spaced apart. That is, in a cross sectional view, embedded region 17 is periodically arranged in a direction parallel to first main surface 10a of silicon carbide substrate 10 and in the direction a21 (see FIG. 3). .

  Conditions for ion implantation such as acceleration voltage and dose so that the impurity concentration of the embedded region 17 on the second main surface 10b side is higher than the impurity concentration of the embedded region 17 on the first main surface 10a side Is adjusted. Preferably, in the step of forming buried region 17, the normal direction of first main surface 10a is perpendicular to off direction a1 and at least 2 ° with the direction parallel to first main surface 10a. For example, aluminum ions are implanted in a direction inclined by 10 ° or less. The direction perpendicular to the off direction a1 and parallel to the first major surface 10a is, for example, the <1-100> direction. As described above, by implanting ions into the first impurity region 12, buried regions 17 having p-type different from n-type and periodically arranged are formed.

  Next, the p-type epitaxial layer formation step (S40: FIG. 6) and the n-type source region formation step (S50: FIG. 6) are performed by the same method as the method described in the first embodiment.

Next, a p-type contact region formation step (S60: FIG. 6) is performed. Referring to FIG. 18, ion implantation mask 34 is formed on base region 13 and source region 14. The ion implantation mask is made of, for example, a material including a TEOS oxide film, and the thickness of the ion implantation mask 31 is, for example, 1.6 μm. Next, RF etching is performed on the ion implantation mask 34 using CHF ₃ and O ₂ . Thereby, a through film of, for example, about 80 nm is left on the region where the contact region 18 is to be formed. Next, ion implantation is performed on base region 13 of silicon carbide epitaxial layer 5 using ion implantation mask 34 having a through film. For example, base region 13 and aluminum ion to a depth closer to second main surface 10b than the lower end portion of source region 14 and to the first main surface 10a side than lower end portion 13a of base region 13 Injected to each of the source regions 14. Thereby, a contact region 18 having a p-type conductivity and being sandwiched between each of source region 14 and a part of base region 13 is formed (see FIG. 18).

Next, a trench formation step (S70: FIG. 6) is performed. Referring to FIG. 19, an etching mask 35 is formed on source region 14 and contact region 18. The etching mask 35 is made of, for example, a material including a TEOS oxide film, and the thickness of the etching mask 35 is, for example, 1.6 μm. Next, RF etching is performed on the etching mask 35 on the region where the trench TR is to be formed using CHF ₃ and O ₂ to form an opening in the etching mask 35. Next, etching is performed on silicon carbide substrate 10 using etching mask 35 in which an opening is formed on the region where trench TR is to be formed. For example, ECR plasma etching is performed on silicon carbide substrate 10 using SF ₆ and O ₂ . Thereby, trench TR having side portion SW connected to first main surface 10a of silicon carbide substrate 10 and bottom portion BT connected to side portion SW is formed. Source region 14, base region 13 and first impurity region 12 are exposed at side portion SW of trench TR, and first impurity region 12 and buried region 17 are exposed at bottom portion BT of trench TR. In other words, trench TR is formed such that buried region 17 is exposed at bottom portion BT of trench TR.

  Referring to FIGS. 3 and 19, the period of trench TR along the direction a21 is the same as the period of buried region 17 along the direction a2. Specifically, one corresponding buried region 17 is provided in contact with each bottom portion BT of the plurality of trenches TR. As described above, it has side portion SW extending through base region 13 and source region 14 to first impurity region 12 and bottom portion BT connected to side portion SW, and has the same cycle as embedded region 17. Trenches TR are formed in the Preferably, depth H of trench TR in a direction normal to first main surface 10a of silicon carbide substrate 10 is 0.3 μm or more and 3 μm or less, and parallel to first main surface 10a of silicon carbide substrate 10 Smaller than the width of the trench TR in one direction.

  Preferably, trench TR is formed such that the width of bottom portion BT of trench TR in the direction parallel to first main surface 10 a of silicon carbide substrate 10 is larger than the width of buried region 17. Referring to FIG. 16, a value obtained by subtracting width W1 of buried region 17 from width W2 of bottom portion BT of trench TR is, for example, 0.1 μm or more and 0.4 μm or less. Preferably, trench TR is formed such that embedded region 17 does not protrude from bottom portion BT of the trench when viewed in the normal direction of first main surface 10a.

  Next, the gate oxide film forming step (S80: FIG. 6), the gate electrode forming step (S90: FIG. 6) and the like are performed in the same manner as the method described in the first embodiment. The MOSFET shown is manufactured.

  Next, the function and effect of MOSFET 1 as a silicon carbide semiconductor device according to the second embodiment will be described.

  According to the method of manufacturing MOSFET 1 in accordance with the second embodiment, in the step of forming trench TR, trench TR is formed such that embedded region 17 is exposed at bottom portion BT of trench TR. As a result, the bottom portion BT of the trench TR is effectively shielded from the high electric field, whereby the breakdown voltage can be improved.

  Further, according to the method of manufacturing MOSFET 1 in accordance with the second embodiment, the width of bottom portion BT of trench TR in the direction parallel to first main surface 10 a is larger than the width of buried region 17. Thereby, it is possible to suppress that the flow of current is interrupted by the depletion layer spreading from the side surface of the embedded region 17. As a result, the on-resistance can be reduced.

Third Embodiment
Next, the configuration of a MOSFET as a silicon carbide semiconductor device according to the third embodiment of the present invention will be described. The MOSFET according to the third embodiment differs from the MOSFET according to the first embodiment in that the first impurity region 12 includes a first region 12a, a second region 12b, and a third region 12c. The other configuration is the same as that of the MOSFET according to the first embodiment. Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

  Referring to FIG. 20, the first impurity region 12 is provided on the third region 12c provided on the buffer layer 22, the second region 12b provided on the third region 12c, and the second region 12b. And the first region 12a. The first region 12 a is in contact with the base region 13. The second region 12 b is in contact with the first region 12 a and is located on the opposite side of the base region 13 as viewed from the first region 12 a. The third region 12c is in contact with the second region 12b, and is located on the opposite side of the first region 12a as viewed from the second region 12b.

The first region 12a, the second region 12b, and the third region 12c contain n-type impurities such as nitrogen, for example, and have n-type. The second region 12 b has a higher impurity concentration than the first region 12 a. The third region 12c has a lower impurity concentration than the second region 12b. Preferably, the concentration of impurities such as nitrogen contained in the first region 12a is 1.5 × 10 ¹⁶ cm ⁻³ or less. The concentration of an impurity such as nitrogen contained in the first region 12a may be higher than the concentration of an impurity such as nitrogen contained in the third region 12c. Preferably, the concentration of impurities such as nitrogen contained in the second region 12 b is 2 × 10 ¹⁶ cm ⁻³ or more. The concentration of an impurity such as nitrogen contained in the second region 12 b may be 2 × 10 ¹⁷ cm ⁻³ or less. When the concentration of the impurity such as nitrogen contained in the second region 12 b is 2 × 10 ¹⁷ cm ⁻³ or less, the electric field concentration in the embedded region 17 can suppress the destruction of the embedded region 17. .

  Preferably, thickness H 2 of first region 12 a along the normal direction of first main surface 10 a is 0.1 μm or more and 0.5 μm or less, and more preferably 0.1 μm or more and 0.4 μm or less. By setting the thickness H2 of the first region 12a to 0.1 μm or more, the breakdown voltage can be improved by effectively suppressing the electric field concentration in the trench TR. By setting the thickness H2 of the first region 12a to 0.5 μm or less, an increase in on-resistance can be suppressed. Preferably, the thickness of the second region 12b along the normal direction of the first major surface 10a is 0.3 μm or more and 2 μm or less. By setting the thickness H3 of the second region 12b to 0.3 μm or more, the carriers can be effectively collected in the trench TR, whereby the on-resistance can be reduced. By setting the thickness H3 of the second region 12b to 2 μm or less, an increase in on-resistance can be suppressed.

  Preferably, the end of the embedded region 17 on the second major surface 10 b side is in contact with the second region 12 b. The side portion of the embedded region 17 is in contact with each of the first region 12a and the second region 12b. The thickness of the embedded region 17 along the normal direction of the first major surface 10a is larger than the thickness of the first region 12a. In a cross sectional view, the first region 12 a and a part of the second region 12 b are formed so as to be sandwiched between the two embedded regions 17. The end of the embedded region 17 on the second major surface 10 b side may be located closer to the second major surface 10 b than the boundary between the second region 12 b and the third region 12 c. That is, the end of the embedded region 17 on the second main surface 10b side may be in contact with the third region 12c.

  In first main surface 10a of silicon carbide substrate 10, a trench TR is formed having a side portion SW connected to first main surface 10a and a bottom portion BT connected to side portion SW. The side portion SW of the trench TR penetrates each of the source region 14 and the base region 13 to reach the first region 12a, and the bottom portion BT of the trench TR is located in the first region 12a. That is, the first region 12a, the base region 13 and the source region 14 are in contact with the side portion SW of the trench, and the first region 12a is in contact with the bottom portion BT of the trench TR.

  Gate insulating film 15 is made of, for example, silicon dioxide, and is provided in contact with side portion SW of trench TR and bottom portion BT. Gate insulating film 15 is in contact with first region 12a, base region 13 and source region 14 at side portion SW of trench TR, and is in contact with first region 12a at bottom portion BT of trench TR. Preferably, bottom portion BT of trench TR is provided separately from each of second region 12 b and third region 12 c.

  Next, a method of manufacturing MOSFET 1 as a silicon carbide semiconductor device according to the third embodiment will be described. The method of manufacturing the MOSFET according to the third embodiment is different from the method of manufacturing the MOSFET according to the first embodiment in that the steps of forming the first region and the steps of forming the second region are included. The other configuration is the same as the method of manufacturing the MOSFET according to the first embodiment. Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

  7 to 10, the n-type epitaxial layer forming step (S10: FIG. 6) and the p-type buried region forming step (S20: FIG. 6) are performed in the same manner as the method described in the first embodiment. And so on.

  Next, an n-type second region forming step is performed. Specifically, the portion of the ion implantation mask 31 on which the second region 12b is to be formed is removed, and the through film 32 having a thickness of, for example, 80 nm is left. Next, for example, nitrogen ions are implanted into both the embedded region 17 and the third region 12c in the direction of the arrow from above the through film 32. Thereby, the second region 12 b is formed in a region sandwiched between the two embedded regions 17 in a cross sectional view.

  Next, an n-type first region forming step is performed. Specifically, for example, nitrogen ions are implanted into both the embedded region 17 and the second region 12 b in the direction of the arrow from above the through film 32. Thus, the first region 12a is formed in the region sandwiched between the through film 32 and the second region 12b (see FIG. 21). Preferably, the ion implantation energy (acceleration voltage) in the step of forming the second region 12 b is larger than the ion implantation energy (acceleration voltage) in the step of forming the first region 12 a. In other words, after nitrogen ions, for example, are implanted into third region 12c using the first acceleration voltage, a second acceleration voltage smaller than the first acceleration voltage is used for the second region 12b. For example, nitrogen ions are implanted. Next, the through film 32 is removed from the surfaces of the buried region 17 and the first region 12a.

  Preferably, in the step of forming the first region 12a and the second region 12b, from the normal direction of the first major surface 10a, in the direction perpendicular to the off direction a1 and parallel to the first major surface 10a For example, nitrogen ions are implanted in a direction inclined by 2 ° or more and 10 ° or less. The direction perpendicular to the off direction a1 and parallel to the first major surface 10a is, for example, the <1-100> direction.

As described above, in the region sandwiched by the embedded regions 17, the first region 12a and the second region 12b having a higher impurity concentration than the first region 12a are formed. Preferably, the impurity concentration of the first region 12a is 1.5 × 10 ¹⁶ cm ⁻³ or less. Preferably, the impurity concentration of the second region 12 b is 2 × 10 ¹⁶ cm ⁻³ or more. Preferably, the thickness of the first region 12a along the normal direction of the first major surface 10a is 0.1 μm or more and 0.5 μm or less. Preferably, the thickness of the second region 12b along the normal direction of the first major surface 10a is 0.3 μm or more and 2 μm or less. In the above description, the n-type second region forming step and the n-type first region forming step are performed after the p-type embedded region forming step is performed, but the n-type second region forming step is described. After the n-type first region formation step is performed, the p-type embedded region formation step may be performed.

  Next, p-type epitaxial layer formation step (S40: FIG. 6), n-type source region formation step (S50: FIG. 6), p-type contact region formation step (S50: FIG. 6) by the same method as described in the first embodiment. S60: FIG. 6), trench formation step (S70: FIG. 6), gate oxide film formation step (S80: FIG. 6), gate electrode formation step (S90: FIG. 6), etc. The MOSFET 1 is manufactured.

  Next, the function and effect of MOSFET 1 as the silicon carbide semiconductor device according to the third embodiment will be described.

  According to MOSFET 1 in accordance with the third embodiment, first impurity region 12 is in contact with first region 12a in contact with second impurity region 13, and in contact with first region 12a, and second impurity region 13 viewed from first region 12a. And the second region 12b having an impurity concentration higher than that of the first region 12a, and in contact with the second region 12b, and located on the opposite side of the first region 12a as viewed from the second region 12b, The third region 12 c has an impurity concentration lower than that of the second region 12 b. As a result, at the time of off, the depletion layer spreads in the first region 12a having a low impurity concentration, whereby the electric field in the trench TR is relaxed, whereby a high breakdown voltage can be maintained. At the on time, the voltage applied to gate electrode 27 allows carriers to be collected around trench TR from second region 12 b having a high impurity concentration. As a result, since high conductivity can be realized, the on-resistance can be reduced. That is, the on-resistance can be reduced and the withstand voltage can be improved.

Embodiment 4
Next, the configuration of an IGBT (Insulated Gate Bipolar Transistor) as a silicon carbide semiconductor device according to the fourth embodiment of the present invention will be described. In the IGBT according to the fourth embodiment, the thickness of the first impurity region 12 is as thick as about 100 μm, and the impurity concentration of the first impurity region 12 is about 5 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁵ cm ⁻³ or less. Is different from the MOSFET according to the first embodiment in that the p-type epitaxial layer is in contact with the back surface electrode and the carrier injection region is in contact with the p-type epitaxial layer. It is almost the same as the related MOSFET. Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

Referring to FIG. 22, IGBT 1 according to the fourth embodiment includes silicon carbide substrate 10, gate electrode 27, gate insulating film 15, interlayer insulating film 21, emitter electrode 16, emitter interconnection 19, and a collector. The electrode 20 and the protective film 24 are mainly included. Silicon carbide substrate 10 mainly includes first impurity region 12, base region 13, emitter region 14, contact region 18, p-type epitaxial layer 29, and carrier injection region 28. The thickness of first impurity region 12 is, for example, about 100 μm. First impurity region 12 includes an n-type impurity such as nitrogen, for example, and has n-type. The concentration of an impurity such as nitrogen contained in first impurity region 12 is, for example, about 5 × 10 ¹⁴ cm ⁻³ or more and 1 × 10 ¹⁵ cm ⁻³ or less.

  The p-type epitaxial layer 29 (second conductivity type epitaxial layer 29) contains p-type impurities such as aluminum, for example, and has p-type. P-type epitaxial layer 29 constitutes second main surface 10 b of silicon carbide substrate 10 and is provided in contact with first impurity region 12. P-type epitaxial layer 29 is in contact with collector electrode 20 at second main surface 10 b of silicon carbide substrate 10. Collector electrode 20 includes, for example, Ti and Al. Carrier injection region 28 includes p-type impurities such as aluminum, for example, and has p-type. Carrier injection region 28 is in contact with p type epitaxial layer 29 and first impurity region 12 and has a higher impurity concentration than p type epitaxial layer 29. In cross section, the carrier injection region 28 has portions of the carrier injection region 28 periodically provided. In the cross sectional view, carrier injection regions 28 are periodically provided at intervals along the lateral direction (see FIG. 3) of trench TR. Preferably, the concentration of the p-type impurity such as aluminum contained in carrier injection region 28 is the same as the concentration of the p-type impurity contained in buried region 17 or higher than the concentration of the impurity contained in buried region 17.

  Next, a method of manufacturing IGBT 1 as a silicon carbide semiconductor device according to the fourth embodiment will be described. The method of manufacturing the IGBT according to the fourth embodiment is different from the method of manufacturing the MOSFET according to the first embodiment in that the carrier injection region 28 and the p-type epitaxial layer 29 are formed, and the other configuration is the embodiment. The method is substantially similar to the method of manufacturing the MOSFET according to 1. Therefore, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

  By removing silicon carbide single crystal substrate 11 from silicon carbide substrate 10, first impurity region 12 is exposed on the back surface side. Next, p-type impurities, such as aluminum, are ion-implanted from the back surface side at intervals to the exposed first impurity region 12. Preferably, the concentration of the p-type impurity contained in carrier injection region 28 is the same as the concentration of the p-type impurity contained in buried region 17 or higher than the concentration of the p-type impurity contained in buried region 17. A p-type impurity is ion implanted into the first impurity region 12. As described above, by performing ion implantation from the side of second main surface 10b of silicon carbide substrate 10 to first impurity region 12, carrier injection region 28 having p-type and periodically arranged can be formed. It is formed.

  Next, p-type epitaxial layer 29 is formed by epitaxial growth so as to be in contact with both carrier injection region 28 and first impurity region 12. P-type epitaxial layer 29 contains a p-type impurity such as aluminum, for example. After the p-type epitaxial layer 29 is formed, p-type impurities such as aluminum may be further ion-implanted into the p-type epitaxial layer 29. Next, for example, after the p-type epitaxial layer 29 is bonded to a polycrystalline silicon carbide substrate (not shown) and a surface process is performed, the polycrystalline silicon carbide substrate is removed from the p-type epitaxial layer 29.

  Next, collector electrode 20 is formed in the direction opposite to carrier injection region 28 as viewed from p type epitaxial layer 29. Collector electrode 20 includes, for example, Ti and Al. Next, laser annealing is performed on the collector electrode 20, whereby the collector electrode 20 and the p-type epitaxial layer 29 form an ohmic junction. As described above, the IGBT shown in FIG. 22 is manufactured.

  Next, the function and effect of the IGBT 1 as a silicon carbide semiconductor device according to the fourth embodiment will be described.

  According to the method of manufacturing silicon carbide semiconductor device 1 in accordance with the fourth embodiment, the step of forming silicon carbide substrate 10 is performed by performing ion implantation to first impurity region 12 from the second main surface 10b side. And the step of forming a periodically arranged carrier injection region 28 of the second conductivity type. As a result, by promoting the injection of carriers from the carrier injection region 28, the on-resistance can be reduced.

  According to silicon carbide semiconductor device 1 in accordance with the fourth embodiment, silicon carbide substrate 10 has the p-type, and forms second main surface 10 b and is provided in contact with first impurity region 12. Carrier injection which has a p-type epitaxial layer 29, is in contact with the p-type epitaxial layer 29 and the first impurity region 12, has an impurity concentration higher than that of the p-type epitaxial layer 29, and is periodically provided. And region 28 is further included. As a result, by promoting the injection of carriers from the carrier injection region 28, the on-resistance can be reduced.

  In the above embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type is p-type and the second conductivity type is n-type. It may be Although side portion SW of trench TR is substantially perpendicular to first main surface 10a of silicon carbide substrate 10, side portion SW of trench TR is inclined relative to first main surface 10a. It may be done.

  It should be understood that the embodiments disclosed herein are illustrative in all respects and not restrictive. The scope of the present invention is shown not by the above description but by the scope of claims, and is intended to include meanings equivalent to the scope of claims and all modifications within the scope.

1 Silicon carbide semiconductor device (MOSFET, IGBT)
5 silicon carbide epitaxial layer 10 silicon carbide substrate 10a first main surface 10b second main surface 11 silicon carbide single crystal substrate 12 first impurity region 12a first region 12b second region 12c third region 13 second impurity region Base area)
13a end 14 third impurity region (source region, emitter region)
15 gate insulating film 16 source electrode (emitter electrode)
17 Buried Region 17a First Buried Region 17b Second Buried Region 18 Contact Region 19 Source Wiring (Emitter Wiring)
20 drain electrode (collector electrode)
21 interlayer insulating film 22 buffer layer 24 protective film 27 gate electrode 28 carrier injection region 29 second conductivity type epitaxial layer (p type epitaxial layer)
31, 33, 34 Ion implantation mask 32 Through film 35 Etching mask 40 Semiconductor chip 41 Guard ring BT Bottom portion CH channel region CR Corner portion SW Side portion SW1 First side portion (surface)
SW2 second side TR trench a1 off direction a11 in-plane off direction a21 direction d1, d2 impurity concentration

Claims (3)

A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface,
The silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region in contact with the first impurity region, and a second conductivity type different from the first conductivity type, and the first impurity region. A third impurity region having a conductivity type, separated from the first impurity region by the second impurity region, and having the second conductivity type, and having an impurity concentration higher than that of the second impurity region; And a buried region extending from a part of the end of the second impurity region toward the second main surface toward the second main surface,
A trench having a side portion connected to the first main surface and a bottom portion connected to the side portion is formed on the first main surface of the silicon carbide substrate;
A gate insulating film in contact with the first impurity region, the second impurity region, and the third impurity region on the side portion of the trench, and in contact with the first impurity region at the bottom of the trench; Equipped
The boundary between the second impurity region and the buried region from the position closest to the second impurity region among the positions in the buried region having an impurity concentration four times the impurity concentration of the second impurity region The distance along the normal direction of the first main surface to the portion is 0.3 μm or less,
When viewed in the normal direction of the first main surface, the buried region overlaps the first buried region surrounding the entire side of the trench and the corner of the bottom of the trench. The silicon carbide semiconductor device which has the 2nd embedded area part arrange | positioned. The first impurity region is a first region in contact with the second impurity region, and is in contact with the first region, and is located opposite to the second impurity region as viewed from the first region, and in the first region. A second region having a higher impurity concentration than the first region, and a second region having a lower impurity concentration than the second region and in contact with the second region and opposite to the first region with respect to the second region The silicon carbide semiconductor device according to claim 1 , having three regions. The silicon carbide substrate has the second conductivity type, forms a second main surface, and a second conductivity type epitaxial layer provided in contact with the first impurity region, and the second conductivity type A carrier injection region periodically provided in contact with the second conductivity type epitaxial layer and the first impurity region, having a higher impurity concentration than the second conductivity type epitaxial layer, and The silicon carbide semiconductor device according to claim 1 or claim 2 comprising.

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