JP2020035807A - Method of manufacturing silicon carbide semiconductor device - Google Patents

Abstract

To provide a method of manufacturing a silicon carbide semiconductor device, with which it is possible to suppress occurrence of alignment deviation.SOLUTION: A first trench is formed on a first principal surface by performing anisotropic etching on a third impurity region and a second impurity region using a mask. A fourth impurity region, which is in contact with a first impurity region and has a second conductivity type, is formed by performing ion implantation on the first trench using a mask. A second trench is formed by extending the first trench through performing thermal etching in an atmosphere containing a halogen gas on the third impurity region, the second impurity region, the first region, and the fourth impurity region. The second trench has a side surface continuing to the first principal surface, and a bottom located at the fourth impurity region. An angle formed by the first principal surface and the side surface is larger than 90°.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a method for manufacturing a silicon carbide semiconductor device.

  JP-A-2015-072999 (Patent Document 1) describes a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a trench gate structure. In the MOSFET, a p-type bottom layer is formed so as to cover the bottom of the trench, and an n-type current distribution layer is formed between the p-type base region and the n-type drift layer.

JP-A-2005-072999

  An object of the present disclosure is to provide a method for manufacturing a silicon carbide semiconductor device that can suppress occurrence of misalignment.

  A method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes the following steps. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface is prepared. The silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, and a first impurity region. A third impurity region is provided on the second impurity region so as to be separated from the first impurity region and is in contact with the first main surface and has the first conductivity type. The first impurity region has a first region in contact with the second impurity region and a second region located on the opposite side of the first region from the second impurity region. Further, a mask is formed on the first main surface. By performing anisotropic etching on the third impurity region and the second impurity region using a mask, a first trench is formed on the first main surface. By performing ion implantation on the first trench using the mask, a fourth impurity region which is in contact with the first impurity region and has the second conductivity type is formed. By performing thermal etching on the third impurity region, the second impurity region, the first region, and the fourth impurity region in an atmosphere containing a halogen gas, the first trench is expanded to form a second trench. It is formed. The second trench has a side surface connected to the first main surface and a bottom located in the fourth impurity region. The angle formed by the first main surface and the side surface is greater than 90 °.

  According to the present disclosure, it is possible to provide a method of manufacturing a silicon carbide semiconductor device capable of suppressing occurrence of misalignment.

FIG. 2 is a schematic cross-sectional view showing a structure of the silicon carbide semiconductor device according to the embodiment. FIG. 3 is a schematic plan view showing a structure of a trench of the silicon carbide semiconductor device according to the present embodiment. FIG. 5 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the present embodiment. FIG. 5 is a schematic cross-sectional view showing a first step of the method for manufacturing the silicon carbide semiconductor device according to the present embodiment. FIG. 10 is a schematic sectional view showing a second step of the method for manufacturing the silicon carbide semiconductor device according to the present embodiment. FIG. 10 is a schematic sectional view showing a third step of the method for manufacturing a silicon carbide semiconductor device according to the present embodiment. FIG. 10 is a schematic sectional view showing a fourth step of the method for manufacturing the silicon carbide semiconductor device according to the present embodiment. FIG. 13 is a schematic sectional view showing a fifth step of the method for manufacturing a silicon carbide semiconductor device according to the present embodiment. FIG. 15 is a schematic sectional view showing a sixth step of the method for manufacturing a silicon carbide semiconductor device according to the present embodiment. FIG. 15 is a schematic sectional view showing a seventh step of the method for manufacturing a silicon carbide semiconductor device according to the present embodiment. FIG. 15 is a schematic sectional view showing an eighth step of the method for manufacturing a silicon carbide semiconductor device according to the present embodiment. FIG. 15 is a schematic sectional view showing a ninth step of the method for manufacturing a silicon carbide semiconductor device according to the present embodiment. FIG. 11 is a schematic cross-sectional view showing a first step of a method for manufacturing a silicon carbide semiconductor device according to a modification of the present embodiment. FIG. 15 is a schematic cross-sectional view showing a second step of the method for manufacturing the silicon carbide semiconductor device according to the modification of the present embodiment. 6 is simulation data showing the relationship between the characteristic on-resistance and the distance from the trench bottom and the relationship between the breakdown voltage and the distance from the trench bottom.

[Overview of Embodiment of the Present Disclosure]
First, an outline of an embodiment of the present disclosure will be described. In the crystallographic description of this specification, [] indicates the individual orientation, <> indicates the collective orientation, () indicates the individual plane, and indicates the collective plane with ｛｝. Negative crystallographic indices are usually represented by a "-" (bar) over the number, but in this specification, a negative sign in front of the number indicates that the crystallographic index is negative. Express the negative exponent above.

  (1) The method for manufacturing silicon carbide semiconductor device 200 according to the present disclosure includes the following steps. Silicon carbide substrate 100 having first main surface 1 and second main surface 2 opposite to first main surface 1 is prepared. Silicon carbide substrate 100 includes a first impurity region 10 having a first conductivity type, a second impurity region 20 provided on first impurity region 10 and having a second conductivity type different from the first conductivity type, A third impurity region provided on second impurity region and separated from first impurity region and in contact with first main surface and having a first conductivity type. The first impurity region 10 has a first region 11 in contact with the second impurity region 20 and a second region 12 located on the opposite side of the first region 11 from the second impurity region 20. Further, a mask 64 is formed on first main surface 1. The first trench 70 is formed in the first main surface 1 by performing anisotropic etching on the third impurity region 30 and the second impurity region 20 using the mask 64. By performing ion implantation into the first trench 70 using the mask 64, the fourth impurity region 40 that is in contact with the first impurity region 10 and has the second conductivity type is formed. The first trench 70 is expanded by performing thermal etching on the third impurity region 30, the second impurity region 20, the first region 11, and the fourth impurity region 40 in an atmosphere containing a halogen gas. Thus, a second trench 5 is formed. Second trench 5 has side surface 3 continuing to first main surface 1 and bottom 4 located in fourth impurity region 40. Angle θ between first main surface 1 and side surface 3 is greater than 90 °.

  (2) In the method for manufacturing silicon carbide semiconductor device 200 according to (1), ion implantation is performed on first trench 70 using mask 64 to be in contact with fourth impurity region 40 and to have a first conductivity type. A third region 13 having a mold and having a higher impurity concentration than the first region 11 may be formed. The third region 13 may be in contact with the side surface 3.

  (3) In the method for manufacturing silicon carbide semiconductor device 200 according to the above (1) or (2), first main surface 1 is inclined by 8 ° or less with respect to the (000-1) plane or the (000-1) plane. Surface may be used.

  (4) In the method of manufacturing silicon carbide semiconductor device 200 according to any one of (1) to (3), the thickness of second impurity region 20 may be 0.3 μm or more and 0.7 μm or less.

(5) In the method for manufacturing silicon carbide semiconductor device 200 according to any one of (1) to (4), the step of forming second trench 5 may be performed using mask 64.
[Details of Embodiment of the Present Disclosure]
Hereinafter, details of the embodiment of the present disclosure will be described. In the following description, the same or corresponding elements have the same reference characters allotted, and the same description will not be repeated.

  A configuration of a MOSFET as silicon carbide semiconductor device 200 according to the present embodiment will be described.

  As shown in FIG. 1, silicon carbide semiconductor device 200 according to the present embodiment includes silicon carbide substrate 100, gate electrode 7, gate insulating film 6, interlayer insulating film 23, source electrode 8, and source wiring 21, a drain electrode 9, and a protective film 22. Silicon carbide substrate 100 has a first main surface 1 and a second main surface 2 opposite to first main surface 1. Silicon carbide substrate 100 includes a silicon carbide single crystal substrate 15 and a silicon carbide epitaxial layer 16 provided on silicon carbide single crystal substrate 15. Silicon carbide single crystal substrate 15 forms second main surface 2 of silicon carbide substrate 100. Silicon carbide epitaxial layer 16 forms first main surface 1 of silicon carbide substrate 100.

  Silicon carbide single crystal substrate 15 is made of, for example, hexagonal silicon carbide of polytype 4H. The maximum diameter of first main surface 1 of silicon carbide substrate 100 is, for example, 150 mm, and preferably 150 mm or more. The first main surface 1 may be, for example, a (000-1) plane or a plane turned off by 8 ° or less with respect to the (000-1) plane. Silicon carbide single crystal substrate 15 has a thickness of, for example, 400 μm. Silicon carbide single crystal substrate 15 has a resistivity of, for example, 0.017 Ωcm.

  Silicon carbide epitaxial layer 16 includes first impurity region 10, base region 20 (second impurity region 20), source region 30 (third impurity region 30), contact region 42, and fourth impurity region 40. Mainly have. The first impurity region 10 is an n-type (first conductivity type) region including an n-type impurity (donor) for imparting an n-type such as nitrogen.

The first impurity region 10 mainly has a first region 11, a second region 12, and a third region 13. The first region 11 is a current spreading layer. The first region 11 is in contact with the second impurity region 20. The first region 11 has a first impurity concentration. The concentration of the n-type impurity (first impurity concentration) included in first region 11 is, for example, not less than 3 × 10 ¹⁶ cm ^{−3 and not} more than 3 × 10 ¹⁷ cm ⁻³ . The thickness of the first region 11 is, for example, not less than 0.2 μm and not more than 0.5 μm.

The second region 12 is a drift layer. The second region 12 is provided between the first region 11 and the second main surface 2. The second region 12 has a second impurity concentration lower than the first impurity concentration. The concentration of the n-type impurity (second impurity concentration) included in second region 12 is, for example, 8 × 10 ¹⁵ cm ⁻³ . The thickness of the second region 12 may be larger than the thickness of the first region 11.

The third region 13 is a local current spreading region. The third area 13 is continuous with the first area 11. The thickness of the third region 13 may be smaller than the thickness of the first region 11. The third region 13 has a third impurity concentration higher than the first impurity concentration. The concentration of the n-type impurity (third impurity concentration) included in third region 13 is, for example, not less than 2 × 10 ¹⁶ cm ^{−3 and not} more than 5 × 10 ¹⁷ cm ⁻³ . The concentration of the n-type impurity (second impurity concentration) included in second region 12 is lower than the concentration of the n-type impurity included in the silicon carbide single crystal substrate. If the concentration of the n-type impurity contained in the first region 11 is too high, punch-through (reach-through) tends to occur. By increasing the concentration of the n-type impurity contained in the third region 13 while keeping the concentration of the n-type impurity contained in the first region 11 low, the spread of current near the channel exit is ensured while suppressing punch-through. be able to. Therefore, on-resistance of silicon carbide semiconductor device 200 can be reduced.

Base region 20 is in contact with first impurity region 10. Base region 20 is provided on first impurity region 10. Base region 20 has a p-type (second conductivity type) different from the n-type. Base region 20 includes a p-type impurity (acceptor) for imparting a p-type such as Al (aluminum) or B (boron). The concentration of the p-type impurity contained in base region 20 is, for example, not less than 1 × 10 ¹⁷ cm ^{−3 and not} more than 2 × 10 ¹⁸ cm ⁻³ . The thickness of base region 20 is, for example, not less than 0.3 μm and not more than 0.7 μm.

Source region 30 is provided on base region 20 so as to be separated from first impurity region 10 by base region 20. The source region 30 contains an n-type impurity for imparting an n-type such as phosphorus and has an n-type. The concentration of the n-type impurity contained in the source region 30 is higher than the concentration of the n-type impurity contained in the second region 12. The concentration of an n-type impurity such as phosphorus contained in the source region 30 is, for example, not less than 2 × 10 ¹⁸ cm ^{−3 and not} more than 1 × 10 ¹⁹ cm ⁻³ . Source region 30 has a thickness of, for example, 0.1 μm or more and 0.2 μm or less.

Contact region 42 is a p-type region containing a p-type impurity such as aluminum or boron. Contact region 42 is in contact with each of source region 30 and base region 20. The concentration of the p-type impurity contained in contact region 42 is higher than the concentration of the p-type impurity contained in base region 20. The concentration of a p-type impurity such as aluminum contained in contact region 42 is, for example, not less than 2 × 10 ¹⁸ cm ^{−3 and not} more than 1 × 10 ¹⁹ cm ⁻³ . Contact region 42 has a thickness of, for example, 0.1 μm or more and 1.3 μm or less.

  On first main surface 1 of silicon carbide substrate 100, trench 5 (gate trench) is provided. The trench 5 has a side surface 3 and a bottom 4. The bottom 4 is continuous with the side surface 3. The side surface 3 extends in a direction inclined with respect to a normal line of the first main surface 1. The depth of trench 5 is, for example, 0.5 μm or more and 1.0 μm or less. Angle θ between first main surface 1 and side surface 3 is greater than 90 °. In a sectional view, trench 5 is, for example, V-shaped. The trench 5 is pointed toward the second main surface 2, for example.

The fourth impurity region 40 is provided between the second main surface 2 and the bottom 4 of the trench 5. As shown in FIG. 1, the fourth impurity region 40 may be in contact with the bottom 4. Fourth impurity region 40 includes a p-type impurity such as aluminum or boron, and has a p-type (second conductivity type). The fourth impurity region 40 has a higher impurity concentration than the base region 20. The fourth impurity region 40 may be electrically connected to the source electrode 8. The concentration of a p-type impurity such as aluminum contained in fourth impurity region 40 is, for example, not less than 1 × 10 ¹⁸ cm ^{−3 and not} more than 9 × 10 ¹⁸ cm ⁻³ .

  As shown in FIG. 1, side surface 3 of trench 5 is in contact with third region 13, second impurity region 20, third impurity region 30, and fourth impurity region 40. The first region 11 may be in contact with the side surface 3 or may be separated from the side surface 3. The second region 12 is separated from the side surface 3. The third region 13 is in contact with the first region 11. Third region 13 may be in contact with second impurity region 20. The third region 13 is in contact with the side surface 3 and protrudes in a direction away from the side surface 3. The first area 11 is in contact with the second area 12. The second region 12 is electrically connected to the third region 13, but may be physically separated from the third region 13.

  The bottom 4 of the trench 5 is in contact with the fourth impurity region 40. As shown in FIG. 2, in the direction parallel to the first main surface 1, the distance (first distance 111) from the bottom 4 of the trench 5 to the end of the third region 13 is the first distance from the bottom 4 of the trench 5. It is shorter than the distance to the end of the four impurity region 40 (second distance 112).

  Note that the end of the third region 13 has a concentration of 1 / e of the maximum value of the concentration of the n-type impurity in the third region 13 and is parallel to the first main surface 1 from the bottom 4 of the trench 5. The most distant position in the direction. Note that “e” is the Napier number. The end of the fourth impurity region 40 has a minimum carrier concentration due to the n-type impurity in the adjacent first impurity region 10 and the p-type impurity in the fourth impurity region 40 being canceled out, and the trench 5 has This is the position farthest from the bottom 4 in the direction parallel to the first main surface 1.

  As shown in FIG. 2, when viewed from a direction perpendicular to second main surface 2, trench 5 may be substantially rectangular. The trench 5 extends along a first direction 101 and a second direction 102. The first direction 101 is a short direction of the trench 5. The second direction 102 is a longitudinal direction of the trench 5. The first direction 101 is, for example, a <1-100> direction. The second direction 102 is, for example, a <11-20> direction. The first direction 101 may be, for example, a direction in which the <1-100> direction is projected on the first main surface 1. The second direction 102 may be, for example, a direction in which the <11-20> direction is projected on the first main surface 1.

  As shown in FIG. 2, each of third region 13 and fourth impurity region 40 extends along the direction in which trench 5 extends. The longitudinal direction of the third region 13 is the same as the longitudinal direction of the trench 5. The short direction of the third region 13 is the same as the short direction of the trench 5. The longitudinal direction of the fourth impurity region 40 is the same as the longitudinal direction of the trench 5. The short direction of the fourth impurity region 40 is the same as the short direction of the trench 5. As shown in FIG. 2, the fourth impurity region 40 overlaps the bottom 4 of the trench 5 when viewed from a direction perpendicular to the second main surface 2. The width of the fourth impurity region 40 in the short direction of the trench 5 may be smaller than the width of the opening of the trench 5. Similarly, the width of the fourth impurity region 40 in the longitudinal direction of the trench 5 may be smaller than the width of the opening of the trench 5.

  Gate insulating film 6 is made of, for example, silicon dioxide. The gate insulating film 6 is provided so as to be in contact with the side surface 3 and the bottom 4 of the trench 5. Gate insulating film 6 is in contact with third region 13, base region 20, source region 30, and fourth impurity region 40 on side surface 3 of trench 5. Gate insulating film 6 is in contact with fourth impurity region 40 at bottom 4 of trench 5. A channel region can be formed in the base region 20 in contact with the gate insulating film 6. Gate insulating film 6 has a thickness of, for example, not less than 40 nm and not more than 150 nm.

  The gate electrode 7 is provided on the gate insulating film 6. Gate electrode 7 is arranged in contact with gate insulating film 6. The gate electrode 7 is provided so as to fill a groove formed by the gate insulating film 6. Gate electrode 7 is made of, for example, a conductor such as polysilicon doped with an impurity.

  Source electrode 8 is made of, for example, a Ni alloy. Source electrode 8 is electrically connected to source region 30 on first main surface 1 side of silicon carbide substrate 100. Source electrode 8 is in contact with contact region 42. Source electrode 8 includes an alloy layer that is in ohmic contact with source region 30. The alloy layer is, for example, silicide with the metal included in the source electrode 8. The source electrode 8 may be made of a material containing Ti, Al, and Si.

  Interlayer insulating film 23 is provided at a position facing first main surface 1 of silicon carbide substrate 100. Specifically, interlayer insulating film 23 is provided in contact with each of gate electrode 7 and gate insulating film 6 so as to cover gate electrode 7. The interlayer insulating film 23 includes, for example, an NSG (None-doped Silicate Glass) film and a PSG (Phosphorus Silicate Glass) film. The NSG may be provided on the PSG. Interlayer insulating film 23 electrically insulates gate electrode 7 and source electrode 8. Source wiring 21 is provided so as to cover interlayer insulating film 23 and to be in contact with source electrode 8. Source wiring 21 is electrically connected to source region 30 via source electrode 8. Source wiring 21 is made of, for example, a material containing AlSiCu. The protection film 22 is provided on the source wiring 21 so as to cover the source wiring 21. The protective film 22 includes, for example, a nitride film and polyimide.

  Drain electrode 9 is provided in contact with second main surface 2 of silicon carbide substrate 100. The drain electrode 9 is electrically connected to the first impurity region 10 on the second main surface 2 side. Drain electrode 9 is made of a material such as NiSi (nickel silicide) capable of ohmic junction with n-type silicon carbide single crystal substrate 15. Drain electrode 9 is electrically connected to silicon carbide single crystal substrate 15.

  Next, the operation of the MOSFET 200 according to the present embodiment will be described. In a state where the voltage applied to the gate electrode 7 is lower than the threshold voltage, that is, in an off state, even if a voltage is applied between the source electrode 8 and the drain electrode 9, the voltage between the base region 20 and the first impurity region 10 is reduced. The pn junction formed at the same time becomes reverse biased and becomes non-conductive. On the other hand, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 7, an inversion layer is formed in the channel region of the base region 20 near the contact with the gate insulating film 6. As a result, the source region 30 and the first impurity region 10 are electrically connected, and a current flows between the source electrode 8 and the drain electrode 9. As described above, MOSFET 200 operates.

  Next, a method for manufacturing silicon carbide semiconductor device 200 according to the present embodiment will be described. FIG. 3 is a flowchart schematically showing a method for manufacturing silicon carbide semiconductor device 200 according to the present embodiment.

  First, a step of preparing a silicon carbide substrate (FIG. 3: S10) is performed. For example, a silicon carbide single crystal ingot grown by the improved Rayleigh method is sliced to cut out a substrate, and the surface of the substrate is mirror-polished to prepare a silicon carbide single crystal substrate 15 (see FIG. 4). Silicon carbide single crystal substrate 15 is, for example, hexagonal silicon carbide of polytype 4H. Silicon carbide single crystal substrate 15 has a third main surface 51 and a second main surface 2 opposite to third main surface 51. The diameter of third main surface 51 is, for example, 150 mm. The third main surface 51 is, for example, a (000-1) plane or a plane off by about 8 ° or less from the (000-1) plane. Silicon carbide single crystal substrate 15 has a thickness of, for example, 400 μm.

Next, a step of forming a silicon carbide epitaxial layer is performed. For example, a carrier gas containing hydrogen, a source gas containing silane and propane, and a dopant gas containing nitrogen are supplied onto silicon carbide single crystal substrate 15, and silicon carbide single crystal substrate 15 is supplied under a pressure of 100 mbar (10 kPa). Is heated, for example, to about 1550 ° C. Thereby, silicon carbide epitaxial layer 16 having n-type is formed on silicon carbide single crystal substrate 15 as shown in FIG. Silicon carbide epitaxial layer 16 is doped with nitrogen as an n-type impurity. The concentration of the n-type impurity is, for example, 8.0 × 10 ¹⁵ cm ⁻³ . Silicon carbide epitaxial layer 16 has a thickness of, for example, 10 μm.

Next, an ion implantation through mask 60 is formed. The ion implantation through mask 60 is formed, for example, by combining a thermal oxide film and a deposited oxide film. The thickness of the ion implantation through mask 60 is, for example, about 50 nm. Next, ion implantation is performed on silicon carbide epitaxial layer 16. For example, N (nitrogen) ions are implanted into silicon carbide epitaxial layer 16 through ion implantation through mask 60 in the direction of the arrow (the direction perpendicular to third main surface 51). Thereby, the first region 11 having the n-type is formed. The concentration of the n-type impurity included in first region 11 is, for example, not less than 3 × 10 ¹⁶ cm ^{−3 and not} more than 3 × 10 ¹⁷ cm ⁻³ . The thickness of the first region 11 is, for example, not less than 0.2 μm and not more than 0.5 μm.

Next, for example, Al (aluminum) ions are ion-implanted in the direction of the arrow into a part of first region 11 of silicon carbide epitaxial layer 16 through ion implantation through mask 60. As a result, a second impurity region 20 having p-type is formed. The concentration of the p-type impurity contained in second impurity region 20 is, for example, not less than 5 × 10 ¹⁶ cm ^{−3 and not} more than 2 × 10 ¹⁸ cm ⁻³ . The thickness of second impurity region 20 is, for example, not less than 0.3 μm and not more than 0.7 μm. The thickness of the second impurity region 20 may be, for example, 0.5 μm or less, or may be 0.4 μm or less.

Next, for example, P (phosphorus) ions are ion-implanted into a part of second impurity region 20 of silicon carbide epitaxial layer 16 in the direction of the arrow through ion implantation through mask 60. Thus, an n-type third impurity region 30 is formed (see FIG. 7). The concentration of the n-type impurity contained in third impurity region 30 is, for example, not less than 2 × 10 ¹⁸ cm ^{−3 and not} more than 1 × 10 ¹⁹ cm ⁻³ . The thickness of third impurity region 30 is, for example, 0.1 μm or more and 0.2 μm or less.

Next, ion implantation through mask 60 is removed by, for example, wet etching. After the ion implantation through mask 60 is removed, an oxide film mask 63 is formed. The oxide film mask 63 has a first portion 61 and a second portion 62. The thickness of the second portion 62 is larger than the thickness of the first portion 61. For example, Al (aluminum) ions are ion-implanted into a part of second impurity region 20 and a part of third impurity region 30 of silicon carbide epitaxial layer 16 through oxide film mask 63. Thus, a p-type contact region 42 is formed (see FIG. 8). The concentration of the p-type impurity contained in contact region 42 is, for example, not less than 2 × 10 ¹⁸ cm ^{−3 and not} more than 1 × 10 ¹⁹ cm ⁻³ . The thickness of contact region 42 is, for example, 0.1 μm or more and 0.3 μm or less. The contact region 42 penetrates through the third impurity region 30 and reaches the second impurity region 20.

  Thus, silicon carbide substrate 100 having first main surface 1 and second main surface 2 opposite to first main surface 1 is prepared. Silicon carbide substrate 100 includes a first impurity region 10 having a first conductivity type, a second impurity region 20 provided on first impurity region 10 and having a second conductivity type different from the first conductivity type, A third impurity region provided on second impurity region and separated from first impurity region and in contact with first main surface and having a first conductivity type. The first impurity region 10 has a first region 11 in contact with the second impurity region 20 and a second region 12 located on the opposite side of the first region 11 from the second impurity region 20. The first main surface 1 is, for example, a (000-1) plane or a plane off by about 8 ° or less from the (000-1) plane.

Next, a step of forming a mask on the first main surface (S20: FIG. 3) is performed. Specifically, mask 64 is formed on first main surface 1. The mask 64 functions as an etching mask. The mask 64 is made of, for example, a material containing a deposited oxide film. The thickness of the mask 64 is, for example, 1 μm. Next, by using CHF ₃ and O ₂ , RF etching is performed on the mask 64 on the region where the first trench 70 is to be formed, so that an opening is formed in the mask 64.

Next, a step of forming the first trench (S30: FIG. 3) is performed. Etching is performed on silicon carbide substrate 100 using mask 64 having an opening formed in a region where first trench 70 is formed. For example, anisotropic etching is performed on third impurity region 30 and second impurity region 20 in an atmosphere of SF ₆ and O ₂ using mask 64. The anisotropic etching is, for example, ECR (Electron Cyclotron Resonance) plasma etching. Thereby, first trench 70 is formed in first main surface 1 of silicon carbide substrate 100.

  As shown in FIG. 9, the first trench 70 has a first side surface 71 and a first bottom surface 72. First side surface 71 is in contact with second impurity region 20 and third impurity region 30. The first bottom surface 72 is in contact with the first region 11. The depth of first trench 70 is, for example, not less than 0.2 μm and not more than 0.7 μm. The width of first trench 70 is, for example, not less than 0.7 μm and not more than 1 μm.

  Next, a step of forming a fourth impurity region by ion implantation (S40: FIG. 3) is performed. Specifically, ion implantation is performed on the first trench 70 using the mask 64. In this step, the mask 64 functions as an ion implantation mask. Specifically, Al (aluminum) ions are ion-implanted into a part of the first region 11 and a part of the second region 12 with the mask 64 provided on the first main surface 1. The ion implantation energy is, for example, 700 keV or more. As a result, a fourth impurity region 40 having p-type is formed.

The fourth impurity region 40 is in contact with the first impurity region 10. Specifically, fourth impurity region 40 is in contact with each of first region 11 and second region 12. In the direction parallel to the first main surface 1, the width of the fourth impurity region 40 is larger than the width of the first bottom surface 72 of the first trench 70. The fourth impurity region 40 extends from each of the pair of first side surfaces 71 of the first trench 70 by about 0.2 μm. The concentration of the p-type impurity contained in fourth impurity region 40 is, for example, not less than 1 × 10 ¹⁸ cm ^{−3 and not} more than 9 × 10 ¹⁸ cm ⁻³ . The thickness of fourth impurity region 40 is, for example, 0.5 μm or more and 1.5 μm or less.

  Next, a step of forming a third region by ion implantation (S50: FIG. 3) is performed. Specifically, ion implantation is performed on the first trench 70 using the mask 64. In this step, the mask 64 functions as an ion implantation mask. Specifically, in a state where the mask 64 is provided on the first main surface 1, N (nitrogen) ions are supplied to a part of the first region 11, a part of the second impurity region 20, and a fourth impurity region. Ion is implanted into a part of 40. The ion implantation energy is, for example, 400 keV or more. Thereby, the third region 13 having the n-type is formed. The ion implantation energy of the step of forming the third region by ion implantation (S50: FIG. 3) is smaller than the ion implantation energy of the step of forming the fourth impurity region by ion implantation (S40: FIG. 3). Third region 13 is formed on first main surface 1 side with respect to fourth impurity region 40.

As shown in FIG. 10, the third region 13 is in contact with the fourth impurity region 40. Specifically, third region 13 is in contact with each of first region 11 and fourth impurity region 40. In the direction parallel to the first main surface 1, the width of the third region 13 is larger than the width of the first bottom surface 72 of the first trench 70 and smaller than the width of the fourth impurity region 40. The third region 13 extends from each of the pair of first side surfaces 71 of the first trench 70 by about 0.1 μm. The impurity concentration of the third region 13 is higher than the impurity concentration of the first region 11. The concentration of the n-type impurity included in third region 13 is, for example, not less than 2 × 10 ¹⁶ cm ^{−3 and not} more than 5 × 10 ¹⁷ cm ⁻³ . The thickness of third region 13 is, for example, not less than 0.3 μm and not more than 1 μm.

  When silicon carbide substrate 100 (off substrate) having first main surface 1 inclined with respect to the (000-1) plane is used, channeling can be suppressed. Thereby, it is possible to effectively perform ion implantation in a direction perpendicular to the first main surface 1. When the ions are implanted in a direction inclined with respect to the normal line of the first main surface 1, the lateral spread can be promoted.

Next, a step of forming the second trench by expanding the first trench (S60: FIG. 3) is performed. Specifically, for example, with the mask 64 used, the third impurity region 30, the second impurity region 20, the first region 11, and the fourth impurity region 40 are exposed to an atmosphere containing a halogen gas. Thermal etching is performed. Thermal etching is performed in an atmosphere containing a reactive gas having at least one or more halogen atoms. The at least one or more halogen atoms include, for example, at least one of a chlorine (Cl) atom and a fluorine (F) atom. The atmosphere includes, for example, chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), sulfur hexafluoride (SF ₆ ), or carbon tetrafluoride (CF ₄ ). For example, thermal etching is performed by using a mixed gas of chlorine gas and oxygen gas as a reaction gas and setting the heat treatment temperature to, for example, 800 ° C. or more and 900 ° C. or less. Note that the reaction gas may include a carrier gas in addition to the chlorine gas and the oxygen gas described above. As the carrier gas, for example, nitrogen gas, argon gas, helium gas, or the like can be used. Thereby, the first trench 70 is expanded to form the second trench 5. The first trench 70 is extended in each of the depth direction and the width direction.

  As shown in FIG. 11, the second trench 5 is, for example, V-shaped in a cross-sectional view. The second trench 5 is pointed, for example, toward the second main surface 2. The second trench 5 has a second side surface 3 and a second bottom 4. The second side surface 3 is in contact with the third region 13, the second impurity region 20, the third impurity region 30, and the fourth impurity region 40. The second side surface 3 is continuous with the first main surface 1. The second bottom 4 is in contact with the fourth impurity region 40. In other words, the second bottom 4 is located in the fourth impurity region 40. The depth of the second trench 5 is larger than the depth of the first trench 70. The depth of second trench 5 is, for example, 0.5 μm or more and 1.0 μm or less. The width of the opening of the second trench 5 is larger than the width of the opening of the first trench 70. The angle θ between the first main surface 1 and the second side surface is larger than 90 °. Angle θ between first main surface 1 and second side surface is, for example, not less than 115 ° and not more than 135 °. Angle θ may be greater than or equal to 120 °. Angle θ may be equal to or smaller than 130 °.

  Next, a step of annealing the silicon carbide substrate (S70: FIG. 3) is performed. First, mask 64 is removed from first main surface 1 of silicon carbide substrate 100. Next, silicon carbide substrate 100 is arranged in case 80 made of silicon carbide (see FIG. 12). The case 80 has a housing section 81 and a lid section 82. Silicon carbide substrate 100 is arranged in accommodation portion 81. A lid part 82 is arranged on the accommodation part 81. Thereby, silicon carbide substrate 100 is sealed in case 80.

  Silicon carbide substrate 100 is heated in a state where silicon carbide substrate 100 is sealed in case 80. Since silicon carbide substrate 100 is arranged in silicon carbide case 80, silicon carbide substrate 100 is heated in a silicon carbide atmosphere. Thereby, the thermal equilibrium state of silicon carbide is maintained. In a silicon carbide atmosphere, silicon carbide substrate 100 is annealed at 1400 ° or more and 1900 ° or less. Preferably, silicon carbide substrate 100 is annealed at 1500 ° or more and 1800 ° or less. The annealing temperature of silicon carbide substrate 100 is, for example, 1700 °. The annealing time is, for example, 10 minutes.

  As described above, the thermal etching of the second trench 5 and the activation of the ion-implanted impurity are simultaneously performed. The damage layer on each of the second side surface 3 and the second bottom 4 of the second trench 5 is removed by thermal etching.

  Next, a step of forming a gate insulating film (S80: FIG. 3) is performed. Specifically, a gate insulating film 6 in contact with the first main surface 1, the second side surface 3, and the second bottom 4 is formed. Gate insulating film 6 is, for example, a deposited oxide film. Gate insulating film 6 is in contact with third region 13, fourth impurity region 40, base region 20, and source region 30 on second side surface 3. The gate insulating film 6 is in contact with the fourth impurity region 40 at the second bottom 4. Gate insulating film 6 is in contact with source region 30 on first main surface 1. Gate insulating film 6 has a thickness of, for example, not less than 40 nm and not more than 150 nm.

  Next, a NO annealing step is performed. Specifically, silicon carbide substrate 100 having gate insulating film 6 formed on first main surface 1 in an atmosphere containing nitrogen is subjected to a heat treatment at a temperature of, for example, 1100 ° C. or more and 1300 ° C. or less. The gas containing nitrogen is, for example, nitric oxide diluted by 10% with nitrogen. Silicon carbide substrate 100 is annealed in a gas containing nitrogen for, for example, 30 minutes or more and 360 minutes or less.

  Next, a step of forming a gate electrode (S90: FIG. 3) is performed. Specifically, a gate electrode 7 is formed on gate insulating film 6 so as to fill a groove formed by gate insulating film 6. Gate electrode 7 is made of, for example, a material containing polysilicon containing impurities. Next, an interlayer insulating film 23 is formed so as to cover the gate electrode 7. The interlayer insulating film 23 includes, for example, an NSG film and a PSG film.

  Next, a step of forming a source electrode (S100: FIG. 3) is performed. Specifically, by removing interlayer insulating film 23 and gate insulating film 6 in a region where source electrode 8 is to be formed, each of source region 30 and contact region 42 is exposed from interlayer insulating film 23. . Next, source electrode 8 is formed on first main surface 1 by, for example, sputtering so as to be in contact with both source region 30 and contact region 42. Source electrode 8 contains, for example, a Ni alloy. Source electrode 8 may be made of a material containing TiAlSi. Next, RTA (Rapid Thermal Anneal) of, for example, 900 ° C. or higher and 1100 ° C. or lower is performed on silicon carbide substrate 100 on which source electrode 8 is formed for about 2 minutes. Thereby, at least a part of source electrode 8 reacts with silicon contained in silicon carbide substrate 100 to be silicided. As a result, the source electrode 8 that forms an ohmic junction with the source region 30 is formed. Preferably, source electrode 8 makes ohmic contact with each of source region 30 and contact region 42.

  Next, source wiring 21 is formed so as to be in contact with source electrode 8 and to cover interlayer insulating film 23. Source wiring 21 is preferably made of a material containing Al, for example, a material containing AlSiCu. Next, a protective film 22 is formed so as to cover the source wiring 21. The protection film 22 is made of a material containing, for example, a nitride film and polyimide.

  Next, a step of forming a drain electrode (S110: FIG. 3) is performed. Specifically, drain electrode 9 made of, for example, NiSi is formed in contact with second main surface 2 of silicon carbide substrate 100. The drain electrode 9 may be, for example, TiAlSi. The drain electrode 9 is preferably formed by a sputtering method, but may be formed by vapor deposition. After the formation of the drain electrode 9, the drain electrode 9 is heated by, for example, laser annealing. Thereby, at least a part of the drain electrode 9 is silicided, and forms an ohmic junction with the silicon carbide single crystal substrate 15. As described above, the MOSFET 200 shown in FIG. 1 is manufactured.

  As shown in FIG. 10, after each of fourth impurity region 40 and third region 13 is formed by ion implantation with mask 64 provided on first main surface 1, mask 64 is removed. May be done. Next, a mask 65 different from the mask 64 may be formed on the first main surface 1 (FIG. 13). The width of the opening of the mask 65 is larger than the width of the opening of the mask 64. Mask 65 is formed on first main surface 1 in contact with each of source region 30 and contact region 42. Part of the first main surface 1 is exposed from the mask 65.

  Next, a step of forming the second trench by expanding the first trench (S60: FIG. 3) is performed. Specifically, for example, with the mask 64 used, the third impurity region 30, the second impurity region 20, the first region 11, and the fourth impurity region 40 are exposed to an atmosphere containing a halogen gas. Thermal etching is performed. The type of halogen gas and the temperature of thermal etching are as described above. Thereby, the first trench 70 is expanded to form the second trench 5 (see FIG. 14). As shown in FIG. 14, the width of the opening of the second trench 5 may be substantially the same as the width of the mask 65.

  Further, in the above description, silicon carbide semiconductor device 200 according to the present disclosure has been described using a MOSFET having trench 5 as an example, but silicon carbide semiconductor device 200 according to the present disclosure is not limited to this. Silicon carbide semiconductor device 200 according to the present disclosure may be, for example, an IGBT (Insulated Gate Bipolar Transistor) or the like. In the above description, the n-type is the first conductivity type and the p-type is the second conductivity type. However, the p-type may be the first conductivity type and the n-type may be the second conductivity type. The concentration of the p-type impurity and the concentration of the n-type impurity in each of the above impurity regions can be measured by, for example, SCM (Scanning Capacity Microscope) or SIMS (Secondary Ion Mass Spectrometry).

  Next, the function and effect of the method for manufacturing a silicon carbide semiconductor device according to the above embodiment will be described.

  According to the method for manufacturing silicon carbide semiconductor device 200 according to the above embodiment, anisotropic etching is performed on third impurity region 30 and second impurity region 20 using a mask, whereby the first main region is formed. The first trench 70 is formed in the surface 1. By performing ion implantation on the first trench 70 using the mask, the fourth impurity region 40 having the second conductivity type and being in contact with the first impurity region 10 is formed. As described above, by performing etching and ion implantation using the same mask 64 (self-alignment), occurrence of misalignment can be suppressed. Therefore, the fourth impurity region 40 can be formed with high accuracy. In addition, the process cost can be reduced by reducing the number of steps.

  Further, according to the method for manufacturing silicon carbide semiconductor device 200 according to the above embodiment, the angle formed between the side surface of second trench 5 and first main surface 1 is greater than 90 °. Accordingly, even when the thickness of the base region 20 is small, a long channel length can be secured. Therefore, it is not necessary to use epitaxial growth to form base region 20. As a result, process costs can be reduced. Further, in silicon carbide semiconductor device 200 according to the above embodiment, fourth impurity region 40 is located at the bottom of second trench 5. This can prevent the gate insulating film 6 from being broken by applying a high electric field to the gate insulating film 6 near the bottom 4. As a result, the breakdown voltage of silicon carbide semiconductor device 200 can be maintained high.

  According to the method for manufacturing silicon carbide semiconductor device 200 according to the above embodiment, ion implantation is performed on first trench 70 using a mask, so that first trench 70 is in contact with first impurity region 10 and has the first conductivity type. May be formed. The third region 13 may be in contact with the side surface. By providing the third region 13 having a higher impurity concentration than the first region 11, current constriction near the channel outlet can be suppressed. Therefore, on-resistance of silicon carbide semiconductor device 200 can be reduced.

  Further, according to the method for manufacturing silicon carbide semiconductor device 200 according to the above embodiment, the step of forming second trench 5 may be performed using a mask. By forming each of the first trench 70 and the second trench 5 using the same mask 64, the occurrence of misalignment can be further suppressed.

The first distance 111 (the distance from the bottom 4 of the trench 5 to the end of the third region 13 in the direction parallel to the second main surface 2) in the MOSFET (see FIG. 1) according to the present embodiment is changed. The result of calculating the characteristic on-resistance and the withstand voltage of the MOSFET in the above case by simulation will be described. The characteristic on-resistance and breakdown voltage of the MOSFET were calculated while changing the value of the first distance 111 from 0 μm to 0.7 μm. The n-type impurity concentration of the first region 11 was set to 1 × 10 ¹⁷ cm ⁻³ . The n-type impurity concentration of the second region 12 was set to 8 × 10 ¹⁵ cm ⁻³ . The n-type impurity concentration of the third region 13 was set to 2 × 10 ¹⁷ cm ⁻³ . The p-type impurity concentration of the fourth impurity region 40 was set to 3 × 10 ¹⁸ cm ⁻³ .

The relationship between the distance from the bottom 4 of the trench 5 (first distance 111) and the characteristic on-resistance and the relationship between the distance from the bottom 4 of the trench 5 (first distance 111) and the breakdown voltage will be described with reference to FIG. I do. In the figure, the horizontal axis represents the distance (μm) from the bottom 4 of the trench 5, the left vertical axis represents the characteristic on-resistance (mΩcm ² ) of the MOSFET, and the right vertical axis represents the breakdown voltage (V) of the MOSFET. I have. In the figure, white circles indicate the value of the withstand voltage, and white triangles indicate the value of the characteristic on-resistance. The specification of the withstand voltage is 1200V.

  In a range where the distance from the bottom 4 of the trench 5 is 0 μm or more and less than 0.4 μm, the characteristic on-resistance gradually decreases. However, when the distance from the bottom 4 of the trench 5 becomes 0.4 μm or more, the characteristic on-resistance maintains a substantially constant value. The breakdown voltage satisfies the specifications in all ranges. In the range where the distance from the bottom 4 of the trench 5 is 0 μm or more and 0.3 μm or less, the withstand voltage shows a particularly high value. However, when the distance from the bottom 4 of the trench 5 exceeds 0.3 μm, the breakdown voltage gradually decreases. From the above results, it has been confirmed that the MOSFET provided with the third region 13 can reduce the characteristic on-resistance while maintaining a high withstand voltage as compared with the MOSFET provided with no third region 13. Was done.

  It should be understood that the embodiments and examples disclosed this time are illustrative in all aspects and are not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 1st main surface 2 2nd main surface 3 2nd side surface (side surface)
4 2nd bottom (bottom)
5 Second trench (trench)
Reference Signs List 6 gate insulating film 7 gate electrode 8 source electrode 9 drain electrode 10 first impurity region 11 first region 12 second region 13 third region 15 silicon carbide single crystal substrate 16 silicon carbide epitaxial layer 20 base region (second impurity region)
DESCRIPTION OF SYMBOLS 21 Source wiring 22 Protective film 23 Interlayer insulating film 30 Source region (third impurity region)
40 fourth impurity region 42 contact region 51 third main surface 60 ion implantation through mask 61 first portion 62 second portion 63 oxide film mask 64, 65 mask 70 first trench 71 first side surface 72 first bottom surface 80 case 81 accommodation Part 82 Cover 100 Silicon carbide substrate 101 First direction 102 Second direction 111 First distance 112 Second distance 200 Silicon carbide semiconductor device (MOSFET)

Claims (5)

Providing a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface,
The silicon carbide substrate,
A first impurity region having a first conductivity type;
A second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type;
A third impurity region provided on the second impurity region so as to be separated from the first impurity region and in contact with the first main surface and having the first conductivity type;
The first impurity region has a first region in contact with the second impurity region, and a second region located on the opposite side of the first region from the second impurity region,
Forming a mask on the first main surface;
Forming a first trench in the first main surface by performing anisotropic etching on the third impurity region and the second impurity region using the mask;
Forming a fourth impurity region in contact with the first impurity region and having the second conductivity type by performing ion implantation on the first trench using the mask;
The first trench is expanded by performing thermal etching on the third impurity region, the second impurity region, the first region, and the fourth impurity region in an atmosphere containing a halogen gas. Forming a second trench by using
The second trench has a side surface connected to the first main surface and a bottom located in the fourth impurity region, and an angle formed by the first main surface and the side surface is larger than 90 °. A method for manufacturing a silicon carbide semiconductor device. By performing ion implantation on the first trench using the mask, the first trench is in contact with the fourth impurity region, has the first conductivity type, and has a higher impurity concentration than the first region. Further comprising a step of forming three regions,
The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein said third region is in contact with said side surface.   3. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the first main surface is a (000-1) plane or a plane inclined by 8 ° or less with respect to the (000-1) plane. 4.   4. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein said second impurity region has a thickness of 0.3 μm or more and 0.7 μm or less. 5.   The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of forming the second trench is performed using the mask.

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