JP6287193B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly to a method for manufacturing a silicon carbide semiconductor device using a silicon carbide substrate including a main surface having an off angle.

  In recent years, in order to enable a semiconductor device to have a high breakdown voltage, low loss, use under a high temperature environment, etc., silicon carbide is being adopted as a material constituting the semiconductor device. Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.

  When the silicon carbide epitaxial layer is grown on the main surface of the silicon carbide substrate including the main surface having an off angle with respect to the {0001} plane, the epitaxial layer is step-flow grown on the main surface of the silicon carbide substrate. Therefore, the epitaxial layer does not grow isotropically but grows in a specific direction with respect to the shape of the alignment mark formed on the main surface of the silicon carbide substrate before forming the epitaxial layer. As a result, since the shape of the alignment mark after the epitaxial layer growth is deformed, alignment cannot be performed with high accuracy.

  As a method for improving alignment accuracy when a silicon carbide substrate including a main surface having an off angle is used, for example, in Japanese Patent Application Laid-Open No. 2011-1000092 (Patent Document 1), the off direction is <11-20>. A method for forming alignment marks on a silicon substrate is described. According to the method described in Japanese Patent Application Laid-Open No. 2011-1000092, the trench having a polygonal shape in which the shape of the opening is symmetric with respect to the off direction and the apex is located at the most downstream side in the off direction. Used as an alignment mark. Thereby, it is supposed that alignment with a silicon carbide substrate and a mask can be performed with high precision.

  Japanese Patent Laying-Open No. 2013-65650 (Patent Document 2) discloses a silicon carbide having a process in which, when the shape of an alignment mark is deformed, the influence of the deformation is corrected and the optical mask is aligned at the original position. A method for manufacturing a semiconductor device is described. Thereby, even when an off-substrate is used, it is said that the alignment of the photolithography optical mask can be accurately performed.

  Furthermore, JP 2009-170558 A (Patent Document 3) discloses that a first trench for forming a device and a second trench for use as an alignment mark have a second solid angle of the first trench. It is described that it is formed to be larger than the solid angle of the trench. As a result, the growth rate of the bottom of the first trench can be made larger than the growth rate of the bottom of the second trench, so that the second trench is formed when the main surface of the substrate is planarized. A concave portion is formed in the portion, and the concave portion can be used as an alignment mark.

JP 2011-1000092 A JP 2013-65650 A JP 2009-170558 A

  However, even when the method described in JP2011-100908A, JP2013-65650A, or JP2009-170558A is used, a silicon carbide substrate including a main surface having an off angle is used. On the other hand, when alignment is performed by forming alignment marks, sufficiently high alignment accuracy may not be obtained.

  The present invention has been made in view of the above problems, and an object thereof is to provide a method for manufacturing a silicon carbide semiconductor device capable of improving alignment accuracy.

  A method for manufacturing a silicon carbide semiconductor device according to the present invention includes the following steps. A silicon carbide substrate including a main surface having an off angle with respect to the {0001} plane is prepared. A mask layer is formed on the main surface of the silicon carbide substrate. A concave alignment mark is formed on the main surface of the silicon carbide substrate using the mask layer. The concave alignment mark includes a side portion connected to the main surface and a bottom portion connected to the side portion. A protective film is formed so as to cover the surface of the mask layer and the side and bottom portions of the alignment mark. The second portion of the protective film covering the surface of the mask layer is removed together with the mask layer while leaving the first portion of the protective film covering each of the side and bottom portions of the alignment mark. After removing the mask layer, an epitaxial layer is formed on the main surface of the silicon carbide substrate. Processing is performed on the epitaxial layer using the alignment mark.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the silicon carbide semiconductor device which can improve alignment precision can be provided.

It is a flowchart of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 1st process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. 1 is a schematic plan view schematically showing a first step of a method for manufacturing a silicon carbide semiconductor device according to one embodiment of the present invention. It is a cross-sectional schematic diagram which shows schematically the 2nd process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 3rd process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 4th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 5th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 6th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 7th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 8th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 9th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 10th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 11th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 12th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 13th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. It is a cross-sectional schematic diagram which shows schematically the 14th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. FIG. 22 is a schematic cross sectional view schematically showing a fifteenth step of the method for manufacturing the silicon carbide semiconductor device according to one embodiment of the present invention. It is a cross-sectional schematic diagram which shows schematically the 16th process of the manufacturing method of the silicon carbide semiconductor device which concerns on one embodiment of this invention. FIG. 11 is a schematic cross sectional view schematically showing a first modification of the fifth step of the method for manufacturing the silicon carbide semiconductor device according to one embodiment of the present invention. FIG. 11 is a schematic cross sectional view schematically showing a second modification of the fifth step of the method for manufacturing the silicon carbide semiconductor device according to one embodiment of the present invention. It is a cross-sectional schematic diagram for demonstrating the shape of the protective film formed using the thin mask. It is a cross-sectional schematic diagram for demonstrating the shape of the protective film formed using the thick mask.

[Description of Embodiment of Present Invention]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding a “-” (bar) above a number, but in this specification a negative sign is added before the number. Yes.

  (1) The manufacturing method of the silicon carbide semiconductor device which concerns on embodiment has the following processes. Silicon carbide substrate 10 including main surface 10a having an off angle with respect to the {0001} plane is prepared. Mask layer 20 is formed on main surface 10a of silicon carbide substrate 10. Using mask layer 20, concave alignment mark 1 is formed on main surface 10a of silicon carbide substrate 10 including side portion 1a connected to main surface 10a and bottom portion 1b connected to side portion 1a. A protective film 30 is formed so as to cover the surface 20 a of the mask layer 20, the side portion 1 a and the bottom portion 1 b of the alignment mark 1. The second portion 30b of the protective film 30 covering the surface 20a of the mask layer 20 is removed together with the mask layer 20 while leaving the first portion 30a of the protective film 30 covering each of the side portion 1a and the bottom portion 1b of the alignment mark 1. Is done. After removing mask layer 20, epitaxial layer 12 is formed on main surface 10 a of silicon carbide substrate 10. Using the alignment mark 1, the epitaxial layer 12 is processed.

  According to the method for manufacturing silicon carbide semiconductor device 100 according to (1) above, alignment mark 1 is formed in which first portion 30a of protective film 30 covering each of side portion 1a and bottom portion 1b of alignment mark 1 is left. Is done. Thereby, when epitaxial layer 12 is formed on main surface 10a of silicon carbide substrate 10, it is possible to suppress step flow growth of silicon carbide on each of side portion 1a and bottom portion 1b of the alignment mark. . Thereby, it can suppress that the alignment mark 1 deform | transforms asymmetrically and alignment accuracy deteriorates. As a result, alignment accuracy in the process of manufacturing silicon carbide semiconductor device 100 having silicon carbide substrate 10 including first main surface 10a having an off angle can be improved.

  (2) Preferably, in the method for manufacturing a silicon carbide semiconductor device according to (1), the step of processing epitaxial layer 12 includes the step of forming impurity region 84 on epitaxial layer 12. Thereby, the alignment accuracy in the process of forming the impurity region 84 can be improved.

  (3) Preferably in the method for manufacturing a silicon carbide semiconductor device according to (1) or (2) above, the material constituting protective film 30 is higher than the temperature of silicon carbide substrate 10 in the step of forming epitaxial layer 12. Has a melting point. Thereby, in the process of forming the epitaxial layer 12, it can suppress that the element which comprises the protective film 30 mixes into the epitaxial layer 12 because the protective film 30 fuse | melts.

  (4) Preferably in the method for manufacturing a silicon carbide semiconductor device according to (3) above, the material forming protective film 30 includes tantalum carbide or a carbon material. Thereby, it is possible to suppress the step flow growth of silicon carbide on protective film 30. As a result, it can be suppressed that the alignment mark 1 is deformed asymmetrically and the alignment accuracy is deteriorated.

  (5) Preferably in the manufacturing method of the silicon carbide semiconductor device which concerns on either of said (1)-(4), the thickness of the mask layer 20 is 0.5 micrometer or more and 2.0 micrometers or less. When the thickness of the mask layer 20 is smaller than 0.5 μm, the first portion 30 a of the protective film 30 is formed up to the upper portion of the side portion 1 a of the alignment mark 1. In this case, the second portion 30b of the protective film 30 in contact with the side surface 20b of the mask layer 20 is connected to the first portion 30a. If the second portion 30b of the protective film 30 is connected to the first portion 30a, the first portion 30a may be removed together with the second portion 30b of the protective film 30 when the mask layer 20 is lifted off. . Since silicon carbide grows in a step flow manner on the side portion 1a of the alignment mark 1 that is not covered by the first portion 30a of the protective film 30, an alignment mark 1 that is asymmetric with respect to the main surface 10a of the silicon carbide substrate 10 is formed. Is done. As a result, alignment accuracy deteriorates. On the other hand, when the thickness of mask layer 20 is larger than 2.0 μm, for example, first portion 30a of protective film 30 is formed only at the lower portion of side portion 1a of alignment mark 1, and the protective film is formed at the upper portion of side portion 1a. 30 first portions 30a are not formed. When the epitaxial layer is formed, silicon carbide grows in a step-flow manner in a region that is not covered by the first portion 30a of the protective film 30 above the side portion 1a of the alignment mark, so that the main surface of the silicon carbide substrate 10 An alignment mark 1 asymmetric with respect to 10a is formed. As a result, alignment accuracy deteriorates. By setting the thickness of the mask layer to 0.5 μm or more and 2.0 μm or less, the protective film 30 can be efficiently formed so as to cover each of the side portion 1 a and the bottom portion 1 b of the alignment mark 1.

[Details of the embodiment of the present invention]
With reference to FIGS. 1-22, the manufacturing method of MOSFET100 as a silicon carbide semiconductor device which concerns on one embodiment of this invention is demonstrated.

First, a silicon carbide substrate preparation step (S10: FIG. 1) is performed. Specifically, referring to FIG. 2, for example, silicon carbide single crystal substrate 80 is prepared by slicing an ingot made of hexagonal silicon carbide having polytype 4H. Next, first epitaxial layer 81 a made of silicon carbide is formed by epitaxial growth on silicon carbide single crystal substrate 80. Epitaxial growth is performed by a CVD (Chemical Vapor Deposition) method using, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and using, for example, hydrogen gas (H ₂ ) as a carrier gas. Can do. At this time, it is preferable to introduce, for example, nitrogen (N) or phosphorus (P) as impurities.

  Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b opposite to the first main surface 10a. Silicon carbide substrate 10 has, for example, a silicon carbide single crystal substrate 80 and a first epitaxial layer 81a formed on silicon carbide single crystal substrate 80 and made of a silicon carbide epitaxial layer. First epitaxial layer 81 a constitutes first main surface 10 a of silicon carbide substrate 10, and silicon carbide single crystal substrate 80 constitutes second main surface 10 b of silicon carbide substrate 10. Silicon carbide substrate 10 is configured only from silicon carbide single crystal substrate 80, and does not need to have first epitaxial layer 81a.

  Referring to FIG. 2, first main surface 10a of silicon carbide substrate 10 has an off angle with respect to the {0001} plane. In other words, first main surface 10a of silicon carbide substrate 10 is a surface that is turned off in the off direction a1 by an off angle θ from the {0001} plane (a surface indicated by a broken line). The off angle θ is preferably an angle of 8 ° or less, for example, 4 ° or 8 °. Specifically, the first principal surface is off from the {0001} plane so that the normal vector z of the first principal surface 10a has at least one component of <11-20> and <1-100>. This is the surface. Preferably, the first main surface 10a is a surface off from the {0001} plane so that the normal vector z of the first main surface 10a has a component of <11-20>. In FIG. 2, the direction c is, for example, the <000-1> direction, and the direction a1 is, for example, the <11-20> direction. In the case of FIG. 2, the off direction is the direction a1 (that is, the <11-20> direction). The direction a11 is a direction obtained by projecting the direction a1 onto the first main surface 10a. Preferably, the first main surface 10a is a surface in which the (000-1) plane is turned off in the direction a1. As described above, silicon carbide substrate 10 including main surface 10a having an off angle with respect to the {0001} plane is prepared.

Referring to FIG. 3, first main surface 10 a of silicon carbide substrate 10 has an alignment mark formation region 102 and an element formation region 101. The alignment mark formation region 102 is, for example, a region where a dicing line is to be formed or a region where a dicing line is formed. A concave dicing line (not shown) may be formed in the alignment mark formation region 102. A dicing line is a region where silicon carbide substrate 10 is to be cut. The alignment mark formation region 102, substantially parallel to the direction in which the orientation flat OF extends (e.g., a ₁₁ direction in FIG. 3) along a predetermined transverse to the first main surface 10a of the silicon carbide substrate 10 A plurality are formed with an interval of. The alignment mark formation region 102, along the direction (for example, a ₁₂ direction in FIG. 3) perpendicular to the direction of orientation flat OF extends to cross the first main surface 10a of the silicon carbide substrate 10 In this way, a plurality are formed at predetermined intervals. In the present embodiment, two adjacent alignment mark formation regions 102 that traverse first main surface 10a of silicon carbide substrate 10, and two adjacent alignment mark formation regions 102 that vertically cross first main surface 10a, A region surrounded by is an element formation region 101.

  Next, a mask layer forming step (S20: FIG. 1) is performed. Referring to FIG. 4, mask layer 20 is formed on first main surface 10 a of silicon carbide substrate 10. The mask layer 20 has an opening 20 b on the alignment mark formation region 102. Mask layer 20 covers the entire first main surface 10 a of silicon carbide substrate 10 in element formation region 101. The mask layer 20 is made of a resist, for example. The thickness of the mask layer 20 is preferably 0.5 μm or more and 2.0 μm or less, and more preferably 1.0 μm or more and 1.5 μm or less. The width x1 of the opening 20b is, for example, not less than 1 μm and not more than 500 μm.

  Next, an alignment mark forming step (S30: FIG. 1) is performed. Referring to FIG. 5, dry etching is performed from the first main surface 10 a side of silicon carbide substrate 10 using mask layer 20 having an opening on alignment mark formation region 102. Thereby, the concave alignment which consists of the 1st main surface 10a of the 1st epitaxial layer 81a of the silicon carbide substrate 10 from the side part 1a connected with the 1st main surface 10a, and the bottom part 1b connected with the side part 1a. A mark 1 is formed. Side portion 1 a of alignment mark 1 is formed substantially perpendicular to first main surface 10 a of silicon carbide substrate 10, and bottom portion 1 b of alignment mark 1 is formed with respect to first main surface 10 a of silicon carbide substrate 10. Are formed almost in parallel. Concave alignment mark 1 is formed on first main surface 10a of silicon carbide substrate 10 such that width x2 of concave alignment mark 1 is wider than width x1 of opening 20b of mask layer 20. In other words, silicon carbide substrate 10 is etched in a direction perpendicular to first main surface 10a of silicon carbide substrate 10 and also in a direction parallel to first main surface 10a. From another viewpoint, the concave alignment mark 1 is formed such that a part of the mask layer 20 is positioned above the concave alignment mark 1. The width x2 of the concave alignment mark 1 is, for example, not less than 1.5 μm and not more than 500 μm.

  Next, a protective film forming step (S40: FIG. 1) is performed. Referring to FIG. 6, protective film 30 is formed so as to cover each of surface 20 a of mask layer 20, side surface 20 b forming an opening of mask layer 20, side portion 1 a and bottom portion 1 b of alignment mark 1. The protective film 30 is made of, for example, tantalum carbide (TaC) or a carbon material. A carbon material is a material containing a carbon element, for example, graphite or diamond. Preferably, the material constituting protective film 30 has a melting point higher than the temperature of silicon carbide substrate 10 in the step of forming an epitaxial layer described later. As shown in FIG. 6, the protective film 30 coats, for example, most of the side portion 1a and the entire bottom portion 1b of the concave alignment mark 1, and covers most of the side portion 1a and the entire bottom portion 1b of the alignment mark 1. Each is configured not to be exposed from the protective film 30. Preferably, protective film 30 is made of a material that hardly causes silicon carbide nucleation on the surface of protective film 30. Thereby, when silicon carbide is epitaxially grown on the entire first main surface 10 a of silicon carbide substrate 10, it is possible to prevent silicon carbide from growing epitaxially on first portion 30 a of protective film 30. Protective film 30 only needs to be able to suppress single-crystal silicon carbide from step-flow growth from above each of side portion 1a and bottom portion 1b of alignment mark 1. For example, polycrystalline silicon carbide is formed on protective film 30. It may be deposited.

  Referring to FIG. 21, when the thickness of mask layer 20 is smaller than 0.5 μm, for example, the incident angle of material 30c (for example, TaC) constituting protective film 30 becomes shallow. Therefore, the first portion 30a of the protective film 30 is formed up to the upper portion of the side portion 1a of the alignment mark 1. In this case, the second portion 30b of the protective film 30 in contact with the side surface 20b of the mask layer 20 is connected to the first portion 30a. When the second portion 30b of the protective film 30 is connected to the first portion 30a, the first portion 30a is removed together with the second portion 30b of the protective film 30 in a mask layer removing step (S50: FIG. 1) described later. There is a risk of being. For this reason, it is preferable that the first portion 30a of the protective film 30 is formed away from the second portion 30b. When the first portion 30a of the protective film 30 is removed together with the second portion 30b, an epitaxial layer forming step (S60: FIG. 1) described later is performed, and then the first portion 30a of the protective film 30 is performed. Since silicon carbide grows in a step-flow manner on the side portion 1a of alignment mark 1 that is not covered with silicon, alignment mark 1 that is asymmetric with respect to main surface 10a of silicon carbide substrate 10 is formed. Therefore, the thickness t3 of the mask layer 20 is preferably 0.5 μm or more, and more preferably 1.0 μm or more.

  Referring to FIG. 22, when the thickness of mask layer 20 is larger than 2.0 μm, for example, the incident angle of material 30c (for example, TaC) constituting protective film 30 becomes deeper. Therefore, the first portion 30a of the protective film 30 is formed only at the lower portion of the side portion 1a of the alignment mark 1, and the first portion 30a of the protective film 30 is not formed at the upper portion of the side portion 1a. When an epitaxial layer forming step (S60: FIG. 1) described later is performed, silicon carbide is step-flow grown in a region that is not covered with the first portion 30a of the protective film 30 above the side portion 1a of the alignment mark. Therefore, alignment mark 1 asymmetric with respect to main surface 10a of silicon carbide substrate 10 is formed. Therefore, the thickness t3 of the mask layer 20 is preferably 2.0 μm or less, and more preferably 1.5 μm or less.

  Next, a mask layer removing step (S50: FIG. 1) is performed. Referring to FIG. 7, mask layer 20 is removed from first main surface 10 a of silicon carbide substrate 10. More specifically, the surface 20a of the mask layer 20 and the side surface 20b forming the opening are each covered while leaving the first portion 30a of the protective film 30 covering each of the side 1a and the bottom 1b of the alignment mark 1. The second portion 30 b of the protective film 30 is removed together with the mask layer 20. Mask layer 20 is lifted off together with second portion 30b of protective film 30 by an organic solvent such as acetone. As a result, the protective film 30 that contacts most of the side portion 1a of the alignment mark 1 and the entire bottom portion 1b is formed. A part of the region close to the first major surface 10a in the side portion 1a of the alignment mark 1 may not be in contact with the first portion 30a of the protective film 30 and may be exposed from the first portion 30a. In other words, upper end portion 30a1 of the portion of protective film 30 that is in contact with side portion 1a of alignment mark 1 is the first portion of silicon carbide substrate 10 in the direction along the normal direction of first main surface 10a of silicon carbide substrate 10. It is located closer to the second main surface 10b than the first main surface 10a. Further, upper end portion 30a1 of the portion of protective film 30 in contact with side portion 1a of alignment mark 1 is the center of bottom portion 1b of alignment mark 1 in the direction along the normal direction of first main surface 10a of silicon carbide substrate 10. It is located on the first main surface 10a side with respect to the upper end portion 30a2 of the protective film 30 in contact therewith.

  As shown in FIG. 19, the protective film 30 may be formed so as to cover the entire side portion 1 a of the concave alignment mark 1. In this case, the position of upper end portion 30a1 of protective film 30 in contact with side portion 1a of alignment mark 1 is the position of silicon carbide substrate 10 in the direction along the normal direction of first main surface 10a of silicon carbide substrate 10. 1 is substantially the same position as the main surface 10a. Preferably, the thickness t1 of the first portion 30a of the protective film 30 at the center of the bottom 1b of the alignment mark 1 is smaller than the depth t2 of the alignment mark 1, and more preferably smaller than the thickness of the mask layer 20. The thickness t1 of the first portion 30a of the protective film 30 at the center of the bottom 1b of the alignment mark 1 is, for example, about 0.5 μm.

  As shown in FIG. 20, most of the concave alignment mark 1 may be filled with a protective film 30. In this case, the position of upper end portion 30a1 of the portion of protective film 30 in contact with side portion 1a of alignment mark 1 is in the direction along the normal direction of first main surface 10a of silicon carbide substrate 10, and silicon carbide substrate 10. This is substantially the same position as the first main surface 10a. Further, upper end portion 30a1 of the portion of protective film 30 in contact with side portion 1a of alignment mark 1 is the center of bottom portion 1b of alignment mark 1 in the direction along the normal direction of first main surface 10a of silicon carbide substrate 10. It is located on the first main surface 10a side with respect to the upper end portion 30a2 of the protective film 30 in contact therewith. For example, the protective film 30 fills more than half of the volume of the concave alignment mark 1 and is formed so as not to protrude from the concave alignment mark 1. Thereby, the mask layer 20 can be lifted off effectively. Moreover, in the exposure apparatus, it is possible to effectively suppress the occurrence of problems in reading the alignment mark 1.

  Next, the p-type region 11 may be formed in the first epitaxial layer 81a. Referring to FIG. 8, p-type region in element formation region 101 that is in contact with a part of first main surface 10a of first epitaxial layer 81a of silicon carbide substrate 10 and has p-type (second conductivity type). 11 is formed. Specifically, for example, aluminum ions are implanted into the first main surface 10a of the first epitaxial layer 81a by using an implantation mask (not shown), whereby the first epitaxial layer 81a. A p-type region 11 exposed on first main surface 10a is formed. The implantation mask may be formed using the alignment mark 1 on which the protective film 30 is formed.

  Next, an epitaxial layer forming step (S60: FIG. 1) is performed. Referring to FIG. 9, after p type region 11 is formed in first epitaxial layer 81a, n type conductivity type is formed in contact with first main surface 10a of silicon carbide substrate 10 and carbonized. A second epitaxial layer 12 made of silicon is formed. The thickness of second epitaxial layer 12 (distance from first main surface 10a to surface 12a of second epitaxial layer 12) is, for example, about 0.5 μm to 5 μm, preferably 1.5 μm to 3 μm. Degree. As shown in FIG. 9, by forming second epitaxial layer 12 in contact with first main surface 10a of silicon carbide substrate 10, p-type region 11 includes first epitaxial layer 81a and second epitaxial layer 81. It is embedded in the epitaxial layer constituted by the epitaxial layer 12. The second epitaxial layer 12 can be formed by the same method as that for the first epitaxial layer 81a.

  Next, an epitaxial layer processing step (S70: FIG. 1) is performed. Referring to FIG. 10, body region 82 is formed by ion implantation of an impurity for imparting p-type, such as aluminum, to surface 12 a of second epitaxial layer 12. Next, a source region 83 is formed on body region 82 by ion-implanting impurities for imparting n-type, such as phosphorus, into body region 82. Next, an implantation mask (not shown) is formed on the surface 12 a of the source region 83, and impurities for imparting p-type such as aluminum are ion-implanted into a part of the source region 83 using the implantation mask. As a result, a contact region 84 is formed (FIG. 11).

  In the step of forming the opening in the implantation mask, the alignment mark 1 is used in which the first portion 30a of the protective film 30 is formed in contact with each of the side portion 1a and the bottom portion 1b of the alignment mark 1. Thereby, in the in-plane direction of first main surface 10a of silicon carbide substrate 10, the position where contact region 84 is formed with respect to p type region 11 is aligned. More specifically, the alignment is performed so that the position corresponding to the opening of the implantation mask with respect to the p-type region 11 is exposed. As a general alignment mark recognition method, there are two methods, an LSA (Laser Step Alignment) method and an FIA (Field Image Alignment) method. The LSA method is an optical alignment method in which a laser is applied to an alignment mark and the reflected light of the laser is analyzed for alignment. The FIA method is an image recognition method and is a method for performing alignment by recognizing an edge of an image recognized by a camera. The alignment according to the present embodiment can be used not only in the LSA method and the FIA method, but also in any method other than the LSA method and the FIA method. The alignment may be performed by recognizing the shape of the alignment mark 1 formed from silicon carbide, or by recognizing the shape of the protective film 30 formed inside the alignment mark 1. Also good. As described above, the second epitaxial layer 12 is processed using the alignment mark 1. The treatment for the second epitaxial layer 12 may be a step of forming a contact region 84 for the second epitaxial layer 12.

  Next, a heat treatment for activating the impurities is performed. The temperature of this heat treatment is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The heat treatment time is, for example, about 30 minutes. The atmosphere of the heat treatment is preferably an inert gas atmosphere, for example, an Ar atmosphere.

  Referring to FIG. 12, mask layer 40 having an opening is formed on surface 20 a made up of source region 83 and contact region 84. As mask layer 40, for example, a silicon oxide film or the like can be used. The opening is formed corresponding to the position of trench TR (see FIG. 18). The mask layer 40 has a position corresponding to the opening by using the alignment mark 1 in which the first portion 30a of the protective film 30 is in contact with each of the side portion 1a and the bottom portion 1b of the alignment mark 1. May be formed so as to be exposed.

Referring to FIG. 13, in the opening of mask layer 40, source region 83, body region 82, and part of upper drift region 81b are removed by etching. As an etching method, for example, reactive ion etching (RIE), particularly inductively coupled plasma (ICP) RIE can be used. Specifically, for example, ICP-RIE using SF ₆ or a mixed gas of SF ₆ and O ₂ as a reaction gas can be used. By such etching, a recess TQ having a side wall substantially perpendicular to the surface 20a made of the source region 83 and the contact region 84 is formed in a region where the trench TR (see FIG. 18) is to be formed.

Next, thermal etching is performed on the recess TQ. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms. The at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. This atmosphere is, for example, Cl ₂ , BCL ₃ , SF ₆ , or CF ₄ . For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and a heat treatment temperature of, for example, 700 ° C. or more and 1000 ° C. or less.

Note that the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen (N ₂ ) gas, argon gas, helium gas or the like can be used. When the heat treatment temperature is set to 700 ° C. or higher and 1000 ° C. or lower as described above, the etching rate of silicon carbide is about 70 μm / hour, for example. Further, in this case, the mask layer 40 made of silicon oxide has a very high selectivity with respect to silicon carbide, and therefore is not substantially etched during the etching of silicon carbide.

  Referring to FIG. 14, trench TR is formed on surface 20a formed of source region 83 and contact region 84 by the thermal etching described above. Trench TR has side wall surface SW passing through source region 83 and body region 82 to upper drift region 81b, and bottom surface BT located on upper drift region 81b. Side wall surface SW and bottom surface BT are separated from p-type region 11. Next, the mask layer 40 is removed by an arbitrary method such as etching.

  Referring to FIG. 15, gate oxide film 91 covering each of side wall surface SW and bottom surface BT of trench TR is formed. Gate oxide film 91 can be formed, for example, by thermal oxidation. Thereafter, NO annealing using nitrogen monoxide (NO) gas as the atmospheric gas may be performed. The temperature profile has, for example, conditions of a temperature of 1100 ° C. to 1300 ° C. and a holding time of about 1 hour. Thereby, nitrogen atoms are introduced into the interface region between gate oxide film 91 and body region 82. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved. As long as such nitrogen atoms can be introduced, a gas other than NO gas may be used as the atmospheric gas. Ar annealing using argon (Ar) as an atmospheric gas may be further performed after the NO annealing. The heating temperature for Ar annealing is preferably higher than the heating temperature for NO annealing and lower than the melting point of the gate oxide film 91. The time during which this heating temperature is maintained is, for example, about 1 hour. Thereby, the formation of interface states in the interface region between gate oxide film 91 and body region 82 is further suppressed. Note that other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.

  Referring to FIG. 16, gate electrode 92 is formed on gate oxide film 91. Specifically, gate electrode 92 is formed on gate oxide film 91 so as to fill the region inside trench TR with gate oxide film 91. The gate electrode 92 can be formed, for example, by depositing a conductor or doped polysilicon and then performing CMP (Chemical Mechanical Polishing) from the first main surface 10a side. Gate electrode 92 is formed to face each of source region 83, body region 82, and upper drift region 81b with gate oxide film 91 interposed therebetween.

  Referring to FIG. 17, interlayer insulating film 93 is formed on gate electrode 92 and gate oxide film 91 so as to cover the exposed surface of gate electrode 92. Next, etching is performed so that openings are formed in interlayer insulating film 93 and gate oxide film 91. Through this opening, each of source region 83 and contact region 84 is exposed from each of gate oxide film 91 and interlayer insulating film 93. Using the alignment mark 1 formed so that the first portion 30a of the protective film 30 is in contact with each of the side portion 1a and the bottom portion 1b of the alignment mark 1, a position to be an opening portion of an etching mask (not shown) is formed. An etching mask may be formed by exposure. Next, source electrode 94 in contact with each of source region 83 and contact region 84 on surface 12a is formed.

  Referring to FIG. 18, source wiring layer 95 is formed so as to cover interlayer insulating film 93 and to be in contact with source electrode 94. Drain electrode 98 is formed in contact with second main surface 10b of silicon carbide single crystal substrate 80. As described above, MOSFET 100 as a silicon carbide semiconductor device having silicon carbide layer 103, gate oxide film 91, gate electrode 92, interlayer insulating film 93, source electrode 94, source wiring layer 95, and drain electrode 98. Is completed.

Referring to FIG. 18, each of first epitaxial layer 81a and upper drift region 81b includes an impurity such as nitrogen and has n type conductivity. The first epitaxial layer 81a constitutes a lower drift region. That is, the drift region is constituted by the first epitaxial layer 81a and the upper drift region 81b. The impurity concentration of each of first epitaxial layer 81 a and upper drift region 81 b is preferably lower than the impurity concentration of silicon carbide single crystal substrate 80. The impurity concentration of each of first epitaxial layer 81a and upper drift region 81b is preferably 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁶ cm ⁻³ or less, for example, 8 × 10 ¹⁵ cm ⁻³ .

Body region 82 includes an impurity such as aluminum and has p type conductivity. Body region 82 is provided on upper drift region 81b. The concentration of impurities contained in body region 82 is, for example, 1 × 10 ¹⁸ cm ⁻³ . Source region 83 includes an impurity such as phosphorus and has n-type conductivity. Source region 83 is provided on body region 82 so as to be separated from upper drift region 81 b by body region 82. Source region 83 forms surface 12 a of silicon carbide layer 103 together with contact region 84. Contact region 84 has a p-type. Contact region 84 is connected to body region 82. Silicon carbide layer 103 includes silicon carbide single crystal substrate 80, first epitaxial layer 81 a, and second epitaxial layer 12.

  Trench TR is provided on surface 12a of silicon carbide layer 103. Preferably, surface 12a of silicon carbide layer 103 is a (000-1) plane (that is, a carbon plane), and second main surface 10b is a (0001) plane (that is, a silicon plane). Trench TR has side wall surface SW and bottom surface BT. Side wall surface SW passes through source region 83 and body region 82 and reaches upper drift region 81b. Sidewall surface SW includes a channel surface of MOSFET 100 on body region 82. Sidewall surface SW is inclined with respect to surface 12a of silicon carbide layer 103, whereby trench TR extends in a tapered shape toward the opening. The plane orientation of the side wall surface SW is preferably inclined by 50 ° or more and 65 ° or less with respect to the {0001} plane, and inclined by 50 ° or more and 65 ° or less with respect to the (000-1) plane. More preferred. Thereby, the mobility in a channel surface can be made high.

  The bottom surface BT is located on the upper drift region 81b. In the present embodiment, bottom surface BT has a flat shape substantially parallel to surface 12a. A portion where bottom surface BT and side wall surface SW are connected constitutes a corner portion of trench TR. In the present embodiment, trench TR extends to form a mesh having a honeycomb structure in a plan view (a visual field along the normal direction of first main surface 10a). Thereby, silicon carbide layer 103 has a surface 12a having a hexagonal shape surrounded by trench TR.

P-type region 11 contains an impurity such as aluminum and has p-type conductivity. P type region 11 is provided in silicon carbide substrate 10. P type region 11 is separated from body region 82 by upper drift region 81b. P type region 11 is separated from each of sidewall surface SW and bottom surface BT of trench TR. The value obtained by integrating the impurity concentration per unit volume of the p-type region 11 in the thickness direction (the normal direction of the first main surface 10a) corresponds to the dose amount of ion implantation for forming the p-type region 11. . This dose is preferably 1 × 10 ¹² cm ⁻² or more and 1 × 10 ¹⁵ cm ⁻² or less, for example 1 × 10 ¹³ cm ⁻² .

  Gate oxide film 91 covers each of sidewall surface SW and bottom surface BT of trench TR. The gate electrode 92 is provided on the gate oxide film 91. Source electrode 94 is in contact with each of source region 83 and contact region 84. The source wiring layer 95 is in contact with the source electrode 94. Source wiring layer 95 is, for example, an aluminum layer. The interlayer insulating film 93 insulates between the gate electrode 92 and the source wiring layer 95.

  Although the case where silicon carbide semiconductor device 100 is a trench MOSFET has been described in the above embodiment, silicon carbide semiconductor device 100 may be a planar MOSFET, for example, a Schottky barrier diode or IGBT (Insulated). Gate Bipolar Transistor). In the above embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type is p-type and the second conductivity type is n-type. It may be. Further, in the above-described embodiment, the process for processing the epitaxial layer using the alignment mark includes various processes such as ion implantation mask alignment, gate electrode 92 patterning, source electrode 94 patterning, and wiring patterning. It can be used for the process. The alignment mark 1 is not limited to the alignment mark in the exposure process. The alignment mark 1 may be, for example, an alignment mark used in a defect inspection process, a laser annealing process, or the like.

  Next, the effect of the method for manufacturing MOSFET 100 according to the present embodiment will be described.

  According to the manufacturing method of MOSFET 100 according to the present embodiment, alignment mark 1 is formed in which first portion 30a of protective film 30 covering each of side portion 1a and bottom portion 1b of alignment mark 1 is left. Thereby, when epitaxial layer 12 is formed on main surface 10a of silicon carbide substrate 10, it is possible to suppress step flow growth of silicon carbide on each of side portion 1a and bottom portion 1b of the alignment mark. . Thereby, it can suppress that the alignment mark 1 deform | transforms asymmetrically and alignment accuracy deteriorates. As a result, it is possible to improve alignment accuracy in the process of manufacturing MOSFET 100 having silicon carbide substrate 10 including first main surface 10a having an off angle.

  In addition, according to the method for manufacturing MOSFET 100 according to the present embodiment, the step of processing epitaxial layer 12 includes the step of forming contact region 84 for epitaxial layer 12. Thereby, the alignment accuracy in the process of forming the contact region 84 can be improved.

  Furthermore, according to MOSFET 100 manufacturing method according to the present embodiment, the material forming protective film 30 has a melting point higher than the temperature of silicon carbide substrate 10 in the step of forming epitaxial layer 12. Thereby, in the process of forming the epitaxial layer 12, it can suppress that the element which comprises the protective film 30 mixes into the epitaxial layer 12 because the protective film 30 fuse | melts.

  Furthermore, according to the method of manufacturing MOSFET 100 according to the present embodiment, the material constituting protective film 30 includes tantalum carbide or a carbon material. Thereby, it is possible to suppress the step flow growth of silicon carbide on protective film 30. As a result, it can be suppressed that the alignment mark 1 is deformed asymmetrically and the alignment accuracy is deteriorated.

  Furthermore, according to the method for manufacturing MOSFET 100 according to the present embodiment, the thickness of mask layer 20 is not less than 0.5 μm and not more than 2.0 μm. When the thickness of the mask layer 20 is smaller than 0.5 μm, the first portion 30 a of the protective film 30 is formed up to the upper portion of the side portion 1 a of the alignment mark 1. In this case, the second portion 30b of the protective film 30 in contact with the side surface 20b of the mask layer 20 is connected to the first portion 30a. If the second portion 30b of the protective film 30 is connected to the first portion 30a, the first portion 30a may be removed together with the second portion 30b of the protective film 30 when the mask layer 20 is lifted off. . Since silicon carbide grows in a step flow manner on the side portion 1a of the alignment mark 1 that is not covered by the first portion 30a of the protective film 30, an alignment mark 1 that is asymmetric with respect to the main surface 10a of the silicon carbide substrate 10 is formed. Is done. As a result, alignment accuracy deteriorates. On the other hand, when the thickness of mask layer 20 is larger than 2.0 μm, for example, first portion 30a of protective film 30 is formed only at the lower portion of side portion 1a of alignment mark 1, and the protective film is formed at the upper portion of side portion 1a. 30 first portions 30a are not formed. When the epitaxial layer is formed, silicon carbide grows in a step-flow manner in a region that is not covered by the first portion 30a of the protective film 30 above the side portion 1a of the alignment mark, so that the main surface of the silicon carbide substrate 10 An alignment mark 1 asymmetric with respect to 10a is formed. As a result, alignment accuracy deteriorates. By setting the thickness of the mask layer to 0.5 μm or more and 2.0 μm or less, the protective film 30 can be efficiently formed so as to cover each of the side portion 1 a and the bottom portion 1 b of the alignment mark 1.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 Alignment Mark 1a Side 1b Bottom 10 Silicon Carbide Substrate 10a First Main Surface (Main Surface)
10b Second main surface 11 p-type region 12 Second epitaxial layer (epitaxial layer)
12a, 20a Surface 20, 40 Mask layer 20b Opening (side surface)
30 Protective films 30a1, 30a2 Upper end 30a First portion 30b Second portion 30c Material 80 Silicon carbide single crystal substrate 81a First epitaxial layer (lower drift region)
81b Upper drift region 82 Body region 83 Source region 84 Impurity region 84 Contact region 91 Gate oxide film 92 Gate electrode 93 Interlayer insulating film 94 Source electrode 95 Source wiring layer 98 Drain electrode 100 Silicon carbide semiconductor device (MOSFET)
101 Element formation region 102 Alignment mark formation region 103 Silicon carbide layer BT Bottom surface OF Orientation flat part SW Side wall surface TQ Concave part TR Trench a1 Direction x1, x2 Width z Normal vector

Claims (5)

Preparing a silicon carbide substrate including a main surface having an off angle with respect to the {0001} plane;
Forming a mask layer on the main surface of the silicon carbide substrate;
Forming a concave alignment mark comprising a side portion connected to the main surface and a bottom portion connected to the side portion on the main surface of the silicon carbide substrate using the mask layer;
Forming a protective film so as to cover the surface of the mask layer, each of the side portion and the bottom portion of the alignment mark;
Removing the second part of the protective film covering the surface of the mask layer together with the mask layer while leaving the first part of the protective film covering each of the side part and the bottom part of the alignment mark When,
Forming an epitaxial layer on the main surface of the silicon carbide substrate after removing the mask layer;
Forming an implantation mask using the alignment mark on which the protective film is formed after removing the mask layer and before the step of forming the epitaxial layer;
And a step of processing the epitaxial layer using the alignment mark.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of performing a process on the epitaxial layer includes a step of forming an impurity region in the epitaxial layer.   3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the material constituting the protective film has a melting point higher than the temperature of the silicon carbide substrate in the step of forming the epitaxial layer.   The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein the material constituting the protective film includes tantalum carbide or a carbon material.   The thickness of the said mask layer is a manufacturing method of the silicon carbide semiconductor device of any one of Claims 1-4 which are 0.5 micrometer or more and 2.0 micrometers or less.

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