JP7031148B2 - Manufacturing method of silicon carbide semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a silicon carbide semiconductor device.

Conventionally, in a power semiconductor device, a vertical MOSFET (Metal Exied Semiconductor Field Effect Transistor) having a trench structure has been manufactured (manufactured) in order to reduce the on-resistance of the device. In a vertical MOSFET, a trench structure in which channels are formed perpendicular to the substrate surface can increase the cell density per unit area rather than a planar structure in which channels are formed parallel to the substrate surface. The current density per area can be increased, which is advantageous in terms of cost.

In addition, as silicon carbide semiconductor devices, to date, Schottky barrier diodes (SBDs), vertical MOSFETs with planar gate structures and trench gate structures (Metal Oxide Semiconductor Field Effect Transistors: isolated gate type field effect transistors) have been used. ) Has been commercialized.

The trench gate structure is a portion along the side wall of the trench in which a MOS gate (insulated gate made of metal-oxide film-semiconductor) is embedded in a trench formed in a semiconductor substrate made of silicon carbide (hereinafter referred to as a silicon carbide substrate). It is a three-dimensional structure using as a channel (reversal layer). Therefore, when comparing elements with the same on-resistance (Ron), the trench gate structure has an overwhelmingly larger element area (chip area) than the planar gate structure in which a MOS gate is provided in a flat plate shape on a silicon carbide substrate. It can be made smaller and can be said to be a promising device structure in the future.

The structure of a conventional silicon carbide semiconductor device will be described by taking a vertical MOSFET having a trench gate structure as an example. FIG. 19 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device shown in FIG. 19 includes a MOS gate having a general trench gate structure on the front surface (the surface on the p-type epitaxial layer 6 side) of the semiconductor substrate made of silicon carbide. The silicon carbide substrate (semiconductor chip) is an n ^- type epitaxial layer 2 and a p-type epitaxial layer 6 on an n ⁺ type support substrate (hereinafter referred to as an n ⁺ type silicon carbide substrate) 1 made of silicon carbide. The layers are epitaxially grown in sequence. Reference numerals 7, 9 to 11, 13 and 15 are n ⁺⁺ type source regions, gate insulating films, gate electrodes, interlayer insulating films, source electrodes and drain electrodes, respectively.

Further, a semiconductor device having a SON (Silicon On Nothing) structure having a cavity inside is known. For example, a semiconductor device in which an upper silicon layer constituting a SON structure becomes a diaphragm including a resistor constituting a Wheatstone bridge of a pressure sensor and an IC circuit or the like is formed around the diaphragm is known (see, for example, Patent Document 1). .. Further, it is a semiconductor device in which a semiconductor element is formed in a region divided by an element separation insulating film on the surface of a semiconductor substrate, and the inside of the substrate in the region divided by the element separation insulating film has a substantially constant depth from the surface. A semiconductor device in which a flat cavity is formed is known (see, for example, Patent Document 2).

Japanese Unexamined Patent Publication No. 2014-120729 Japanese Unexamined Patent Publication No. 2003-332540

Here, as the n ⁺ type silicon carbide substrate 1, silicon carbide (4H—SiC) having a four-layer period hexagonal crystal is used. When a silicon carbide semiconductor device is formed on a 4H-SiC substrate, it is usually formed on a substrate having a thickness of 350 μm to 400 μm. In a vertical device (for example, a trench MOSFET), a current flows in the direction of arrow A in FIG. Therefore, the thickness of the 4H-SiC substrate is a cause of increasing the resistance occupying the whole.

Since the element performance can be improved by reducing the resistance of the substrate, a technique is used in which the substrate is ground from the back surface by polishing or the like to make the substrate thinner to reduce the resistance of the substrate. However, there is a limit in strength even if it is made thinner, and there is a limit in the amount that can be ground, which increases the possibility of substrate damage and makes it difficult to handle in the manufacturing process.

The present invention manufactures a silicon carbide semiconductor device capable of improving device performance by thinning a silicon carbide semiconductor substrate without scraping the back surface of the silicon carbide semiconductor substrate in order to solve the problems caused by the above-mentioned prior art. The purpose is to provide a method.

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, the first step of forming a silicon carbide semiconductor substrate having a plurality of cavities inside is performed. Next, the second step of forming the silicon carbide semiconductor element on the silicon carbide semiconductor substrate is performed. Next, a third step of cutting out the silicon carbide semiconductor element from the silicon carbide semiconductor substrate is performed. The first step is a step of connecting a plurality of trenches formed from one main surface side of the silicon carbide semiconductor substrate to form a cavity, and the longitudinal direction of the plurality of trenches is the silicon carbide semiconductor. One of the silicon carbide semiconductor substrates has a plurality of trenches deviated from the crystal axis direction <11-20> of the substrate by a predetermined angle or more based on the accuracy of guaranteeing the formation of the orientation flat provided on the silicon carbide semiconductor substrate. One of the silicon carbide semiconductor substrates is formed by heat treatment in a gas atmosphere containing a gas having an etching effect and a gas as a raw material for a silicon carbide film after the eleventh step of forming from the main surface side. A twelfth step of forming the silicon carbide film on the main surface side of the semiconductor and forming the cavity by etching the side walls of a plurality of the trenches. In the eleventh step, the trench is formed in a striped shape, and the longitudinal direction of the trench is formed in a direction included in a range deviated by ± 5 degrees or more from the m plane.

Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the second step, the carbide is formed on the cavity so that the area of the silicon carbide semiconductor element is smaller than the area of the cavity. It is characterized by forming a silicon semiconductor element.

Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, in the third step, the cut surface for cutting the silicon carbide semiconductor substrate passes through the cavity.

Further, in the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, the width of the cavity in the direction parallel to the silicon carbide semiconductor substrate is 10 μm or more and 5 mm or less, and the height of the cavity is 1. It is characterized in that it is 1 μm or more and 20 μm or less, and the depth of the cavity in the direction orthogonal to the width and the height is 10 μm or more and 5 mm or less.

Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, a fourth step of forming a back surface electrode on the cut-out silicon carbide semiconductor element is further included after the third step. do.

Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the back surface electrode is formed on the surface of the silicon carbide semiconductor substrate in contact with the cavity in the fourth step.

According to the above-mentioned invention, the silicon carbide semiconductor device is manufactured on the silicon carbide substrate having a cavity. This makes it possible to manufacture a silicon carbide semiconductor device having a thinner thickness than when the silicon carbide substrate is scraped from the back surface and used as a thin wafer. Therefore, the resistance of the silicon carbide element can be reduced, and the on-resistance of the silicon carbide semiconductor device can be reduced.

Further, in the manufacturing process of the silicon carbide semiconductor device, the silicon carbide substrate has a sufficient thickness, the strength of the silicon carbide substrate is secured, there is little concern about damage, and the wafer can be easily handled. Therefore, no special equipment for thin wafers is required, and the cost does not increase.

According to the method for manufacturing a silicon carbide semiconductor device according to the present invention, there is an effect that the silicon carbide semiconductor substrate can be thinned and the device performance can be improved without scraping the back surface of the silicon carbide semiconductor substrate.

It is sectional drawing which shows the structure of the silicon carbide semiconductor substrate used for manufacturing the silicon carbide semiconductor device which concerns on embodiment. It is explanatory drawing which shows the state example (the 1) of the main part in the manufacturing process of the silicon carbide substrate which concerns on embodiment. It is explanatory drawing which shows the state example (the 2) of the main part in the manufacturing process of the silicon carbide substrate which concerns on embodiment. It is explanatory drawing which shows the state example (the 3) of the main part in the manufacturing process of the silicon carbide substrate which concerns on embodiment. It is explanatory drawing which shows the state example (the 4) of the main part in the manufacturing process of the silicon carbide substrate which concerns on embodiment. It is explanatory drawing which shows the example of the formation direction of the trench which concerns on this embodiment. It is explanatory drawing which shows the state example (the 5) of the main part in the manufacturing process of the silicon carbide substrate which concerns on embodiment. It is explanatory drawing which shows the state example (the 6) of the main part in the manufacturing process of the silicon carbide substrate which concerns on embodiment. It is explanatory drawing which shows the state example (the 7) of the main part in the manufacturing process of the silicon carbide substrate which concerns on embodiment. It is a top view which shows the state example (the 8) of the main part in the manufacturing process of the silicon carbide substrate which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 1). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 2). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 3). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 4). It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 5). It is sectional drawing which shows the cut surface of the silicon carbide semiconductor device which concerns on embodiment. It is a top view which shows the cut surface of the silicon carbide semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the silicon carbide semiconductor device which concerns on embodiment (the 6). It is sectional drawing which shows the structure of the conventional silicon carbide semiconductor device.

Hereinafter, preferred embodiments of the method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electron or hole is a large number of carriers in the layer or region marked with n or p, respectively. Further, + and-attached to n and p mean that the concentration of impurities is higher and the concentration of impurities is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted. In the present specification and the accompanying drawings, in the notation of the Miller index, "-" means a bar attached to the index immediately after that, and "-" is added in front of the index to indicate a negative index. There is.

(Embodiment)
The semiconductor device according to the present invention is configured by using a semiconductor having a bandgap wider than that of silicon (hereinafter referred to as a wide bandgap semiconductor). Here, a structure of a semiconductor device (silicon carbide semiconductor device) using, for example, silicon carbide (SiC) as the wide bandgap semiconductor will be described as an example.

FIG. 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor substrate used for manufacturing the silicon carbide semiconductor device according to the embodiment. The silicon carbide substrate (semiconductor wafer) 30 is an epitaxial growth substrate obtained by epitaxially growing an n ^- type epitaxial layer 2 made of silicon carbide on one main surface of an n ⁺ type silicon carbide substrate 1. Further, the n ⁺ type silicon carbide substrate (first conductive type silicon carbide substrate) 1 is made of single crystal silicon carbide such as 4H—SiC.

Inside the n ^- type epitaxial layer 2 is long in the direction parallel to the surface of the silicon carbide substrate 30 (the surface on the side of the n ^- type epitaxial layer 2 or the surface on the side of the n ⁺ type silicon carbide substrate 1). A plurality of cavities 20 having silicon are provided. The cross-sectional shape of the cavity 20 is a substantially flat plate shape. In the example of FIG. 1, the cavity 20 is provided inside the n ^- type epitaxial layer 2, but the cavity 20 is provided inside across the boundary between the n ^- type epitaxial layer 2 and the n ⁺ type silicon carbide substrate 1. May be. The cavity 20 is in a state where a small amount of decompressed hydrogen (H ₂ ) gas is contained, and the relative permittivity of the cavity 20 is approximately 1. The size of the cavity 20 is larger than that of the silicon carbide semiconductor device described later. The lateral width x of the cavity 20 is, for example, 10 μm or more and 5 mm or less, and the height y of the cavity 20 in the direction perpendicular to the surface of the silicon carbide substrate 30 is, for example, 1 μm or more and 20 μm or less. The depth in the direction orthogonal to y is, for example, 10 μm or more and 5 mm or less.

Next, a method for manufacturing the silicon carbide semiconductor device according to the embodiment will be described. 2 to 5 and 7 to 10 are explanatory views showing an example of a state of a main part in the middle of manufacturing the silicon carbide substrate according to the embodiment. 11 to 14 are cross-sectional views showing a state in the middle of manufacturing the silicon carbide semiconductor device according to the embodiment. First, the silicon carbide substrate 30 having the cavity 20 inside as shown in FIG. 1 is formed. For example, the silicon carbide substrate 30 of FIG. 1 is formed based on the following reference 1 of the application filed by the applicant of the present application.

(Reference 1) Japanese Patent Application No. 2016-170353

For example, it is formed as follows. FIG. 2 is an explanatory diagram showing an example of a state (No. 1) of a main part in the middle of manufacturing the silicon carbide substrate 30 according to the embodiment. First, the silicon carbide substrate 1 is washed. Examples of the cleaning include organic cleaning and RCA (wet cleaning using a strong acid and a high base solution) cleaning.

Next, the front surface (Si surface) or the back surface (C surface) of the semiconductor substrate 1 is doped with, for example, nitrogen (N) at a predetermined concentration to form an n ^- type epitaxial layer 2. The thickness d1 of the n ^- type epitaxial layer 2, the doping concentration, and the doping carrier may be appropriately determined according to the intended use of the silicon carbide substrate 30, and are not particularly limited. Here, the thickness d1 is, for example, 25 μm.

FIG. 3 is an explanatory diagram showing an example of a state (No. 2) of a main part in the middle of manufacturing the silicon carbide substrate 30 according to the embodiment. After forming the n ^- type epitaxial layer 2, the silicon carbide substrate 30 is washed. Next, a silicon dioxide (SiO ₂ ) film 31 is formed on the surface of the n ^- type epitaxial layer 2 of the silicon carbide substrate 30 (the surface opposite to the n ⁺ type silicon carbide substrate 1 side). Examples of the film forming method include plasma chemical vapor deposition (abbreviated as CVD) and the like. The SiO ₂ film 31 is used as a mask for a dry etching pattern when forming a trench in a later step. Therefore, the thickness d2 of the SiO ₂ film 31 is a thickness that is not lost by dry etching.

FIG. 4 is an explanatory diagram showing an example of a state (No. 3) of a main part in the middle of manufacturing the silicon carbide substrate 30 according to the embodiment. Next, after forming the SiO ₂ film 31, the photoresist 32 is applied to the surface of the SiO ₂ film 31 (the surface opposite to the n ^- type epitaxial layer 2 side).

FIG. 5 is an explanatory diagram showing an example of a state (No. 4) of a main part in the middle of manufacturing the silicon carbide substrate 30 according to the embodiment. Next, after applying the photoresist 32, it is exposed with a photomask to pattern a trench pattern. In the trench pattern of the photomask, the width L (line width) in the lateral direction of the trench is a length in the range of 2.5 μm or more and 5 μm or less, and the trench spacing S is a length in the range of 1 μm or more and 3 μm or less. That's right. When the trench pattern is patterned by exposure with the photoresist 32, the mask pattern is matched based on the first orientation flat. The shape of the trench here is a linear planar shape extending in the crystal axis direction. Next, the formation direction of the trench will be described with reference to FIG.

FIG. 6 is an explanatory diagram showing an example of a trench forming direction according to the present embodiment. FIG. 6 shows an example in which the front surface (0001) or the back surface (000-1) of the silicon carbide substrate 1 is viewed from above. As described above, the crystal axis direction indicated by the first orientation flat is [11-20].

FIG. 6 shows the crystal axis direction [1-100], the crystal axis direction [-1-120], and the crystal axis direction [-1100] in addition to the crystal axis direction [11-20]. The crystal axis direction [11-20] is represented by an arrow pointing to the right in FIG. The crystal axis direction [-1-120] is represented by an arrow pointing to the left in FIG. The crystal axis direction [1-100] is represented by a downward arrow in FIG. The crystal axis direction [-1100] is represented by an upward arrow in FIG. The crystal axis direction [11-20] is opposite to the crystal axis direction [-1-120]. Further, the crystal axis direction [11-20] is orthogonal to the crystal axis direction [1-100] and the crystal axis direction [-1100]. The crystal axis direction [1-100] is opposite to the crystal axis direction [-1100]. Further, the crystal axis direction [1-100] is orthogonal to the crystal axis direction [-1-120] and the crystal axis direction [11-20].

In FIG. 6, the solid line indicates the trench 33. A plurality of trenches 33 are formed in the rectangular region 34 of the silicon carbide substrate 1. The size of the region 34 is a size that can be exposed based on the stepper. One cavity 20 (not shown) is formed in the rectangular region 34 by a plurality of trenches 33 formed in the region 34 and adjacent to each other at predetermined intervals. Since the cavity 20 can be formed for each region 34, a plurality of cavities 20 can be formed at the same time.

Further, the formation direction of the trench 33, which is the longitudinal direction of the trench 33, is a direction deviated by a predetermined angle θ or more from the crystal axis direction <11-20>. For example, the formation direction of the trench 33 is a direction deviated by a predetermined angle θ or more from the crystal axis direction [11-20] to the crystal axis direction [-1100] or the crystal axis direction [1-100]. In other words, the formation direction of the trench 33 is included in the range from the crystal axis direction [11-20] to the direction rotated by a predetermined angle θ in the crystal axis direction [-1100] and the crystal axis direction [1-100], respectively. It is a direction that cannot be done.

Here, the predetermined angle θ is determined based on the accuracy of guaranteeing the formation of the first orientation flat of the silicon carbide substrate 1. For example, when the accuracy of guaranteeing the formation of the first tilter is within 1 degree, the predetermined angle θ is set to 5 degrees. When the accuracy of guaranteeing the formation of the first tilter is within 5 degrees, the predetermined angle θ is set to 9 degrees. In the present embodiment, the accuracy of guaranteeing the formation of the first orientation flat is set to 1 degree or less, and the predetermined angle θ is set to 5 degrees.

Further, the forming direction of the trench 33 is a direction in which the side wall of the trench 33 does not become the m-plane, and is included in a range deviated by ± 5 degrees or more from the m-plane. Here, the m-plane is the crystal plane {10-10} of the silicon carbide substrate. The crystal planes {10-10} are six planes of (1-100), (0-110), (-1010), (-1100), (01-10), and (10-10). The plane perpendicular to the crystal axis direction <11-20> is the m plane. In other words, the plane perpendicular to the crystal axis direction [11-20] and the plane perpendicular to the line shifted every 60 degrees from the crystal axis direction [11-20] are the m-planes. The line shifted every 60 degrees from the crystal axis direction [11-20] is the first broken line shown in FIG. The range within ± 5 degrees from the first broken line is represented by the second broken line. As a result, the side wall of the trench 33 is etched when the silicon carbide film is formed due to the deviation between the m-plane and the formation direction of the trench 33, and the silicon carbide film grows diagonally near the opening of the trench. However, a substantially flat plate-shaped cavity is obtained.

Here, in the n ⁺ type silicon carbide substrate 1, there are crystal planes such as the m-plane that can stably grow crystals, and crystal planes that cannot stably grow crystals. .. The forming direction of the trench 33 formed in the area surrounded by the circle is a direction included in a range within 5 degrees from the m-plane. The side wall of the trench 33 formed in the area surrounded by the circle is substantially m-plane. Since crystals are stably grown on the side wall of the trench 33 formed in the region surrounded by the circles when the SiC film is formed, the side wall of the trench 33 is less likely to be etched. If the side wall of the trench is not easily etched, it is difficult to connect the trenches, and it is difficult to form the cavity 20. On the other hand, when the formation direction of the trench 33 is a direction not included in the range represented by the m-plane and the second broken line, or a direction included in the range represented by the m-plane and the second broken line. In comparison, Si atoms and C atoms are more likely to move on the side wall of the trench 33. Therefore, the side wall of the trench 33 is easily etched, the trenches can be connected to each other, and the cavity 20 can be formed.

FIG. 7 is an explanatory diagram showing an example of a state (No. 5) of a main part in the middle of manufacturing the silicon carbide substrate 30 according to the embodiment. After turning the photoresist 32, the SiO ₂ film 31 is dry-etched using the photoresist 32 as a mask. Examples of the dry etching include anisotropic etching such as reactive ion etching (RIE). Here, dry etching is performed until the n ⁺ type silicon carbide substrate 1 or the n ⁻ type epitaxial layer 2 is exposed. In the example of FIG. 7, dry etching is performed until the n ^- type epitaxial layer 2 is exposed, and a trench pattern is formed on the SiO ₂ film 31.

FIG. 8 is an explanatory diagram showing an example of a state (No. 6) of a main part in the middle of manufacturing the silicon carbide substrate 30 according to the embodiment. The photoresist 32 is peeled off. Then, using the SiO ₂ film 31 in which the mask pattern is patterned as a mask, the n ^- type epitaxial layer 2 or the n ^- type epitaxial layer 2 and the n ⁺ type silicon carbide substrate 1 are dry-etched to a predetermined depth d3 and trenched. Form 33. The predetermined depth d3 here is 20 μm or more. FIG. 8 shows an example in which a trench 33 having a depth d3 of 20 μm is formed in an n ^- type epitaxial layer 2 having a depth d1 of 25 μm. Although not shown, when the depth d1 of the n ^- type epitaxial layer 2 is 25 μm and the depth d3 of the trench 33 is 25 μm or more, the trench 33 is the n ^- type epitaxial layer 2 and n ^+. It is formed so as to straddle the boundary with the type silicon carbide substrate 1.

FIG. 9 is an explanatory diagram showing an example of a state (No. 7) of a main part in the middle of manufacturing the silicon carbide substrate 30 according to the embodiment. After forming the trench 33, the SiO ₂ film 31 is peeled off with a hydrogen fluoride (HF) solution or the like. Then, after the SiO ₂ film 31 is peeled off, the silicon carbide substrate 30 is washed. As a result, the trench 33 in which the crystal axis [11-20] of the n ⁺ type silicon carbide substrate 1 and the formation direction of the trench 33 deviate by ± 5 degrees or more, and the m-plane and the formation direction of the trench 33 deviate by ± 5 degrees or more. The formed silicon carbide substrate 30 is obtained.

FIG. 10 is a plan view showing a state example (No. 8) of a main part in the middle of manufacturing the silicon carbide substrate 30 according to the embodiment. It is explanatory drawing which shows the plan view of the example of the growth direction of a crystal at the time of the SiC film formation. The cross-sectional view taken along the cutting line AA'shown in FIG. 10 corresponds to the cross-sectional view shown in FIG. The crystal axis direction [-1100] is represented by an upward arrow in FIG. Further, the crystal axis direction [11-20] is represented by an arrow in the right direction in FIG. The formation direction of the trench 33 shown in FIG. 10 is a direction parallel to the crystal axis direction [-1100].

Next, the silicon carbide substrate 30 is subjected to SiC by heat treatment in a gas atmosphere containing a gas having an etching effect, a gas containing Si which is a raw material for forming a SiC film, and a gas containing carbon (C). A film is formed. For the heat treatment, the halide CVD method is used.

For example, after cleaning the silicon carbide substrate 30, the silicon carbide substrate 30 is placed in a CVD device capable of growing a SiC film. Then, a gas having an etching effect, a gas containing Si which is a raw material for forming a SiC film, and a gas containing C are simultaneously introduced to form a film under predetermined film forming conditions by a CVD apparatus.

Examples of the gas having an etching effect include hydrogen chloride (HCl) gas and chlorine (Cl ₂ ) gas. Examples of the gas containing Si include monosilane (SiH ₄ ) gas. Examples of the gas containing C include propane (C ₃ H ₈ ) gas. The film forming conditions are, for example, conditions such that the amount of SiC deposited> the amount of etching of SiC is satisfied. The amount of SiC deposited is the lateral thickness of the SiC film formed from the side wall of the trench 33 in the direction perpendicular to the side wall (lateral direction) per unit time. The etching amount of SiC is the lateral length in which the side wall of the trench 33 is etched per unit time.

Further, when the amount of gas having an etching effect is small, the thickness of the SiC film deposited on the surface of the silicon carbide substrate 30 (the surface on the side of the n ^- type epixical film 2) becomes thick, and at the same time, the side wall of the trench 33 becomes thick. The amount of etching is reduced, and the voids formed in each trench 33 are less likely to be connected to each other. Therefore, the gas amount of the gas having the etching effect is set to the maximum amount among the gas amounts such that the accumulated amount of SiC is slightly larger than the etching amount of SiC. As a result, the opening of the trench 33 can be closed, and the voids generated in the trench 33 can be connected to each other.

Further, in addition to the gas that is a raw material for forming the SiC film and the gas that has an etching effect, a gas that is a dopant may be introduced at the same time. When forming an n-type SiC film, examples of the gas serving as a dopant include nitrogen (N ₂ ) gas. When forming a p-type SiC film, examples of the gas serving as a dopant include trimethylaluminum (TMA) gas.

Here, in order to form a SiC film, hydrogen (H ₂ ) gas is used as the carrier gas, Si H ₄ gas and C ₃ H ₈ gas are used as raw materials for forming the SiC film, and a gas having an etching effect. As an HCl gas and as a gas as a dopant, TMA is introduced. The temperature of the heat treatment by CVD is preferably in the range of 1635 degrees or more and 1665 degrees or less. Further, the heat treatment time by CVD is preferably in the range of 5 hours or more and 7 hours or less. The thickness of the SiC film that closes the cavity 20 can be adjusted by the time of the heat treatment by CVD.

Here, the temperature of the heat treatment by CVD is set to 1650 degrees, and the SiC film is grown on the silicon carbide substrate 30 for 6 hours by the CVD apparatus. The flow rate of SiH ₄ gas is, for example, 36 sccm (standard cubic centimeter per minute). The flow rate of the C ₃ H ₈ gas is, for example, 12 sccm. The flow rate of HCl gas is, for example, 6 sccm. In this way, the side wall of the trench 33 is scooped out by the gas having an etching effect, the voids are connected, and the cavity 20 is formed inside the silicon carbide substrate 30.

In the embodiment, the silicon carbide semiconductor element is formed so that the silicon carbide semiconductor element fits in the region S1 above the cavity 20. Therefore, the area of the silicon carbide semiconductor element is smaller than the area of the cavity 20. 11 to 15 and 18 show the state of the silicon carbide semiconductor device formed in the region S1 in the middle of manufacturing, which corresponds to the region S2 in FIG. In the present specification, the semiconductor structure formed on the silicon carbide substrate 30 is referred to as a silicon carbide semiconductor element, and a silicon carbide semiconductor device obtained by dividing a silicon carbide semiconductor element from the silicon carbide substrate 30 to form an electrode or the like. It is called.

Next, the surface of the silicon carbide substrate 30 is polished. For example, rough polishing and CMP (Chemical Mechanical Polishing) polishing are performed. The amount to be polished shall be less than or equal to the amount such that the required thickness of the deposited n ^- type epitaxial layer 2 remains. During polishing, it is desirable to minimize the load during polishing and slowly polish so that the pillar 21 supporting the cavity 20 is not damaged. The pillar 21 is a portion provided between the cavity 20 and the cavity 20 in the n ^- type epitaxial layer 2. It is preferable that the pillar 21 is provided for each cavity 20 in both the lateral direction and the depth direction (see FIG. 17 described later), but the pillar 21 is provided for each cavity 20 only in the lateral direction, or is provided for each cavity 20 only in the depth direction. You may be able to do it.

Next, the silicon carbide substrate 30 is washed. For example, organic cleaning and RCA cleaning are performed. Next, the n ^- type epitaxial layer 2 is epitaxially grown to an amount required for the configuration (thickness, concentration, doping material) of the silicon carbide semiconductor device.

Next, the first n ⁺ type drift region 5a is epitaxially grown on the n ⁻ type epitaxial layer 2. The first n ⁺ type drift region 5a is a part of the n ⁺ type drift region 5. Next, the p ⁺ type region 3 and the lower p ⁺ type base region 4a are selectively formed on the surface layer of the first n ⁺ type drift region 5a by photolithography and ion implantation of p-type impurities. This lower p ⁺ type base region 4a is a part of the p ⁺ type base region 4. The state up to this point is shown in FIG.

Next, the second n ⁺ type drift region 5b is epitaxially grown on the first n ⁺ type drift region 5a, the p ⁺ type region 3 and the lower p ⁺ type base region 4a. The second n ⁺ type drift region 5b is a part of the n ⁺ type drift region 5, and the first n ⁺ type drift region 5a and the second n ⁺ type drift region 5b are combined to form the n ⁺ type drift region 5. Next, the upper p ⁺ type base region 4b is selectively formed on the surface layer of the second n ⁺ type drift region 5b by photolithography and ion implantation of p-type impurities. This upper p ⁺ type base region 4b is a part of the p ⁺ type base region 4, and the lower p ⁺ type base region 4a and the upper p ⁺ type base region 4b are combined to form the p ⁺ type base region 4. .. The state up to this point is shown in FIG.

Next, the p-type epitaxial layer (second conductive type silicon carbide layer) 6 is epitaxially grown on the second n ⁺ type drift region 5b and the upper p ⁺ type base region 4b. Next, the n ⁺⁺ type source region 7 is selectively formed on the surface layer of the p-type epitaxial layer 6 by photolithography and ion implantation of n-type impurities. Next, the p ⁺⁺ type contact region 8 is selectively formed on the surface layer of the p-type epitaxial layer 6 by photolithography and ion implantation of the p-type impurity so as to be in contact with the n ⁺⁺ type source region 7. The formation order of the n ⁺⁺ type source region 7 and the p ⁺⁺ type contact region 8 may be exchanged. After all the ion implantation is completed, activation annealing is performed. The state up to this point is shown in FIG.

Next, photolithography and etching are used to form a trench gate 18 that penetrates the n ⁺⁺ type source region 7 and the p-type epitaxial layer 6 and reaches the p ⁺ type region 3 inside the n ⁺ type drift region 5. An oxide film is used as a mask when forming a trench. Further, after the trench etching, isotropic etching for removing damage to the trench gate 18 and hydrogen annealing for rounding the corners of the bottom of the trench gate 18 and the opening of the trench gate 18 may be performed. Only one of isotropic etching and hydrogen annealing may be performed. Further, hydrogen annealing may be performed after performing isotropic etching. The state up to this point is shown in FIG.

Next, the gate insulating film 9 is formed along the front surface of the silicon carbide substrate 30 and the inner wall of the trench gate 18. Next, for example, polysilicon is deposited and etched so as to be embedded in the trench gate 18, so that the polysilicon to be the gate electrode 10 is left inside the trench gate 18. At that time, the polysilicon may be etched back so as to remain inside the surface of the substrate, or the polysilicon may be projected outward from the surface of the substrate by performing patterning and etching.

Next, the interlayer insulating film 11 is formed on the entire front surface of the silicon carbide substrate 30 so as to cover the gate electrode 10. The interlayer insulating film 11 is, for example, NSG (None-topped Silicate Glass), PSG (Phospho Silicate Glass), BPSG (Boro Phospho Silicate Glass), HTO (High Temperature), or a combination of HTO (High Temperature). The glass. Next, the interlayer insulating film 11 and the gate insulating film 9 are patterned to form a contact hole, and the n ⁺⁺ type source region 7 and the p ⁺⁺ type contact region 8 are exposed.

Next, the barrier metal 12 is formed and patterned so as to cover the interlayer insulating film 11, and the n ⁺⁺ type source region 7 and the p ⁺⁺ type contact region 8 are exposed again. Next, the source electrode 13 is formed so as to be in contact with the n ⁺⁺ type source region 7. The source electrode 13 may be formed so as to cover the barrier metal 12 or may be left only in the contact hole. The state up to this point is shown in FIG.

Next, in order to protect the silicon carbide semiconductor element formed on the silicon carbide substrate 30, a resist is applied on the source electrode 13. The resist has a film thickness of, for example, 2 μm or less. Next, the silicon carbide semiconductor element is divided (diced). For example, the element is divided by stealth dicing technology. Stealth dicing is a method of concentrating laser light with a transmissive wavelength on a semiconductor wafer so as to focus on the inside of the semiconductor wafer, scanning along the cutting line, and creating a modified region in the area where the laser processing has been performed. This is a method of dividing a semiconductor wafer from the inside by forming and generating cracks vertically perpendicular to the front and back surfaces starting from a modified region.

Here, FIG. 16 is a cross-sectional view showing a cut surface of the silicon carbide semiconductor device according to the embodiment. FIG. 17 is a top view showing a cut surface of the silicon carbide semiconductor device according to the embodiment. The cut surface D is a surface for cutting the semiconductor wafer during dicing, and as shown in FIG. 16, the cut surface D passes through the cavity 20. Further, as shown in FIG. 17, the cut surface D passes through the cavity 20 and does not pass through the silicon carbide semiconductor element 22. That is, in dicing, the pillar 21 supporting the cavity 20 and the outermost peripheral portion of the silicon carbide semiconductor element 20 are cut.

By setting such a cut surface D, the n ^- type epitaxial layer 2 does not remain on the divided silicon carbide semiconductor element 22, and the back surface of the silicon carbide semiconductor element 22 becomes substantially flat. Further, since the cavity 20 is below the silicon carbide semiconductor element 22 (in one direction of the n ⁺ type silicon carbide substrate) and the n ^- type epitaxial layer 2 is above the cavity 20, the thickness and the required carrier concentration can be arbitrarily set. can. Therefore, the thickness of the silicon carbide semiconductor element 22 can be reduced, and the electric resistance can be reduced. For example, the thickness of the silicon carbide semiconductor element 22 can be set to 30 to 120 μm.

Further, since the end of the cavity 20 has a rounded shape, it is preferable that the cut surface D is inside the end of the cavity 20 (on the silicon carbide semiconductor element 22 side). For example, the cut surface D is preferably 2 to 300 μm away from the end of the cavity 20.

Further, when cutting the silicon carbide semiconductor element 22, the silicon carbide semiconductor element 22 can be cut out from the wafer in the order shown in FIG. Specifically, dicing is performed along the cut surface D in the order of (1) and (2), and then dicing is performed along the cut surface D in the order of (3) to (10). Thereby, the silicon carbide semiconductor element 22 can be cut out in the order of C1, C2, C3, C4. Next, dicing is performed along the cut surface D in the order of (11) and (12), and the subsequent dicing is performed in the same manner.

Further, the back surface of the cut out silicon carbide semiconductor element 22 does not have to be polished. Some unevenness of the n ^- type epitaxial layer 2 when the cavity 20 is formed remains on the back surface of the silicon carbide semiconductor element 22, but the unevenness expands the adhesion and contact area with the drain electrode 15 formed below, and carbonizes the silicon carbide semiconductor element 22. The resistance of silicon semiconductor devices is reduced.

Next, the resist that protected the surface of the silicon carbide semiconductor element 22 is peeled off. Next, the cut out silicon carbide semiconductor elements 22 are arranged on a tray so that the back surface faces up, and a metal mask that covers the end of the chip is set and fixed. The metal mask prevents the film formed below from adhering to the end portion of the silicon carbide semiconductor element 22, and prevents the film from wrapping around to the side surface of the silicon carbide semiconductor element 22.

Next, a metal film such as a nickel (Ni) film or a titanium (Ti) film is formed on the contact portion of the drain electrode 15 by sputter vapor deposition or the like. This metal film may be laminated by combining a plurality of Ni films and Ti films. Then, annealing such as high-speed heat treatment (RTA: Rapid Thermal Annealing) is performed so that the metal film is silicated to form ohmic contacts. Then, for example, a thick film such as a laminated film in which a Ti film, a Ni film, and gold (Au) are laminated in this order is formed by electron beam (EB: Electron Beam) vapor deposition or the like to form a drain electrode 15.

Next, arrange the cut out silicon carbide semiconductor elements 22 on the tray so that the front surface faces up, set and fix a metal mask that covers the end of the chip, and fix the source so as to embed the contact holes. The electrode pad 14 is formed. A part of the metal layer deposited to form the source electrode pad 14 may be used as a gate pad.

In the above-mentioned epitaxial growth and ion implantation, examples of n-type impurities (n-type dopants) include nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb), which are n-type with respect to silicon carbide. Should be used. As the p-type impurity (p-type dopant), for example, boron (B), aluminum (Al), gallium (Ga), indium (In), thallium (Tl), etc., which are p-type with respect to silicon carbide, may be used. .. In this way, the MOSFET shown in FIG. 18 is completed.

In the above-described embodiment, one silicon carbide semiconductor element 22 is formed on the cavity 20, but a plurality of silicon carbide semiconductor elements 22 may be formed on the cavity 20. In this case, the width x and depth of the cavity 20 are increased.

As described above, according to the embodiment, the silicon carbide semiconductor device is manufactured on the silicon carbide substrate having a cavity. This makes it possible to manufacture a silicon carbide semiconductor device having a thinner thickness than when the silicon carbide substrate is scraped from the back surface and used as a thin wafer. Therefore, the resistance of the silicon carbide device can be reduced, and the on-resistance of the silicon carbide semiconductor device can be reduced.

Further, in the manufacturing process of the silicon carbide semiconductor device, the silicon carbide substrate has a sufficient thickness, the strength of the silicon carbide substrate is secured, there is little concern about damage, and the wafer can be easily handled. Therefore, no special equipment for thin wafers is required, and the cost does not increase.

In the above, the present invention can be variously modified without departing from the spirit of the present invention, and in the above-described embodiment, for example, the dimensions of each part, the impurity concentration, and the like are set variously according to the required specifications and the like. Further, in the above-described embodiment, MOSFET is described as an example, but the present invention is not limited to this, and all silicon carbide semiconductor devices manufactured by using a silicon carbide semiconductor substrate, for example, a diode and a super junction (SJ). ) Applicable to silicon carbide semiconductor devices with a structure. Further, in the embodiment, the first conductive type is n-type and the second conductive type is p-type, but in the present invention, the first conductive type is p-type and the second conductive type is n-type. ..

As described above, the method for manufacturing a silicon carbide semiconductor device according to the present invention is useful for a power semiconductor device used in a power conversion device, a power supply device for various industrial machines, etc., and is particularly useful for carbonization of a trench gate structure. Suitable for silicon semiconductor devices.

1 n ⁺ type silicon carbide substrate 2 n ^- type epitaxial layer 3 p ⁺ type region 4 p ⁺ type base region 4a lower p ⁺ type base region 4b upper p ⁺ type base region 5 n ⁺ type drift region 5a 1st n ⁺ type Drift region 5b 2nd n ⁺ type drift region 6 p-type epitaxial layer 7 n ⁺⁺ type source region 8 p ⁺⁺ type contact region 9 Gate insulating film 10 Gate electrode 11 Interlayer insulating film 12 Barrier metal 13 Source electrode 14 Source electrode pad 15 Drain electrode 18 Trench gate 20 Cavity 21 Pillar 22 Silicon carbide semiconductor element 30 Silicon carbide substrate 31 Silicon dioxide (SiO ₂ ) film 32 Photoresist 33 Trench 34 Region

Claims (6)

The first step of forming a silicon carbide semiconductor substrate having a plurality of cavities inside,
The second step of forming the silicon carbide semiconductor element on the silicon carbide semiconductor substrate and
A third step of cutting out the silicon carbide semiconductor element from the silicon carbide semiconductor substrate,
Including
The first step is a step of connecting a plurality of trenches formed from one main surface side of the silicon carbide semiconductor substrate to form a cavity.
The longitudinal direction of the plurality of trenches deviates from the crystal axis direction <11-20> of the silicon carbide semiconductor substrate by a predetermined angle or more based on the formation guarantee accuracy of the orientation flat provided on the silicon carbide semiconductor substrate. The eleventh step of forming the plurality of trenches from one main surface side of the silicon carbide semiconductor substrate, and
After the eleventh step, the silicon carbide film is formed on one main surface side of the silicon carbide semiconductor substrate by heat treatment in a gas atmosphere containing a gas having an etching effect and a gas as a raw material for the silicon carbide film. A twelfth step of forming the cavity by forming a film and etching the side walls of the plurality of trenches.
Including
In the eleventh step, a silicon carbide semiconductor device is manufactured, wherein the trench is formed in a striped shape, and the longitudinal direction of the trench is formed in a direction included in a range deviated by ± 5 degrees or more from the m plane. Method. The silicon carbide semiconductor according to claim 1, wherein in the second step, the silicon carbide semiconductor element is formed on the cavity so that the area of the silicon carbide semiconductor element is smaller than the area of the cavity. How to manufacture the device. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein in the third step, a cut surface for cutting the silicon carbide semiconductor substrate passes through the cavity. The width of the cavity in the direction parallel to the silicon carbide semiconductor substrate is 10 μm or more and 5 mm or less, the height of the cavity is 1 μm or more and 20 μm or less, and the width and the height of the cavity are orthogonal to each other. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the depth is 10 μm or more and 5 mm or less. After the third step,
The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 4, further comprising a fourth step of forming a back surface electrode on the cut-out silicon carbide semiconductor element. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein in the fourth step, the back surface electrode is formed on the surface of the silicon carbide semiconductor substrate in contact with the cavity.

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