WO2019230206A1 - Method for producing silicon carbide semiconductor device - Google Patents

Method for producing silicon carbide semiconductor device Download PDF

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Publication number
WO2019230206A1
WO2019230206A1 PCT/JP2019/015674 JP2019015674W WO2019230206A1 WO 2019230206 A1 WO2019230206 A1 WO 2019230206A1 JP 2019015674 W JP2019015674 W JP 2019015674W WO 2019230206 A1 WO2019230206 A1 WO 2019230206A1
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Prior art keywords
silicon carbide
photoresist
alignment mark
opening
epitaxial film
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PCT/JP2019/015674
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French (fr)
Japanese (ja)
Inventor
秀人 玉祖
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住友電気工業株式会社
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Priority to JP2020521764A priority Critical patent/JP7230909B2/en
Publication of WO2019230206A1 publication Critical patent/WO2019230206A1/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically

Definitions

  • the present disclosure relates to a method for manufacturing a silicon carbide semiconductor device.
  • Silicon carbide is used in high breakdown voltage semiconductor devices and the like because it has a wider band gap than silicon that has been widely used in semiconductor devices.
  • alignment is performed and processes such as ion implantation and etching are performed.
  • a silicon carbide epitaxial film is formed on a silicon carbide crystal substrate on which a concave first alignment mark is formed, thereby forming a silicon carbide epitaxial layer on the first alignment mark.
  • a step of forming a second opening in the first photoresist is formed on a silicon carbide crystal substrate on which a concave first alignment mark is formed, thereby forming a silicon carbide epitaxial layer on the first alignment mark.
  • FIG. 1 is an explanatory diagram (1) of alignment marks in a semiconductor device.
  • FIG. 2 is an explanatory diagram (2) of alignment marks in the semiconductor device.
  • FIG. 3 is an explanatory diagram (3) of the alignment mark in the semiconductor device.
  • FIG. 4 is an explanatory diagram (4) of alignment marks in the semiconductor device.
  • FIG. 5 is an explanatory diagram (5) of alignment marks in the semiconductor device.
  • FIG. 6A is an explanatory diagram (1) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 6B is an explanatory diagram (2) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 7A is an explanatory diagram (3) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 7B is an explanatory diagram (4) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 8A is an explanatory diagram (5) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 8B is an explanatory diagram (6) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 9A is an explanatory diagram (7) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 9B is an explanatory diagram (8) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure.
  • FIG. 10A is an explanatory diagram (1) of the method for manufacturing the semiconductor device according to the second embodiment of the present disclosure.
  • FIG. 10B is an explanatory diagram (2) of the method for manufacturing the semiconductor device according to the second embodiment of the present disclosure.
  • FIG. 11A is an explanatory diagram (3) of the method for manufacturing the semiconductor device according to the second embodiment of the present disclosure.
  • FIG. 11B is an explanatory diagram (4) of the method for manufacturing the semiconductor device according to the second embodiment of the present disclosure.
  • FIG. 12A is an explanatory diagram (5) of the method for manufacturing the semiconductor device according to the second embodiment of the present disclosure.
  • FIG. 12B is an explanatory diagram (6) of the method for manufacturing the semiconductor device according to the second embodiment of the present disclosure.
  • FIG. 13A is an explanatory diagram (1) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 13B is an explanatory diagram (2) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 14A is an explanatory diagram (3) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 14B is an explanatory diagram (4) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 15A is an explanatory diagram (5) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 15B is an explanatory diagram (6) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 16A is an explanatory diagram (7) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 16B is an explanatory diagram (8) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 17A is an explanatory diagram (9) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 17B is an explanatory diagram (10) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 18A is an explanatory diagram (11) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 18B is an explanatory diagram (12) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 19A is an explanatory diagram (13) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • FIG. 19B is an explanatory diagram (14) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
  • alignment is performed based on the alignment mark, and various manufacturing processes are performed.
  • Such alignment marks are formed on the surface of the silicon carbide substrate by concave portions or convex portions having a predetermined shape.
  • the shape of the alignment mark changes.
  • accurate alignment may not be possible.
  • a semiconductor device includes a silicon carbide epitaxial film formed on a silicon carbide crystal substrate on which a concave first alignment mark is formed.
  • the present inventor When manufacturing a silicon carbide semiconductor device, the present inventor forms a silicon carbide epitaxial film on a silicon carbide crystal substrate on which a concave alignment mark is formed, and further applies a photoresist to recognize the alignment mark. It was obtained as a knowledge that it is difficult to be done. Further, the alignment mark appearing on the surface of such a silicon carbide epitaxial film is more easily recognized when the photoresist is not applied than when the photoresist is applied.
  • the first opening is formed by removing the photoresist in the region where the concave alignment mark is formed. Form and expose alignment marks. In the subsequent exposure or the like, alignment is performed with reference to the first alignment mark exposed in the first opening. Thereby, the second opening of the photoresist can be formed at an accurate position. By using the second opening formed in this manner to form a new alignment mark or to process the silicon carbide epitaxial film, it becomes possible to manufacture a silicon carbide semiconductor device with a high yield.
  • the processing is etching of the silicon carbide epitaxial film.
  • the processing is ion implantation into the silicon carbide epitaxial film.
  • the first photoresist is a positive type.
  • the first opening and the second opening are formed by a step of exposing the first photoresist and a step of developing the exposed first photoresist.
  • Forming a first opening, aligning using the second alignment mark exposed in the first opening, and forming the second opening in the first photoresist A part of the silicon carbide epitaxial film in the second opening after the step of forming the second opening Removing the first alignment mark; and removing the first photoresist; and after removing the first photoresist, the surface of the silicon carbide epitaxial film is removed.
  • the first photoresist is a positive type, and the first opening and the second opening are formed by exposing the first photoresist and developing the exposed first photoresist. Forming the step.
  • the first opening and the second opening are formed by a step of exposing the first photoresist and a step of developing the exposed first photoresist.
  • the present embodiment an embodiment of the present disclosure (hereinafter referred to as “the present embodiment”) will be described in detail, but the present embodiment is not limited thereto.
  • a convex alignment mark 11 that is convex with respect to main surface 10a of silicon carbide single crystal substrate 10 shown in FIG. 1, or a silicon carbide single crystal substrate shown in FIG.
  • a concave alignment mark 12 which is concave with respect to the ten main surfaces 10a.
  • a silicon carbide epitaxial film or the like may be formed on the main surface 10a of the silicon carbide single crystal substrate 10 by epitaxial growth.
  • the shape of the alignment mark changes.
  • silicon carbide epitaxial film 20 is formed on main surface 10a of silicon carbide single crystal substrate 10 on which convex alignment mark 11 having a rectangular cross section as shown in FIG. 1 is formed.
  • alignment mark 21 appears on the surface 20 a of silicon carbide epitaxial film 20 in the region where convex alignment mark 11 was formed.
  • the alignment mark 21 has a mountain shape whose cross-sectional shape has an inclined surface 21a, and is different in shape from the alignment mark 11 as shown in FIG.
  • a silicon carbide epitaxial film 20 is formed on main surface 10a of silicon carbide single crystal substrate 10 on which concave alignment mark 12 having a rectangular cross section as shown in FIG. 2 is formed.
  • alignment mark 22 appears on the surface 20 a of silicon carbide epitaxial film 20 in the region where concave alignment mark 12 was formed.
  • the alignment mark 22 has a shape having inclined surfaces 22a and 22b whose cross-sectional shape is not perpendicular to the main surface 10a, and is different from the alignment mark 12 as shown in FIG.
  • the alignment mark 22 is more easily recognized than the alignment mark 21.
  • the alignment mark formed on main surface 10a of silicon carbide single crystal substrate 10 has a concave alignment mark 12 as shown in FIG. 2 rather than a convex alignment mark 11 as shown in FIG. preferable.
  • the alignment mark 22 may not be recognized.
  • the alignment light interferes with the gently inclined portions such as the inclined surfaces 22 a and 22 b and the surface of the photoresist 30. It is guessed. This is because the light amount of the alignment light gradually and continuously changes in a wide range due to interference between the gently inclined portions such as the inclined surfaces 22a and 22b and the surface of the photoresist 30.
  • the simple alignment may mean fine alignment.
  • silicon carbide epitaxial film 20 is formed on silicon carbide single crystal substrate 10 on which concave alignment mark 12 is formed and a photoresist is applied, silicon carbide semiconductor device capable of alignment by alignment can be used. There is a need for a manufacturing method.
  • a concave first alignment mark 111 is formed on main surface 110 a of silicon carbide single crystal substrate 110.
  • a photoresist is applied to main surface 110a of silicon carbide single crystal substrate 110, and exposure and development are performed by an exposure apparatus, whereby an opening is formed in a region where concave alignment mark 111 is formed.
  • a resist pattern (not shown) is formed.
  • the silicon carbide single crystal substrate 110 in a region where the resist pattern is not formed is removed by dry etching such as RIE (Reactive Ion Etching), thereby forming a concave first alignment mark 111.
  • RIE Reactive Ion Etching
  • the silicon carbide single crystal substrate 110 is removed by dry etching, SF 6 + O 2 is used as an etching gas, and the applied power is 800 W, the bias power is 40 W, and the pressure in the chamber of the dry etching apparatus is 1 Pa. .
  • the resist pattern is removed by oxygen ashing, and then SPM cleaning and RCA cleaning are performed.
  • Silicon carbide single crystal substrate 110 has a main surface 110a inclined by an off angle ⁇ from a predetermined crystal plane.
  • the predetermined crystal plane is preferably a (0001) plane or a (000-1) plane.
  • the silicon carbide polytype in silicon carbide single crystal substrate 110 is 4H. This is because 4H polytype silicon carbide has better electron mobility, breakdown field strength, and the like than other polytypes.
  • Silicon carbide single crystal substrate 110 has a diameter of 150 mm or more (for example, 6 inches or more). This is because the larger the diameter, the more advantageous in reducing the manufacturing cost of the semiconductor device.
  • main surface 110a is inclined with respect to the ⁇ 0001 ⁇ plane at an off angle ⁇ of 4 ° in the ⁇ 11-20> orientation. In the present embodiment, the off angle ⁇ may be greater than 0 ° and 6 ° or less.
  • a silicon carbide epitaxial film 120 is formed on main surface 110a of silicon carbide single crystal substrate 110 by epitaxial growth.
  • the film thickness of silicon carbide epitaxial film 120 formed is 1 ⁇ m to 3 ⁇ m.
  • second alignment mark 121 appears on surface 120a of silicon carbide epitaxial film 120 in the region where concave first alignment mark 111 has been formed.
  • the second alignment mark 121 has a shape having an inclined surface whose cross-sectional shape is inclined with respect to the surface 120a.
  • a first photoresist 130 is applied to the surface 120 a of the silicon carbide epitaxial film 120.
  • the first photoresist 130 is applied by a spin coater or the like so that the film thickness is about 2 ⁇ m.
  • second alignment mark 121 appearing on surface 120a of silicon carbide epitaxial film 120 is buried in first photoresist 130, and the surface of first photoresist 130 becomes flat.
  • baking etc. are performed as needed.
  • the first photoresist 130 is a positive photoresist.
  • a first opening 131 of the first photoresist 130 is formed in a region including the entire second alignment mark 121 on the surface 120a of the silicon carbide epitaxial film 120.
  • the first opening 131 of the first photoresist 130 is formed by performing exposure and development with an exposure apparatus.
  • a stepper having a wavelength of 365 nm (i-line) is used for the exposure apparatus, and an alkaline solution such as TMAH (tetramethylammonium hydroxide) is used for the developer.
  • the first opening 131 is formed to be approximately 10 ⁇ m wider than the outer shape of the second alignment mark 121.
  • first opening 131 second alignment mark 121 on surface 120 a of silicon carbide epitaxial film 120 is exposed in first opening 131.
  • this alignment is performed by rough alignment, visual observation, etc. of a stepper.
  • a second opening 132 of the first photoresist 130 is formed in a region where a concave third alignment mark 122 described later is formed. Specifically, alignment is performed using the second alignment mark 121 exposed in the first opening 131 of the first photoresist 130, and exposure and development are performed by an exposure apparatus. Thereby, the second opening 132 of the first photoresist 130 is formed at a predetermined position.
  • a stepper having a wavelength of 365 nm is used for the exposure apparatus, and an alkaline solution such as TMAH is used for the developer.
  • TMAH alkaline solution
  • a part of the silicon carbide epitaxial film 120 exposed in the second opening 132 of the first photoresist 130 is removed, thereby forming a concave third alignment mark 122.
  • the silicon carbide epitaxial film 120 exposed in the second opening 132 of the first photoresist 130 is removed by dry etching such as RIE, so that the concave third alignment mark 122 is formed.
  • the depth to the bottom of the concave third alignment mark 122 formed in this way is about 0.5 ⁇ m to 1.0 ⁇ m.
  • Such concave third alignment mark 122 may be formed in a region to be a scribe line cut by a dicing saw when manufacturing the silicon carbide semiconductor device.
  • silicon carbide epitaxial film 120 When removing silicon carbide epitaxial film 120, SF 6 + O 2 is used as an etching gas under the conditions of applied power: 800 W, bias power: 40 W, and pressure in the chamber of the dry etching apparatus: 1 Pa. At this time, the silicon carbide epitaxial film 120 in the region where the second alignment mark 121 exposed in the first opening 131 of the first photoresist 130 is formed is also partially removed at the same time. There is no hindrance to the manufacture of the semiconductor device.
  • the first photoresist 130 is removed.
  • SPM cleaning and RCA cleaning are performed.
  • accurate alignment can be performed by performing alignment using the formed concave third alignment mark 122, and a desired silicon carbide semiconductor device can be obtained. Can be manufactured at a high yield.
  • the concave third alignment mark 122 is a rectangular concave alignment mark, and after that, as shown in FIG. 9B, even when the second photoresist 140 is applied, Positioning by fine alignment by an exposure apparatus is possible. Therefore, the silicon carbide semiconductor device can be manufactured with a high yield by performing alignment using the concave third alignment mark 122 and performing exposure.
  • a concave first alignment mark 111 is formed on main surface 110 a of silicon carbide single crystal substrate 110.
  • silicon carbide epitaxial film 120 is formed on main surface 110a of silicon carbide single crystal substrate 110 by epitaxial growth.
  • a first photoresist 130 is applied to the surface 120 a of the silicon carbide epitaxial film 120.
  • a first opening 131 of the first photoresist 130 is formed on the surface 120a of the silicon carbide epitaxial film 120 in a region including the entire second alignment mark 121.
  • a second opening 232 of the first photoresist 130 is formed in a region where an n + region 221 of a silicon carbide epitaxial film 120 described later is formed. Specifically, alignment is performed using the second alignment mark 121 exposed in the first opening 131 of the first photoresist 130, and exposure and development are performed by an exposure apparatus. Thus, the second opening 232 of the first photoresist 130 is formed at a predetermined position. In this step, since the second alignment mark 121 exposed in the first opening 131 of the first photoresist 130 can be used, accurate alignment can be performed by fine alignment. As a result, the second opening 232 can be accurately formed at a desired position of the first photoresist 130.
  • n + -type impurity elements are ion-implanted into the silicon carbide epitaxial film 120 exposed in the second opening 232 of the first photoresist 130, whereby n + Region 221 is formed.
  • P is used as an n-type impurity element, and ion implantation is performed under the conditions of acceleration energy: 10 keV to 900 keV and dose amount: 1 ⁇ 10 11 cm ⁇ 2 to 1 ⁇ 10 16 cm ⁇ 2 .
  • the impurity element to be ion-implanted is Al. Thereafter, the first photoresist 130 is removed.
  • second opening 232 of first photoresist 130 is formed in a so-called element region. Further, in the present embodiment, a trench or the like is formed by removing silicon carbide epitaxial film 120 in the region where second opening 232 of first photoresist 130 is formed by etching. Good.
  • a concave first alignment mark 111 is formed on main surface 110a of silicon carbide single crystal substrate 110.
  • a silicon carbide epitaxial film 120 is formed on main surface 110a of silicon carbide single crystal substrate 110 by epitaxial growth.
  • a first photoresist 130 is applied to the surface 120 a of the silicon carbide epitaxial film 120.
  • a first opening 131 of the first photoresist 130 is formed in a region including the entire second alignment mark 121 on the surface 120 a of the silicon carbide epitaxial film 120.
  • a second opening 132 of the first photoresist 130 is formed in a region where a concave third alignment mark 122 described later is formed.
  • the silicon carbide epitaxial film 120 exposed in the second opening 132 of the first photoresist 130 is removed, thereby forming a concave third alignment mark 122. .
  • the first photoresist 130 is removed.
  • a silicon oxide film 350 having a thickness of about 2 ⁇ m is formed on the surface 120 a of the silicon carbide epitaxial film 120.
  • a photoresist 360 is applied on the silicon oxide film 350.
  • the thickness of the applied photoresist 360 is about 2.5 ⁇ m.
  • a third opening 361 of photoresist 360 is formed in a region where n + region 321 is formed in silicon carbide epitaxial film 120.
  • alignment is performed using a concave third alignment mark 122 formed in the silicon carbide epitaxial film 120, and exposure and development are performed by an exposure apparatus, whereby a third opening is formed in the photoresist 360.
  • a portion 361 is formed.
  • concave third alignment mark 122 having a side surface substantially perpendicular to surface 120a of silicon carbide epitaxial film 120 can be used. Therefore, even if the silicon oxide film 350 is formed on the concave third alignment mark 122, the concave third alignment mark 122 can be recognized by the exposure apparatus. Therefore, accurate alignment can be performed by fine alignment using the concave third alignment mark 122. Thereby, the third opening 361 can be accurately formed at a desired position of the photoresist 360.
  • the silicon oxide film 350 in the third opening 361 of the photoresist 360 is removed by dry etching such as RIE to form an opening 351. Thereby, an ion implantation mask is formed by the remaining silicon oxide film 350.
  • a mixed gas of CF 4 , CHF 3 , and Ar is used as an etching gas
  • the applied power is 500 W
  • the bias power is 50 W
  • the pressure in the chamber of the dry etching apparatus is 1 Pa.
  • silicon oxide film 350 in third opening 361 of photoresist 360 is removed until surface 120a of silicon carbide epitaxial film 120 is exposed, opening 351 is formed in silicon oxide film 350, and an ion implantation mask is used. Form.
  • the photoresist 360 is removed.
  • SPM cleaning and RCA cleaning are performed.
  • an n + region is formed by ion-implanting an n-type impurity element into the silicon carbide epitaxial film 120 in the region using the silicon oxide film 350 having the opening 351 as an ion implantation mask. 321 is formed.
  • P is used as an n-type impurity element, and ion implantation is performed under the conditions of acceleration energy: 10 keV to 900 keV and dose amount: 1 ⁇ 10 11 cm ⁇ 2 to 1 ⁇ 10 16 cm ⁇ 2 .
  • acceleration energy 10 keV to 900 keV
  • dose amount 1 ⁇ 10 11 cm ⁇ 2 to 1 ⁇ 10 16 cm ⁇ 2 .
  • the silicon oxide film 350 is removed by wet etching.
  • HF hydrofluoric acid
  • BHF biuffered hydrofluoric acid

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Abstract

This method for producing a silicon carbide semiconductor device comprises: a step of forming a silicon carbide epitaxial layer 120 on a silicon carbide crystal substrate 110 having formed a recessed first alignment mark 111, thereby forming a recessed second alignment mark 121 on a surface 120a of the silicon carbide epitaxial layer 120 over the first alignment mark 111; a step of applying a first photoresist 130 to the surface 120a of the silicon carbide epitaxial layer 120; a step of removing the first photoresist 130 in a region including the second alignment mark 121, thereby forming a first opening 131; and a step of performing positioning using the second alignment mark 121, which is exposed in the first opening 131, thereby forming a second opening 132 in the first photoresist 130.

Description

炭化珪素半導体装置の製造方法Method for manufacturing silicon carbide semiconductor device
　本開示は、炭化珪素半導体装置の製造方法に関するものである。 The present disclosure relates to a method for manufacturing a silicon carbide semiconductor device.
　本出願は、２０１８年５月３０日出願の日本特許出願第２０１８－１０３１１５号に基づく優先権を主張し、前記日本特許出願に記載された全ての記載内容を援用するものである。 This application claims priority based on Japanese Patent Application No. 2018-103115 filed on May 30, 2018, and incorporates all the contents described in the Japanese Patent Application.
　炭化珪素は、従来から半導体装置に幅広く用いられている珪素に比べてバンドギャップが広いことから、高耐圧の半導体装置等に用いられている。このような炭化珪素を用いた半導体装置を製造する際には、位置合わせを行いイオン注入やエッチング等の工程が行われる。 Silicon carbide is used in high breakdown voltage semiconductor devices and the like because it has a wider band gap than silicon that has been widely used in semiconductor devices. When manufacturing such a semiconductor device using silicon carbide, alignment is performed and processes such as ion implantation and etching are performed.
特開２０１５－２１９８号公報Japanese Patent Laid-Open No. 2015-2198
　本実施形態の一観点によれば、凹状の第１のアライメントマークが形成されている炭化珪素結晶基板に、炭化珪素エピタキシャル膜を成膜することにより、第１のアライメントマークの上の炭化珪素エピタキシャル膜の表面に凹状の第２のアライメントマークを形成する工程と、炭化珪素エピタキシャル膜の表面に第１のフォトレジストを塗布する工程とを有する。更に、第２のアライメントマークを含む領域の第１のフォトレジストを除去し、第１の開口部を形成する工程と、第１の開口部において露出している第２のアライメントマークを用いて位置合わせを行い、第１のフォトレジストに第２の開口部を形成する工程とを有する。 According to one aspect of the present embodiment, a silicon carbide epitaxial film is formed on a silicon carbide crystal substrate on which a concave first alignment mark is formed, thereby forming a silicon carbide epitaxial layer on the first alignment mark. Forming a concave second alignment mark on the surface of the film; and applying a first photoresist on the surface of the silicon carbide epitaxial film. Further, the step of removing the first photoresist in the region including the second alignment mark to form the first opening, and the position using the second alignment mark exposed in the first opening. And a step of forming a second opening in the first photoresist.
図１は半導体装置におけるアライメントマークの説明図（１）である。FIG. 1 is an explanatory diagram (1) of alignment marks in a semiconductor device. 図２は半導体装置におけるアライメントマークの説明図（２）である。FIG. 2 is an explanatory diagram (2) of alignment marks in the semiconductor device. 図３は半導体装置におけるアライメントマークの説明図（３）である。FIG. 3 is an explanatory diagram (3) of the alignment mark in the semiconductor device. 図４は半導体装置におけるアライメントマークの説明図（４）である。FIG. 4 is an explanatory diagram (4) of alignment marks in the semiconductor device. 図５は半導体装置におけるアライメントマークの説明図（５）である。FIG. 5 is an explanatory diagram (5) of alignment marks in the semiconductor device. 図６Ａは本開示の第１の実施形態の半導体装置の製造方法の説明図（１）である。FIG. 6A is an explanatory diagram (1) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. 図６Ｂは本開示の第１の実施形態の半導体装置の製造方法の説明図（２）である。FIG. 6B is an explanatory diagram (2) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. 図７Ａは本開示の第１の実施形態の半導体装置の製造方法の説明図（３）である。FIG. 7A is an explanatory diagram (3) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. 図７Ｂは本開示の第１の実施形態の半導体装置の製造方法の説明図（４）である。FIG. 7B is an explanatory diagram (4) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. 図８Ａは本開示の第１の実施形態の半導体装置の製造方法の説明図（５）である。FIG. 8A is an explanatory diagram (5) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. 図８Ｂは本開示の第１の実施形態の半導体装置の製造方法の説明図（６）である。FIG. 8B is an explanatory diagram (6) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. 図９Ａは本開示の第１の実施形態の半導体装置の製造方法の説明図（７）である。FIG. 9A is an explanatory diagram (7) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. 図９Ｂは本開示の第１の実施形態の半導体装置の製造方法の説明図（８）である。FIG. 9B is an explanatory diagram (8) of the method for manufacturing the semiconductor device according to the first embodiment of the present disclosure. 図１０Ａは本開示の第２の実施形態の半導体装置の製造方法の説明図（１）である。FIG. 10A is an explanatory diagram (1) of the method for manufacturing the semiconductor device according to the second embodiment of the present disclosure. 図１０Ｂは本開示の第２の実施形態の半導体装置の製造方法の説明図（２）である。FIG. 10B is an explanatory diagram (2) of the method for manufacturing the semiconductor device according to the second embodiment of the present disclosure. 図１１Ａは本開示の第２の実施形態の半導体装置の製造方法の説明図（３）である。FIG. 11A is an explanatory diagram (3) of the method for manufacturing the semiconductor device according to the second embodiment of the present disclosure. 図１１Ｂは本開示の第２の実施形態の半導体装置の製造方法の説明図（４）である。FIG. 11B is an explanatory diagram (4) of the method for manufacturing the semiconductor device according to the second embodiment of the present disclosure. 図１２Ａは本開示の第２の実施形態の半導体装置の製造方法の説明図（５）である。FIG. 12A is an explanatory diagram (5) of the method for manufacturing the semiconductor device according to the second embodiment of the present disclosure. 図１２Ｂは本開示の第２の実施形態の半導体装置の製造方法の説明図（６）である。FIG. 12B is an explanatory diagram (6) of the method for manufacturing the semiconductor device according to the second embodiment of the present disclosure. 図１３Ａは本開示の第３の実施形態の半導体装置の製造方法の説明図（１）である。FIG. 13A is an explanatory diagram (1) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure. 図１３Ｂは本開示の第３の実施形態の半導体装置の製造方法の説明図（２）である。FIG. 13B is an explanatory diagram (2) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure. 図１４Ａは本開示の第３の実施形態の半導体装置の製造方法の説明図（３）である。FIG. 14A is an explanatory diagram (3) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure. 図１４Ｂは本開示の第３の実施形態の半導体装置の製造方法の説明図（４）である。FIG. 14B is an explanatory diagram (4) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure. 図１５Ａは本開示の第３の実施形態の半導体装置の製造方法の説明図（５）である。FIG. 15A is an explanatory diagram (5) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure. 図１５Ｂは本開示の第３の実施形態の半導体装置の製造方法の説明図（６）である。FIG. 15B is an explanatory diagram (6) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure. 図１６Ａは本開示の第３の実施形態の半導体装置の製造方法の説明図（７）である。FIG. 16A is an explanatory diagram (7) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure. 図１６Ｂは本開示の第３の実施形態の半導体装置の製造方法の説明図（８）である。FIG. 16B is an explanatory diagram (8) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure. 図１７Ａは本開示の第３の実施形態の半導体装置の製造方法の説明図（９）である。FIG. 17A is an explanatory diagram (9) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure. 図１７Ｂは本開示の第３の実施形態の半導体装置の製造方法の説明図（１０）である。FIG. 17B is an explanatory diagram (10) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure. 図１８Ａは本開示の第３の実施形態の半導体装置の製造方法の説明図（１１）である。FIG. 18A is an explanatory diagram (11) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure. 図１８Ｂは本開示の第３の実施形態の半導体装置の製造方法の説明図（１２）である。FIG. 18B is an explanatory diagram (12) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure. 図１９Ａは本開示の第３の実施形態の半導体装置の製造方法の説明図（１３）である。FIG. 19A is an explanatory diagram (13) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure. 図１９Ｂは本開示の第３の実施形態の半導体装置の製造方法の説明図（１４）である。FIG. 19B is an explanatory diagram (14) of the method for manufacturing the semiconductor device according to the third embodiment of the present disclosure.
　炭化珪素半導体装置の製造工程においては、アライメントマークを基準に位置合わせを行い様々な製造プロセスが行われる。このようなアライメントマークは、炭化珪素基板の表面に所定の形状の凹部や凸部により形成されているが、アライメントマークの上に炭化珪素膜等が成膜されると、アライメントマークの形が変化し、正確な位置合わせを行うことができない場合がある。 In the manufacturing process of the silicon carbide semiconductor device, alignment is performed based on the alignment mark, and various manufacturing processes are performed. Such alignment marks are formed on the surface of the silicon carbide substrate by concave portions or convex portions having a predetermined shape. However, when a silicon carbide film or the like is formed on the alignment mark, the shape of the alignment mark changes. However, accurate alignment may not be possible.
　このため、炭化珪素半導体装置の製造工程において、アライメントマークを用いて正確に位置合わせをすることのできる炭化珪素半導体装置の製造方法が求められる。 For this reason, in the manufacturing process of a silicon carbide semiconductor device, a method for manufacturing a silicon carbide semiconductor device that can be accurately aligned using an alignment mark is required.
　本開示によれば、炭化珪素半導体装置の製造工程において、アライメントマークを用いて正確に位置合わせをすることのできる炭化珪素半導体装置の製造方法を提供することができる。 According to the present disclosure, it is possible to provide a method for manufacturing a silicon carbide semiconductor device that can be accurately aligned using an alignment mark in the manufacturing process of the silicon carbide semiconductor device.
　実施するための形態について、以下に説明する。 The form for carrying out will be described below.
　［本開示の実施形態の説明］
　最初に本開示の実施態様を列記して説明する。以下の説明では、同一または対応する要素には同一の符号を付し、それらについて同じ説明は繰り返さない。また本明細書の結晶学的記載においては、個別方位を［］、集合方位を＜＞、個別面を（）、集合面を｛｝でそれぞれ示している。ここで結晶学上の指数が負であることは、通常、数字の上に”－”（バー）を付すことによって表現されるが、本明細書では数字の前に負の符号を付すことによって結晶学上の負の指数を表現している。また、本開示のエピタキシャル成長は、ホモエピタキシャル成長である。 [Description of Embodiment of Present Disclosure]
First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description is not repeated. In the crystallographic description of the present specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. Here, a negative crystallographic index is usually expressed by adding a “−” (bar) above a number, but in this specification a negative sign is added before the number. It represents a negative index in crystallography. The epitaxial growth of the present disclosure is homoepitaxial growth.
〔１〕　本開示の一態様に係る半導体装置は、凹状の第１のアライメントマークが形成されている炭化珪素結晶基板に、炭化珪素エピタキシャル膜を成膜することにより、前記第１のアライメントマークの上の前記炭化珪素エピタキシャル膜の表面に凹状の第２のアライメントマークを形成する工程と、前記炭化珪素エピタキシャル膜の表面に第１のフォトレジストを塗布する工程と、前記第２のアライメントマークを含む領域の前記第１のフォトレジストを除去し、第１の開口部を形成する工程と、前記第１の開口部において露出している前記第２のアライメントマークを用いて位置合わせを行い、前記第１のフォトレジストに第２の開口部を形成する工程と、を有する。 [1] A semiconductor device according to an aspect of the present disclosure includes a silicon carbide epitaxial film formed on a silicon carbide crystal substrate on which a concave first alignment mark is formed. A step of forming a concave second alignment mark on the surface of the silicon carbide epitaxial film, a step of applying a first photoresist to the surface of the silicon carbide epitaxial film, and the second alignment mark. Removing the first photoresist in a region to form a first opening, and performing alignment using the second alignment mark exposed in the first opening; Forming a second opening in one photoresist.
　本願発明者は、炭化珪素半導体装置を製造する際、凹状のアライメントマークが形成されている炭化珪素結晶基板に、炭化珪素エピタキシャル膜を成膜し、更に、フォトレジストを塗布すると、アライメントマークが認識されにくくなることを知見として得た。また、このような炭化珪素エピタキシャル膜の表面に現れるアライメントマークは、フォトレジストが塗布されてる状態よりも、フォトレジストが塗布されていない状態の方が認識されやすい。 When manufacturing a silicon carbide semiconductor device, the present inventor forms a silicon carbide epitaxial film on a silicon carbide crystal substrate on which a concave alignment mark is formed, and further applies a photoresist to recognize the alignment mark. It was obtained as a knowledge that it is difficult to be done. Further, the alignment mark appearing on the surface of such a silicon carbide epitaxial film is more easily recognized when the photoresist is not applied than when the photoresist is applied.
　本願は、このように発明者により得られた知見に基づくものである。具体的には、凹状のアライメントマークが形成されている炭化珪素結晶基板にフォトレジストを塗布した後、凹状のアライメントマークが形成されている領域のフォトレジストを除去することにより第１の開口部を形成し、アライメントマークを露出させる。この後の露光等においては、第１の開口部において露出している前記第１のアライメントマークを基準に位置合わせを行う。これにより、正確な位置にフォトレジストの第２の開口部を形成することができる。このように形成された第２の開口部を用いて、新たなアライメントマークを形成したり、炭化珪素エピタキシャル膜を加工することにより、炭化珪素半導体装置を高い歩留まりで製造することが可能となる。 This application is based on the knowledge thus obtained by the inventors. Specifically, after applying a photoresist to the silicon carbide crystal substrate on which the concave alignment mark is formed, the first opening is formed by removing the photoresist in the region where the concave alignment mark is formed. Form and expose alignment marks. In the subsequent exposure or the like, alignment is performed with reference to the first alignment mark exposed in the first opening. Thereby, the second opening of the photoresist can be formed at an accurate position. By using the second opening formed in this manner to form a new alignment mark or to process the silicon carbide epitaxial film, it becomes possible to manufacture a silicon carbide semiconductor device with a high yield.
　〔２〕　前記第２の開口部を形成する工程の後、前記第２の開口部における前記炭化珪素エピタキシャル膜の一部を除去し、第３のアライメントマークを形成する工程と、前記第１のフォトレジストを除去する工程と、を有する。 [2] After the step of forming the second opening, removing a part of the silicon carbide epitaxial film in the second opening to form a third alignment mark; Removing the photoresist.
　〔３〕　前記第１のフォトレジストを除去する工程の後、前記炭化珪素エピタキシャル膜の表面に第２のフォトレジストを塗布する工程と、前記第３のアライメントマークを用いて位置合わせを行い、前記第２のフォトレジストに第３の開口部を形成する工程と、を有する。 [3] After the step of removing the first photoresist, a step of applying a second photoresist to the surface of the silicon carbide epitaxial film, and performing alignment using the third alignment mark, Forming a third opening in the second photoresist.
　〔４〕　凹状の第１のアライメントマークが形成されている炭化珪素結晶基板に、炭化珪素エピタキシャル膜を成膜する工程と、前記炭化珪素エピタキシャル膜の表面に第１のフォトレジストを塗布する工程と、前記第１のアライメントマークの上の炭化珪素エピタキシャル膜の表面に形成された第２のアライメントマークを含む領域の前記第１のフォトレジストを除去し、第１の開口部を形成する工程と、前記第１の開口部において露出している前記第２のアライメントマークを用いて位置合わせを行い、前記第１のフォトレジストに第２の開口部を形成する工程と、前記第２の開口部における前記炭化珪素エピタキシャル膜を加工する工程と、前記第１のフォトレジストを除去する工程と、を有する。 [4] A step of forming a silicon carbide epitaxial film on a silicon carbide crystal substrate on which a concave first alignment mark is formed, and a step of applying a first photoresist to the surface of the silicon carbide epitaxial film; Removing the first photoresist in a region including the second alignment mark formed on the surface of the silicon carbide epitaxial film on the first alignment mark, and forming a first opening; Performing alignment using the second alignment mark exposed in the first opening and forming a second opening in the first photoresist; and in the second opening A step of processing the silicon carbide epitaxial film; and a step of removing the first photoresist.
　〔５〕　前記加工は、前記炭化珪素エピタキシャル膜のエッチングである。 [5] The processing is etching of the silicon carbide epitaxial film.
　〔６〕　前記加工は、前記炭化珪素エピタキシャル膜へのイオン注入である。 [6] The processing is ion implantation into the silicon carbide epitaxial film.
　〔７〕　前記第１のフォトレジストは、ポジ型である。 [7] The first photoresist is a positive type.
　〔８〕　前記第１の開口部及び前記第２の開口部は、前記第１のフォトレジストを露光する工程と、露光された前記第１のフォトレジストを現像する工程と、により形成される。 [8] The first opening and the second opening are formed by a step of exposing the first photoresist and a step of developing the exposed first photoresist.
　〔９〕　凹状の第１のアライメントマークが形成されている炭化珪素結晶基板に、炭化珪素エピタキシャル膜を成膜することにより、前記第１のアライメントマークの上の前記炭化珪素エピタキシャル膜の表面に凹状の第２のアライメントマークを形成する工程と、前記炭化珪素エピタキシャル膜の表面に第１のフォトレジストを塗布する工程と、前記第２のアライメントマークを含む領域の前記第１のフォトレジストを除去し、第１の開口部を形成する工程と、前記第１の開口部において露出している前記第２のアライメントマークを用いて位置合わせを行い、前記第１のフォトレジストに第２の開口部を形成する工程と、を有し、前記第２の開口部を形成する工程の後、前記第２の開口部における前記炭化珪素エピタキシャル膜の一部を除去し、第３のアライメントマークを形成する工程と、前記第１のフォトレジストを除去する工程と、を有し、前記第１のフォトレジストを除去する工程の後、前記炭化珪素エピタキシャル膜の表面に第２のフォトレジストを塗布する工程と、前記第３のアライメントマークを用いて位置合わせを行い、前記第２のフォトレジストに第３の開口部を形成する工程と、を有し、前記第１のフォトレジストは、ポジ型であって、前記第１の開口部及び前記第２の開口部は、前記第１のフォトレジストを露光する工程と、露光された前記第１のフォトレジストを現像する工程と、により形成される。 [9] By forming a silicon carbide epitaxial film on the silicon carbide crystal substrate on which the concave first alignment mark is formed, a concave shape is formed on the surface of the silicon carbide epitaxial film on the first alignment mark. Forming a second alignment mark, applying a first photoresist to the surface of the silicon carbide epitaxial film, and removing the first photoresist in a region including the second alignment mark. , Forming a first opening, aligning using the second alignment mark exposed in the first opening, and forming the second opening in the first photoresist A part of the silicon carbide epitaxial film in the second opening after the step of forming the second opening Removing the first alignment mark; and removing the first photoresist; and after removing the first photoresist, the surface of the silicon carbide epitaxial film is removed. Applying a second photoresist to the first photoresist, and performing alignment using the third alignment mark to form a third opening in the second photoresist. The first photoresist is a positive type, and the first opening and the second opening are formed by exposing the first photoresist and developing the exposed first photoresist. Forming the step.
　〔１０〕　凹状の第１のアライメントマークが形成されている炭化珪素結晶基板に、炭化珪素エピタキシャル膜を成膜する工程と、前記炭化珪素エピタキシャル膜の表面に第１のフォトレジストを塗布する工程と、前記第１のアライメントマークの上の炭化珪素エピタキシャル膜の表面に形成された第２のアライメントマークを含む領域の前記第１のフォトレジストを除去し、第１の開口部を形成する工程と、前記第１の開口部において露出している前記第２のアライメントマークを用いて位置合わせを行い、前記第１のフォトレジストに第２の開口部を形成する工程と、前記第２の開口部における前記炭化珪素エピタキシャル膜を加工する工程と、前記第１のフォトレジストを除去する工程と、を有し、前記第１のフォトレジストは、ポジ型であって、前記第１の開口部及び前記第２の開口部は、前記第１のフォトレジストを露光する工程と、露光された前記第１のフォトレジストを現像する工程と、により形成される。 [10] A step of forming a silicon carbide epitaxial film on a silicon carbide crystal substrate on which a concave first alignment mark is formed, and a step of applying a first photoresist to the surface of the silicon carbide epitaxial film; Removing the first photoresist in a region including the second alignment mark formed on the surface of the silicon carbide epitaxial film on the first alignment mark, and forming a first opening; Performing alignment using the second alignment mark exposed in the first opening and forming a second opening in the first photoresist; and in the second opening A step of processing the silicon carbide epitaxial film; and a step of removing the first photoresist. In the mold, the first opening and the second opening are formed by a step of exposing the first photoresist and a step of developing the exposed first photoresist. The
　［本開示の実施形態の詳細］
　以下、本開示の一実施形態（以下「本実施形態」と記す）について詳細に説明するが、本実施形態はこれらに限定されるものではない。 [Details of Embodiment of the Present Disclosure]
Hereinafter, an embodiment of the present disclosure (hereinafter referred to as “the present embodiment”) will be described in detail, but the present embodiment is not limited thereto.
　最初に、炭化珪素半導体装置の製造工程において形成されるアライメントマークについて説明する。半導体装置を製造する際のアライメントマークには、図１に示される炭化珪素単結晶基板１０の主面１０ａに対し凸となる凸状のアライメントマーク１１や、図２に示される炭化珪素単結晶基板１０の主面１０ａに対し凹となる凹状のアライメントマーク１２がある。 First, alignment marks formed in the manufacturing process of the silicon carbide semiconductor device will be described. As alignment marks for manufacturing a semiconductor device, a convex alignment mark 11 that is convex with respect to main surface 10a of silicon carbide single crystal substrate 10 shown in FIG. 1, or a silicon carbide single crystal substrate shown in FIG. There is a concave alignment mark 12 which is concave with respect to the ten main surfaces 10a.
　炭化珪素半導体装置を製造する際には、炭化珪素単結晶基板１０の主面１０ａに、炭化珪素エピタキシャル膜等をエピタキシャル成長により成膜する場合があるが、この場合、アライメントマークの形状が変化する場合がある。具体的には、図１に示されるような断面が矩形の凸状のアライメントマーク１１が形成されている炭化珪素単結晶基板１０の主面１０ａに、炭化珪素エピタキシャル膜２０を成膜する。この場合、図３に示されるように、炭化珪素エピタキシャル膜２０の表面２０ａには、凸状のアライメントマーク１１が形成されていた領域にアライメントマーク２１が現れる。このアライメントマーク２１は、断面形状が傾斜面２１ａを有する山形であり、図１に示されるようなアライメントマーク１１とは形状が異なる。 When manufacturing a silicon carbide semiconductor device, a silicon carbide epitaxial film or the like may be formed on the main surface 10a of the silicon carbide single crystal substrate 10 by epitaxial growth. In this case, the shape of the alignment mark changes. There is. Specifically, silicon carbide epitaxial film 20 is formed on main surface 10a of silicon carbide single crystal substrate 10 on which convex alignment mark 11 having a rectangular cross section as shown in FIG. 1 is formed. In this case, as shown in FIG. 3, alignment mark 21 appears on the surface 20 a of silicon carbide epitaxial film 20 in the region where convex alignment mark 11 was formed. The alignment mark 21 has a mountain shape whose cross-sectional shape has an inclined surface 21a, and is different in shape from the alignment mark 11 as shown in FIG.
　また、図２に示されるような断面が矩形の凹状のアライメントマーク１２が形成されている炭化珪素単結晶基板１０の主面１０ａに、炭化珪素エピタキシャル膜２０を成膜する。この場合、図４に示されるように、炭化珪素エピタキシャル膜２０の表面２０ａには、凹状のアライメントマーク１２が形成されていた領域にアライメントマーク２２が現れる。このアライメントマーク２２は、断面形状が主面１０ａに対し垂直ではない傾斜面２２ａ、２２ｂを有する形状であり、図２に示されるようなアライメントマーク１２とは形状が異なる。 Further, a silicon carbide epitaxial film 20 is formed on main surface 10a of silicon carbide single crystal substrate 10 on which concave alignment mark 12 having a rectangular cross section as shown in FIG. 2 is formed. In this case, as shown in FIG. 4, alignment mark 22 appears on the surface 20 a of silicon carbide epitaxial film 20 in the region where concave alignment mark 12 was formed. The alignment mark 22 has a shape having inclined surfaces 22a and 22b whose cross-sectional shape is not perpendicular to the main surface 10a, and is different from the alignment mark 12 as shown in FIG.
　検討の結果、ステッパー等の露光装置においては、アライメントマーク２１は認識することはできない場合であっても、アライメントマーク２２は認識することが可能である場合がある。従って、アライメントマーク２１よりも、アライメントマーク２２は認識されやすい。このため、炭化珪素単結晶基板１０の主面１０ａに形成されるアライメントマークは、図１に示されるような凸状のアライメントマーク１１よりも、図２に示されるような凹状のアライメントマーク１２が好ましい。 As a result of examination, in an exposure apparatus such as a stepper, even when the alignment mark 21 cannot be recognized, the alignment mark 22 may be recognized. Therefore, the alignment mark 22 is more easily recognized than the alignment mark 21. For this reason, the alignment mark formed on main surface 10a of silicon carbide single crystal substrate 10 has a concave alignment mark 12 as shown in FIG. 2 rather than a convex alignment mark 11 as shown in FIG. preferable.
　ところで、このようなアライメントマーク２２において、図５に示すように、炭化珪素エピタキシャル膜２０の表面２０ａにフォトレジスト３０等を塗布した場合には、アライメントマーク２２が認識されなくなる場合がある。このようにアライメントマーク２２が認識されなくなると、位置合わせをすることができず、炭化珪素半導体装置を製造することができない。このようにフォトレジスト３０を塗布した場合に、アライメントマーク２２が認識されなくなるのは、アライメント光が傾斜面２２ａ、２２ｂのような緩やかな傾斜部とフォトレジスト３０の表面とにおける干渉することによるものと推察される。傾斜面２２ａ、２２ｂのような緩やかな傾斜部とフォトレジスト３０の表面とにおける干渉では、アライメント光の光量が広い範囲で徐々に連続的に変化するからである。 By the way, in such an alignment mark 22, as shown in FIG. 5, when a photoresist 30 or the like is applied to the surface 20a of the silicon carbide epitaxial film 20, the alignment mark 22 may not be recognized. Thus, if alignment mark 22 is no longer recognized, alignment cannot be performed and a silicon carbide semiconductor device cannot be manufactured. The reason why the alignment mark 22 is not recognized when the photoresist 30 is applied in this manner is that the alignment light interferes with the gently inclined portions such as the inclined surfaces 22 a and 22 b and the surface of the photoresist 30. It is guessed. This is because the light amount of the alignment light gradually and continuously changes in a wide range due to interference between the gently inclined portions such as the inclined surfaces 22a and 22b and the surface of the photoresist 30.
　尚、ステッパー等の露光装置によるアライメントマークを用いたアライメントには、大凡の位置合わせを行うためのラフアライメント機能と、正確な位置合わせを行うファインアライメント機能とが存在しているものがある。ラフアライメントでは、大凡の位置合わせしかできないが、アライメント条件が緩く、図５に示すような炭化珪素エピタキシャル膜２０の表面２０ａにフォトレジスト３０等を塗布した場合であっても、アライメントマークを認識し位置合わせが可能である。一方、ファインアライメントでは、正確な位置合わせのため、アライメント条件が厳しく、図５に示すような炭化珪素エピタキシャル膜２０の表面２０ａにフォトレジスト３０等を塗布した場合は、アライメントマークが認識されず位置合わせをすることができない。 There are some types of alignment using an alignment mark by an exposure apparatus such as a stepper, which have a rough alignment function for roughly aligning and a fine alignment function for accurately aligning. In rough alignment, only approximate positioning is possible, but the alignment conditions are loose, and even when the photoresist 30 or the like is applied to the surface 20a of the silicon carbide epitaxial film 20 as shown in FIG. Alignment is possible. On the other hand, in the fine alignment, alignment conditions are strict for accurate alignment, and when the photoresist 30 or the like is applied to the surface 20a of the silicon carbide epitaxial film 20 as shown in FIG. I can't match.
　実際の炭化珪素半導体装置の製造工程においては、ラフアライメントを行い大凡の位置合わせを行った後、更に、ファインアライメントによる微調整を行い、正確な位置合わせを行って露光を行う。従って、一般的には、炭化珪素半導体装置を製造する際には、ファインアライメントまで行うため、本願において、単にアライメントと記載する場合には、ファインアライメントを意味する場合がある。 In the actual manufacturing process of a silicon carbide semiconductor device, rough alignment is performed and rough alignment is performed, and then fine adjustment by fine alignment is performed to perform accurate alignment and exposure. Therefore, in general, when a silicon carbide semiconductor device is manufactured, fine alignment is performed. Therefore, in the present application, the simple alignment may mean fine alignment.
　よって、凹状のアライメントマーク１２が形成されている炭化珪素単結晶基板１０に炭化珪素エピタキシャル膜２０が成膜され、フォトレジストが塗布されていても、アライメントによる位置合わせが可能な炭化珪素半導体装置の製造方法が求められている。 Therefore, even if silicon carbide epitaxial film 20 is formed on silicon carbide single crystal substrate 10 on which concave alignment mark 12 is formed and a photoresist is applied, silicon carbide semiconductor device capable of alignment by alignment can be used. There is a need for a manufacturing method.
　〔第１の実施の形態〕
　次に、第１の実施の形態における炭化珪素半導体装置の製造方法について、図６Ａから図９Ｂに基づき説明する。 [First Embodiment]
Next, a method for manufacturing the silicon carbide semiconductor device in the first embodiment will be described with reference to FIGS. 6A to 9B.
　最初に、図６Ａに示すように、炭化珪素単結晶基板１１０の主面１１０ａに凹状の第１のアライメントマーク１１１を形成する。具体的には、炭化珪素単結晶基板１１０の主面１１０ａにフォトレジストを塗布し、露光装置による露光、現像を行うことにより、凹状の第１のアライメントマーク１１１が形成される領域に開口部を有する不図示のレジストパターンを形成する。この後、ＲＩＥ（Reactive Ion Etching）等のドライエッチングによりレジストパターンの形成されていない領域の炭化珪素単結晶基板１１０を除去することにより、凹状の第１のアライメントマーク１１１を形成する。この後、不図示のレジストパターンを除去する。このように形成される凹状の第１のアライメントマーク１１１は、底部までの深さｄが約１μｍである。 First, as shown in FIG. 6A, a concave first alignment mark 111 is formed on main surface 110 a of silicon carbide single crystal substrate 110. Specifically, a photoresist is applied to main surface 110a of silicon carbide single crystal substrate 110, and exposure and development are performed by an exposure apparatus, whereby an opening is formed in a region where concave alignment mark 111 is formed. A resist pattern (not shown) is formed. Thereafter, the silicon carbide single crystal substrate 110 in a region where the resist pattern is not formed is removed by dry etching such as RIE (Reactive Ion Etching), thereby forming a concave first alignment mark 111. Thereafter, a resist pattern (not shown) is removed. The concave first alignment mark 111 thus formed has a depth d to the bottom of about 1 μm.
　炭化珪素単結晶基板１１０をドライエッチングにより除去する際には、エッチングガスとしてＳＦ６＋Ｏ２を用い、印加パワー：８００Ｗ、バイアスパワー：４０Ｗ、ドライエッチング装置のチャンバー内の圧力：１Ｐａの条件で行う。また、レジストパターンの除去する際には、酸素アッシングによりレジストパターンを除去した後、ＳＰＭ洗浄、ＲＣＡ洗浄を行う。 When the silicon carbide single crystal substrate 110 is removed by dry etching, SF 6 + O 2 is used as an etching gas, and the applied power is 800 W, the bias power is 40 W, and the pressure in the chamber of the dry etching apparatus is 1 Pa. . When removing the resist pattern, the resist pattern is removed by oxygen ashing, and then SPM cleaning and RCA cleaning are performed.
　炭化珪素単結晶基板１１０は、所定の結晶面からオフ角θだけ傾斜した主面１１０ａを有している。所定の結晶面は、（０００１）面または（０００－１）面が好ましい。炭化珪素単結晶基板１１０における炭化珪素のポリタイプは４Ｈである。４Ｈのポリタイプの炭化珪素は、電子移動度、絶縁破壊電界強度等が、他のポリタイプよりも優れているからである。炭化珪素単結晶基板１１０の径は、１５０ｍｍ以上（たとえば６インチ以上）である。径が大きい程、半導体装置の製造コスト削減に有利であるからである。炭化珪素単結晶基板１１０は、主面１１０ａが｛０００１｝面に対し、＜１１－２０＞方位に４°のオフ角θで傾斜している。尚、本実施形態においては、オフ角θは、０°を越え、６°以下であってもよい。 Silicon carbide single crystal substrate 110 has a main surface 110a inclined by an off angle θ from a predetermined crystal plane. The predetermined crystal plane is preferably a (0001) plane or a (000-1) plane. The silicon carbide polytype in silicon carbide single crystal substrate 110 is 4H. This is because 4H polytype silicon carbide has better electron mobility, breakdown field strength, and the like than other polytypes. Silicon carbide single crystal substrate 110 has a diameter of 150 mm or more (for example, 6 inches or more). This is because the larger the diameter, the more advantageous in reducing the manufacturing cost of the semiconductor device. In silicon carbide single crystal substrate 110, main surface 110a is inclined with respect to the {0001} plane at an off angle θ of 4 ° in the <11-20> orientation. In the present embodiment, the off angle θ may be greater than 0 ° and 6 ° or less.
　次に、図６Ｂに示すように、炭化珪素単結晶基板１１０の主面１１０ａに、エピタキシャル成長により、炭化珪素エピタキシャル膜１２０を形成する。成膜される炭化珪素エピタキシャル膜１２０の膜厚は１μｍ～３μｍである。これにより炭化珪素エピタキシャル膜１２０の表面１２０ａには、凹状の第１のアライメントマーク１１１が形成されていた領域に第２のアライメントマーク１２１が現れる。この第２のアライメントマーク１２１は、断面形状が表面１２０ａに対し傾斜した傾斜面を有する形状である。 Next, as shown in FIG. 6B, a silicon carbide epitaxial film 120 is formed on main surface 110a of silicon carbide single crystal substrate 110 by epitaxial growth. The film thickness of silicon carbide epitaxial film 120 formed is 1 μm to 3 μm. As a result, second alignment mark 121 appears on surface 120a of silicon carbide epitaxial film 120 in the region where concave first alignment mark 111 has been formed. The second alignment mark 121 has a shape having an inclined surface whose cross-sectional shape is inclined with respect to the surface 120a.
　次に、図７Ａに示すように、炭化珪素エピタキシャル膜１２０の表面１２０ａに第１のフォトレジスト１３０を塗布する。第１のフォトレジスト１３０は、膜厚が約２μｍとなるように、スピンコーター等により塗布する。これにより、炭化珪素エピタキシャル膜１２０の表面１２０ａに現れる第２のアライメントマーク１２１は、第１のフォトレジスト１３０に埋め込まれ、第１のフォトレジスト１３０の表面は平坦になる。尚、必要に応じてベーキング等を行う。本願においては、第１のフォトレジスト１３０は、ポジ型のフォトレジストが用いられる。 Next, as shown in FIG. 7A, a first photoresist 130 is applied to the surface 120 a of the silicon carbide epitaxial film 120. The first photoresist 130 is applied by a spin coater or the like so that the film thickness is about 2 μm. Thereby, second alignment mark 121 appearing on surface 120a of silicon carbide epitaxial film 120 is buried in first photoresist 130, and the surface of first photoresist 130 becomes flat. In addition, baking etc. are performed as needed. In the present application, the first photoresist 130 is a positive photoresist.
　次に、図７Ｂに示すように、炭化珪素エピタキシャル膜１２０の表面１２０ａの第２のアライメントマーク１２１の全体を含む領域に、第１のフォトレジスト１３０の第１の開口部１３１を形成する。具体的には、露光装置による露光、現像を行うことにより、第１のフォトレジスト１３０の第１の開口部１３１を形成する。露光装置には、波長３６５ｎｍ（ｉ線）のステッパーが用いられ、現像液には、例えば、ＴＭＡＨ（テトラメチルアンモニウムハイドロオキサイド）等のアルカリ溶液が用いられる。第１の開口部１３１は、第２のアライメントマーク１２１の外形よりも約１０μｍ程広く形成されている。従って、第１の開口部１３１を形成することにより、第１の開口部１３１において、炭化珪素エピタキシャル膜１２０の表面１２０ａの第２のアライメントマーク１２１が露出する。尚、第１の開口部１３１を形成する際には、位置合わせを行う必要があるが、この位置合わせは、ステッパーのラフアライメントや目視等により行う。 Next, as shown in FIG. 7B, a first opening 131 of the first photoresist 130 is formed in a region including the entire second alignment mark 121 on the surface 120a of the silicon carbide epitaxial film 120. Specifically, the first opening 131 of the first photoresist 130 is formed by performing exposure and development with an exposure apparatus. A stepper having a wavelength of 365 nm (i-line) is used for the exposure apparatus, and an alkaline solution such as TMAH (tetramethylammonium hydroxide) is used for the developer. The first opening 131 is formed to be approximately 10 μm wider than the outer shape of the second alignment mark 121. Therefore, by forming first opening 131, second alignment mark 121 on surface 120 a of silicon carbide epitaxial film 120 is exposed in first opening 131. In addition, when forming the 1st opening part 131, it is necessary to align, but this alignment is performed by rough alignment, visual observation, etc. of a stepper.
　次に、図８Ａに示すように、後述する凹状の第３のアライメントマーク１２２が形成される領域に、第１のフォトレジスト１３０の第２の開口部１３２を形成する。具体的には、第１のフォトレジスト１３０の第１の開口部１３１において露出している第２のアライメントマーク１２１を用いて、位置合わせを行い露光装置による露光、現像を行う。これにより、所定の位置に第１のフォトレジスト１３０の第２の開口部１３２を形成する。露光装置には、波長３６５ｎｍのステッパーが用いられ、現像液には、例えば、ＴＭＡＨ等のアルカリ溶液が用いられる。この工程においては、第１のフォトレジスト１３０の第１の開口部１３１において露出している第２のアライメントマーク１２１を用いることができるため、ファインアライメントにより正確な位置合わせを行うことができる。これにより、第１のフォトレジスト１３０の所望の位置に正確に第２の開口部１３２を形成することができる。 Next, as shown in FIG. 8A, a second opening 132 of the first photoresist 130 is formed in a region where a concave third alignment mark 122 described later is formed. Specifically, alignment is performed using the second alignment mark 121 exposed in the first opening 131 of the first photoresist 130, and exposure and development are performed by an exposure apparatus. Thereby, the second opening 132 of the first photoresist 130 is formed at a predetermined position. A stepper having a wavelength of 365 nm is used for the exposure apparatus, and an alkaline solution such as TMAH is used for the developer. In this step, since the second alignment mark 121 exposed in the first opening 131 of the first photoresist 130 can be used, accurate alignment can be performed by fine alignment. Thereby, the second opening 132 can be accurately formed at a desired position of the first photoresist 130.
　次に、図８Ｂに示すように、第１のフォトレジスト１３０の第２の開口部１３２において露出している炭化珪素エピタキシャル膜１２０の一部を除去することにより、凹状の第３のアライメントマーク１２２を形成する。具体的には、ＲＩＥ等のドライエッチングにより、第１のフォトレジスト１３０の第２の開口部１３２において露出している炭化珪素エピタキシャル膜１２０を除去することにより、凹状の第３のアライメントマーク１２２を形成する。このように形成される凹状の第３のアライメントマーク１２２の底部までの深さは約０．５μｍ～１．０μｍである。このような凹状の第３のアライメントマーク１２２は、炭化珪素半導体装置を製造する際のダイシングソーにより切断されるスクライブラインとなる領域に形成してもよい。炭化珪素エピタキシャル膜１２０を除去する際には、エッチングガスとしてＳＦ６＋Ｏ２を用い、印加パワー：８００Ｗ、バイアスパワー：４０Ｗ、ドライエッチング装置のチャンバー内の圧力：１Ｐａの条件で行う。この際、第１のフォトレジスト１３０の第１の開口部１３１において露出している第２のアライメントマーク１２１が形成されている領域の炭化珪素エピタキシャル膜１２０も同時に一部除去されるが、炭化珪素半導体装置の製造に支障をきたすことはない。 Next, as shown in FIG. 8B, a part of the silicon carbide epitaxial film 120 exposed in the second opening 132 of the first photoresist 130 is removed, thereby forming a concave third alignment mark 122. Form. Specifically, the silicon carbide epitaxial film 120 exposed in the second opening 132 of the first photoresist 130 is removed by dry etching such as RIE, so that the concave third alignment mark 122 is formed. Form. The depth to the bottom of the concave third alignment mark 122 formed in this way is about 0.5 μm to 1.0 μm. Such concave third alignment mark 122 may be formed in a region to be a scribe line cut by a dicing saw when manufacturing the silicon carbide semiconductor device. When removing silicon carbide epitaxial film 120, SF 6 + O 2 is used as an etching gas under the conditions of applied power: 800 W, bias power: 40 W, and pressure in the chamber of the dry etching apparatus: 1 Pa. At this time, the silicon carbide epitaxial film 120 in the region where the second alignment mark 121 exposed in the first opening 131 of the first photoresist 130 is formed is also partially removed at the same time. There is no hindrance to the manufacture of the semiconductor device.
　次に、図９Ａに示すように、第１のフォトレジスト１３０を除去する。第１のフォトレジスト１３０の除去する際には、酸素アッシングにより第１のフォトレジスト１３０を除去した後、ＳＰＭ洗浄、ＲＣＡ洗浄を行う。この後の炭化珪素半導体装置の製造工程においては、形成された凹状の第３のアライメントマーク１２２を用いて位置合わせを行うことにより、正確な位置合わせを行うことができ、所望の炭化珪素半導体装置を高い歩留まりで製造することができる。 Next, as shown in FIG. 9A, the first photoresist 130 is removed. When removing the first photoresist 130, after removing the first photoresist 130 by oxygen ashing, SPM cleaning and RCA cleaning are performed. In the subsequent manufacturing process of the silicon carbide semiconductor device, accurate alignment can be performed by performing alignment using the formed concave third alignment mark 122, and a desired silicon carbide semiconductor device can be obtained. Can be manufactured at a high yield.
　具体的には、凹状の第３のアライメントマーク１２２は矩形の凹状のアライメントマークであり、この後、図９Ｂに示すように、第２のフォトレジスト１４０が塗布されている場合であっても、露光装置によるファインアライメントによる位置合わせが可能である。従って、凹状の第３のアライメントマーク１２２を用いて位置合わせを行い、露光することにより、炭化珪素半導体装置を高い歩留まりで製造することができる。 Specifically, the concave third alignment mark 122 is a rectangular concave alignment mark, and after that, as shown in FIG. 9B, even when the second photoresist 140 is applied, Positioning by fine alignment by an exposure apparatus is possible. Therefore, the silicon carbide semiconductor device can be manufactured with a high yield by performing alignment using the concave third alignment mark 122 and performing exposure.
　〔第２の実施の形態〕
　次に、第２の実施の形態における炭化珪素半導体装置の製造方法について、図１０Ａから図１２Ｂに基づき説明する。 [Second Embodiment]
Next, the manufacturing method of the silicon carbide semiconductor device in 2nd Embodiment is demonstrated based on FIG. 10A to FIG. 12B.
　最初に、図１０Ａに示すように、炭化珪素単結晶基板１１０の主面１１０ａに凹状の第１のアライメントマーク１１１を形成する。 First, as shown in FIG. 10A, a concave first alignment mark 111 is formed on main surface 110 a of silicon carbide single crystal substrate 110.
　次に、図１０Ｂに示すように、炭化珪素単結晶基板１１０の主面１１０ａに、エピタキシャル成長により、炭化珪素エピタキシャル膜１２０を形成する。 Next, as shown in FIG. 10B, silicon carbide epitaxial film 120 is formed on main surface 110a of silicon carbide single crystal substrate 110 by epitaxial growth.
　次に、図１１Ａに示すように、炭化珪素エピタキシャル膜１２０の表面１２０ａに第１のフォトレジスト１３０を塗布する。 Next, as shown in FIG. 11A, a first photoresist 130 is applied to the surface 120 a of the silicon carbide epitaxial film 120.
　次に、図１１Ｂに示すように、第２のアライメントマーク１２１の全体を含む領域の炭化珪素エピタキシャル膜１２０の表面１２０ａに、第１のフォトレジスト１３０の第１の開口部１３１を形成する。 Next, as shown in FIG. 11B, a first opening 131 of the first photoresist 130 is formed on the surface 120a of the silicon carbide epitaxial film 120 in a region including the entire second alignment mark 121. Next, as shown in FIG.
　次に、図１２Ａに示すように、後述する炭化珪素エピタキシャル膜１２０のｎ＋領域２２１が形成される領域に、第１のフォトレジスト１３０の第２の開口部２３２を形成する。具体的には、第１のフォトレジスト１３０の第１の開口部１３１において露出している第２のアライメントマーク１２１を用いて、位置合わせを行い露光装置による露光、現像を行う。これにより、所定の位置に第１のフォトレジスト１３０の第２の開口部２３２を形成する。この工程においては、第１のフォトレジスト１３０の第１の開口部１３１において露出している第２のアライメントマーク１２１を用いることができるため、ファインアライメントにより正確な位置合わせを行うことができる。これにより、第１のフォトレジスト１３０の所望の位置に正確に第２の開口部２３２を形成することができる。 Next, as shown in FIG. 12A, a second opening 232 of the first photoresist 130 is formed in a region where an n + region 221 of a silicon carbide epitaxial film 120 described later is formed. Specifically, alignment is performed using the second alignment mark 121 exposed in the first opening 131 of the first photoresist 130, and exposure and development are performed by an exposure apparatus. Thus, the second opening 232 of the first photoresist 130 is formed at a predetermined position. In this step, since the second alignment mark 121 exposed in the first opening 131 of the first photoresist 130 can be used, accurate alignment can be performed by fine alignment. As a result, the second opening 232 can be accurately formed at a desired position of the first photoresist 130.
　次に、図１２Ｂに示すように、第１のフォトレジスト１３０の第２の開口部２３２において露出している炭化珪素エピタキシャル膜１２０に、ｎ型となる不純物元素をイオン注入することにより、ｎ＋領域２２１を形成する。ｎ型となる不純物元素としてはＰを用い、加速エネルギー：１０ｋｅＶ～９００ｋｅＶ、ドーズ量：１×１０１１ｃｍ－２～１×１０１６ｃｍ－２の条件でイオン注入を行う。尚、炭化珪素エピタキシャル膜１２０にｎ＋領域２２１に代えて、ｐ＋領域を形成する場合には、イオン注入する不純物元素をＡｌにする。この後、第１のフォトレジスト１３０を除去する。 Next, as shown in FIG. 12B, n + -type impurity elements are ion-implanted into the silicon carbide epitaxial film 120 exposed in the second opening 232 of the first photoresist 130, whereby n + Region 221 is formed. P is used as an n-type impurity element, and ion implantation is performed under the conditions of acceleration energy: 10 keV to 900 keV and dose amount: 1 × 10 11 cm −2 to 1 × 10 16 cm −2 . When a p + region is formed in silicon carbide epitaxial film 120 instead of n + region 221, the impurity element to be ion-implanted is Al. Thereafter, the first photoresist 130 is removed.
　本実施の形態における炭化珪素半導体装置を製造方法においては、第１のフォトレジスト１３０の第２の開口部２３２は、いわゆる素子領域に形成される。また、本実施の形態は、第１のフォトレジスト１３０の第２の開口部２３２が形成されている領域の炭化珪素エピタキシャル膜１２０をエッチングにより除去することによりトレンチ等を形成するものであってもよい。 In the method for manufacturing the silicon carbide semiconductor device in the present embodiment, second opening 232 of first photoresist 130 is formed in a so-called element region. Further, in the present embodiment, a trench or the like is formed by removing silicon carbide epitaxial film 120 in the region where second opening 232 of first photoresist 130 is formed by etching. Good.
　尚、上記以外の内容については、第１の実施の形態と同様である。 The contents other than the above are the same as those in the first embodiment.
　〔第３の実施の形態〕
　次に、第３の実施の形態における炭化珪素半導体装置の製造方法について、図１３Ａから図１９Ｂに基づき説明する。 [Third Embodiment]
Next, a method for manufacturing the silicon carbide semiconductor device in the third embodiment will be described with reference to FIGS. 13A to 19B.
　最初に、図１３Ａに示すように、炭化珪素単結晶基板１１０の主面１１０ａに凹状の第１のアライメントマーク１１１を形成する。 First, as shown in FIG. 13A, a concave first alignment mark 111 is formed on main surface 110a of silicon carbide single crystal substrate 110.
　次に、図１３Ｂに示すように、炭化珪素単結晶基板１１０の主面１１０ａに、エピタキシャル成長により、炭化珪素エピタキシャル膜１２０を形成する。 Next, as shown in FIG. 13B, a silicon carbide epitaxial film 120 is formed on main surface 110a of silicon carbide single crystal substrate 110 by epitaxial growth.
　次に、図１４Ａに示すように、炭化珪素エピタキシャル膜１２０の表面１２０ａに第１のフォトレジスト１３０を塗布する。 Next, as shown in FIG. 14A, a first photoresist 130 is applied to the surface 120 a of the silicon carbide epitaxial film 120.
　次に、図１４Ｂに示すように、炭化珪素エピタキシャル膜１２０の表面１２０ａの第２のアライメントマーク１２１の全体を含む領域に、第１のフォトレジスト１３０の第１の開口部１３１を形成する。 Next, as shown in FIG. 14B, a first opening 131 of the first photoresist 130 is formed in a region including the entire second alignment mark 121 on the surface 120 a of the silicon carbide epitaxial film 120.
　次に、図１５Ａに示すように、後述する凹状の第３のアライメントマーク１２２が形成される領域に、第１のフォトレジスト１３０の第２の開口部１３２を形成する。 Next, as shown in FIG. 15A, a second opening 132 of the first photoresist 130 is formed in a region where a concave third alignment mark 122 described later is formed.
　次に、図１５Ｂに示すように、第１のフォトレジスト１３０の第２の開口部１３２において露出している炭化珪素エピタキシャル膜１２０を除去することにより、凹状の第３のアライメントマーク１２２を形成する。 Next, as shown in FIG. 15B, the silicon carbide epitaxial film 120 exposed in the second opening 132 of the first photoresist 130 is removed, thereby forming a concave third alignment mark 122. .
　次に、図１６Ａに示すように、第１のフォトレジスト１３０を除去する。 Next, as shown in FIG. 16A, the first photoresist 130 is removed.
　次に、図１６Ｂに示すように、炭化珪素エピタキシャル膜１２０の表面１２０ａに、膜厚が約２μｍの酸化シリコン膜３５０を成膜する。 Next, as shown in FIG. 16B, a silicon oxide film 350 having a thickness of about 2 μm is formed on the surface 120 a of the silicon carbide epitaxial film 120.
　次に、図１７Ａに示すように、酸化シリコン膜３５０の上にフォトレジスト３６０を塗布する。塗布されるフォトレジスト３６０の厚さは、約２．５μｍである。 Next, as shown in FIG. 17A, a photoresist 360 is applied on the silicon oxide film 350. The thickness of the applied photoresist 360 is about 2.5 μm.
　次に、図１７Ｂに示すように、炭化珪素エピタキシャル膜１２０においてｎ＋領域３２１が形成される領域に、フォトレジスト３６０の第３の開口部３６１を形成する。具体的には、炭化珪素エピタキシャル膜１２０に形成されている凹状の第３のアライメントマーク１２２を用いて位置合わせを行い、露光装置による露光、現像を行うことにより、フォトレジスト３６０に第３の開口部３６１を形成する。この工程においては、炭化珪素エピタキシャル膜１２０の表面１２０ａに対し略垂直な側面を有する凹状の第３のアライメントマーク１２２を用いることができる。従って、凹状の第３のアライメントマーク１２２の上に酸化シリコン膜３５０が成膜されていても、凹状の第３のアライメントマーク１２２は、露光装置において認識可能である。よって、凹状の第３のアライメントマーク１２２を用いてファインアライメントにより正確な位置合わせを行うことができる。これにより、フォトレジスト３６０の所望の位置に正確に第３の開口部３６１を形成することができる。 Next, as shown in FIG. 17B, a third opening 361 of photoresist 360 is formed in a region where n + region 321 is formed in silicon carbide epitaxial film 120. Specifically, alignment is performed using a concave third alignment mark 122 formed in the silicon carbide epitaxial film 120, and exposure and development are performed by an exposure apparatus, whereby a third opening is formed in the photoresist 360. A portion 361 is formed. In this step, concave third alignment mark 122 having a side surface substantially perpendicular to surface 120a of silicon carbide epitaxial film 120 can be used. Therefore, even if the silicon oxide film 350 is formed on the concave third alignment mark 122, the concave third alignment mark 122 can be recognized by the exposure apparatus. Therefore, accurate alignment can be performed by fine alignment using the concave third alignment mark 122. Thereby, the third opening 361 can be accurately formed at a desired position of the photoresist 360.
　次に、図１８Ａに示すように、フォトレジスト３６０の第３の開口部３６１における酸化シリコン膜３５０をＲＩＥ等のドライエッチングにより除去することにより開口部３５１を形成する。これにより、残存する酸化シリコン膜３５０によりイオン注入マスクが形成される。酸化シリコン膜３５０を除去する際には、エッチングガスとして、ＣＦ４、ＣＨＦ３、Ａｒの混合ガスを用い、印加パワー：５００Ｗ、バイアスパワー：５０Ｗ、ドライエッチング装置のチャンバー内の圧力：１Ｐａの条件で行う。これにより、フォトレジスト３６０の第３の開口部３６１における酸化シリコン膜３５０を炭化珪素エピタキシャル膜１２０の表面１２０ａが露出するまで除去し、酸化シリコン膜３５０に開口部３５１を形成し、イオン注入マスクを形成する。 Next, as shown in FIG. 18A, the silicon oxide film 350 in the third opening 361 of the photoresist 360 is removed by dry etching such as RIE to form an opening 351. Thereby, an ion implantation mask is formed by the remaining silicon oxide film 350. When removing the silicon oxide film 350, a mixed gas of CF 4 , CHF 3 , and Ar is used as an etching gas, the applied power is 500 W, the bias power is 50 W, and the pressure in the chamber of the dry etching apparatus is 1 Pa. To do. Thus, silicon oxide film 350 in third opening 361 of photoresist 360 is removed until surface 120a of silicon carbide epitaxial film 120 is exposed, opening 351 is formed in silicon oxide film 350, and an ion implantation mask is used. Form.
　次に、図１８Ｂに示すように、フォトレジスト３６０を除去する。フォトレジスト３６０の除去する際には、酸素アッシングによりフォトレジスト３６０を除去した後、ＳＰＭ洗浄、ＲＣＡ洗浄を行う。 Next, as shown in FIG. 18B, the photoresist 360 is removed. When removing the photoresist 360, after removing the photoresist 360 by oxygen ashing, SPM cleaning and RCA cleaning are performed.
　次に、図１９Ａに示すように、開口部３５１を有する酸化シリコン膜３５０をイオン注入マスクとして、領域の炭化珪素エピタキシャル膜１２０に、ｎ型となる不純物元素をイオン注入することにより、ｎ＋領域３２１を形成する。ｎ型となる不純物元素としてはＰを用い、加速エネルギー：１０ｋｅＶ～９００ｋｅＶ、ドーズ量：１×１０１１ｃｍ－２～１×１０１６ｃｍ－２の条件でイオン注入を行う。尚、炭化珪素エピタキシャル膜１２０にｎ＋領域３２１に代えて、ｐ＋領域を形成する場合には、不純物元素をＰからＡｌに代えてイオン注入する。 Next, as shown in FIG. 19A, an n + region is formed by ion-implanting an n-type impurity element into the silicon carbide epitaxial film 120 in the region using the silicon oxide film 350 having the opening 351 as an ion implantation mask. 321 is formed. P is used as an n-type impurity element, and ion implantation is performed under the conditions of acceleration energy: 10 keV to 900 keV and dose amount: 1 × 10 11 cm −2 to 1 × 10 16 cm −2 . When a p + region is formed in silicon carbide epitaxial film 120 instead of n + region 321, an impurity element is ion-implanted instead of P to Al.
　次に、図１９Ｂに示すように、酸化シリコン膜３５０をウェットエッチングにより除去する。酸化シリコン膜３５０を除去する際には、エッチング液としてＨＦ（フッ酸）またはＢＨＦ（バッファードフッ酸）を用いる。 Next, as shown in FIG. 19B, the silicon oxide film 350 is removed by wet etching. When the silicon oxide film 350 is removed, HF (hydrofluoric acid) or BHF (buffered hydrofluoric acid) is used as an etchant.
　尚、上記以外の内容については、第１の実施の形態と同様である。 The contents other than the above are the same as those in the first embodiment.
　以上、実施形態について詳述したが、特定の実施形態に限定されるものではなく、請求の範囲に記載された範囲内において、種々の変形及び変更が可能である。 As mentioned above, although embodiment was explained in full detail, it is not limited to specific embodiment, A various deformation | transformation and change are possible within the range described in the claim.
１０　　　　炭化珪素単結晶基板
１０ａ　　　主面
１１　　　　凸状のアライメントマーク
１２　　　　凹状のアライメントマーク
２０　　　　炭化珪素エピタキシャル膜
２０ａ　　　表面
２１　　　　アライメントマーク
２１ａ　　　傾斜面
２２　　　　アライメントマーク
２２ａ、２２ｂ　　　傾斜面
３０　　　　フォトレジスト
１１０　　　炭化珪素単結晶基板
１１０ａ　　主面
１１１　　　第１のアライメントマーク
１２０　　　炭化珪素エピタキシャル膜
１２０ａ　　表面
１２１　　　第２のアライメントマーク
１２２　　　第３のアライメントマーク
１３０　　　第１のフォトレジスト
１３１　　　第１の開口部
１３２　　　第２の開口部
１４０　　　第２のフォトレジスト
２２１　　　ｎ＋領域
２３２　　　第２の開口部
３２１　　　ｎ＋領域
３５０　　　酸化シリコン膜
３５１　　　開口部
３６０　　　フォトレジスト
３６１　　　第３の開口部 DESCRIPTION OF SYMBOLS 10 Silicon carbide single crystal substrate 10a Main surface 11 Convex alignment mark 12 Concave alignment mark 20 Silicon carbide epitaxial film 20a Surface 21 Alignment mark 21a Inclined surface 22 Alignment marks 22a and 22b Inclined surface 30 Photoresist 110 Silicon carbide single crystal substrate 110a Main surface 111 First alignment mark 120 Silicon carbide epitaxial film 120a Surface 121 Second alignment mark 122 Third alignment mark 130 First photoresist 131 First opening 132 Second opening 140 Second Photoresist 221 n + region 232 Second opening 321 n + region 350 Silicon oxide film 351 Opening 360 Photoresist 361 Third opening

Claims (10)

  1. 　凹状の第１のアライメントマークが形成されている炭化珪素結晶基板に、炭化珪素エピタキシャル膜を成膜することにより、前記第１のアライメントマークの上の前記炭化珪素エピタキシャル膜の表面に凹状の第２のアライメントマークを形成する工程と、
    　前記炭化珪素エピタキシャル膜の表面に第１のフォトレジストを塗布する工程と、
    　前記第２のアライメントマークを含む領域の前記第１のフォトレジストを除去し、第１の開口部を形成する工程と、
    　前記第１の開口部において露出している前記第２のアライメントマークを用いて位置合わせを行い、前記第１のフォトレジストに第２の開口部を形成する工程と、
    　を有する炭化珪素半導体装置の製造方法。     By forming a silicon carbide epitaxial film on the silicon carbide crystal substrate on which the concave first alignment mark is formed, a concave second is formed on the surface of the silicon carbide epitaxial film on the first alignment mark. Forming an alignment mark of
    Applying a first photoresist to the surface of the silicon carbide epitaxial film;
    Removing the first photoresist in a region including the second alignment mark to form a first opening;
    Performing alignment using the second alignment mark exposed in the first opening, and forming a second opening in the first photoresist;
    A method for manufacturing a silicon carbide semiconductor device comprising:
  2. 　前記第２の開口部を形成する工程の後、
    　前記第２の開口部における前記炭化珪素エピタキシャル膜の一部を除去し、第３のアライメントマークを形成する工程と、
    　前記第１のフォトレジストを除去する工程と、
    　を有する請求項１に記載の炭化珪素半導体装置の製造方法。     After the step of forming the second opening,
    Removing a part of the silicon carbide epitaxial film in the second opening to form a third alignment mark;
    Removing the first photoresist;
    The manufacturing method of the silicon carbide semiconductor device of Claim 1 which has these.
  3. 　前記第１のフォトレジストを除去する工程の後、
    　前記炭化珪素エピタキシャル膜の表面に第２のフォトレジストを塗布する工程と、
    　前記第３のアライメントマークを用いて位置合わせを行い、前記第２のフォトレジストに第３の開口部を形成する工程と、
    　を有する請求項２に記載の炭化珪素半導体装置の製造方法。     After the step of removing the first photoresist,
    Applying a second photoresist to the surface of the silicon carbide epitaxial film;
    Performing alignment using the third alignment mark and forming a third opening in the second photoresist;
    The manufacturing method of the silicon carbide semiconductor device of Claim 2 which has these.
  4. 　凹状の第１のアライメントマークが形成されている炭化珪素結晶基板に、炭化珪素エピタキシャル膜を成膜する工程と、
    　前記炭化珪素エピタキシャル膜の表面に第１のフォトレジストを塗布する工程と、
    　前記第１のアライメントマークの上の炭化珪素エピタキシャル膜の表面に形成された第２のアライメントマークを含む領域の前記第１のフォトレジストを除去し、第１の開口部を形成する工程と、
    　前記第１の開口部において露出している前記第２のアライメントマークを用いて位置合わせを行い、前記第１のフォトレジストに第２の開口部を形成する工程と、
    　前記第２の開口部における前記炭化珪素エピタキシャル膜を加工する工程と、
    　前記第１のフォトレジストを除去する工程と、
    　を有する炭化珪素半導体装置の製造方法。     Forming a silicon carbide epitaxial film on the silicon carbide crystal substrate on which the concave first alignment mark is formed;
    Applying a first photoresist to the surface of the silicon carbide epitaxial film;
    Removing the first photoresist in a region including the second alignment mark formed on the surface of the silicon carbide epitaxial film on the first alignment mark, and forming a first opening;
    Performing alignment using the second alignment mark exposed in the first opening, and forming a second opening in the first photoresist;
    Processing the silicon carbide epitaxial film in the second opening;
    Removing the first photoresist;
    A method for manufacturing a silicon carbide semiconductor device comprising:
  5. 　前記加工は、前記炭化珪素エピタキシャル膜のエッチングである請求項４に記載の炭化珪素半導体装置の製造方法。 The method of manufacturing a silicon carbide semiconductor device according to claim 4, wherein the processing is etching of the silicon carbide epitaxial film.
  6. 　前記加工は、前記炭化珪素エピタキシャル膜へのイオン注入である請求項４に記載の炭化珪素半導体装置の製造方法。 The method for manufacturing a silicon carbide semiconductor device according to claim 4, wherein the processing is ion implantation into the silicon carbide epitaxial film.
  7. 　前記第１のフォトレジストは、ポジ型である請求項１から請求項６のいずれか１項に記載の炭化珪素半導体装置の製造方法。 The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the first photoresist is a positive type.
  8. 　前記第１の開口部及び前記第２の開口部は、
    　前記第１のフォトレジストを露光する工程と、
    　露光された前記第１のフォトレジストを現像する工程と、
    　により形成される請求項１から請求項７のいずれか１項に記載の炭化珪素半導体装置の製造方法。     The first opening and the second opening are:
    Exposing the first photoresist;
    Developing the exposed first photoresist;
    The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 7, formed by:
  9. 　凹状の第１のアライメントマークが形成されている炭化珪素結晶基板に、炭化珪素エピタキシャル膜を成膜することにより、前記第１のアライメントマークの上の前記炭化珪素エピタキシャル膜の表面に凹状の第２のアライメントマークを形成する工程と、
    　前記炭化珪素エピタキシャル膜の表面に第１のフォトレジストを塗布する工程と、
    　前記第２のアライメントマークを含む領域の前記第１のフォトレジストを除去し、第１の開口部を形成する工程と、
    　前記第１の開口部において露出している前記第２のアライメントマークを用いて位置合わせを行い、前記第１のフォトレジストに第２の開口部を形成する工程と、
    　を有し、
    　前記第２の開口部を形成する工程の後、
    　前記第２の開口部における前記炭化珪素エピタキシャル膜の一部を除去し、第３のアライメントマークを形成する工程と、
    　前記第１のフォトレジストを除去する工程と、
    　を有し、
    　前記第１のフォトレジストを除去する工程の後、
    　前記炭化珪素エピタキシャル膜の表面に第２のフォトレジストを塗布する工程と、
    　前記第３のアライメントマークを用いて位置合わせを行い、前記第２のフォトレジストに第３の開口部を形成する工程と、
    　を有し、
    　前記第１のフォトレジストは、ポジ型であって、
    　前記第１の開口部及び前記第２の開口部は、
    　前記第１のフォトレジストを露光する工程と、
    　露光された前記第１のフォトレジストを現像する工程と、
    　により形成される炭化珪素半導体装置の製造方法。     By forming a silicon carbide epitaxial film on the silicon carbide crystal substrate on which the concave first alignment mark is formed, a concave second is formed on the surface of the silicon carbide epitaxial film on the first alignment mark. Forming an alignment mark of
    Applying a first photoresist to the surface of the silicon carbide epitaxial film;
    Removing the first photoresist in a region including the second alignment mark to form a first opening;
    Performing alignment using the second alignment mark exposed in the first opening, and forming a second opening in the first photoresist;
    Have
    After the step of forming the second opening,
    Removing a part of the silicon carbide epitaxial film in the second opening to form a third alignment mark;
    Removing the first photoresist;
    Have
    After the step of removing the first photoresist,
    Applying a second photoresist to the surface of the silicon carbide epitaxial film;
    Performing alignment using the third alignment mark and forming a third opening in the second photoresist;
    Have
    The first photoresist is a positive type,
    The first opening and the second opening are:
    Exposing the first photoresist;
    Developing the exposed first photoresist;
    The manufacturing method of the silicon carbide semiconductor device formed by this.
  10. 　凹状の第１のアライメントマークが形成されている炭化珪素結晶基板に、炭化珪素エピタキシャル膜を成膜する工程と、
    　前記炭化珪素エピタキシャル膜の表面に第１のフォトレジストを塗布する工程と、
    　前記第１のアライメントマークの上の炭化珪素エピタキシャル膜の表面に形成された第２のアライメントマークを含む領域の前記第１のフォトレジストを除去し、第１の開口部を形成する工程と、
    　前記第１の開口部において露出している前記第２のアライメントマークを用いて位置合わせを行い、前記第１のフォトレジストに第２の開口部を形成する工程と、
    　前記第２の開口部における前記炭化珪素エピタキシャル膜を加工する工程と、
    　前記第１のフォトレジストを除去する工程と、
    　を有し、
    　前記第１のフォトレジストは、ポジ型であって、
    　前記第１の開口部及び前記第２の開口部は、
    　前記第１のフォトレジストを露光する工程と、
    　露光された前記第１のフォトレジストを現像する工程と、
    　により形成される炭化珪素半導体装置の製造方法。     Forming a silicon carbide epitaxial film on the silicon carbide crystal substrate on which the concave first alignment mark is formed;
    Applying a first photoresist to the surface of the silicon carbide epitaxial film;
    Removing the first photoresist in a region including the second alignment mark formed on the surface of the silicon carbide epitaxial film on the first alignment mark, and forming a first opening;
    Performing alignment using the second alignment mark exposed in the first opening, and forming a second opening in the first photoresist;
    Processing the silicon carbide epitaxial film in the second opening;
    Removing the first photoresist;
    Have
    The first photoresist is a positive type,
    The first opening and the second opening are:
    Exposing the first photoresist;
    Developing the exposed first photoresist;
    The manufacturing method of the silicon carbide semiconductor device formed by this.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021092718A (en) * 2019-12-12 2021-06-17 トヨタ自動車株式会社 Method for producing semiconductor device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278658A (en) * 2005-03-29 2006-10-12 Seiko Epson Corp Process for fabricating semiconductor device
JP2006278657A (en) * 2005-03-29 2006-10-12 Seiko Epson Corp Process for fabricating semiconductor device
JP2008053363A (en) * 2006-08-23 2008-03-06 Matsushita Electric Ind Co Ltd Semiconductor substrate, and its manufacturing method
JP2013021040A (en) * 2011-07-08 2013-01-31 Mitsubishi Electric Corp Silicon carbide semiconductor device manufacturing method and silicon carbide semiconductor device
JP2013183064A (en) * 2012-03-02 2013-09-12 Toshiba Corp Method of manufacturing semiconductor device
JP2015126110A (en) * 2013-12-26 2015-07-06 住友電気工業株式会社 Silicon carbide semiconductor device manufacturing method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006278658A (en) * 2005-03-29 2006-10-12 Seiko Epson Corp Process for fabricating semiconductor device
JP2006278657A (en) * 2005-03-29 2006-10-12 Seiko Epson Corp Process for fabricating semiconductor device
JP2008053363A (en) * 2006-08-23 2008-03-06 Matsushita Electric Ind Co Ltd Semiconductor substrate, and its manufacturing method
JP2013021040A (en) * 2011-07-08 2013-01-31 Mitsubishi Electric Corp Silicon carbide semiconductor device manufacturing method and silicon carbide semiconductor device
JP2013183064A (en) * 2012-03-02 2013-09-12 Toshiba Corp Method of manufacturing semiconductor device
JP2015126110A (en) * 2013-12-26 2015-07-06 住友電気工業株式会社 Silicon carbide semiconductor device manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021092718A (en) * 2019-12-12 2021-06-17 トヨタ自動車株式会社 Method for producing semiconductor device
JP7264034B2 (en) 2019-12-12 2023-04-25 株式会社デンソー Semiconductor device manufacturing method

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