JP6673232B2 - 炭化珪素半導体装置 - Google Patents
炭化珪素半導体装置 Download PDFInfo
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- JP6673232B2 JP6673232B2 JP2017006003A JP2017006003A JP6673232B2 JP 6673232 B2 JP6673232 B2 JP 6673232B2 JP 2017006003 A JP2017006003 A JP 2017006003A JP 2017006003 A JP2017006003 A JP 2017006003A JP 6673232 B2 JP6673232 B2 JP 6673232B2
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims description 54
- 229910010271 silicon carbide Inorganic materials 0.000 title claims description 54
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Description
第1実施形態について説明する。ここでは半導体素子で構成されるパワー素子としてトレンチゲート構造の反転型のMOSFETが形成されたSiC半導体装置を例に挙げて説明する。
このように求められるファセット長Lに基づき、p型ディープ層30とトレンチゲート構造の先端との距離については、n+型基板1の表面に対する法線方向から見て、ファセット面Fがトレンチゲート構造の先端とオーバラップしない長さに設定してある。例えば、膜厚tが0.8μm、オフ角θが4°、凹部5aのエッチング量が0.4μmである場合、ファセット長Lは6μm程度になる。
まず、半導体基板として、n+型基板1の主表面上にSiCからなるn-型ドリフト層2をエピタキシャル成長させたものを用意する。
続いて、マスク40を配置し、p型ディープ層5やp型ディープ層30およびp型ガードリング21の形成予定領域においてマスク40を開口させる。そして、マスク40を用いてRIE(Reactive Ion Etching)などの異方性エッチングを行うことにより、凹部5a、21a、30aを形成する。さらに、マスク40を用いてp型不純物をイオン注入する。これにより、p型ディープ層5とp型ディープ層30およびp型ガードリング21が形成される。
マスク40を除去した後、p型ディープ層5とp型ディープ層30およびp型ガードリング21の上を含めて、n-型ドリフト層2の上にp型ベース領域3をエピタキシャル成長させる。このとき、図6および図7中には記載していないが、図5に示したように、凹部30aが形成されることに起因して、p型ディープ層30の表面にファセット面Fが形成される。
p型ディープ層30の上に図示しないマスクを配置したのち、マスクのうちn+型ソース領域4の形成予定領域を開口させる。そして、そのマスクを用いてn型不純物をイオン注入することでn+型ソース領域4を形成する。さらに、マスクを除去したのち、改めて図示しないマスクを配置し、マスクのうちのp型コンタクト領域3aの形成予定領域を開口させる。そして、そのマスクを用いてp型不純物をイオン注入することでp型コンタクト領域3aを形成する。
n+型ソース領域4やp型ベース領域3などの上に図示しないマスクを形成したのち、マスクのうちのゲートトレンチ6の形成予定領域を開口させる。そして、マスクを用いてRIEなどの異方性エッチングを行うことで、p型ディープ層5よりも浅い深さのゲートトレンチ6を形成する。
マスクを除去した後、例えば熱酸化を行うことによって、ゲート絶縁膜7を形成し、ゲート絶縁膜7によってゲートトレンチ6の内壁面上およびn+型ソース領域4の表面上を覆う。そして、p型不純物もしくはn型不純物がドープされたPoly−Siをデポジションした後、これをエッチバックし、少なくともゲートトレンチ6内にPoly−Siを残すことでゲート電極8を形成する。
ゲート電極8およびゲート絶縁膜7の表面を覆うように、例えば酸化膜などによって構成される層間絶縁膜10を形成する。そして、層間絶縁膜10の表面上に図示しないマスクを形成したのち、マスクのうち各ゲート電極8の間に位置する部分、つまりp型コンタクト領域3aと対応する部分およびその近傍を開口させる。この後、マスクを用いて層間絶縁膜10をパターニングすることでp型コンタクト領域3aおよびn+型ソース領域4を露出させるコンタクトホールを形成する。
層間絶縁膜10の表面上に例えば複数の金属の積層構造により構成される電極材料を形成する。そして、電極材料をパターニングすることで、ソース電極9およびゲートパッド31を形成する。なお、本図とは異なる断面において各セルのゲート電極8に繋がるゲート引出部が設けられている。その引出部において層間絶縁膜10にコンタクトホールが開けられることで、ゲートパッド31とゲート電極8との電気的接続が行われるようになっている。
第2実施形態について説明する。本実施形態は、第1実施形態に対して製造方法を変更したものであり、その他については第1実施形態と同様であるため、第1実施形態と異なる部分について主に説明する。
第3実施形態について説明する。本実施形態は、第1、第2実施形態に対してゲート配置領域GPの形状を変更したものであり、その他については第1、第2実施形態と同様であるため、第1、第2実施形態と異なる部分についてのみ説明する。
第4実施形態について説明する。本実施形態は、第1〜第3実施形態に対してゲート配置領域GPの形状を変更したものであり、その他については第1〜第3実施形態と同様であるため、第1〜第3実施形態と異なる部分についてのみ説明する。なお、ここでは第3実施形態のように、ゲート配置領域GPが非対称形状となるレイアウトについて本実施形態の構造を適用する場合を例に挙げて説明する。
第5実施形態について説明する。本実施形態は、第4実施形態に対してゲート配置領域GPの形状を変更したものであり、その他については第4実施形態と同様であるため、第4実施形態と異なる部分についてのみ説明する。
第6実施形態について説明する。本実施形態は、第4実施形態に対してゲート配置領域GPの形状を変更したものであり、その他については第4実施形態と同様であるため、第4実施形態と異なる部分についてのみ説明する。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
2 n-型ドリフト層
3 p型ベース領域
4 n+型ソース領域
5、30 p型ディープ層
5a、30a 凹部
8 ゲート電極
9 ソース電極
11 ドレイン電極
F ファセット面
Claims (7)
- 裏面側が第1導電型もしくは第2導電型の高濃度不純物層(1)とされていると共に表面側が前記高濃度不純物層よりも低不純物濃度とされた第1導電型のドリフト層(2)とされ、炭化珪素にて構成された半導体基板(1、2)と、
前記ドリフト層(2)の上に形成された第2導電型の炭化珪素からなるベース領域(3)と、
前記ベース領域の上に形成され、前記ドリフト層よりも高不純物濃度の第1導電型の炭化珪素で構成されたソース領域(4)と、
前記ベース領域よりも深く高不純物濃度で構成された第2導電型のディープ層(5、30)と、
前記ソース領域の表面から前記ベース領域よりも深く、かつ、前記ディープ層よりも浅く形成されたゲートトレンチ(6)内に形成され、該ゲートトレンチの内壁面に形成されたゲート絶縁膜(7)と、前記ゲート絶縁膜の上に形成されたゲート電極(8)と、を有し、一方向を長手方向として構成されたトレンチゲート構造と、
前記ベース領域と前記ソース領域および前記ディープ層に電気的に接続されるソース電極(10)と、
前記高濃度不純物層と電気的に接続されるドレイン電極(12)と、を有する縦型の半導体素子を備え、
前記ディープ層は、前記トレンチゲート構造の両側に配置されると共に前記トレンチゲート構造の長手方向に沿って形成されるストライプ状部(5)と、前記トレンチゲート構造の両端に対向して配置される先端対向部(30)とを有して構成され、
前記ベース領域には、前記トレンチゲート構造の両先端のうちの一方と対向する前記先端対向部について、当該先端対向部から前記トレンチゲート構造の先端側に向かってファセット面F(F)が形成されており、当該先端対向部から前記トレンチゲート構造の先端に向かう方向における前記ファセット面Fの長さをファセット長Lとして、当該先端対向部から前記トレンチゲート構造の先端までの距離が前記ファセット長Lよりも長くされている炭化珪素半導体装置。 - 前記ドリフト層には、前記ディープ層と対応する位置に凹部(5a、30a)が形成されており、該凹部の底面から前記ディープ層が形成されており、
前記ベース領域は、前記凹部内を含めて前記ドリフト層の上に形成されたエピタキシャル膜によって構成されている請求項1に記載の炭化珪素半導体装置。 - 前記半導体基板はオフ角を有するオフ基板であり、
前記ベース領域および前記ソース領域の膜厚をt、前記凹部の深さをd、前記オフ角をθとして、
前記ファセット長Lは、L=(t−d)/tanθで表される請求項2に記載の炭化珪素半導体装置。 - 前記半導体基板の表面に対する法線方向から見て、前記ディープ層によって囲まれた前記トレンチゲート構造が配置される領域をゲート配置領域(GP)として、
前記ゲート配置領域のうち前記ファセット面Fが形成される側の端部は、前記トレンチゲート構造の配置される位置よりも幅が狭くなっている請求項1ないし3のいずれか1つに記載の炭化珪素半導体装置。 - 前記ゲート配置領域のうち前記ファセット面Fが形成される側の端部は、該ゲート配置領域の先端に向かうに連れて徐々に幅が狭くされている請求項4に記載の炭化珪素半導体装置。
- 前記ゲート配置領域のうち前記ファセット面Fが形成される側の先端は鋭角の尖った形状なっている請求項5に記載の炭化珪素半導体装置。
- 前記ゲート配置領域のうち前記ファセット面Fが形成される側の端部の幅は前記トレンチゲート構造の幅以上とされている請求項4または5に記載の炭化珪素半導体装置。
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