CN110226233B - 碳化硅半导体装置 - Google Patents

碳化硅半导体装置 Download PDF

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CN110226233B
CN110226233B CN201880006962.4A CN201880006962A CN110226233B CN 110226233 B CN110226233 B CN 110226233B CN 201880006962 A CN201880006962 A CN 201880006962A CN 110226233 B CN110226233 B CN 110226233B
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type
gate structure
trench
region
trench gate
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CN110226233A (zh
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竹内有一
秋叶敦也
青井佐智子
铃木克己
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Denso Corp
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Denso Corp
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Abstract

使得从相对于半导体衬底的表面的法线方向观察时小平面(F)不与沟槽栅构造的前端重叠。由此，用来形成沟槽栅构造的沟槽(6)的底面的深度变得均匀，能够以在底面没有凹凸的状态形成栅极绝缘膜(7)，所以能够使栅极绝缘膜(7)的膜厚成为一定。因而，能够将p型深层(5)及p型深层(30)形成到较深的位置，并且能够得到栅极绝缘膜(7)的耐压。

Description

碳化硅半导体装置
相关申请的相互参照
本申请基于2017年1月17日提出申请的日本专利申请第2017－6003号，在此参照引用其全部内容。
技术领域
本公开涉及具有深层(deep layer)的沟槽栅(trench-gate)构造的碳化硅(以下称作SiC)半导体装置。
背景技术
在能得到高的击穿电场强度的SiC半导体装置中，由于击穿电场强度较高所以发生高电场，在形成沟槽栅构造的元件的情况下，特别在栅极底部发生高电场。因此，向栅极氧化膜施加的电场变高，栅极氧化膜寿命下降。为了防止该情况，以往例如如专利文献1所示，采用了在形成沟槽栅的沟槽的附近形成作为电场缓和层的p型深层、能够将施加于沟槽栅的电场缓和的构造。
此外，在SiC半导体装置中，具备：形成有沟槽栅构造的元件的单元部；以及将单元部的周围包围的保护环部，在单元部与保护环部之间，设置有用来将它们之间相连的连结部。并且，在连结部中，在n型漂移层的表层部具备p型深层，从而在单元部内及连结部内不会电场集中，等电位线被从单元部朝向保护环部延伸，在保护环部中被截止。
在这样的SiC半导体装置中，作为p型深层的形成方法可以举出离子注入法，但由于SiC非常硬，离子注入的射程较短，所以难以使p型深层成为希望的深度。因此，以往还提出了以下的技术：在进行p型深层的离子注入之前，在p型深层的计划形成位置，通过将n型漂移层蚀刻而形成凹部，将p型杂质从那里向凹部的底面进行离子注入。如果这样做，则能够将p型深层形成得更深。
现有技术文献
专利文献
专利文献1：日本特开2011－101036号公报
发明内容
在SiC半导体装置中，也能够做成沿着沟槽栅构造的长边方向形成p型深层、在p型深层之间配置沟槽栅构造那样的构造。在这样的构造中，通过配置在沟槽栅构造的两侧的p型深层抑制向沟槽底部的电场的升高。因此，能够将沟槽底部的电场集中缓和，能够保护栅极绝缘膜。
但是，除此以外需要在沟槽栅构造的前端也能够抑制由电场的升高带来的影响。因此，可以考虑除了在沟槽栅构造的两侧配置p型深层以外，还以与沟槽栅构造的前端重叠的方式设置p型深层。如果这样以与沟槽栅构造的前端重叠的方式设置p型深层，则在沟槽栅构造的前端也能够抑制因电场的升高带来的影响，能够保护栅极绝缘膜。
但是，为了如上述那样将p型深层形成得更深，在通过在n型漂移层形成凹部后进行离子注入从而形成p型深层的情况下，可能发生以下这样的课题。
即，由于为了使p型深层更深而形成凹部，所以在n型漂移层及p型深层之上外延生长的p型基极区的表面不为平坦面。进而，在外延生长面，形成以凹部为起点的小平面(facet)。例如，作为SiC衬底(基板)而使用偏轴衬底(off substrate)，沿着偏轴衬底的偏轴方向(off direction)而设定沟槽栅构造的长边方向。在此情况下，为沟槽栅构造的一方的前端与小平面重合、另一方的前端与没有小平面处的由于凹部而造成的凹凸重合的状态。
因此，用来形成沟槽栅构造的沟槽的底面其深度成为不均匀，形成由于凹凸而产生的弯曲部。并且，在沟槽的弯曲部中栅极绝缘膜的膜厚变薄，发生不能得到栅极绝缘膜的耐压的问题。
本公开的目的是提供一种能够将深层形成到较深的位置、并且能够确保栅极绝缘膜的耐压的SiC半导体装置。
本公开1观点的SiC半导体装置，具备纵型的半导体元件，所述纵型的半导体元件具有：半导体衬底，背面侧为第1导电型或第2导电型的高浓度杂质层，并且正面侧为杂质浓度比高浓度杂质层低的第1导电型的漂移层，该半导体衬底由碳化硅构成；基极区，形成在漂移层之上，由第2导电型的碳化硅构成；源极区，形成在基极区之上，由与漂移层相比杂质浓度高的第1导电型的碳化硅构成；第2导电型的深层，比基极区深，由高杂质浓度构成；沟槽栅构造，形成在从源极区的表面比基极区深且比深层浅地形成的栅极沟槽内，具有形成在该栅极沟槽的内壁面上的栅极绝缘膜和形成在栅极绝缘膜之上的栅极电极，将一方向作为长边方向而构成；源极电极，电连接在基极区、源极区及深层；以及漏极电极，与高浓度杂质层电连接。
在这样的结构中，深层构成为具有配置在沟槽栅构造的两侧并沿着沟槽栅构造的长边方向形成的条纹状部、和与沟槽栅构造的两端对置配置的前端对置部；在基极区中，关于与沟槽栅构造的两前端中的一方对置的前端对置部，从该前端对置部朝向沟槽栅构造的前端侧形成有小平面F，将从该前端对置部朝向沟槽栅构造的前端的方向上的小平面F的长度设为小平面长L，使从该前端对置部到沟槽栅构造的前端的距离比小平面长L长。
通过做成这样的结构，能够使得小平面不与沟槽栅构造的前端重叠。因此，用来形成沟槽栅构造的沟槽的底面的深度变得均匀，能够在底面上没有凹凸的状态下形成栅极绝缘膜，所以能够使栅极绝缘膜的膜厚成为一定。因而，能够将深层形成到较深的位置，并且能够得到栅极绝缘膜的耐压。
附图说明
图1是有关第1实施方式的SiC半导体装置的上表面布局图。
图2是图1的II－II剖视图。
图3是图1中的沟槽栅构造附近的部分放大图。
图4是表示在使沟槽栅构造的前端与p型深层重叠的情况下上表面布局与截面中的沟槽的底面的形状的关系的图。
图5是表示在不使沟槽栅构造的前端与p型深层重叠的情况下上表面布局与截面中的沟槽的底面的形状的关系的图。
图6A是表示图2所示的SiC半导体装置的制造工序的剖视图。
图6B是表示接着图6A的SiC半导体装置的制造工序的剖视图。
图6C是表示接着图6B的SiC半导体装置的制造工序的剖视图。
图6D是表示接着图6C的SiC半导体装置的制造工序的剖视图。
图6E是表示接着图6D的SiC半导体装置的制造工序的剖视图。
图6F是表示接着图6E的SiC半导体装置的制造工序的剖视图。
图6G是表示接着图6F的SiC半导体装置的制造工序的剖视图。
图6H是表示接着图6G的SiC半导体装置的制造工序的剖视图。
图7A是表示有关第2实施方式的SiC半导体装置的制造工序的剖视图。
图7B是表示接着图7A的SiC半导体装置的制造工序的剖视图。
图7C是表示接着图7B的SiC半导体装置的制造工序的剖视图。
图7D是表示接着图7C的SiC半导体装置的制造工序的剖视图。
图8是有关第3实施方式的SiC半导体装置的沟槽栅构造附近的部分放大图。
图9是有关第4实施方式的SiC半导体装置的沟槽栅构造附近的部分放大图。
图10是有关第5实施方式的SiC半导体装置的沟槽栅构造附近的部分放大图。
图11是有关第6实施方式的SiC半导体装置的沟槽栅构造附近的部分放大图。
图12是在其他实施方式中说明的SiC半导体装置的沟槽栅构造附近的部分放大图。
具体实施方式
以下，基于附图对本公开的实施方式进行说明。另外，在以下的各实施方式中，对相互相同或等同的部分赋予相同的标号而进行说明。
(第1实施方式)
对第1实施方式进行说明。这里，举出形成有沟槽栅(trench-gate)构造的反转型的MOSFET的SiC半导体装置作为由半导体元件构成的功率元件为例进行说明。
图1所示的SiC半导体装置为如下结构，具有形成有沟槽栅构造的MOSFET的单元(cell)部、和将该单元部包围的外周部。外周部为如下结构，具有保护环部、和配置在比保护环部靠内侧、即配置在单元部与保护环部之间的连结部(相连部)。另外，图1虽然不是剖视图，但为了使图容易观察而部分地表示了阴影。
如图2所示，SiC半导体装置使用由SiC构成的n+型衬底1形成，在n+型衬底1的主表面上形成由SiC构成的n－型漂移层2和p型基极区3外延生长而成的外延膜。进而，在p型基极区3之上形成有n+型源极区4。关于n+型源极区4，也可以是通过外延生长形成的外延膜，但在本实施方式中通过离子注入而形成。
n+型衬底1例如为n型杂质浓度是1.0×1019/cm3、以表面为(0001)Si面、偏轴方向为<11－20>方向的偏轴衬底(off substrate)。n－型漂移层2例如n型杂质浓度为0.5～2.0×1016/cm3。另外，这里设为在n－型漂移层2之上直接配置p型基极区3的构造，但也可以是在n－型漂移层2之上经由n型电流分散层而形成p型基极区3的构造。n型电流分散层是与n－型漂移层2相比n型杂质浓度为高浓度、即为低电阻的层。如果具备该n型电流分散层，则能够使电流向更大范围分散而流动，能够降低JFET电阻。
此外，p型基极区3是形成有沟道区域的部分，p型杂质浓度例如为2.0×1017/cm3左右，厚度构成为300nm。在p型基极区3的表层部、即被n+型源极区4夹着的地方，部分性地形成有使p型杂质为高浓度的p型接触区3a。n+型源极区4被设为比n－型漂移层2高的杂质浓度，表层部中的n型杂质浓度例如为2.5×1018～1.0×1019/cm3，厚度构成为0.5μm左右。
在单元部，在n+型衬底1的表面侧残留有p型基极区3及n+型源极区4，在保护环部，以将p型基极区3贯通而达到n－型漂移层2的方式形成有凹部20。通过做成这样的构造，构成台面(mesa)构造。
此外，在单元部中，在n－型漂移层2的表层部，形成有与p型基极区3相比p型杂质浓度高的p型深层5。更详细地讲，通过对于在p型深层5的计划形成位置将n－型漂移层2的表面蚀刻而形成的凹部5a的底面离子注入p型杂质，从而形成p型深层5。凹部5a的深度例如被设为0.3～0.6μm，p型深层5形成在比其深的位置。
p型深层5在n－型漂移层2内以等间隔配置有多条，通过相互没有交点地相离而配置从而成为条纹状，构成条纹状部。上述的p型基极区3及n+型源极区4形成在该p型深层5之上。
各p型深层5形成为相同的杂质浓度、相同的宽度且相同的深度，例如构成为p型杂质浓度为1.0×1017～1.0×1019cm3、宽度为0.7μm、深度为2.0μm左右。各p型深层5如图1所示那样遍及从单元部的一端到另一端而形成。并且，p型深层5以与后述的沟槽栅构造同方向作为长边方向而被延伸设置，并与比沟槽栅构造的两端更靠单元部的外侧地延伸设置的后述的连结部的p型深层30连接。
关于p型深层5的延伸设置方向即凹部5a的延伸设置方向是任意的，但在本实施方式中，设为与偏轴方向相同的<11－20>方向。如果将p型深层5在这样的方向上延伸设置，则能够使凹部5a中的构成长边的对置的两壁面成为相同的(1－100)面，埋入外延时的生长在两壁面相等。因此，能够使以将凹部5a埋入的方式形成的p型基极区3成为均匀的膜质，并且还能得到对埋入不良的抑制效果。
另外，当在n－型漂移层2之上直接形成p型基极区3时，p型深层5被形成于n－型漂移层2，但当在n－型漂移层2之上经由n型电流分散层而形成p型基极区3时，p型深层5被形成于n型电流分散层。在此情况下，如果为p型基极区3的底部比n型电流分散层浅、即在p型基极区3的底部与n－型漂移层2之间残留n型电流分散层那样的构造，则在该部分也进行电流分散，所以是优选的。
此外，以贯通p型基极区3及n+型源极区4而到达n－型漂移层2、并且比p型深层5浅的方式形成例如宽度为0.8μm、深度为1.0μm的栅极沟槽6。以与该栅极沟槽6的侧面接触的方式配置上述的p型基极区3及n+型源极区4。栅极沟槽6形成为以图2的纸面左右方向为宽度方向、纸面垂直方向为长边方向(长度方向)、纸面上下方向为深度方向的线状的布局。此外，如图1所示，栅极沟槽6以多条分别夹在p型深层5之间的方式配置，并分别以相等间隔平行地排列，从而成为条纹状。
进而，将p型基极区3中的位于栅极沟槽6的侧面的部分作为在纵型MOSFET的动作时连接n+型源极区4与n－型漂移层2之间的沟道区域，在包括沟道区域的栅极沟槽6的内壁面形成有栅极绝缘膜7。并且，在栅极绝缘膜7的表面形成有由掺杂Poly－Si构成的栅极电极8，通过这些栅极绝缘膜7及栅极电极8，栅极沟槽6内被填满。由此，构成沟槽栅构造。另外，在图1中，为了使图容易观察而将沟槽栅构造及p型深层5的数量减少而记载，但实际上配置有多个同样的构造。
沟槽栅构造的前端从后述的p型深层30离开规定距离。因此，沟槽栅构造成为配置在由p型深层5和p型深层30包围的区域(以下称作栅极配置区域)GP内的状态。在本实施方式的情况下，使从沟槽栅构造的两前端到p型深层30的距离相等。关于从该沟槽栅构造的两前端到p型深层30的距离，将后续详细地说明。
此外，在n+型源极区4及p型深层5的表面、栅极电极8的表面，隔着层间绝缘膜10形成有相当于第1电极的源极电极9或被配置在电极焊盘部的栅极焊盘31。源极电极9及栅极焊盘31由多种金属例如Ni/Al等构成。并且，多种金属中的至少n型SiC、具体而言是与n+型源极区4或n型掺杂时的栅极电极8接触的部分，由能够与n型SiC欧姆接触的金属构成。此外，多个金属中的至少p型SiC、具体而言是与p型深层5接触的部分，由能够与p型SiC欧姆接触的金属构成。另外，这些源极电极9及栅极焊盘31通过形成在层间绝缘膜10上而被电气地绝缘。并且，经由形成在层间绝缘膜10的接触孔，源极电极9与n+型源极区4及p型接触区3a电接触，栅极焊盘31与栅极电极8电接触。
进而，在n+型衬底1的背面侧形成有与n+型衬底1电连接的相当于第2电极的漏极电极11。通过这样的构造，构成n沟道型的反转型的沟槽栅构造的MOSFET。并且，通过将这样的MOSFET配置多个单元而构成单元部。
另一方面，在保护环部，如上述那样，以贯通p型基极区3而到达n－型漂移层2的方式形成有凹部20。因此，在距单元部相离的位置将n+型源极区4及p型基极区3去除，使n－型漂移层2露出。并且，在n+型SiC衬底1的厚度方向上，成为位于比凹部20靠内侧的位置处的单元部或连结部呈岛状突出的台面(mesa)部。
此外，在位于凹部20的下方的n－型漂移层2的表层部，以将单元部包围的方式具备多条p型保护环21。在本实施方式的情况下，将p型保护环21构成为四角被倒圆的四边形状，但也可以构成为圆形状等其他框形状。p型保护环21通过对形成在n－型漂移层2的凹部21a的底面离子注入p型杂质而形成。凹部21a也有可能根据用来形成台面部的凹部20的深度而消失，但在图2中图示了残留的情况。此外，在凹部21a残留的情况下，成为p型基极区3的一部分残留在凹部21a内的状态。
构成p型保护环21的各部为与上述p型深层5同样的结构。p型保护环21上表面形状为将单元部及连结部包围的框形状的线状，这一点与形成为直线状的p型深层5不同，但其他相同。即，p型保护环21为与p型深层5同样的杂质浓度、同样的宽度、同样的深度。此外，关于各p型保护环21的间隔，既可以是等间隔，但也可以是p型保护环21的间隔在单元部侧较窄而越朝向外周侧越大，以使得在更靠内周侧即单元部侧缓和电场集中从而等电位线朝向更外周侧。
另外，虽然没有图示，但根据需要而在比p型保护环21靠外周具备EQR构造，由此构成具备将单元部包围的外周耐压构造的保护环部。
进而，将从单元部到保护环部之间作为连结部，在连结部，在n－型漂移层2的表层部形成有p型深层30。p型深层30由于与p型基极区3接触，所以被固定为源极电位。在本实施方式的情况下，如图1中的实线阴影所示，连结部以将单元部包围的方式形成，进而以将该连结部的外侧包围的方式，形成有多条使四角被倒圆的四边形状的p型保护环21。p型深层30形成在被作为该连结部的实线阴影部分，与形成在单元部的p型深层5连结。因此，如图1及图3所示，p型深层30构成与沟槽栅构造的两前端对置而配置的前端对置部，与p型深层5一起将沟槽栅构造包围。
各p型深层30通过对于形成在n－型漂移层2的表面的凹部30a的底面离子注入p型杂质而形成。p型深层30的杂质浓度及深度被设为与上述的p型深层5及p型保护环21同样。
在本实施方式中，p型深层30与沟槽栅构造的两前端对置的边被倒圆。因此，栅极配置区域GP成为前端被倒圆的线状。并且，p型深层30与沟槽栅构造的前端的距离考虑了小平面F的形成范围而被设定。以下，对该p型深层30与沟槽栅构造的前端的距离进行说明。
如本实施方式那样，在使用偏轴方向为<11－20>方向的偏轴衬底作为n+型衬底1、并且用来形成p型深层5的凹部5a的延伸设置方向也为与偏轴方向相同的<11－20>方向的情况下，小平面F形成在栅极配置区域GP的一端。在图3中用实线阴影表示的部分是小平面F。小平面F由于外延生长的面方向依存性而形成。具体而言，在与凹部5a中的以<11－20>方向为法线方向的面的一面对应的位置，在p型深层5的表面，以沿着偏轴方向倾斜的方式形成小平面F。
该小平面F的形成范围由形成在p型深层5及n－型漂移层2之上的p型基极区3及n+型源极区4的膜厚和n+型衬底1的偏轴角及凹部5a的深度决定，能够通过计算来求出。具体而言，设从p型深层30朝向沟槽栅构造的前端的方向、在本实施方式的情况下偏轴方向上的小平面F的长度为小平面长L。该小平面长L基于p型基极区3及n+型源极区4的膜厚t和偏轴角θ及凹部5a的深度d如下式那样计算。
(数式1)小平面长L＝(t－d)/tanθ
基于这样求出的小平面长L，关于p型深层30与沟槽栅构造的前端的距离设定为，从相对于n+型衬底1的表面的法线方向观察时，小平面F不与沟槽栅构造的前端重叠的长度。例如，在膜厚t是0.8μm，偏轴角θ是4°，凹部5a的蚀刻量是0.4μm的情况下，小平面长L为6μm左右。
另外，这里所述的p型深层30与沟槽栅构造的前端的距离，是指在沿着沟槽栅构造的长边方向的中心线上从p型深层30中的与该中心线交叉的点到沟槽栅构造的前端的距离。
此外，小平面F沿着偏轴方向形成，在偏轴方向的上游侧为凹部5a下游侧为突出的形状的位置处形成，在偏轴方向的上游侧为突出的形状下游侧为凹部5a的位置处不形成。因此，在本实施方式的情况下，小平面F形成在栅极配置区域GP中的图3中的纸面左侧的端部，不形成在纸面右侧的端部。但是，在本实施方式的情况下，使从沟槽栅构造的两前端到p型深层30的距离一致，以使得以沟槽栅构造为中心而在沟槽栅构造的长边方向上栅极配置区域GP为对称形状。
通过形成这样的p型深层30，并且将p型深层5彼此之间设定为规定间隔，从而能够抑制在被它们包围的区域、即栅极配置区域GP中等电位线过度地升高。由此，能够抑制在p型深层30之间形成发生电场集中的部位，能够抑制耐压下降。
此外，如上述那样，各p型深层30中的与沟槽栅构造的两前端对置的边被倒圆，所以栅极配置区域GP的上表面形状为前端被倒圆的线状。将栅极配置区域GP的两端的上表面形状设为四边形状，但在角部有可能发生电场集中。因此，通过如本实施方式那样使栅极配置区域GP的形状为使前端变圆的形状，能够缓和电场集中。
进而，在连结部中，也在n+型源极区4的表面形成有层间绝缘膜10。上述的栅极焊盘31在连结部中形成在层间绝缘膜10之上。
这样，通过为在单元部与保护环部之间具备连结部的构造，在连结部形成p型深层30，从而与配置在沟槽栅构造的两侧的p型深层5连结。由此，能够抑制在栅极配置区域GP中等电位线过度地升高，并且能够使等电位线从单元部朝向保护环部伸展而在保护环部截止。
通过以上这样的构造，构成了有关本实施方式的SiC半导体装置。这样构成的SiC半导体装置，在将MOSFET导通时，通过控制向栅极电极8的施加电压，在位于栅极沟槽6的侧面的p型基极区3的表面部形成沟道区域。由此，使电流经由n+型源极区4及n－型漂移层2向源极电极9及漏极电极11之间流动。
此外，在MOSFET的断开时，即使被施加高电压，通过被形成到比沟槽栅构造深的位置的p型深层5及p型深层30也抑制了电场向栅极沟槽底部的进入。因此，栅极沟槽底部处的电场集中被缓和。由此，防止栅极绝缘膜7被破坏。
进而，关于p型深层30与沟槽栅构造的前端的距离设定为，从相对于n+型衬底1的表面的法线方向观察时，小平面F不与沟槽栅构造的前端重叠的长度。因此，用来形成沟槽栅构造的沟槽6的底面的深度变得均匀，能够以底面没有凹凸的状态形成栅极绝缘膜7，所以能够使栅极绝缘膜7的膜厚成为一定。对此，使用图4及图5进行说明。
图4表示以往技术中以沟槽栅构造的前端与p型深层30重叠的方式布局的情况下的各部的关系。此外，图5表示如本实施方式那样，以沟槽栅构造的前端不与小平面F重叠的方式布局的情况下的各部的关系。
如图4及图5所示，在形成了凹部30a的情况下，由于沿着偏轴方向形成小平面F，所以在沟槽栅构造中的图中左侧的前端所处的部分中，在p型基极区3及n+型源极区4的表面形成凹凸。
并且，如图4所示，在以沟槽栅构造的前端与p型深层30重叠的方式布局的情况下，以与小平面F重叠的方式配置沟槽栅构造的前端。因此，沟槽6的底部如在图中用粗线表示那样形成为与n+型源极区4的表面相同的形状，为具有与小平面F同样的凹凸的形状。由此，在沟槽6内形成有栅极绝缘膜7的情况下，在用图中的点A1、A2表示的弯曲部及其附近，栅极绝缘膜7的膜厚变薄，不能得到栅极绝缘膜7的耐压。
此外，关于沟槽栅构造中的图中右侧的前端所处的部分，由于形成凹部30a，也在p型基极区3及n+型源极区4的表面形成凹凸。因此，在以沟槽栅构造的前端与p型深层30重叠的方式布局的情况下，沟槽6的底部如图中用虚线表示那样成为与n+型源极区4的表面相同的形状，成为具有与凹部30a对应的凹凸的形状。由此，在沟槽6内形成有栅极绝缘膜7的情况下，在图中的用点A3表示的弯曲部及其附近，栅极绝缘膜7的膜厚变薄，不再能得到栅极绝缘膜7的耐压。
因而，在如以往那样以沟槽栅构造的前端与p型深层30重叠的方式布局的情况下，不再能得到栅极绝缘膜7的耐压。
另一方面，如图5所示，在使得沟槽栅构造的前端不与小平面F重叠的情况下，沟槽6如在图中用虚线表示那样形成在n+型源极区4的表面为平坦的位置。
此外，关于沟槽栅构造中的图中右侧的前端所处的部分，也由于形成凹部30a而在p型基极区3及n+型源极区4的表面形成凹凸。但是，由于使沟槽栅构造的前端从p型深层30相离，所以在形成沟槽6的位置，p型基极区3及n+型源极区4的表面为平坦。
因此，沟槽6的底部也为平坦的形状。由此，在沟槽6内形成了栅极绝缘膜7的情况下，形成在平坦的形状之上的栅极绝缘膜7的膜厚成为均匀。由此，能够得到栅极绝缘膜7的耐压。
作为参考，通过实验，进行了通常被作为栅极绝缘膜的耐压试验被使用的TZDB(Time Zero Dielectric Break down)试验及高温逆偏压试验，没有发现栅极绝缘膜7的破坏。因此，根据该实验结果也可知能够得到上述效果。
接着，参照图6A～图6H对有关本实施方式的SiC半导体装置的制造方法进行说明。
〔图6A所示的工序〕
首先，准备在n+型衬底1的主表面上外延生长了由SiC构成的n－型漂移层2的衬底作为半导体衬底。
〔图6B所示的工序〕
接着，配置掩模40，使掩模40在p型深层5、p型深层30及p型保护环21的计划形成区域处开口。并且，通过使用掩模40进行RIE(Reactive IonEtching)等的各向异性蚀刻，形成凹部5a、21a、30a。进而，使用掩模40将p型杂质进行离子注入。由此，形成p型深层5和p型深层30及p型保护环21。
〔图6C所示的工序〕
在将掩模40除去之后，包括p型深层5和p型深层30及p型保护环21之上，在n－型漂移层2之上外延生长p型基极区3。此时，在图6A～图6H中虽然没有记载，但如图5中所示，由于形成凹部30a而在p型深层30的表面形成小平面F。
〔图6D所示的工序〕
在p型深层30之上配置未图示的掩模之后，使掩模中的n+型源极区4的计划形成区域处开口。并且，通过使用该掩模将n型杂质进行离子注入，从而形成n+型源极区4。进而，在将掩模除去之后，重新配置未图示的掩模，使掩模中的p型接触区3a的计划形成区域处开口。接着，通过使用该掩模将p型杂质进行离子注入，从而形成p型接触区3a。
〔图6E所示的工序〕
在n+型源极区4及p型基极区3等之上形成未图示的掩模之后，使掩模中的栅极沟槽6的计划形成区域处开口。接着，通过使用掩模进行RIE等的各向异性蚀刻，从而形成与p型深层5相比浅的深度的栅极沟槽6。
进而，在将掩模除去之后，再次形成未图示的掩模，使掩模中的凹部20的计划形成区域处开口。接着，通过使用掩模进行RIE等的各向异性蚀刻，从而形成凹部20。由此，在形成了凹部20的位置，将n+型源极区4及p型基极区3贯通而使n－型漂移层2露出，构成从n－型漂移层2的表面配置了多条p型保护环21的构造。
另外，这里将栅极沟槽6和凹部20以使用不同的掩模的不同工序来形成，但也可以使用相同的掩模同时形成。
〔图6F所示的工序〕
在将掩模去除之后，例如通过进行热氧化，形成栅极绝缘膜7，由栅极绝缘膜7覆盖栅极沟槽6的内壁面上及n+型源极区4的表面上。接着，在将掺杂有p型杂质或n型杂质的Poly－Si沉积后，对其进行回蚀，至少在栅极沟槽6内残留Poly－Si从而形成栅极电极8。
〔图6G所示的工序〕
以将栅极电极8及栅极绝缘膜7的表面覆盖的方式，形成例如由氧化膜等构成的层间绝缘膜10。并且，在层间绝缘膜10的表面上形成未图示的掩模之后，使掩模中的位于各栅极电极8之间的部分、即与p型接触区3a对应的部分及其附近开口。然后，使用掩模对层间绝缘膜10进行布图，从而形成使p型接触区3a及n+型源极区4露出的接触孔。
〔图6H所示的工序〕
在层间绝缘膜10的表面上形成例如由多种金属的层叠构造构成的电极材料。并且，通过对电极材料进行图案加工，形成源极电极9及栅极焊盘31。另外，在与本图不同的截面中设置有与各单元的栅极电极8相连的栅极引出部。在该引出部中，在层间绝缘膜10开设有接触孔，由此进行栅极焊盘31与栅极电极8的电连接。
关于之后的工序没有图示，通过进行在n+型衬底1的背面侧形成漏极电极11等的工序，完成有关本实施方式的SiC半导体装置。
如以上说明，在本实施方式中，使得从相对于n+型衬底1的表面的法线方向观察时、小平面F不与沟槽栅构造的前端重叠。因此，用来形成沟槽栅构造的沟槽6的底面的深度变得均匀，能够以在底面没有凹凸的状态来形成栅极绝缘膜7，所以能够使栅极绝缘膜7的膜厚成为一定。因而，能够将p型深层5及p型深层30形成到较深的位置，并且能够得到栅极绝缘膜7的耐压。
(第2实施方式)
对第2实施方式进行说明。本实施方式相对于第1实施方式变更了制造方法，关于其他与第1实施方式相同，因此主要对与第1实施方式不同的部分进行说明。
参照图7A～图7D，对有关本实施方式的SiC半导体装置的制造方法进行说明。首先，图7A、图7B所示的工序，进行与在第1实施方式中说明的图6A、图6B同样的工序。接着，图7C所示的工序，在p型基极区3的表面使n+型源极区4外延生长。然后，图7D所示的工序，在n+型源极区4的表面配置未图示的掩模之后，使掩模在p型接触区3a的计划形成区域处开口。接着，通过使用掩模进行RIE等的各向异性蚀刻，将n+型源极区4部分地去除，使p型基极区3露出。进而，使用掩模离子注入p型杂质。由此，形成p型接触区3a。
然后，通过进行与图6E～图6H同样的工序，完成与第1实施方式同样的结构的SiC半导体装置。这样，也可以通过使n+型源极区4在p型基极区3之上外延生长来形成。
(第3实施方式)
对第3实施方式进行说明。本实施方式相对于第1、第2实施方式变更了栅极配置区域GP的形状，关于其他与第1、第2实施方式同样，所以仅对与第1、第2实施方式不同的部分进行说明。
如图8所示，在本实施方式中，在沟槽栅构造的长边方向上，以沟槽栅构造为中心的栅极配置区域GP的形状为非对称形状。具体而言，关于形成有小平面F的一侧的沟槽栅构造的前端，使p型深层30与沟槽栅构造的前端的距离为小平面长L以上。并且，关于另一方的前端，仅使其从p型深层30相离，与p型深层30的距离比小平面长L短。
如上述那样，小平面F只是形成在与沟槽栅构造的一方的前端对应的位置，在与另一方的前端对应的位置没有形成。因而，只要至少在形成小平面F的一侧，使p型深层30与沟槽栅构造的前端的距离为小平面长L以上，另一方的前端从p型深层30相离，就能够使沟槽6的底面成为平坦。
这样，即使在沟槽栅构造的长边方向上以沟槽栅构造为中心的栅极配置区域GP的形状为非对称形状，也能够得到与第1实施方式同样的效果。此外，在做成这样的布局的情况下，由于能够将没有形成沟道的无效区域缩小，所以能够提高针对形成SiC半导体装置的芯片的面积的有效面积的比例，也能够实现低导通电阻化。
(第4实施方式)
对第4实施方式进行说明。本实施方式相对于第1～第3实施方式变更了栅极配置区域GP的形状，关于其他与第1～第3实施方式相同，所以仅对与第1～第3实施方式不同的部分进行说明。另外，这里举出将如第3实施方式那样栅极配置区域GP为非对称形状的布局应用到本实施方式的构造的情况为例进行说明。
如图9所示，在本实施方式中，关于栅极配置区域GP中的形成小平面F的一侧的端部，通过将p型深层5的宽度扩大，栅极配置区域GP的宽度被缩窄。更详细地讲，以使栅极配置区域GP中的形成小平面F的一侧的前端(以下称作小平面侧前端)成为锐角的方式，栅极配置区域GP的宽度从沟槽栅构造的前端到小平面侧前端逐渐被缩窄。在从相对于n+型衬底1的表面的法线方向观察时，使p型深层5相对于偏轴方向以直线状倾斜，从而使栅极配置区域GP的宽度变化。
栅极配置区域GP被p型深层5及p型深层30包围，所以能够抑制电场的过度的升高。但是，在形成有沟槽栅构造的区域中，通过基于栅极电极8等的电场的推回效应，能够进一步抑制电场的过度的升高，但在没有形成沟槽栅构造的区域中，与形成有沟槽栅构造的区域相比电场的升高变大。
实际上，在断开时没有形成沟槽栅构造的区域中的电场相对地变大，根据设计，通过发光解析表明，在该位置发生击穿而产生耐压下降。以确认该现象为目的进行了模拟仿真可知，在没有形成沟槽栅构造的位置，在p型深层5的底部的角部电场强度变高，在该位置有可能发生击穿而产生耐压下降。
因而，如本实施方式那样，在小平面侧前端将栅极配置区域GP的宽度缩窄，从而能够进一步抑制没有配置沟槽栅构造的区域中的电场的升高。由此，能够抑制因不使沟槽栅构造的前端与p型深层30重叠带来的电场的过度的升高，能够实现SiC半导体装置的进一步的耐压提高。
另外，这里如第3实施方式那样，举出了关于栅极配置区域GP为非对称形状的布局应用于本实施方式的构造的情况为例，但关于第1、第2实施方式那样的为对称形状的布局也能够应用。在此情况下，关于栅极配置区域GP中的与小平面侧前端相反侧的前端，也只要设为与小平面侧前端同样的形状即可。
(第5实施方式)
对第5实施方式进行说明。本实施方式相对于第4实施方式变更了栅极配置区域GP的形状，关于其他与第4实施方式相同，所以仅对与第4实施方式不同的部分进行说明。
如图10所示，在本实施方式中，关于栅极配置区域GP中的小平面侧前端将宽度缩窄但没有做成尖的形状。即，将栅极配置区域GP中的形成小平面F的一侧的端部的宽度比配置有沟槽栅构造的位置处缩窄，并且设为沟槽栅构造的宽度以上的宽度。此外，关于p型深层30中的与沟槽栅构造的前端对置的边，也仅保留沟槽栅构造的宽度以上的宽度。并且，从沟槽栅构造的前端到小平面侧前端，逐渐使栅极配置区域GP的宽度变窄。使从相对于n+型衬底1的表面的法线方向观察时、p型深层5相对于偏轴方向以直线状倾斜，从而使栅极配置区域GP的宽度变化。
如果做成这样的构造，由于直到沟槽栅构造的前端的附近能够成为栅极配置区域GP的宽度较窄的区域，所以能够进一步抑制电场的升高，能够实现SiC半导体装置的进一步的耐压提高。
(第6实施方式)
对第6实施方式进行说明。本实施方式相对于第4实施方式变更了栅极配置区域GP的形状，关于其他与第4实施方式相同，所以仅对与第4实施方式不同的部分进行说明。
如图11所示，在本实施方式中，关于栅极配置区域GP中的小平面侧前端，将宽度缩窄但没有做成尖的形状。并且，使p型深层30中的与沟槽栅构造的前端对置的边保留与沟槽栅构造相等的宽度。更详细地讲，在小平面侧前端，通过将p型深层5的宽度扩大，使得对置的p型深层5之间的间隔与沟槽栅构造的宽度相等。并且，在沟槽栅构造侧中，通过从小平面侧前端到沟槽栅构造的前端使p型深层5的宽度逐渐变窄，从而栅极配置区域GP的宽度逐渐被拓宽。
如此这样，直到沟槽栅构造的前端的附近能够成为栅极配置区域GP的宽度窄的区域，所以能够进一步抑制电场的升高，能够实现SiC半导体装置的进一步的耐压提高。
(其他实施方式)
本公开是按照上述的实施方式进行记述的，但不限于该实施方式，还包括各种的变形例或等同范围内的变形。另外，各种的组合或方式、进而是在这些组合或方式中仅包括一个因素、包括其以上或者其以下的要素构成的其它的组合或方式，都应纳入在本发明的范畴或思想范围中。
例如，在上述实施方式中，将p型深层30形成在连结部的全域中，但也可以并不一定形成在全域中。此外，关于p型深层30，只要具备至少将相邻的p型深层5相连的部分即可，也可以在单元部的外周做成例如条纹状，或做成同心状的多个框形状的线状。
此外，在上述实施方式中，将沟槽栅构造的长边方向设为<11－20>方向，但并不需要一定是该方向。即，在将沟槽栅构造的长边方向设为<11－20>方向以外的方向的情况下，只要使从沟槽栅构造的前端到p型深层30的距离比小平面长L长即可。但是，在将沟槽栅构造的长边方向变更的情况下，由于与其对应而小平面长L也变化，所以只要与其对应地设定从沟槽栅构造的前端到p型深层30的距离即可。
此外，在上述各实施方式中，举出了在n+型衬底1的表面形成有n－型漂移层2的构造，作为背面侧为高浓度杂质层、正面侧与其相比为低杂质浓度的漂移层、由偏轴衬底构成的半导体衬底，进行了说明。但是，这只不过表示半导体衬底的一例，例如也可以是向由n－型漂移层2构成的衬底的背面侧离子注入n型掺杂剂、或通过外延生长而构成了背面层的半导体衬底。
此外，在上述第4～第6实施方式中，表示了对于栅极配置区域GP中的形成小平面F的一侧的端部、使宽度比配置有沟槽栅构造的位置处窄的一例，但这些也只不过表示了一例，也可以设为其他的布局。例如，如图12所示，也可以关于小平面侧前端为保留了使宽度变窄的区域的构造，并且将p型深层30中的与沟槽栅构造的两前端对应的边都做成倒圆的形状、优选的是倒圆为半圆状的形状。
进而，在上述第1～第6实施方式中，举出使第1导电型为n型、使第2导电型为p型的n沟道型的MOSFET为例进行了说明，但也可以为使各构成要素的导电型反转的p沟道型的MOSFET。此外，作为沟槽栅构造的元件而举MOSFET为例进行了说明，但对于同样的构造的IGBT也能够应用本公开。IGBT相对于上述各实施方式只是将n+型衬底1的导电型从n型变更为p型，关于其他的构造及制造方法与上述各实施方式相同。
另外，在表示出结晶的方位的情况下，本来应该在期望的数字上标注横杠(-)，但由于存在基于电子申请的表述上的限制，因而在本说明书中是在期望的数字的前面标注横杠(-)。

Claims (5)

1.一种碳化硅半导体装置，具备纵型的半导体元件，该纵型的半导体元件具有：
半导体衬底(1、2)，背面侧为第1导电型或第2导电型的高浓度杂质层(1)，并且正面侧为与上述高浓度杂质层相比被设为低杂质浓度的第1导电型的漂移层(2)，上述半导体衬底由碳化硅构成；
基极区(3)，形成在上述漂移层(2)之上，由第2导电型的碳化硅构成；
源极区(4)，形成在上述基极区之上，由与上述漂移层相比为高杂质浓度的第1导电型的碳化硅构成；
第2导电型的深层(5、30)，比上述基极区深，被构成为高杂质浓度；
沟槽栅构造，形成在栅极沟槽(6)内，具有形成在该栅极沟槽的内壁面的栅极绝缘膜(7)、和形成在上述栅极绝缘膜之上的栅极电极(8)，该沟槽栅构造将一方向作为长边方向，上述栅极沟槽(6)从上述源极区的表面形成到比上述基极区深且比上述深层浅处；
源极电极(10)，与上述基极区、上述源极区及上述深层电连接；以及
漏极电极(12)，与上述高浓度杂质层电连接；
上述深层构成为，具有配置在上述沟槽栅构造的两侧并且沿着上述沟槽栅构造的长边方向形成的条纹状部(5)、和与上述沟槽栅构造的两端对置地配置的前端对置部(30)；
在上述基极区，关于与上述沟槽栅构造的两前端中的一方对置的上述前端对置部，从该前端对置部朝向上述沟槽栅构造的前端侧形成有小平面(F)，将从该前端对置部朝向上述沟槽栅构造的前端的方向上的上述小平面(F)的长度设为小平面长L，使从该前端对置部到上述沟槽栅构造的前端的距离比上述小平面长L长，
在上述漂移层，与上述深层对应的位置处形成有凹部(5a、30a)，从该凹部的底面形成有上述深层；
上述基极区由包括上述凹部内而形成在上述漂移层之上的外延膜构成，
上述半导体衬底是具有偏轴角的偏轴衬底；
设上述基极区及上述源极区的膜厚为t，设上述凹部的深度为d，设上述偏轴角为θ，
上述小平面长L由L＝(t－d)/tanθ表示。
2.如权利要求1所述的碳化硅半导体装置，
将从相对于上述半导体衬底的表面的法线方向观察时、由上述深层包围的配置有上述沟槽栅构造的区域作为栅极配置区域(GP)；
上述栅极配置区域中的形成上述小平面(F)的一侧的端部与配置上述沟槽栅构造的位置相比宽度窄。
3.如权利要求2所述的碳化硅半导体装置，
上述栅极配置区域中的形成上述小平面(F)的一侧的端部随着朝向该栅极配置区域的前端而宽度逐渐变窄。
4.如权利要求3所述的碳化硅半导体装置，
上述栅极配置区域中的形成上述小平面(F)的一侧的前端为锐角的尖锐的形状。
5.如权利要求2所述的碳化硅半导体装置，
上述栅极配置区域中的形成上述小平面(F)的一侧的端部的宽度为上述沟槽栅构造的宽度以上。
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