WO2014155166A1 - Procede de dissolution d'une couche de dioxyde de silicium - Google Patents
Procede de dissolution d'une couche de dioxyde de silicium Download PDFInfo
- Publication number
- WO2014155166A1 WO2014155166A1 PCT/IB2014/000250 IB2014000250W WO2014155166A1 WO 2014155166 A1 WO2014155166 A1 WO 2014155166A1 IB 2014000250 W IB2014000250 W IB 2014000250W WO 2014155166 A1 WO2014155166 A1 WO 2014155166A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- traps
- dissolution
- silicon dioxide
- structures
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P36/00—Gettering within semiconductor bodies
- H10P36/20—Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P36/00—Gettering within semiconductor bodies
- H10P36/03—Gettering within semiconductor bodies within silicon bodies
- H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/90—Thermal treatments, e.g. annealing or sintering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Definitions
- the present invention relates to a method for dissolving a silicon dioxide layer in a semiconductor-on-insulator structure.
- a dissolution method known from the state of the art, and illustrated in FIGS. 1A and 1B, is a method of dissolving a layer of silicon dioxide 9 in a structure 5 of the semiconductor-on-insulator type, comprising its rear face 6 towards its front face 7 a support substrate 8, the silicon dioxide layer 9 and a semiconductor layer 10.
- the front face 7 corresponds to the free surface of the semiconductor layer 10.
- This dissolution process can be implemented in a furnace 1, illustrated in FIG. 2, in which a plurality of structures 5 are held on a support 4 so that the support 4 is adapted to maintain the structures 5 with a predetermined distance. - typically a few millimeters - between each structure 5, the front face 7 of a structure 5 facing the rear face 6 of the structure 5 adjacent to said front face 7.
- the structures are subjected to a non-oxidizing atmosphere.
- the non-oxidizing atmosphere is provided by a continuous stream of inert or reducing gas.
- the flow of inert gas enters the furnace 1 through an inlet 2, and exits through an outlet 3.
- the implementation of such a heat treatment results in the diffusion of oxygen atoms included in the silicon dioxide layer 9 through the semiconductor layer 10.
- the semiconductor monoxide slows down the dissolution reaction as its surface concentration of the structures increases.
- composition of the atmosphere of the furnace 1 is not homogeneous.
- the atmosphere of the furnace 1 is obtained by a constant flow of an inert or reducing gas.
- the flow of gas leads from its inlet 2 in the furnace 1 to its outlet 3 at least a portion of the volatile products.
- the structures are therefore subject to a variable concentration of volatile products.
- the gas stream may contain small amounts of oxygen.
- the oxygen contained in the gas stream reacts preferentially with the structures 5 close to the gas inlet 2.
- the gas flow is therefore depleted of oxygen from the inlet 2 of the furnace 1 to the outlet 3.
- the thickness of the silicon dioxide layer 9 and the thickness of the semiconductor layer 10 are greater in the center than at the edge of the structure.
- the silicon dioxide layer 9 is not dissolved in the same proportions from one structure to the other.
- some applications require the use of a layer of silicon dioxide 9 having a thickness of less than 50 nm, so that, for example, an electrical voltage can be applied to devices made in or on the layer Semiconductor 10. A very precise control of the thickness of said silicon dioxide layer is then necessary.
- FDSOI Flufly Depleted Silicon On Insulator
- FDMOS transistors analog for Fully Depleted Metal Oxide Semiconductor
- the threshold voltage of the transistor (usually denoted Vt), which depends on this thickness, is very sensitive to variations in thickness of the semiconductor layer 10.
- An object of the invention is therefore to provide a method of dissolving a silicon dioxide layer for precise control of the thicknesses of the semiconductor layers and silicon dioxide.
- the present invention aims to remedy all or part of the aforementioned drawbacks, and relates to a method for dissolving a silicon dioxide layer in a semiconductor-on-insulator type structure, comprising from its rear face to its front face a substrate support, the silicon dioxide layer and a semiconductor layer, the dissolution method being implemented in an oven in which a plurality of structures are held on a support, the support being adapted to maintain a predetermined distance between each structure , the front face of a structure being facing the rear face of the structure adjacent to said front face, the atmosphere of the furnace being a non-oxidizing atmosphere, the dissolution process causing the diffusion of oxygen atoms included in the silicon dioxide layer through the semiconductor layer and generating volatile products resulting from the reaction desdit s oxygen atoms with the semi- conductor, said process characterized in that the furnace comprises traps adapted to react with volatiles so as to reduce the concentration gradient of volatiles parallel to the front face of at least one structure.
- the vertical direction is defined as perpendicular to the floor on which the oven is installed.
- the terms “upper” and “lower” are defined with respect to this vertical direction.
- Volatile product concentration gradient parallel to the front face of a structure means the variation of the concentration of volatile products in the space between the front face of the structure and the rear face of the structure adjacent to said face. before, and along directions in a plane parallel to the front face of the structure.
- a concentration gradient of volatiles perpendicular to the front face of a structure is defined as being the nonuniformity of the concentration of volatile products in the space between the front face of the structure and the rear face of the structure. structure adjacent to said front face, and in a direction perpendicular to the front face of the structure.
- the provision in the oven traps adapted to react with the volatile products allows to absorb said products.
- the dissolution kinetics of the silicon dioxide layer is substantially equal at every point of the structure.
- the absorption of the volatile products makes it possible to have substantially the same concentration of volatile products in the vicinity of the front face of each structure.
- the dissolution process is substantially uniform from one structure to another.
- the traps disposed on the rear face of the semiconductor-on-insulator type structures.
- each structure is uniformly exposed to the layer comprising the traps.
- the concentration of volatile products on the surface of each structure is thus more uniform, so the parallel gradient reduces.
- the arrangement of the traps in the immediate vicinity of the front face of each structure limits the amount of volatile products entrained by the gas flow.
- the dissolution reaction is no longer limited by the distance separating two successive structures, it is possible to increase the load capacity of the furnace to perform the dissolution process.
- this mode of implementation does not require modification of the oven.
- the traps disposed on the back face are included in a layer with a thickness greater than 30 nm, preferably greater than 50 nm.
- the traps are included in a coating covering all or part of the support.
- the support being taken out of the oven after each dissolution process, it can easily be coated with a suitable trapping material.
- the traps are included in trapping layers at least partially covering the front face of substrates known as "trap substrates".
- the trap substrates are arranged on the support, each trap substrate being positioned in place of a semiconductor-type structure, and inserted between two structures of the semiconductor-on-insulator type, the front face of the trap substrate being opposite the rear face of the semiconductor-on-insulator type structure.
- the traps are included in a coating covering all or part of the inner wall of the furnace.
- interior of the furnace is meant the space in which the support holding the structures is introduced during the execution of the dissolution process.
- the reaction between the volatile products and the traps is a reaction of absorption of the volatile products by the traps.
- the traps include silicon dioxide.
- a thin layer comprising silicon dioxide disposed on the rear face of a structure, and having a thickness greater than 30 nm, or greater than 50 nm, will withstand a dissolution process at a temperature of between 900 ° C. and 1300 ° C. ° C.
- the native oxide naturally present on the back face of a silicon-on-insulator structure, due to its small thickness and its chemical composition evaporates during such treatment and can not play the role of trap.
- the silicon dioxide is compatible with the semiconductor structures manufacturing processes.
- the traps comprise at least one of the following materials: Tungsten, aluminum nitride, alumina.
- the semiconductor layer comprises silicon.
- the semiconductor layer has a thickness greater than 100 nm, preferably greater than 200 nm, even more preferably greater than 300 nm.
- the silicon dioxide layer has a thickness less than 50 nm, preferably less than 25 nm, even more preferably less than 15 nm.
- the furnace atmosphere comprises at least one species selected from: argon, dihydrogen.
- the temperature of the oven is maintained between 900 ° C and 1300 ° C.
- traps adapted to react with the oxygen in the furnace atmosphere are arranged in the oven.
- the traps for reacting with oxygen are silicon substrates.
- FIGS. 1A-1B are schematic representations of a structure treated by a dissolution method of a semiconductor-on-insulator type structure according to the techniques known from the prior art;
- FIG. 2 is a schematic representation of an oven for performing a thermal treatment of dissolution of a silicon dioxide layer according to the known techniques of the prior art
- FIGS. 3A-3B are schematic representations of a structure treated according to the invention.
- FIG. 4 is a diagrammatic representation of an oven intended for carrying out a thermal treatment for dissolving a silicon dioxide layer according to the invention
- FIG. 5 is a schematic representation of a structure treated according to one embodiment of the invention.
- FIG. 6 is a schematic representation of a trap substrate according to the invention.
- the dissolution process is a method for dissolving a layer of silicon dioxide 90 in a structure 50 of the semiconductor-on-insulator type.
- the structure 50 of the semiconductor-on-insulator type comprises from its rear face 60 towards its front face 70 a support substrate 80, the silicon dioxide layer 90 and a semiconductor layer 100.
- the dissolution process is carried out in an oven 10, illustrated in FIG. 4, in which a plurality of structures 50 are held on a support 40, said structures being parallel to one another.
- the front face 70 of a structure 50 is opposite the rear face
- the support 40 is adapted to maintain the structures 50 with a predetermined distance between each structure 50.
- the predetermined distance between each structure 50 may be less than 15 mm, preferably less than 10 mm.
- the atmosphere of the furnace 10 is a non-oxidizing atmosphere.
- the dissolution process results in the diffusion of oxygen atoms included in the layer of silicon dioxide 90 through the semiconductor layer 100.
- Volatile products include semiconductor monoxide
- Traps 0 adapted to react with the volatile products are arranged in the furnace 10 so as to reduce the concentration gradient of the volatile products parallel to the front face 70 of at least one structure 50.
- the oxygen content of the non-oxidizing atmosphere is preferably less than 10 ppm (ppm: parts per million).
- the non-oxidizing atmosphere of the furnace 10 is provided by a flow of inert or reducing gas.
- the flow of inert gas or reducing agent can enter the furnace 10 through an inlet 20, and emerges through an outlet 30.
- the furnace atmosphere may comprise at least one species selected from one of the following species: argon, dihydrogen.
- the temperature of the oven 10 can be maintained at a temperature between 900 ° C and 1300 ° C, for example 150 ° C.
- the conditions of implementation of this dissolution process may be adapted to partially dissolve the layer of silicon dioxide 90.
- the support substrate 80 may comprise at least one of the following materials: silicon, germanium, alumina, quartz.
- the semiconductor layer 100 may comprise at least one of the following materials: Silicon, Germanium, Silicon alloy Germanium.
- the traps 10 are arranged on the rear face 60 of structures 50.
- a coating comprising the traps 110 may be formed on the rear face 60 of the structures 50.
- traps 110 are closer to the front face 70 of each structure 50.
- each structure is uniformly exposed to the layer comprising the traps 110.
- the concentration of volatile products on the front face 70 of each structure 50 is thus more uniform, so the reduced parallel gradient.
- the arrangement of the traps 110 in the immediate vicinity of the front face 70 of each structure 50 limits the amount of volatile products entrained by the gas flow. As a result, the volatile product concentration changes in the furnace 10 are reduced.
- the silicon dioxide layer 90 is dissolved substantially in the same proportions from one structure 50 to the other.
- the traps 0 can be included in trapping layers on the front face 70 of substrates known as trap substrates 120.
- the trap substrates 120 are arranged on the support 40 in place of certain structures 50.
- the traps 0 disposed on the rear face 60 of the structures 50 or on the front face of the trap layers trapping substrates 120 may comprise silicon dioxide.
- the native oxide naturally present on the back side of a silicon-on-insulator structure, because of its small thickness and its chemical composition evaporates during such treatment and can not act as a trap.
- the traps 110 comprising silicon dioxide are advantageously formed by thin film deposition techniques.
- film deposition techniques are low pressure vapor deposition techniques and plasma enhanced vapor deposition techniques known to those skilled in the art.
- a rear-facing silicon dioxide film 60 of a silicon substrate support substrate 80 or the front face of a silicon trap substrate 120 may advantageously be performed by thermal oxidation.
- the film formed on the rear face 60 of a structure 50 or on the front face of a trap substrate 120 may have a thickness greater than 30 nm, preferably greater than 50 nm.
- the traps 110 may comprise at least one of the following materials: Titanium, Tungsten, Aluminum Nitride, Alumina.
- These materials can absorb the semiconductor monoxide formed during the dissolution process of the silicon dioxide layer 90.
- These materials can be formed into films by film deposition techniques known to those skilled in the art. For example evaporation techniques are particularly well suited for the formation of titanium films, Tungsten. Aluminum nitride and alumina are advantageously formed by chemical vapor deposition or atomic layer deposition techniques.
- traps 10 may be included in a coating covering all or part of the support 40.
- the traps 110 comprise silicon dioxide.
- the traps 110 comprising silicon dioxide are advantageously formed by vapor phase deposition techniques, or by thermal oxidation.
- the coating formed on the support 40 may have a thickness greater than 50 nm, or even greater than 500 nm.
- the traps 110 may comprise at least one of the following materials: Titanium, Tungsten, Aluminum Nitride, Alumina.
- These materials can be formed into film form by film deposition techniques known to those skilled in the art.
- film deposition techniques known to those skilled in the art.
- techniques of chemical vapor deposition techniques, or deposition of atomic layer By example techniques of chemical vapor deposition techniques, or deposition of atomic layer.
- the traps 110 are comprised in a coating covering wholly or partly the inner wall of the furnace 10.
- the traps 110 comprise silicon dioxide.
- the traps 110 may comprise at least one of the following materials: Titanium, Tungsten, Aluminum Nitride, Alumina.
- the semiconductor layer 100 has a thickness greater than 100 nm, preferably greater than 200 nm, even more preferably greater than 300 nm.
- the dissolution rate is less than 0.5 A / min.
- the volatile products formed during the dissolution process have time to diffuse to the traps.
- the silicon dioxide layer 90 has a thickness less than 50 nm, preferably less than 25 nm, even more preferably less than 15 nm.
- traps 120 adapted to react with the oxygen included in the furnace atmosphere 10 may also be arranged in furnace 0.
- the traps 120 intended to react with the oxygen may be silicon substrates arranged on the support 40 in place of certain structures 50.
- the silicon substrates for reacting with oxygen in the furnace atmosphere are disposed near the inlet of inert or reducing gas. Even more preferentially, the silicon substrates are arranged upstream of the flow of inert or reducing gas with respect to the structures 50.
- the oxygen included in the flow of inert or reducing gas reacts with the traps 120 before reaching a structure 50.
- the method of dissolving a layer of silicon dioxide 90 according to the invention makes it possible to homogenize the composition of the atmosphere of the furnace 10.
- the method according to the invention allows the more uniform dissolution of a structure 50 to the other, compared to the method of the prior art.
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- Formation Of Insulating Films (AREA)
- Non-Volatile Memory (AREA)
- Silicon Compounds (AREA)
Abstract
Description
Claims
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201480017598.3A CN105051881B (zh) | 2013-03-25 | 2014-03-03 | 用于分解二氧化硅层的方法 |
| SG11201507920XA SG11201507920XA (en) | 2013-03-25 | 2014-03-03 | Method for dissolving a silicon dioxide layer |
| US14/779,477 US9514960B2 (en) | 2013-03-25 | 2014-03-03 | Method for dissolving a silicon dioxide layer |
| JP2016504764A JP6442478B2 (ja) | 2013-03-25 | 2014-03-03 | 二酸化ケイ素層を分解する方法 |
| DE112014001629.2T DE112014001629B4 (de) | 2013-03-25 | 2014-03-03 | Verfahren zum Auflösen einer Siliciumdioxidschicht |
| KR1020157029834A KR102308646B1 (ko) | 2013-03-25 | 2014-03-03 | 실리콘 이산화물 층 용해 방법 |
| US15/350,290 US9911624B2 (en) | 2013-03-25 | 2016-11-14 | Method for dissolving a silicon dioxide layer |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1300706A FR3003684B1 (fr) | 2013-03-25 | 2013-03-25 | Procede de dissolution d'une couche de dioxyde de silicium. |
| FR1300706 | 2013-03-25 |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US14/779,477 A-371-Of-International US9514960B2 (en) | 2013-03-25 | 2014-03-03 | Method for dissolving a silicon dioxide layer |
| US15/350,290 Continuation US9911624B2 (en) | 2013-03-25 | 2016-11-14 | Method for dissolving a silicon dioxide layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2014155166A1 true WO2014155166A1 (fr) | 2014-10-02 |
Family
ID=48741255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IB2014/000250 Ceased WO2014155166A1 (fr) | 2013-03-25 | 2014-03-03 | Procede de dissolution d'une couche de dioxyde de silicium |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US9514960B2 (fr) |
| JP (1) | JP6442478B2 (fr) |
| KR (1) | KR102308646B1 (fr) |
| CN (1) | CN105051881B (fr) |
| DE (1) | DE112014001629B4 (fr) |
| FR (1) | FR3003684B1 (fr) |
| SG (1) | SG11201507920XA (fr) |
| WO (1) | WO2014155166A1 (fr) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018069067A1 (fr) | 2016-10-13 | 2018-04-19 | Soitec | Procédé de dissolution d'un oxyde enfoui dans une tranche de silicium sur isolant |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009066135A1 (fr) * | 2007-11-23 | 2009-05-28 | S.O.I.Tec Silicon On Insulator Technologies | Dissolution d'oxyde précise |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6087242A (en) * | 1998-02-26 | 2000-07-11 | International Business Machines Corporation | Method to improve commercial bonded SOI material |
| JP3697106B2 (ja) | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
| JP2000277526A (ja) * | 1999-03-24 | 2000-10-06 | Canon Inc | 半導体製造装置及びそれを用いた半導体部材の製造方法 |
| KR100574150B1 (ko) * | 2002-02-28 | 2006-04-25 | 가부시키가이샤 히다치 고쿠사이 덴키 | 반도체 장치의 제조방법 |
| JP4407127B2 (ja) * | 2003-01-10 | 2010-02-03 | 信越半導体株式会社 | Soiウエーハの製造方法 |
| TWI248681B (en) | 2004-03-29 | 2006-02-01 | Imec Inter Uni Micro Electr | Method for fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel |
| JP4631347B2 (ja) * | 2004-08-06 | 2011-02-16 | 株式会社Sumco | 部分soi基板およびその製造方法 |
| WO2008050176A1 (fr) * | 2006-10-27 | 2008-05-02 | S.O.I.Tec Silicon On Insulator Technologies | Procédé optimisé de transfert d'une couche mince formée dans un substrat avec groupes de trous |
| EP2095415B1 (fr) | 2006-12-26 | 2010-10-27 | S.O.I.Tec Silicon on Insulator Technologies | Procédé de production d'une structure semiconducteur sur isolant |
| EP2109883A1 (fr) * | 2007-02-08 | 2009-10-21 | S.O.I.T.E.C. Silicon on Insulator Technologies | Procede de fabrication de substrats dissipant la chaleur de maniere importante |
| CN101669193B (zh) | 2007-04-27 | 2012-02-15 | 株式会社半导体能源研究所 | Soi衬底及其制造方法和半导体器件 |
| JP5183969B2 (ja) * | 2007-05-29 | 2013-04-17 | 信越半導体株式会社 | Soiウェーハのシリコン酸化膜形成方法 |
| FR2936356B1 (fr) * | 2008-09-23 | 2010-10-22 | Soitec Silicon On Insulator | Procede de dissolution locale de la couche d'oxyde dans une structure de type semi-conducteur sur isolant |
| JP5493345B2 (ja) * | 2008-12-11 | 2014-05-14 | 信越半導体株式会社 | Soiウェーハの製造方法 |
| FR2941324B1 (fr) * | 2009-01-22 | 2011-04-29 | Soitec Silicon On Insulator | Procede de dissolution de la couche d'oxyde dans la couronne d'une structure de type semi-conducteur sur isolant. |
| FR2964495A1 (fr) * | 2010-09-02 | 2012-03-09 | Soitec Silicon On Insulator | Procede de fabrication d'une structure seoi multiple comportant une couche isolante ultrafine |
| FR2972564B1 (fr) * | 2011-03-08 | 2016-11-04 | S O I Tec Silicon On Insulator Tech | Procédé de traitement d'une structure de type semi-conducteur sur isolant |
-
2013
- 2013-03-25 FR FR1300706A patent/FR3003684B1/fr active Active
-
2014
- 2014-03-03 WO PCT/IB2014/000250 patent/WO2014155166A1/fr not_active Ceased
- 2014-03-03 JP JP2016504764A patent/JP6442478B2/ja active Active
- 2014-03-03 SG SG11201507920XA patent/SG11201507920XA/en unknown
- 2014-03-03 DE DE112014001629.2T patent/DE112014001629B4/de active Active
- 2014-03-03 US US14/779,477 patent/US9514960B2/en active Active
- 2014-03-03 CN CN201480017598.3A patent/CN105051881B/zh active Active
- 2014-03-03 KR KR1020157029834A patent/KR102308646B1/ko active Active
-
2016
- 2016-11-14 US US15/350,290 patent/US9911624B2/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009066135A1 (fr) * | 2007-11-23 | 2009-05-28 | S.O.I.Tec Silicon On Insulator Technologies | Dissolution d'oxyde précise |
Non-Patent Citations (3)
| Title |
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| E.BUSSMANN ET AL.: "Thermal instability of silicon-on-insulator thin films measured by low- energy électron microscopy", INNOVATION IN THIN FILM PROCESSING AND CHARACTERISATION, vol. 12, 2010, pages 012016 |
| KONOCHUCK ET AL.: "Internai Dissolution of Buried Oxide in SOI Wafers", SOLID STATE PHENOMENA, vol. 131-133, 2008, pages 113 - 118, XP009108625 |
| KONONCHUCK ET AL.: "Novel trends in SOI technology for CMOS applications", SOLID STATE PHENOMENA, vol. 156-158, 2010, pages 69 - 76, XP008165382 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018069067A1 (fr) | 2016-10-13 | 2018-04-19 | Soitec | Procédé de dissolution d'un oxyde enfoui dans une tranche de silicium sur isolant |
| DE112017005180T5 (de) | 2016-10-13 | 2019-07-04 | Soitec | Verfahren zum Auflösen eines vergrabenen Oxids in einem Silicon-On-Insulator-Wafer |
| US10847370B2 (en) | 2016-10-13 | 2020-11-24 | Soitec | Method for dissolving a buried oxide in a silicon-on-insulator wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105051881B (zh) | 2017-10-17 |
| US9911624B2 (en) | 2018-03-06 |
| JP6442478B2 (ja) | 2018-12-19 |
| JP2016519432A (ja) | 2016-06-30 |
| DE112014001629B4 (de) | 2021-08-05 |
| KR102308646B1 (ko) | 2021-10-05 |
| CN105051881A (zh) | 2015-11-11 |
| DE112014001629T5 (de) | 2015-12-24 |
| FR3003684A1 (fr) | 2014-09-26 |
| US9514960B2 (en) | 2016-12-06 |
| KR20150135368A (ko) | 2015-12-02 |
| FR3003684B1 (fr) | 2015-03-27 |
| US20170062236A1 (en) | 2017-03-02 |
| SG11201507920XA (en) | 2015-10-29 |
| US20160056052A1 (en) | 2016-02-25 |
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