WO2014146363A1 - 薄膜晶体管及其制备方法、阵列基板、显示装置 - Google Patents

薄膜晶体管及其制备方法、阵列基板、显示装置 Download PDF

Info

Publication number
WO2014146363A1
WO2014146363A1 PCT/CN2013/077590 CN2013077590W WO2014146363A1 WO 2014146363 A1 WO2014146363 A1 WO 2014146363A1 CN 2013077590 W CN2013077590 W CN 2013077590W WO 2014146363 A1 WO2014146363 A1 WO 2014146363A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive layer
layer
drain
source
film transistor
Prior art date
Application number
PCT/CN2013/077590
Other languages
English (en)
French (fr)
Inventor
陈海晶
王东方
姜春生
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020147009939A priority Critical patent/KR20140123924A/ko
Priority to US14/348,427 priority patent/US20150255618A1/en
Priority to JP2016503516A priority patent/JP6333357B2/ja
Priority to EP13840128.6A priority patent/EP2978012B1/en
Publication of WO2014146363A1 publication Critical patent/WO2014146363A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
    • H01L21/47635—After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, an array substrate, and a display device. Background technique
  • Thin Film Transistor is a thin film type semiconductor device which is widely used in the fields of display technology (for example, liquid crystal display technology, organic light emitting diode display technology), integrated circuit technology and the like.
  • FIG. 1 A structure of a top gate thin film transistor is shown in FIG.
  • a semiconductor layer (active layer) 1 is provided on the substrate 9, and a gate insulating layer 21 and a gate electrode 2 are sequentially disposed above the central portion of the semiconductor layer 1.
  • the semiconductor layer 1, the gate electrode 2, and the gate insulating layer 21 are entirely covered by the protective layer 5.
  • the semiconductor layers 1 on both sides of the gate insulating layer 21 are connected to the source 3 and the drain 4 through via holes in the protective layer 5, respectively.
  • the portion of the semiconductor layer 1 between the source 3 and the drain 4 serves to conduct current, that is, to form a "conductive channel". Summary of the invention
  • Embodiments of the present invention provide a thin film transistor having a high on-state current and stable performance.
  • One aspect of the present invention provides a thin film transistor including a source, a drain, a semiconductor layer, a gate, a gate insulating layer, a mutually spaced source conductive layer and a drain conductive provided on a surface of the semiconductor layer Floor.
  • the source conductive layer is connected to the source
  • the drain conductive layer is connected to the drain; and the shortest distance between the source conductive layer and the drain conductive layer is smaller than the shortest distance between the source and the drain .
  • the source conductive layer, the drain conductive layer, and the gate insulating layer are both formed on the semiconductor layer, and the gate is formed on the gate insulating layer;
  • the thin film transistor further includes a protective layer covering the semiconductor layer, the source conductive layer, the drain conductive layer, the gate electrode, and the gate insulating layer, wherein the source and the drain pass through via holes in the protective layer and the source conductive layer and the drain, respectively The pole conductive layers are connected.
  • a portion of the upper surface of the semiconductor layer that is not covered by the gate insulating layer is The gate insulating layer is divided into independent source regions and drain regions, and the source conductive layer and the drain conductive layer cover the source region and the drain region, respectively.
  • the semiconductor layer is a metal oxide semiconductor layer; the source conductive layer and the drain conductive layer are formed by an electroless plating process.
  • the semiconductor layer is any one of a metal oxide semiconductor layer, an amorphous silicon semiconductor layer, a polysilicon semiconductor layer, and an organic semiconductor layer.
  • the source conductive layer and the drain conductive layer are made of at least one of molybdenum, copper, aluminum, and tungsten.
  • the source conductive layer is composed of at least two sub-source conductive layers that overlap each other; and/or the drain conductive layer is composed of at least two sub-drain conductive layers that overlap each other.
  • Another aspect of the present invention provides a method of fabricating a thin film transistor including a source, a drain, a semiconductor layer, a gate, and a gate insulating layer, wherein the thin film transistor further includes a semiconductor layer a surface-spaced source conductive layer and a drain conductive layer, the source conductive layer is connected to the source, the drain conductive layer is connected to the drain; and the source conductive layer and the drain conductive layer The shortest distance between them is less than the shortest distance between the source and the drain; the method includes: forming a pattern including the source conductive layer and the drain conductive layer.
  • the method of fabricating the thin film transistor further includes: forming a pattern including a semiconductor layer by a patterning process; forming a gate insulating layer on the semiconductor layer by a patterning process and located on the gate insulating layer a pattern of a gate electrode; forming a protective layer covering the semiconductor layer, the source conductive layer, the drain conductive layer, the gate electrode, the gate insulating layer, and forming a via hole in the protective layer by a patterning process; The process forms a pattern including a source and a drain, wherein the source and the drain are respectively connected to the source conductive layer and the drain conductive layer through via holes in the protective layer; wherein the source conductive layer and the drain are formed
  • the step of conducting the conductive layer is performed between the step of forming the semiconductor layer and the step of forming the protective layer.
  • a portion of the upper surface of the semiconductor layer that is not covered by the gate insulating layer is divided into independent source regions and drain regions by a gate insulating layer, the source conductive layer and the drain conductive layer.
  • the source and drain regions are covered, respectively.
  • the semiconductor layer is a metal oxide semiconductor layer; the step of forming the source conductive layer and the drain conductive layer is performed between a step of forming a gate insulating layer and a step of forming a protective layer;
  • the pattern forming the source conductive layer and the drain conductive layer includes: The plating process forms a source conductive layer and a drain conductive layer in the source region and the drain region of the upper surface of the semiconductor layer, respectively.
  • the semiconductor layer is any one of a metal oxide semiconductor layer, an amorphous silicon semiconductor layer, a polysilicon semiconductor layer, and an organic semiconductor layer.
  • the forming the pattern including the source conductive layer and the drain conductive layer includes: forming a pattern including the source conductive layer and the drain conductive layer by a patterning process.
  • the source conductive layer and the drain conductive layer are made of at least one of molybdenum, copper, aluminum, and tungsten.
  • the source conductive layer is composed of at least two sub-source conductive layers that overlap each other; and/or the drain conductive layer is composed of at least two sub-drain conductive layers that overlap each other.
  • Still another aspect of the present invention provides an array substrate comprising any of the thin film transistors described above. Still another aspect of the present invention provides a display device including the above array substrate.
  • FIG. 1 is a cross-sectional structural view showing a surface of a conventional thin film transistor passing through a source and a drain
  • FIG. 2 is a cross-sectional structural view showing a surface of a thin film transistor according to Embodiment 2 of the present invention through a source and a drain;
  • FIG. 3 is a schematic plan view showing a structure of a thin film transistor according to Embodiment 2 of the present invention before forming a conductive layer;
  • FIG. 4 is a cross-sectional structural view of the thin film transistor of FIG. 3 along AA;
  • FIG. 5 is a schematic top plan view showing a state in which a conductive layer is formed in a process of fabricating a thin film transistor according to Embodiment 2 of the present invention
  • FIG. 6 is a cross-sectional structural view of the thin film transistor of FIG. 5 taken along line BB;
  • FIG. 7 is a cross-sectional structural view of another thin film transistor according to Embodiment 2 of the present invention; wherein the reference numerals are: 1. a semiconductor layer; 2, a gate electrode; 21, a gate insulating layer; 22, a metal layer; , source; 31, source conductive layer; 4, drain; 41, drain conductive layer; 5, protective layer; 9, substrate; d, length of the semiconductor region for conduction.
  • the reference numerals are: 1. a semiconductor layer; 2, a gate electrode; 21, a gate insulating layer; 22, a metal layer; , source; 31, source conductive layer; 4, drain; 41, drain conductive layer; 5, protective layer; 9, substrate; d, length of the semiconductor region for conduction.
  • the inventors found that at least the following problems exist in the study: In order to prevent the protective layer 5 between the gate 2 and the source 3 and the drain 4 from being broken down, the source 3 and the drain are 4 (ie between two vias) need a larger distance.
  • the source layer 3 and the drain electrode 4 are electrically conductive through the semiconductor layer 1, and the semiconductor layer 1 has a limited conductivity. Therefore, the larger the length d of the semiconductor region for conducting electricity, the lower the on-state current of the thin film transistor and the worse the conductivity.
  • the distance between the source 3 and the drain 4 (or the minimum distance between the source 3 and the drain 4 and the contact portion of the semiconductor layer 1) should be as small as possible; at the same time, the via is easily deformed during the formation process.
  • the square hole originally designed will become a round hole when exposed (especially for small-sized via holes), and the shape of the via hole will also have a certain influence on the length d of the semiconductor region for conduction, which will This length d is unstable, which affects the stability of the performance of the thin film transistor.
  • This embodiment provides a thin film transistor including a source, a drain, a semiconductor layer, a gate, and a gate insulating layer.
  • the thin film transistor further includes: a source conductive layer and a drain conductive layer which are disposed on the surface of the semiconductor layer, the source conductive layer is connected to the source, and the drain conductive layer is connected to the drain; The shortest distance between the source conductive layer and the drain conductive layer is smaller than the shortest distance between the source and the drain.
  • the thin film transistor of this embodiment is provided with a source conductive layer and a drain conductive layer, and currents on the source and the drain thereof can be respectively conducted to the source conductive layer and the drain conductive layer. Therefore, the length of the semiconductor region for conduction is determined by the shortest distance between the two conductive layers, rather than by the distance between the source and the drain (or the distance between the vias). Thus, as long as the positions and shapes of the two conductive layers are determined, the length of the semiconductor region for conducting does not change regardless of the position of the source and the drain and the shape of the via, so that the thin film transistor can avoid the attack. Wear problems and ensure a large and stable on-state current.
  • This embodiment provides a thin film transistor, as shown in FIG. 2 to FIG. 7, including a source 3, a drain 4, a semiconductor layer 1, a gate 2, a gate insulating layer 21, a source conductive layer 31, and a drain.
  • the source conductive layer 31 and the drain conductive layer 41 are disposed on the surface of the semiconductor layer 1, that is, the two conductive layers 31, 41 are in contact with the surface of the semiconductor layer 1; the two conductive layers 31, 41 are spaced apart from each other, that is, two conductive layers 31, 41 are not in contact.
  • the shortest distance d between the source conductive layer 31 and the drain conductive layer 32 is smaller than the shortest distance D between the source 3 and the drain 2.
  • the gate insulating layer 21 separates the gate electrode 2 from the semiconductor layer 1, and the source electrode 3 and the drain electrode 4 and the semiconductor layer 1 on both sides of the gate insulating layer 21, respectively.
  • the source 3 and the drain 4 are connected to the semiconductor layer 1 on both sides of the gate insulating layer 21 through the source conductive layer 31 and the drain conductive layer 41, respectively.
  • the source conductive layer 31 and the drain conductive layer 41 should also not be in contact with the gate 2.
  • the thin film transistor can be classified into a top gate type (the gate 2 is disposed above the semiconductor layer 1, farther from the substrate 9 than the semiconductor layer 1) and the bottom gate type (gate 2) It is provided between the semiconductor layer 1 and the substrate 9).
  • the thin film transistor of this embodiment is a top gate type thin film transistor.
  • the semiconductor layer 1 is disposed on the substrate 9, the gate insulating layer 21 is disposed on the middle of the semiconductor layer 1, the gate 2 is disposed on the gate insulating layer 21, and the source conductive layer 31 and the drain are provided.
  • Conductive layers 41 are respectively provided on the surfaces of the semiconductor layers 1 on both sides of the gate insulating layer 21.
  • the semiconductor layer 1, the gate 2, the gate insulating layer 21, The source conductive layer 31, the drain conductive layer 41, and the like are all covered by the protective layer 5, and the source 3 and the drain 4 are connected to the source conductive layer 31 and the drain conductive layer 41 through via holes in the protective layer 5, respectively.
  • the source 3, the drain 4, and the gate 2 are also provided on the top side of the semiconductor layer 1, breakdown between the source 3, the drain 4, and the gate 2 is more likely to occur. This embodiment can reduce or avoid such problems.
  • a portion of the upper surface of the semiconductor layer 1 not covered by the gate insulating layer 21 is divided into independent source regions (regions on the left side of the gate insulating layer 21) by the gate insulating layer 21 and The drain region (the region on the right side of the gate insulating layer 21).
  • the source conductive layer 31 and the drain conductive layer 41 cover the source region and the drain region, respectively.
  • the source conductive layer 31 and the drain conductive layer 41 respectively cover the exposed surface of the semiconductor layer 1, and are respectively adjacent to both sides of the gate insulating layer 21, which can be used for the conductive semiconductor region.
  • the length d is minimized, and such a source conductive layer 31 and a drain conductive layer 41 are also easily prepared by an electroless plating process.
  • the source conductive layer 31 and the drain conductive layer 41 are made of at least one of molybdenum, copper, aluminum, tungsten, for example, an alloy composed of any one or more of these metals.
  • metal/alloy materials are commonly used conductive metals in the semiconductor field and do not adversely affect the performance of semiconductor devices. Of course, it is also possible to use other types of conductive materials.
  • the source conductive layer 31 is composed of at least two sub-source conductive layers that overlap each other; or, the drain conductive layer 41 may also be composed of at least two sub-drain conductive layers that overlap each other.
  • At least one of the source conductive layer 31 and the drain conductive layer 41 may be composed of a plurality of overlapping layers, and the materials of each layer may be the same or different.
  • the properties of the source conductive layer 31 and the drain conductive layer 41 can be better adjusted, for example, it is bonded to the semiconductor layer and has good electrical conductivity.
  • the semiconductor layer 1 is a metal oxide semiconductor layer, that is, the thin film transistor is a metal oxide thin film transistor.
  • the metal oxide thin film transistor is preferable in that it has many advantages such as high carrier mobility, a simple preparation process, good film formation uniformity, and low cost.
  • a-Si amorphous silicon semiconductor
  • P-Si polycrystalline silicon semiconductor
  • organic semiconductor organic semiconductor
  • the source conductive layer 31 and the drain conductive layer 41 may be fabricated by an electroless plating process.
  • the thin film transistor of the present embodiment is not limited to the top gate type structure, and other forms of thin film transistors are also possible.
  • the gate electrode 2 and the gate insulating layer 21 are disposed between the semiconductor layer 1 and the substrate 9, that is, the thin film transistor is a bottom gate type structure;
  • the thin film transistor may have other structures.
  • the substrate 9 may be provided with a buffer layer, and the semiconductor layer 1 may further include various doping regions and the like for improving the performance thereof. Since the specific form of the thin film transistor is various, it will not be described one by one here, but as long as the source 3 and the drain 4 are connected to the semiconductor layer 1 through the source conductive layer 31 and the drain conductive layer 41, respectively. It belongs to the scope of protection of the present invention.
  • the preparation of the thin film transistor of the above embodiment may include the following steps S01 to S06.
  • a pattern including the semiconductor layer 1 is formed on the substrate 9 by, for example, a patterning process.
  • the patterning process is, for example, a photolithography process, and generally includes the steps of forming a deposited layer, photoresist coating, exposure, development, etching, photoresist stripping, and the like.
  • the source conductive layer 31 and the drain conductive layer 41 can be formed by an electroless plating process.
  • the electroless plating process is easy and low cost; and due to its process characteristics, it will only form a film on metal or metal oxide.
  • the substrate 9 is usually a glass material, and the gate insulating layer 21 is usually made of silicon nitride or the like, so that the source conductive layer 31 and the drain conductive layer 41 are directly formed on the gate insulating layer 21.
  • the surface of the semiconductor layer 1 on the side, and the conductive layer is not formed on the gate insulating layer 21 and the substrate 9.
  • the thin film transistor having the shortest length d of the semiconductor region for conduction as shown in Figs. 5 and 6 can be directly formed.
  • the gate electrode 2 is usually of a metallic material, the metal layer 22 is also formed thereon, but the presence of this layer has no effect on the performance of the gate electrode 2.
  • the electroless plating phase liquid is coated on the substrate 9 having the structure shown in FIGS. 3 and 4 at a temperature between room temperature and 100 ° C, and is subjected to The reaction is completed to obtain the structure shown in Figs. 5 and 6, and then washed, dried, and subjected to subsequent steps.
  • the composition of the electroless molybdenum plating solution may include: 0.1 to 0.3 mol/L of molybdenum sulfate, 0.05 to 0.15 mol/L of sodium sulfide (stabilizer), 0.1 to 1 mol/L of sodium acetate (buffer), 0.1 ⁇ Lmol/L of tartaric acid (complexing agent), the balance of water.
  • the above is only a specific example of the electroless plating liquid, and the composition thereof may be different.
  • other substances such as an accelerator, a pH adjuster, and the like may be contained, and the concentration and substance selection of each of the existing components may be different.
  • the step of forming the source conductive layer 31 and the drain conductive layer 41 by the electroless plating process may be performed after the gate insulating layer 21 is formed, and should be before the step of forming the protective layer 5 described below. That is to say, the steps S03 and S04 are interchangeable, that is, the conductive layers 31, 41 can be formed first, and then the gate 2 is formed, so that the metal layer 22 is not formed on the gate 2.
  • a pattern including the source conductive layer 31 and the drain conductive layer 41 can also be formed by a patterning process.
  • the patterning process is relatively complicated, it has a wide range of applications and can be used to form conductive layers 31, 41 of various materials (for example, a conductive layer which can form a non-metal material), and can form any form of conductive layer 31, 41, for example.
  • the conductive layers 31, 41 covering only a part of the surface of the semiconductor layer 1 as shown in Fig. 7 can be formed, and it is difficult to form such a structure by an electroless plating process.
  • this step may be performed after the step of forming the semiconductor layer 1, and should be interchanged with the step of forming the protective layer 5 described below, that is, it can be replaced with the step of forming the gate electrode 2 to form the gate insulating layer 21.
  • a protective layer 5 is formed, and via holes are formed in the protective layer 5 by a patterning process.
  • the specific preparation method thereof is also various and will not be described one by one, but it is within the scope of the present invention as long as it includes the steps of forming the source conductive layer 31 and the drain conductive layer 41.
  • the array substrate may include a substrate and gate lines and data lines formed on the substrate, the gate lines and the data lines crossing each other and defining a plurality of pixel units, each of the pixel units being provided with at least one thin film transistor, and At least one of the thin film transistors is the above thin film transistor.
  • the array substrate may also have other known structures such as a storage capacitor, a pixel electrode, an organic light emitting diode, a pixel defining layer (PDL), and the like, and will not be described in detail herein.
  • a storage capacitor such as a capacitor, a pixel electrode, an organic light emitting diode, a pixel defining layer (PDL), and the like, and will not be described in detail herein.
  • PDL pixel defining layer
  • the array substrate of the present embodiment has the above-described thin film transistor, its performance is stable and can be used for realizing high quality display.
  • This embodiment provides a display device including the above array substrate.
  • the display device is a liquid crystal display device or an organic light emitting diode display device.
  • the display device is a liquid crystal display device
  • the array substrate and the opposite substrate are opposed to each other to form a liquid crystal cell
  • the liquid crystal cell is filled with a liquid crystal material.
  • the opposite substrate is, for example, a color filter substrate.
  • a power supply unit for example, a frame, a driving unit, a color film, a liquid crystal layer, and the like may be provided in the display device, and will not be described in detail herein.
  • the display device of the present embodiment has the above array substrate, its display quality is high and stable.
  • the above is only an exemplary embodiment of the present invention, and is not intended to limit the scope of the present invention.
  • the scope of the present invention is defined by the appended claims.

Abstract

一种薄膜晶体管及其制备方法、阵列基板、显示装置，属于薄膜晶体管技术领域，其可解决现有的薄膜晶体管开态电流低且性能不稳定的问题。本发明的薄膜晶体管包括源极（3）、漏极（4）、半导体层（1）、栅极（2）、栅极绝缘层（21），且还包括：设于所述半导体层表面的、相互间隔的源极导电层（31）和漏极导电层（41），源极导电层与源极相连，漏极导电层与漏极相连；且源极导电层与漏极导电层间的最短距离小于源极与漏极间的最短距离。薄膜晶体管的制备方法包括形成源极导电层和漏极导电层的步骤。阵列基板和显示装置包括上述薄膜晶体管。上述薄膜晶体管可用于显示装置中，尤其是用于液晶显示装置、有机发光二极管显示装置。

Description

薄膜晶体管及其制备方法、 阵列基板、 显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管及其制备方法、 阵列基板、 显示装 置。 背景技术
薄膜晶体管 (Thin Film Transistor)是一种薄膜型的半导体器件， 其在显示 技术 (例如液晶显示技术、 有机发光二极管显示技术)、 集成电路技术等领域 中被广泛应用。
一种顶栅型薄膜晶体管的结构如图 1所示。 半导体层 （有源层） 1设于基 底 9上，半导体层 1中部上方依次设有栅极绝缘层 21和栅极 2。半导体层 1、 栅极 2和栅极绝缘层 21整体被保护层 5覆盖。 栅极绝缘层 21两侧的半导体 层 1分别通过保护层 5中的过孔与源极 3和漏极 4相连。 在薄膜晶体管导通 时， 位于源极 3和漏极 4之间的半导体层 1部分用于传导电流， 也就是形成 "导电沟道" 。 发明内容
本发明的实施例提供一种开态电流高且性能稳定的薄膜晶体管。
本发明的一个方面提供了一种薄膜晶体管， 包括源极、 漏极、半导体层、 栅极、 栅极绝缘层、 设于所述半导体层表面的、 相互间隔的源极导电层和漏 极导电层。 所述源极导电层与源极相连， 所述漏极导电层与漏极相连； 且所 述源极导电层与漏极导电层间的最短距离小于所述源极与漏极间的最短距 离。
在一个示例中， 所述源极导电层、 漏极导电层、 栅极绝缘层均形成在所 述半导体层上，所述栅极形成在所述栅极绝缘层上；所述薄膜晶体管还包括： 覆盖所述半导体层、 源极导电层、 漏极导电层、栅极、栅极绝缘层的保护层， 所述源极和漏极通过保护层中的过孔分别与源极导电层和漏极导电层相连。
在一个示例中， 所述半导体层上表面未被所述栅极绝缘层覆盖的部分被 栅极绝缘层分割为独立的源极区和漏极区， 所述源极导电层和漏极导电层分 别覆盖所述源极区和漏极区。
在一个示例中， 所述半导体层为金属氧化物半导体层； 所述源极导电层 和漏极导电层是通过化学镀工艺形成的。
在一个示例中，所述半导体层为金属氧化物半导体层、非晶硅半导体层、 多晶硅半导体层、 有机半导体层中的任意一种。
在一个示例中， 所述源极导电层和漏极导电层由钼、 铜、 铝、 钨中的至 少一种金属制成。
在一个示例中， 所述源极导电层由至少两个相互重叠的子源极导电层构 成； 和 /或所述漏极导电层由至少两个相互重叠的子漏极导电层构成。
本发明的另一个方面提供了一种薄膜晶体管的制备方法， 所述薄膜晶体 管包括源极、 漏极、 半导体层、 栅极、 栅极绝缘层， 所述薄膜晶体管还包括 设于所述半导体层表面的、 相互间隔的源极导电层和漏极导电层， 所述源极 导电层与源极相连， 所述漏极导电层与漏极相连； 且所述源极导电层与漏极 导电层间的最短距离小于所述源极与漏极间的最短距离； 所述方法包括： 形 成包括所述源极导电层和漏极导电层的图形。
在一个示例中， 所述薄膜晶体管的制备方法还包括： 通过构图工艺形成 包括半导体层的图形； 通过构图工艺形成包括位于所述半导体层上的栅极绝 缘层以及位于所述栅极绝缘层上的栅极的图形； 形成覆盖所述半导体层、 源 极导电层、 漏极导电层、 栅极、 栅极绝缘层的保护层， 并通过构图工艺在所 述保护层中形成过孔； 通过构图工艺形成包括源极和漏极的图形， 所述源极 和漏极通过保护层中的过孔分别与源极导电层和漏极导电层相连； 其中， 所 述形成源极导电层和漏极导电层的步骤在形成半导体层的步骤和形成保护层 的步骤之间进行。
在一个示例中， 所述半导体层上表面未被所述栅极绝缘层覆盖的部分被 栅极绝缘层分割为独立的源极区和漏极区， 所述源极导电层和漏极导电层分 别覆盖所述源极区和漏极区。
在一个示例中， 所述半导体层为金属氧化物半导体层； 所述形成源极导 电层和漏极导电层的步骤在形成栅极绝缘层的步骤和形成保护层的步骤之间 进行； 且， 所述形成包括所述源极导电层和漏极导电层的图形包括： 通过化 学镀工艺在所述半导体层上表面的源极区和漏极区中分别形成源极导电层和 漏极导电层。
在一个示例中，所述半导体层为金属氧化物半导体层、非晶硅半导体层、 多晶硅半导体层、 有机半导体层中的任意一种。
在一个示例中，所述形成包括所述源极导电层和漏极导电层的图形包括： 通过构图工艺形成包括所述源极导电层和漏极导电层的图形。
在一个示例中， 所述源极导电层和漏极导电层由钼、 铜、 铝、 钨中的至 少一种金属制成。
在一个示例中， 所述源极导电层由至少两个相互重叠的子源极导电层构 成； 和 /或所述漏极导电层由至少两个相互重叠的子漏极导电层构成。
本发明的再一个方面提供了一种阵列基板，包括上述任一的薄膜晶体管。 本发明的再一个方面提供了一种显示装置， 包括上述阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有的薄膜晶体管经过源极和漏极的面的剖视结构示意图； 图 2为本发明的实施例 2的薄膜晶体管经过源极和漏极的面的剖视结构 示意图；
图 3为本发明的实施例 2的薄膜晶体管的制备过程中在形成导电层前的 俯视结构示意图；
图 4为图 3的薄膜晶体管沿 AA，面的剖视结构示意图；
图 5为本发明的实施例 2的薄膜晶体管的制备过程中在形成导电层后的 俯视结构示意图；
图 6为图 5的薄膜晶体管沿 BB，面的剖视结构示意图；
图 7为本发明的实施例 2的另一种薄膜晶体管的剖视结构示意图； 其中附图标记为： 1、 半导体层； 2、 栅极； 21、 栅极绝缘层； 22、 金属 层； 3、 源极； 31、 源极导电层； 4、 漏极； 41、 漏极导电层； 5、 保护层； 9、 基底； d、 用于导电的半导体区的长度。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个" 、 "一" 或者 "该"等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或 者物件涵盖出现在 "包括"或者 "包含"后面列举的元件或者物件及其等同， 并不排除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定 于物理的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间 接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用于表示相对位置关系， 当被 描述对象的绝对位置改变后， 则该相对位置关系也可能相应地改变。
对于图 1所示的薄膜晶体管，发明人在研究中发现其至少存在如下问题： 为避免栅极 2与源极 3、漏极 4间的保护层 5被击穿，故源极 3和漏极 4间（即 两个过孔间）需要有较大的距离。 源极 3和漏极 4之间通过半导体层 1导电， 而半导体层 1导电能力有限， 故用于导电的半导体区的长度 d越大则薄膜晶 体管的开态电流越低， 导电能力越差， 因此这又要求而源极 3和漏极 4间的 距离 (或者说源极 3和漏极 4与半导体层 1接触部分间的最小距离)应尽量小； 同时， 过孔在形成过程中易变形， 例如原本设计的方孔在曝光时会变为圓孔 (对小尺寸的过孔尤其明显)， 而过孔的形状也会对用于导电的半导体区的长 度 d产生一定的影响， 这会导致该长度 d不稳定， 影响薄膜晶体管性能的稳 定性。
实施例 1
本实施例提供一种薄膜晶体管， 其包括源极、 漏极、 半导体层、 栅极、 栅极绝缘层。 该薄膜晶体管还包括： 设于半导体层表面的、 相互间隔的源极导电层和 漏极导电层， 所述源极导电层与源极相连， 所述漏极导电层与漏极相连； 且 所述源极导电层与漏极导电层间的最短距离小于所述源极与漏极间的最短距 离。
本实施例的薄膜晶体管中设有源极导电层和漏极导电层， 其源极和漏极 上的电流可分别传导到源极导电层和漏极导电层上。 所以， 用于导电的半导 体区的长度是由两个导电层间的最短距离决定的， 而非由源极和漏极间的距 离 (或者说过孔间的距离）决定。 这样， 只要两个导电层的位置、 形状确定， 则不论源极和漏极处于什么位置以及过孔形状如何， 用于导电的半导体区的 长度都不会变化， 因此该薄膜晶体管既可避免击穿问题， 又可保证较大且稳 定的开态电流。
实施例 2
本实施例提供一种薄膜晶体管， 如图 2至图 7所示， 其包括源极 3、 漏 极 4、 半导体层 1、 栅极 2、 栅极绝缘层 21、 源极导电层 31、 漏极导电层 41。 源极导电层 31和漏极导电层 41设于半导体层 1表面， 即两个导电层 31、 41 均与半导体层 1表面接触； 两个导电层 31、 41相互隔开， 即两个导电层 31、 41间不接触。源极导电层 31与漏极导电层 32间的最短距离 d小于源极 3与 漏极 2间的最短距离 D。
在图 1所示的薄膜晶体管的常规结构中，栅极绝缘层 21将栅极 2与半导 体层 1隔开，而源极 3和漏极 4分别与栅极绝缘层 21两侧的半导体层 1相连。 与上述常规的薄膜晶体管不同， 本实施例中源极 3和漏极 4是分别通过源极 导电层 31和漏极导电层 41与栅极绝缘层 21两侧的半导体层 1相连， 因此， 在此种情况下该源极导电层 31和漏极导电层 41也不应与栅极 2接触。
根据栅极 2与栅极绝缘层 21位置的不同， 薄膜晶体管可分为顶栅型 (栅 极 2设在半导体层 1上方，比半导体层 1更远离基底 9)和底栅型 (栅极 2设在 半导体层 1与基底 9之间）。
优选的， 本实施例的薄膜晶体管为顶栅型薄膜晶体管。 如图 2所示， 其 半导体层 1设在基底 9上， 栅极绝缘层 21设在半导体层 1的中部上， 栅极 2 设在栅极绝缘层 21上，源极导电层 31和漏极导电层 41分别设在栅极绝缘层 21两侧的半导体层 1表面上。 同时， 半导体层 1、 栅极 2、 栅极绝缘层 21、 源极导电层 31、 漏极导电层 41等均被保护层 5覆盖， 源极 3和漏极 4通过 保护层 5中的过孔分别与源极导电层 31和漏极导电层 41相连。
对于顶栅型薄膜晶体管， 因其源极 3、 漏极 4、栅极 2同样设在半导体层 1的顶侧， 故更容易发生源极 3、 漏极 4、 栅极 2间的击穿， 本实施例则可以 减少或避免这样的问题。
进一步优选的，如图 3所示，半导体层 1上表面未被栅极绝缘层 21覆盖 的部分被栅极绝缘层 21分割为独立的源极区 （栅极绝缘层 21左侧的区域） 和漏极区 （栅极绝缘层 21右侧的区域） 。 如图 5所示， 源极导电层 31和漏 极导电层 41分别覆盖源极区和漏极区。
也就是说， 源极导电层 31和漏极导电层 41分别覆盖满了半导体层 1的 棵露表面，并分别紧邻栅极绝缘层 21的两侧，这种方式可将用于导电的半导 体区的长度 d减少到最小， 同时这样的源极导电层 31和漏极导电层 41也便 于用化学镀工艺制备。
优选的， 例如， 源极导电层 31和漏极导电层 41由钼、 铜、 铝、 钨中的 至少一种金属制成， 例如由这些金属中的任意一种或多种组成的合金构成。
以上的金属 /合金材料为半导体领域的常用导电金属，不会对半导体器件 的性能产生不良影响。 当然， 如果使用其他类型的导电材料， 也是可行的。
优选的，例如，源极导电层 31由至少两个相互重叠的子源极导电层构成； 或者， 漏极导电层 41也可以由至少两个相互重叠的子漏极导电层构成。
也就是说， 源极导电层 31和漏极导电层 41至少之一可由多个重叠的层 组成， 每个层的材料可以相同或不同。 通过采用这种多层的结构， 可以更好 的调整源极导电层 31和漏极导电层 41的性能， 比如使其既与半导体层结合 紧密又导电性能良好。
优选的， 例如， 半导体层 1为金属氧化物半导体层， 即薄膜晶体管为金 属氧化物薄膜晶体管。
金属氧化物薄膜晶体管具有载流子迁移率高、 制备工艺筒单、 成膜均匀 性好、 成本低等诸多优点， 故是优选的。 当然， 如果以非晶硅半导体 (a-Si)、 多晶硅半导体 (P-Si)、 有机半导体等其他材料作为半导体层 1 , 也是可行的。
同时， 优选的， 当半导体层 1为金属氧化物半导体层时， 源极导电层 31 和漏极导电层 41可由化学镀工艺制造。 当然， 应当理解， 本实施例的薄膜晶体管并不限于顶栅型结构， 其他形 式的薄膜晶体管也是可行的。
例如， 如图 7所示， 在另一个实施例的薄膜晶体管中， 栅极 2和栅极绝 缘层 21设于半导体层 1与基底 9之间， 即该薄膜晶体管为底栅型结构)； 同 时， 根据具体的需要， 薄膜晶体管中还可具有其他的结构， 例如基底 9上还 可设有緩沖层， 半导体层 1中还可包括用于改善其性能的各种掺杂区等。 由 于薄膜晶体管的具体形式是多样的， 故在此不再逐一描述， 但只要其源极 3 和漏极 4是分别通过源极导电层 31和漏极导电层 41与半导体层 1相连的， 即属于本发明的保护范围。
上述实施例的薄膜晶体管的制备可包括以下步骤 S01~S06。
501、 例如通过构图工艺在基底 9上形成包括半导体层 1的图形。
构图工艺例如为光刻工艺， 通常包括形成沉积层、 光刻胶涂布、 曝光、 显影、 刻蚀、 光刻胶剥离等步骤。
502、 在完成上述步骤的基板上沉积栅极绝缘层薄膜。
S03、 在完成上述步骤的基板上沉积栅金属薄膜， 通过构图工艺形成包 括栅极绝缘层 21与栅极 2的图形， 得到如图 3、 图 4所示的结构。
S04、 形成源极导电层 31和漏极导电层 41 , 得到如图 5、 图 6所示的结 构。
例如， 对于如图 2所示的顶栅型薄膜晶体管， 若其半导体层 1为金属氧 化物半导体层，则其源极导电层 31和漏极导电层 41可通过化学镀工艺形成。
化学镀工艺筒单易行， 成本低； 且由于其工艺特点， 其只会在金属或金 属氧化物上成膜。 对于顶栅型薄膜晶体管， 其基底 9通常为玻璃材料， 栅极 绝缘层 21通常为氮化硅等材料 ,故源极导电层 31和漏极导电层 41会直接形 成在栅极绝缘层 21两侧的半导体层 1表面， 而栅极绝缘层 21和基底 9上不 形成导电层。 这样， 可直接制成如图 5、 图 6所示的具有最短的用于导电的 半导体区的长度 d的薄膜晶体管。
当然， 由于栅极 2通常是金属材料的， 故其上也会形成金属层 22, 但该 层的存在对栅极 2的性能没有影响。
以形成钼导电层作为化学镀工艺的例子说明如下。 在室温至 100°C间的 温度下， 将化学镀相液涂布在具有如图 3、 图 4所示结构的基底 9上， 待其 反应完全即可得到如图 5、 图 6所示的结构， 之后清洗、 烘干， 进行后续步 骤。
例如，化学镀钼液的成分可包括： 0.1~0.3mol/L的硫酸钼， 0.05-0.15mol/L 的硫化钠 (稳定剂）， 0.1~lmol/L的醋酸钠 (緩沖剂）， 0.1~lmol/L的酒石酸 (络 合剂）， 余量的水。 当然， 以上只是化学镀相液的一个具体例子， 其成分可有 不同， 例如其中还可含有加速剂、 pH值调节剂等其他物质， 且各已有组分的 浓度、 物质选择也可不同。
由于通过化学镀形成导电层的工艺是已知的， 故在此不再对其进行详细 介绍。
当然， 应当理解， 通过化学镀工艺形成源极导电层 31和漏极导电层 41 的步骤只要在形成栅极绝缘层 21之后进行即可，而应当在下述的形成保护层 5的步骤之前， 也就是说， S03与 S04步骤是可以互换的， 即可以先成导电 层 31、 41 , 再形成栅极 2, 这样栅极 2上就不会再形成金属层 22了。
例如， 也可通过构图工艺形成包括源极导电层 31和漏极导电层 41的图 形。
构图工艺虽然相对复杂， 但是其适用范围广， 可用于形成各种材料的导 电层 31、 41(例如其可形成非金属材料的导电层)， 且可形成任何形式的导电 层 31、 41 , 例如， 可形成如图 7所示的只覆盖半导体层 1表面一部分的导电 层 31、 41 , 而化学镀工艺则难以形成这样的结构。
当然，应当理解，如果是通过构图工艺形成源极导电层 31和漏极导电层
41 , 则此步骤只要在形成半导体层 1的步骤之后即可， 而应当在下述的形成 保护层 5的步骤之前，即其可与形成栅极 2、形成栅极绝缘层 21的步骤互换。
505、 例如形成保护层 5 , 并通过构图工艺在保护层 5中形成过孔。
506、 通过构图工艺形成包括源极 3和漏极 4的图形， 其中源极 3和漏 极 4通过保护层 5中的过孔分别与源极导电层 31和漏极导电层 41相连。
当然， 根据薄膜晶体管结构的不同， 其具体制备方法也是多样的， 在此 不再逐一描述， 但只要其包括形成源极导电层 31和漏极导电层 41的步骤即 属于本发明的保护范围。
实施例 3
本实施例提供一种阵列基板， 其包括上述的薄膜晶体管。 例如， 该阵列基板可包括基底和形成于基底上的栅极线和数据线， 栅极 线和数据线相互交叉并定义了多个像素单元， 每个像素单元中设有至少一个 薄膜晶体管， 且其中至少有一个薄膜晶体管是上述的薄膜晶体管。
该阵列基板还可以具有存储电容、 像素电极、 有机发光二极管、 像素限 定层 (PDL)等其他的已知结构， 在此不再详细描述。
由于本实施例的阵列基板具有上述的薄膜晶体管， 故其性能稳定， 可用 于实现高质量的显示。
实施例 4
本实施例提供一种显示装置， 其包括上述的阵列基板。
例如， 该显示装置为液晶显示装置或有机发光二极管显示装置。
例如， 当该显示装置为液晶显示装置时， 该阵列基板与对置基板彼此对 置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如为彩膜基板。
例如， 在显示装置中还可以具有电源单元、 框架、 驱动单元、 彩膜、 液 晶层等其他的已知结构， 在此不再详细描述。
由于本实施例的显示装置具有上述的阵列基板，故其显示质量高且稳定。 以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1. 一种薄膜晶体管， 包括：
源极、 漏极、 半导体层、 栅极、 栅极绝缘层， 以及
设于所述半导体层表面的、相互间隔的源极导电层和漏极导电层，其中， 所述源极导电层与源极相连， 所述漏极导电层与漏极相连； 且所述源极导电 层与漏极导电层间的最短距离小于所述源极与漏极间的最短距离。
2.根据权利要求 1所述的薄膜晶体管， 其中，
所述源极导电层、 漏极导电层、 栅极绝缘层均形成在所述半导体层上， 所述栅极形成在所述栅极绝缘层上； 且， 所述薄膜晶体管还包括：
覆盖所述半导体层、 源极导电层、 漏极导电层、 栅极、 栅极绝缘层的保 护层， 所述源极和漏极通过保护层中的过孔分别与源极导电层和漏极导电层 相连。
3.根据权利要求 2所述的薄膜晶体管， 其中，
所述半导体层上表面未被所述栅极绝缘层覆盖的部分被栅极绝缘层分割 为独立的源极区和漏极区， 所述源极导电层和漏极导电层分别覆盖所述源极 区和漏极区。
4.根据权利要求 1-3任一所述的薄膜晶体管， 其中，
所述半导体层为金属氧化物半导体层；
所述源极导电层和漏极导电层是通过化学镀工艺形成的。
5.根据权利要求 1-3任一所述的薄膜晶体管， 其中，
所述半导体层为金属氧化物半导体层、 非晶硅半导体层、 多晶硅半导体 层、 有机半导体层中的任意一种。
6.根据权利要求 1至 4中任意一项所述的薄膜晶体管， 其中，
所述源极导电层和漏极导电层由钼、铜、铝、钨中的至少一种金属制成。
7.根据权利要求 1至 4中任意一项所述的薄膜晶体管， 其中，
所述源极导电层和所述漏极导电层至少之一由至少两个相互重叠的子源 极导电层构成。
8.一种薄膜晶体管的制备方法， 所述薄膜晶体管包括源极、 漏极、 半导 体层、 栅极、 栅极绝缘层、 设于所述半导体层表面的、 相互间隔的源极导电 层和漏极导电层，所述源极导电层与源极相连，所述漏极导电层与漏极相连； 且所述源极导电层与漏极导电层间的最短距离小于所述源极与漏极间的最短 巨离； 该方法包括：
形成包括所述源极导电层和漏极导电层的图形。
9.根据权利要求 8所述的薄膜晶体管的制备方法， 其中， 还包括： 通过构图工艺形成包括半导体层的图形；
通过构图工艺形成包括位于所述半导体层上的栅极绝缘层以及位于所述 栅极绝缘层上的栅极的图形；
形成覆盖所述半导体层、 源极导电层、 漏极导电层、 栅极、 栅极绝缘层 的保护层， 并通过构图工艺在所述保护层中形成过孔；
通过构图工艺形成包括源极和漏极的图形， 所述源极和漏极通过保护层 中的过孔分别与源极导电层和漏极导电层相连；
其中，
所述形成源极导电层和漏极导电层的步骤在形成半导体层的步骤和形成 保护层的步骤之间进行。
10.根据权利要求 9所述的薄膜晶体管的制备方法， 其中，
所述半导体层上表面未被所述栅极绝缘层覆盖的部分被栅极绝缘层分割 为独立的源极区和漏极区， 所述源极导电层和漏极导电层分别覆盖所述源极 区和漏极区。
11.根据权利要求 10所述的薄膜晶体管的制备方法， 其中， 所述半导体 层为金属氧化物半导体层； 所述形成源极导电层和漏极导电层的步骤在形成 栅极绝缘层的步骤和形成保护层的步骤之间进行； 且， 所述形成包括所述源 极导电层和漏极导电层的图形包括：
通过化学镀工艺在所述半导体层上表面的源极区和漏极区中分别形成源 极导电层和漏极导电层。
12.根据权利要求 8至 10中任意一项所述的薄膜晶体管的制备方法，其 中， 所述半导体层为金属氧化物半导体层、 非晶硅半导体层、 多晶硅半导体 层、 有机半导体层中的任意一种。
13.根据权利要求 8至 10中任意一项所述的薄膜晶体管的制备方法，其 中， 所述形成包括所述源极导电层和漏极导电层的图形包括： 通过构图工艺形成包括所述源极导电层和漏极导电层的图形。
14.根据权利要求 8至 11中任意一项所述的薄膜晶体管的制备方法，其 中， 所述源极导电层和漏极导电层由钼、铜、 铝、 钨中的至少一种金属制成。
15.根据权利要求 8至 11中任意一项所述的薄膜晶体管的制备方法，其 中，
所述源极导电层和所述漏极导电层至少之一由至少两个相互重叠的子源 极导电层构成。
16. 一种阵列基板， 包括： 权利要求 1至 7中任意一项所述的薄膜晶体 管。
17. —种显示装置， 包括： 权利要求 16所述的阵列基板。
PCT/CN2013/077590 2013-03-20 2013-06-20 薄膜晶体管及其制备方法、阵列基板、显示装置 WO2014146363A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020147009939A KR20140123924A (ko) 2013-03-20 2013-06-20 박막 트랜지스터(ｔｆｔ), 그의 제조 방법, 어레이 기판 및 디스플레이 장치
US14/348,427 US20150255618A1 (en) 2013-03-20 2013-06-20 Thin-film transistor (tft), preparation method thereof, array substrate and display device
JP2016503516A JP6333357B2 (ja) 2013-03-20 2013-06-20 薄膜トランジスタ及びその製造方法、アレイ基板、ディスプレイ
EP13840128.6A EP2978012B1 (en) 2013-03-20 2013-06-20 Thin-film transistor and preparation method therefor, array substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310090696.7A CN103199113B (zh) 2013-03-20 2013-03-20 薄膜晶体管及其制备方法、阵列基板、显示装置
CN201310090696.7 2013-03-20

Publications (1)

Publication Number Publication Date
WO2014146363A1 true WO2014146363A1 (zh) 2014-09-25

Family

ID=48721558

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/077590 WO2014146363A1 (zh) 2013-03-20 2013-06-20 薄膜晶体管及其制备方法、阵列基板、显示装置

Country Status (6)

Country Link
US (1) US20150255618A1 (zh)
EP (1) EP2978012B1 (zh)
JP (1) JP6333357B2 (zh)
KR (1) KR20140123924A (zh)
CN (1) CN103199113B (zh)
WO (1) WO2014146363A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104752517A (zh) * 2013-12-31 2015-07-01 昆山工研院新型平板显示技术中心有限公司 一种薄膜晶体管及其制备方法和应用
GB2548721B (en) * 2014-12-16 2020-11-11 Lg Display Co Ltd Thin-film transistor array substrate
CN105842941B (zh) * 2015-01-13 2019-07-05 群创光电股份有限公司 显示面板
US11315961B2 (en) * 2017-03-17 2022-04-26 Ricoh Company, Ltd. Field-effect transistor, method for producing same, display element, display device, and system
JP2018157206A (ja) * 2017-03-17 2018-10-04 株式会社リコー 電界効果型トランジスタ及びその製造方法、表示素子、表示装置、システム
CN108735761A (zh) * 2017-04-20 2018-11-02 京东方科技集团股份有限公司 导电图案结构及其制备方法、阵列基板和显示装置
CN107170807B (zh) * 2017-05-11 2020-07-31 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
CN108389867A (zh) * 2018-02-26 2018-08-10 深圳市华星光电半导体显示技术有限公司 阵列基板及阵列基板的制作方法
CN108447916B (zh) * 2018-03-15 2022-04-15 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板、显示装置
CN110571226B (zh) 2019-09-05 2021-03-16 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制备方法
CN110600517B (zh) * 2019-09-16 2021-06-01 深圳市华星光电半导体显示技术有限公司 一种显示面板及其制备方法
CN110729359A (zh) * 2019-10-25 2020-01-24 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管、显示面板及薄膜晶体管的制作方法
CN112635572A (zh) * 2020-12-24 2021-04-09 广东省科学院半导体研究所 薄膜晶体管及其制备方法和显示器件
CN117177620A (zh) * 2021-05-12 2023-12-05 厦门天马微电子有限公司 显示面板及显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5658806A (en) * 1995-10-26 1997-08-19 National Science Council Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration
CN102544104A (zh) * 2012-01-12 2012-07-04 清华大学 一种耐高压的隧穿晶体管及其制备方法
CN102636927A (zh) * 2011-12-23 2012-08-15 京东方科技集团股份有限公司 阵列基板及其制造方法
CN103000531A (zh) * 2012-12-14 2013-03-27 友达光电股份有限公司 一种用于低温多晶硅薄膜晶体管的制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7378286B2 (en) * 2004-08-20 2008-05-27 Sharp Laboratories Of America, Inc. Semiconductive metal oxide thin film ferroelectric memory transistor
US20060197092A1 (en) * 2005-03-03 2006-09-07 Randy Hoffman System and method for forming conductive material on a substrate
JP2008218960A (ja) * 2007-02-08 2008-09-18 Mitsubishi Electric Corp 薄膜トランジスタ装置、その製造方法、及び表示装置
JP5415001B2 (ja) * 2007-02-22 2014-02-12 株式会社半導体エネルギー研究所 半導体装置
KR101453829B1 (ko) * 2007-03-23 2014-10-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치 및 그 제조 방법
TWI351765B (en) * 2007-08-29 2011-11-01 Au Optronics Corp Display element and method of manufacturing the sa
JP4650521B2 (ja) * 2008-06-05 2011-03-16 ソニー株式会社 電極及びその形成方法、半導体デバイス
KR101108175B1 (ko) * 2010-06-09 2012-01-31 삼성모바일디스플레이주식회사 박막 트랜지스터, 이를 포함하는 디스플레이 장치용 어레이 기판 및 그 제조 방법
CN102122620A (zh) * 2011-01-18 2011-07-13 北京大学深圳研究生院 一种自对准薄膜晶体管的制作方法
US8541781B2 (en) * 2011-03-10 2013-09-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9012905B2 (en) * 2011-04-08 2015-04-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including transistor comprising oxide semiconductor and method for manufacturing the same
US8435832B2 (en) * 2011-05-26 2013-05-07 Cbrite Inc. Double self-aligned metal oxide TFT
US8643008B2 (en) * 2011-07-22 2014-02-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN203179896U (zh) * 2013-03-20 2013-09-04 京东方科技集团股份有限公司 薄膜晶体管、阵列基板、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5658806A (en) * 1995-10-26 1997-08-19 National Science Council Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration
CN102636927A (zh) * 2011-12-23 2012-08-15 京东方科技集团股份有限公司 阵列基板及其制造方法
CN102544104A (zh) * 2012-01-12 2012-07-04 清华大学 一种耐高压的隧穿晶体管及其制备方法
CN103000531A (zh) * 2012-12-14 2013-03-27 友达光电股份有限公司 一种用于低温多晶硅薄膜晶体管的制造方法

Also Published As

Publication number Publication date
CN103199113B (zh) 2018-12-25
JP6333357B2 (ja) 2018-05-30
EP2978012B1 (en) 2019-08-07
KR20140123924A (ko) 2014-10-23
US20150255618A1 (en) 2015-09-10
EP2978012A1 (en) 2016-01-27
JP2016520995A (ja) 2016-07-14
EP2978012A4 (en) 2016-10-19
CN103199113A (zh) 2013-07-10

Similar Documents

Publication Publication Date Title
WO2014146363A1 (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
CN103456742B (zh) 一种阵列基板及其制作方法、显示装置
WO2018099052A1 (zh) 阵列基板的制备方法、阵列基板及显示装置
WO2016041304A1 (zh) 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
WO2015096355A1 (zh) 阵列基板及其制作方法、显示装置
US10236388B2 (en) Dual gate oxide thin-film transistor and manufacturing method for the same
WO2016176881A1 (zh) 双栅极tft基板的制作方法及其结构
WO2015100898A1 (zh) 薄膜晶体管、tft阵列基板及其制造方法和显示装置
CN105762195B (zh) 金属氧化物薄膜晶体管及其制备方法
WO2014183422A1 (zh) 薄膜晶体管及其制备方法、阵列基板
WO2014117443A1 (zh) 氧化物薄膜晶体管阵列基板及其制作方法、显示面板
WO2016201609A1 (zh) 金属氧化物薄膜晶体管、显示面板及两者的制备方法
WO2018176784A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
US10615282B2 (en) Thin-film transistor and manufacturing method thereof, array substrate, and display apparatus
WO2015096350A1 (zh) 阵列基板及其制备方法
WO2015067068A1 (zh) 低温多晶硅薄膜晶体管阵列基板及其制作方法、显示装置
CN105336746B (zh) 一种双栅极薄膜晶体管及其制作方法、以及阵列基板
WO2015100897A1 (zh) 阵列基板及其制备方法、显示装置
WO2020113771A1 (zh) 阵列基板及其制作方法、显示面板
WO2019042251A1 (zh) 薄膜晶体管、薄膜晶体管制备方法和阵列基板
WO2016201778A1 (zh) 阵列基板及其制造方法
CN110233156A (zh) 薄膜晶体管基板的制作方法及薄膜晶体管基板
WO2013181902A1 (zh) 薄膜晶体管及其制造方法、阵列基板和显示装置
JP2015517206A (ja) トランジスタの製造方法、トランジスタ、アレイ基板及び表示装置
WO2021179330A1 (zh) 阵列基板及其制作方法

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2016503516

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 14348427

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2013840128

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 20147009939

Country of ref document: KR

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13840128

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE